A vertical interconnect wafer level packaging method and structure

Abstract

The present invention discloses a vertical interconnect wafer-level packaging method and structure, belonging to the technical field of integrated circuit wafer-level packaging. The vertical interconnect wafer-level packaging structure includes a bare silicon substrate and a passivation layer and a metal line of a double-sided multi-layer rewiring thereof. After wafer-level double-sided rewiring, it is separated into a single vertical interconnect channel unit by dicing technology. This vertical interconnect channel unit can replace through holes such as TSV, TMV and TGV and be applied in three-dimensional silicon-based fan-out packaging and 2.5D adapter boards. The preparation method is simple and the cost is low, which is suitable for large-scale mass production applications.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit wafer-level packaging, and in particular to a vertical interconnect wafer-level packaging method and structure. Background Art

[0002] With the continuous development of microelectronics technology, users have higher and higher requirements for miniaturization, multi-function, low power consumption and high reliability of the system. In particular, the blowout of market demand for portable handheld terminals in recent years, such as laptops, smart phones and tablets, requires higher integration and interconnection capabilities. In order to meet high-density interconnection, achieve higher integration, achieve high-frequency and high-speed performance of the system, and reduce transmission delay, three-dimensional stacking packaging has a good application prospect.

[0003] The most important vertical interconnect structures in 3D stacking are TSV (Through Silicon Via), TMV (Through Molding Via) and TGV (Through Glass Via). Among them, the aspect ratio of TSV can generally be the highest. In TSV adapter boards, the standard thickness of conventional TSV adapter boards is between 100 microns and 300 microns, and the TSV aperture can be 10-100 microns. However, when the depth of the through hole is too large, it is easy to cause hole defects, thereby affecting the yield and reliability of the product, and the higher the aspect ratio and through hole integration, the more difficult and costly it is. Summary of the invention

[0004] The purpose of the present invention is to provide a vertical interconnect wafer-level packaging method and structure to solve the problem that hole defects are easily caused by excessive through-hole depth in the current packaging process, thereby affecting product yield and reliability.

[0005] In order to solve the above technical problems, the present invention provides a vertical interconnection wafer-level packaging method, comprising:

[0006] Providing a first bare silicon substrate, making n layers of rewiring on the front and back sides thereof and cutting them into vertical interconnection channel units, wherein n≥1;

[0007] Providing a second bare silicon substrate, bonding it to a glass substrate through a temporary bonding adhesive, etching a groove and burying a vertical interconnection channel unit;

[0008] Making n-layer rewiring on the front and back sides of the second bare silicon substrate;

[0009] Welding a plurality of first heterogeneous or heterogeneous chips on the back side of the second bare silicon substrate and filling the bottom with underfill, and growing bumps on the front side;

[0010] Cut and separate to form a single three-dimensional system-level packaging unit.

[0011] Optionally, after etching the groove and burying the vertical interconnection channel unit, the vertical interconnection wafer-level packaging method further includes: burying a second heterogeneous or heterogeneous chip in the groove, with the pad of the second heterogeneous or heterogeneous chip facing outward.

[0012] Optionally, fine grinding is performed on the front and back sides of the bare silicon to form a first bare silicon substrate; the thickness of the first bare silicon substrate is not less than 1 μm.

[0013] Optionally, the n-layer rewiring includes a passivation layer and a metal circuit layer; the passivation layer is an inorganic material or polyimide or resin, and the metal circuit layer is one or more metal materials;

[0014] The inorganic materials include SiO2, SiN and SiC; the metal materials include Ti, W, Cu, Ni and Au.

[0015] Optionally, forming n-layer rewiring on the front and back sides of the second bare silicon substrate includes:

[0016] Forming n-layer rewiring on the front side of the second bare silicon substrate;

[0017] The glass carrier is disassembled and the bonding adhesive is cleaned, and an n-layer rewiring is made on the back side of the second bare silicon substrate.

[0018] Optionally, a plurality of first heterogeneous or heterogeneous chips are welded to the back side of the second bare silicon substrate through micro bumps using a flip chip welding technology.

[0019] The present invention also provides a vertical interconnect wafer-level packaging structure, comprising:

[0020] A second bare silicon substrate, wherein the second bare silicon substrate has a groove;

[0021] vertically interconnected channel units buried in the grooves;

[0022] The front and back sides of the second bare silicon substrate are both made with n-layer rewiring; the back side of the second bare silicon substrate is welded with a plurality of first heterogeneous or heterogeneous chips through micro-bumps, and the front side is grown with bumps.

[0023] Optionally, a second heterogeneous or heterogeneous chip is buried in the groove, and a pad of the second heterogeneous or heterogeneous chip faces outwards.

[0024] Optionally, the vertical interconnection channel unit includes a first bare silicon substrate, and n layers of rewiring are formed on both the front and back sides of the first bare silicon substrate.

[0025] The present invention provides a vertical interconnect wafer-level packaging method and structure, the vertical interconnect wafer-level packaging structure includes a bare silicon substrate and a passivation layer and a metal line of a double-sided multi-layer rewiring. After wafer-level double-sided rewiring, it is separated into a single vertical interconnect channel unit by dicing technology. This vertical interconnect channel unit is applied to three-dimensional silicon-based fan-out packaging and 2.5D adapter board. The preparation method is simple, the cost is low, and it is suitable for large-scale mass production applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a schematic flow chart of the vertical interconnect wafer-level packaging method provided by the present invention;

[0027] Figure 2 is a schematic diagram of finely grinding the front and back sides of bare silicon to form a first bare silicon substrate;

[0028] Figure 3 It is a schematic diagram of n-layer rewiring on the front and back sides of the first bare silicon substrate;

[0029] Figure 4 It is a top view after making n-layer rewiring;

[0030] Figure 5 is a schematic diagram of the structure of a vertically interconnected channel unit;

[0031] Figure 6 is a schematic diagram of etching a groove on a second bare silicon substrate;

[0032] Figure 7 is a schematic diagram of burying vertical interconnected channel units in grooves;

[0033] Figure 8 It is a schematic diagram of making n-layer rewiring on the front and back sides of the second bare silicon substrate;

[0034] Fig. 9 It is a schematic diagram of a 2.5D package based on vertically interconnected channel units;

[0035] Fig.10 is a schematic diagram of etching a plurality of grooves on a second bare silicon substrate;

[0036] Fig.11 is a schematic diagram of burying a second heterogeneous or heterogeneous chip and a vertical interconnection channel unit in a groove;

[0037] Fig.12 It is a schematic diagram of making n-layer rewiring on the front and back sides of the second bare silicon substrate;

[0038] Fig.13 It is a schematic diagram of a three-dimensional fan-out package based on vertically interconnected channel units. DETAILED DESCRIPTION

[0039] The following is a further detailed description of a vertical interconnect wafer-level packaging method and structure proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description and claims. It should be noted that the drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0040] Embodiment 1

[0041] The present invention provides a vertical interconnect wafer level packaging method, the process of which is as follows: Figure 1 As shown, the following steps are included:

[0042] Step S11, providing a first bare silicon substrate, making n layers of rewiring on the front and back sides thereof and cutting them into vertical interconnection channel units, wherein n≥1;

[0043] Step S12, providing a second bare silicon substrate, bonding it to a glass carrier through a temporary bonding adhesive, etching a groove and embedding a vertical interconnection channel unit;

[0044] Step S13, making n-layer rewiring on the front and back sides of the second bare silicon substrate;

[0045] Step S14, welding a plurality of first heterogeneous or heterogeneous chips on the back side of the second bare silicon substrate and filling the bottom with underfill, and growing bumps on the front side;

[0046] Step S15 , cutting and separating to form a single three-dimensional system-level package unit.

[0047] First, the front and back sides of the bare silicon are finely ground to form Figure 2 The first bare silicon substrate 101 shown has a target thickness of not less than 1 μm;

[0048] like Figure 3 As shown, double-sided wiring technology is used to perform n-layer rewiring on the front and back sides of the first bare silicon substrate 101, where n≥1; the n-layer rewiring includes a passivation layer 102a and a metal circuit layer 102b; wherein the passivation layer 102a is an inorganic material such as SiO2, SiN, SiC or an organic material such as polyimide and resin, and the metal circuit layer 102b is made of metal, including one or more of Ti, W, Cu, Ni and Au.

[0049] Figure 4 It is a top view after making n-layer rewiring; after the n-layer rewiring is prepared, it is separated into single independent vertical interconnection channel units by laser and mechanical cutting. The separated vertical interconnection channel units need to be rotated 90° before use. The vertical interconnection channel units are specifically shown in 5;

[0050] When a 2.5D interposer is used, a second bare silicon substrate 201 is provided, bonded to a glass carrier 203 via a temporary bonding adhesive 202, and then a groove is etched by dry etching or wet etching, such as Figure 6 As shown;

[0051] Using chip mounting technology to embed such Figure 5 The vertically interconnected channel units shown, such as Figure 7 As shown;

[0052] like Figure 8 As shown, an n-layer rewiring is made on the front side of the second bare silicon substrate 201; the glass carrier 203 is removed and the bonding adhesive 202 is cleaned, and an n-layer rewiring is made on the back side of the second bare silicon substrate 201; the n-layer rewiring on the front and back sides of the second bare silicon substrate 201 is the same as the n-layer rewiring on the front and back sides of the first bare silicon substrate 101, and the n-layer rewiring includes a passivation layer 102a and a metal circuit layer 102b; wherein the passivation layer 102a is an inorganic material such as SiO2, SiN, SiC or an organic material such as polyimide and resin, and the metal circuit layer 102b is a metal material, including one or more of Ti, W, Cu, Ni and Au;

[0053] like Fig. 9 As shown, a plurality of first heterogeneous or heterogeneous chips (including heterogeneous or heterogeneous chips 301, heterogeneous or heterogeneous chips 302 and heterogeneous or heterogeneous chips 303) are welded on the back of the second bare silicon substrate 201 through micro bumps 304 using flip-chip welding technology, and bumps 103 are grown on the front of the second bare silicon substrate 201; bottom filler 305 is filled at the bottom of the first heterogeneous or heterogeneous chips; and finally, they are cut and separated to form a single three-dimensional system-level packaging unit.

[0054] In the case of a three-dimensional fan-out packaging application, a second bare silicon substrate 201 is provided, bonded to a glass carrier 203 via a temporary bonding adhesive 202, and then a plurality of grooves are etched by dry etching or wet etching, such as Fig.10 As shown;

[0055] A plurality of second heterogeneous or heterogeneous chips 401 are buried in the groove, with the pads 401a facing outwards, and at the same time, a plurality of second heterogeneous or heterogeneous chips 401 are buried. Figure 5 The vertically interconnected channel units shown, such as Fig.11 As shown;

[0056] like Fig.12As shown, an n-layer rewiring is made on the front side of the second bare silicon substrate 201; the glass carrier 203 is removed and the bonding adhesive 202 is cleaned, and an n-layer rewiring is made on the back side of the second bare silicon substrate 201; the n-layer rewiring on the front and back sides of the second bare silicon substrate 201 is the same as the n-layer rewiring on the front and back sides of the first bare silicon substrate 101, and the n-layer rewiring includes a passivation layer 102a and a metal circuit layer 102b; wherein the passivation layer 102a is an inorganic material such as SiO2, SiN, SiC or an organic material such as polyimide and resin, and the metal circuit layer 102b is a metal material, including one or more of Ti, W, Cu, Ni and Au;

[0057] like Fig.13 As shown, a plurality of first heterogeneous or heterogeneous chips (including heterogeneous or heterogeneous chips 301, heterogeneous or heterogeneous chips 302 and heterogeneous or heterogeneous chips 303) are welded on the back of the second bare silicon substrate 201 through micro bumps 304 using flip-chip welding technology, and bumps 103 are grown on the front of the second bare silicon substrate 201; bottom filler 305 is filled at the bottom of the first heterogeneous or heterogeneous chips; and finally, they are cut and separated to form a single three-dimensional system-level packaging unit.

[0058] Embodiment 2

[0059] The present invention provides a vertical interconnect wafer-level packaging structure. When used in a 2.5D interposer (silicon interposer), the structure is as follows: Fig. 9 As shown, it includes a second bare silicon substrate 201, wherein the second bare silicon substrate 201 has a groove; the vertical interconnection channel unit is buried in the groove;

[0060] The second bare silicon substrate 201 has n-layer rewiring on both the front and back sides; a plurality of first heterogeneous or heterogeneous chips (including heterogeneous or heterogeneous chip 301, heterogeneous or heterogeneous chip 302 and heterogeneous or heterogeneous chip 303) are welded on the back side of the second bare silicon substrate 201 through micro-bumps 304, and bumps 103 are grown on the front side.

[0061] The vertically interconnected channel units are as follows Figure 5 As shown, it includes a first bare silicon substrate 101, and n-layer rewiring is made on the front and back sides of the first bare silicon substrate 101; wherein the n-layer rewiring includes a passivation layer 102a and a metal circuit layer 102b.

[0062] When the vertical interconnect wafer-level packaging structure is applied in a three-dimensional fan-out packaging, its structure is as follows: Fig.13 As shown, a second heterogeneous or heterogeneous chip 401 is also buried in the groove, and the pad 401a of the second heterogeneous or heterogeneous chip faces outward; the rest is the same as when a 2.5D interposer (silicon interposer) is used.

[0063] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A vertical interconnect wafer level packaging method, characterized in that: include: Providing a first bare silicon substrate, making n layers of rewiring on the front and back sides thereof and cutting them into vertical interconnection channel units, wherein n≥1; Providing a second bare silicon substrate, bonding it to a glass substrate through a temporary bonding adhesive, etching a groove and burying a vertical interconnection channel unit; Making n-layer rewiring on the front and back sides of the second bare silicon substrate; Welding a plurality of first heterogeneous or heterogeneous chips on the back side of the second bare silicon substrate and filling the bottom with underfill, and growing bumps on the front side; Cut and separate to form a single three-dimensional system-level packaging unit.

2. The vertical interconnect wafer level packaging method according to claim 1, characterized in that: After etching the groove and burying the vertical interconnection channel unit, the vertical interconnection wafer-level packaging method further includes: burying a second heterogeneous or heterogeneous chip in the groove, with the pad of the second heterogeneous or heterogeneous chip facing outward.

3. The vertical interconnect wafer level packaging method according to claim 1 or 2, characterized in that: A first bare silicon substrate is formed by fine grinding on the front and back sides of the bare silicon; the thickness of the first bare silicon substrate is not less than 1 μm.

4. The vertical interconnect wafer level packaging method according to claim 1 or 2, characterized in that: The n-layer rewiring includes a passivation layer and a metal circuit layer; the passivation layer is an inorganic material or polyimide or resin, and the metal circuit layer is one or more metal materials; The inorganic materials include SiO2, SiN and SiC; the metal materials include Ti, W, Cu, Ni and Au.

5. The vertical interconnect wafer level packaging method according to claim 1 or 2, characterized in that: The n-layer rewiring is fabricated on the front and back sides of the second bare silicon substrate, including: Forming n-layer rewiring on the front side of the second bare silicon substrate; The glass carrier is disassembled and the bonding adhesive is cleaned, and an n-layer rewiring is made on the back side of the second bare silicon substrate.

6. The vertical interconnect wafer level packaging method according to claim 1 or 2, characterized in that: A plurality of first heterogeneous or heterogeneous chips are welded to the back side of the second bare silicon substrate by using a flip chip welding technology through micro bumps.

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