Reliable surface mount integrated power module

Abstract

The present invention relates to a reliable surface mount integral power module, and discloses a surface mount packaging structure that produces improved thermo-mechanical reliability and more robust secondary packaging interconnects. The surface mount packaging structure includes a submodule having a dielectric layer, a semiconductor device attached to the dielectric layer, a first level metal interconnect electrically connected to the semiconductor device, and a second level I / O connection electrically connected to the first level interconnect and formed on the dielectric layer on a side opposite to the semiconductor device, wherein the second level I / O connection is configured to connect the submodule to an external circuit. The semiconductor device of the submodule is attached to a first surface of a multi-layer substrate structure, wherein a dielectric material is positioned between the dielectric layer and the multi-layer substrate structure to fill gaps in the surface mount structure and provide additional structural integrity thereto.

Description

Technical Field

[0001] Embodiments of the present invention relate generally to structures and methods for packaging semiconductor devices, and more particularly to surface mount packaging structures that produce improved thermo-mechanical reliability and more robust second level packaging interconnects. Background Art

[0002] Surface mount technology is a method for constructing electronic circuits or other similar external circuits in which surface mount components or packages are mounted directly to the surface of a printed circuit board (PCB). In the industry, surface mount technology has replaced the through-hole technology construction method of assembling components with leads in holes in a circuit board.

[0003] One common type of surface mounted component is a power semiconductor device, which is a semiconductor device used as a switch or rectifier in a power electronic circuit, such as, for example, a switch mode power supply. Most power semiconductor devices are used only in switching mode (i.e., they are either switched on or off), and are therefore optimized for this. Many power semiconductor devices are used in high voltage power applications, and are designed to carry large amounts of current and support large voltages. In use, the high voltage power semiconductor device is surface mounted to an external circuit with the aid of a power overlay (POL) package and interconnect system, wherein the POL package also provides a way to remove heat generated by the device and protect the device from the external environment.

[0004] The standard POL package manufacturing process typically begins with placing one or more power semiconductor devices onto a dielectric layer via an adhesive. Metal interconnects (e.g., copper interconnects) are then electroplated onto the dielectric layer to form direct metal connections to the power semiconductor devices to form a POL submodule. The metal interconnects may be in the form of low-profile (e.g., less than 200 microns thick), flat interconnect structures that are used to form input / output (I / O) systems to and from the power semiconductor devices. The POL submodule is then soldered to a ceramic substrate (alumina with DBC, AlN with AMB Cu, etc.) using solder interconnects for electrical and thermal connections. The gap around the semiconductor between the POL dielectric layer and the ceramic substrate is then filled with a dielectric organic material using capillary flow (capillary underfill), no-flow underfill, or injection molding (molding compound) to form a POL package.

[0005] In existing surface mounted POL packages, the long term reliability of the package is limited by the thermo-mechanical stresses generated due to the different coefficients of thermal expansion (CTE) of the constituent materials. More specifically, the different CTEs of the dielectric organic material / underfill and the ceramic substrate of the POL package cause thermal and bending stresses in the underfill and the ceramic substrate. These thermal and bending stresses in the underfill and the ceramic substrate in turn cause warping of the package. When warping of the package occurs, the reliability of the second level interconnects of the package is affected.

[0006] Therefore, it would be desirable to provide a surface mount package having a stress balance based design strategy that reduces package warpage and thermal stress so that package reliability during thermal cycling can be improved. It is also desirable that such a package design strategy improves the reliability of second level interconnects. Summary of the invention

[0007] Embodiments of the present invention overcome the aforementioned disadvantages by providing a surface mount packaging structure that results in improved thermo-mechanical reliability and more robust second level packaging interconnects.

[0008] According to one aspect of the present invention, a surface mount structure includes a submodule having a dielectric layer and at least one semiconductor device attached to the dielectric layer, wherein each of the at least one semiconductor device includes a substrate composed of a semiconductor material. The submodule also includes: a primary metal interconnect structure electrically coupled to the at least one semiconductor device, which extends through a via formed through the dielectric layer so as to connect to the at least one semiconductor device; and a secondary input / output (I / O) connection electrically coupled to the primary metal interconnect structure and formed on the dielectric layer on a side opposite to the at least one semiconductor device, the secondary I / O connection being configured to connect the submodule to an external circuit. The surface mount structure also includes a multilayer substrate structure having a first surface and a second surface, wherein the at least one semiconductor device of the submodule is attached to the first surface of the multilayer substrate. The surface mount structure also includes one or more dielectric materials positioned between the dielectric layer and the first surface of the multilayer substrate structure and at least partially surrounding the at least one semiconductor device of the submodule, the one or more dielectric materials being configured to fill gaps in the surface mount structure and provide additional structural integrity thereto.

[0009] According to another aspect of the present invention, a method for manufacturing a surface mount package and interconnect structure includes the steps of forming a submodule, the submodule including at least one semiconductor device and a package structure formed thereabout, wherein the step of forming the submodule further includes: attaching the at least one semiconductor device to a dielectric layer; forming a first level metal interconnect structure above the dielectric layer, which extends through a through hole in the dielectric layer to electrically connect to the at least one semiconductor device; and forming a second level input / output (I / O) connection on the dielectric layer on a side opposite to the at least one semiconductor device, wherein the second level I / O connection is configured to connect the submodule to an external circuit. The method also includes the steps of forming a substrate structure, the substrate structure including a central substrate layer and first and second metal layers located on opposite sides of the central substrate layer, so that the first and second metal layers form a first surface and a second surface of the substrate structure, respectively. The method also includes the steps of attaching the submodule to the first surface of the substrate structure and providing a dielectric fill material between the dielectric layer and the first surface of the substrate structure, the dielectric fill material at least partially encapsulating the at least one semiconductor device of the submodule.

[0010] According to another aspect of the present invention, a power overlay (POL) package structure includes a POL submodule having: a dielectric layer; a plurality of semiconductor devices attached to the dielectric layer; a primary interconnect structure electrically coupled to the plurality of semiconductor devices and extending through a through hole formed through the dielectric layer so as to be connected to the plurality of semiconductor devices; and a secondary interconnect structure for electrically coupling the POL submodule to an external circuit structure, wherein the secondary interconnect structure includes a plurality of solder bumps formed over the dielectric layer and the primary interconnect structure and configured to establish interconnections to the external circuit structure. The POL package structure also includes a multilayer substrate structure having a first surface and a second surface, wherein the plurality of semiconductor devices of the POL submodule are attached to the first surface of the multilayer substrate structure. The multilayer substrate structure of the POL package structure also includes a first direct bond copper (DBC) layer forming the first surface of the multilayer substrate structure, a second DBC layer forming the second surface of the multilayer substrate structure, and a ceramic layer sandwiched between the first and second DBC layers. The POL package structure also includes an encapsulant positioned between the dielectric layer and the first surface of the multilayer substrate structure and at least partially surrounding the plurality of semiconductor devices of the submodule.

[0011] The present invention discloses a surface mounting structure, which includes: a submodule; a multilayer substrate structure having a first surface and a second surface, wherein at least one semiconductor device of the submodule is attached to the first surface of the multilayer substrate; and one or more dielectric materials, which are positioned between the dielectric layer and the first surface of the multilayer substrate structure and at least partially surround the at least one semiconductor device of the submodule, and the one or more dielectric materials are configured to fill the gap in the surface mounting structure and provide additional structural integrity to it. The submodule includes: a dielectric layer; at least one semiconductor device attached to the dielectric layer, each of the at least one semiconductor device includes a substrate composed of a semiconductor material; a first-level metal interconnect structure electrically connected to the at least one semiconductor device, the metal interconnect structure extending through a through hole formed through the dielectric layer so as to connect to the at least one semiconductor device; and a second-level input / output (I / O) connection, which is electrically connected to the first-level metal interconnect structure and formed on the dielectric layer on the side opposite to the at least one semiconductor device, and the second-level I / O connection is configured to connect the submodule to an external circuit.

[0012] Preferably, the multilayer substrate structure comprises: a ceramic insulating layer; a first metal layer positioned on one side of the insulating layer to form a first surface of the multilayer substrate structure; and a second metal layer positioned on the other side of the insulating layer to form a second surface of the multilayer substrate structure.

[0013] Preferably, the first and second metal layers comprise first and second direct bonded copper (DBC) layers.

[0014] Preferably, the first DBC layer comprises a patterned DBC layer, and the second DBC layer comprises a patterned or unpatterned DBC layer.

[0015] Preferably, the volume of the second DBC layer is greater than the volume of the first DBC layer.

[0016] Preferably, the volume of the second DBC layer is between 1 and 2.5 times the volume of the first DBC layer.

[0017] Preferably, the thickness or area and corresponding volume of the second DBC layer is controlled based on at least one of the thickness and material properties of one or more dielectric materials, the density, thickness and spacing of at least one semiconductor device, and the thickness and material properties of the ceramic insulating layer.

[0018] Preferably, the material properties of the one or more dielectric materials and the ceramic insulating layer include elastic modulus, coefficient of thermal expansion (CTE), and at least one of fracture stress and toughness.

[0019] Preferably, the volume ratio between the second DBC layer and the first DBC layer provides a stress-balanced surface mount package and interconnect structure with reduced warpage and thermal stress therein.

[0020] Preferably, the one or more dielectric materials include an underfill material, an encapsulant, a silicone or a molding compound positioned between the dielectric layer and the first surface of the multi-layer substrate structure.

[0021] Preferably, the one or more dielectric materials include: a ceramic or dielectric sheet positioned between the dielectric layer and the first surface of the multi-layer substrate structure, the ceramic or dielectric sheet having a cutout formed therein to accommodate at least one semiconductor device; and a dielectric filling material positioned between the ceramic or dielectric sheet and the first surface of the multi-layer substrate structure so as to fill a gap between the ceramic or dielectric sheet and the multi-layer substrate structure.

[0022] Preferably, the secondary I / O connection comprises one of a land grid array (LGA) solder bump and a ball grid array (BGA) solder bump.

[0023] Preferably, the surface mounting structure further comprises one of a soldering material, a conductive adhesive or a sintered metal joint positioned between the multi-layer substrate structure and the sub-module to secure the sub-module to the multi-layer substrate structure.

[0024] Preferably, the submodule comprises a power overlay (POL) submodule.

[0025] Preferably, the at least one semiconductor device comprises a plurality of semiconductor devices attached to a dielectric layer.

[0026] These and other advantages and features will be more readily understood from the following detailed description of the preferred embodiments of the present invention provided in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The drawings illustrate embodiments presently contemplated for carrying out the invention.

[0028] In the attached picture:

[0029] Figure 1 is a schematic cross-sectional side view of a power overlay (POL) structure according to an embodiment of the present invention;

[0030] Figures 2 to 11 is a schematic cross-sectional side view of a POL structure during various stages of a manufacturing / building process according to an embodiment of the present invention;

[0031] Fig.12 is a schematic cross-sectional side view of a POL structure according to another embodiment of the present invention.

[0032] Reference numerals:

[0033] 10 Surface Mount Packaging and Interconnect Structures

[0034] 12 Semiconductor devices

[0035] 14 POL submodule

[0036] 16 Secondary Input-Output (I / O) Connections

[0037] 17 Soldering Bumps

[0038] 18 Multilayer substrate structure

[0039] 20 Alumina

[0040] 22 Direct copper coating

[0041] 24 Direct copper coating

[0042] 26 Dielectric Materials

[0043] 30 Dielectric layer

[0044] 32 Frame structure

[0045] 34 Adhesive layer

[0046] 36+ through holes

[0047] 37 Copper gasket

[0048] 38 First level interconnection

[0049] 39 Top

[0050] 40 Solder mask layer

[0051] 42 Welding materials

[0052] 44 Thickness

[0053] 46 Coverage Area

[0054] 50 POL structure

[0055] 52 Ceramic or dielectric sheet

[0056] 54 Incision

[0057] 56 Polymer underfill material or molding compound

[0058] 58 gap. DETAILED DESCRIPTION

[0059] Embodiments of the present invention provide a surface mount package with improved thermo-mechanical reliability, and a method of forming such a surface mount package.

[0060] Reference Figure 1 , shows a surface mount package and interconnect structure 10 according to an embodiment of the present invention. Figure 1In the embodiment shown in FIG. 1 , the surface mount package structure 10 is in the form of a power overlay (POL) structure, but it is recognized that other surface mount package structures are considered to be within the scope of the present invention. The POL structure 10 includes one or more semiconductor devices 12 therein, which may be in the form of a die, diode, or other power electronic device according to various embodiments. Figure 1 As shown in FIG, three semiconductor devices 12 are provided in the POL structure 10, however it is recognized that a greater or lesser number of semiconductor devices 12 may be included in the POL structure 10. The semiconductor devices 12 are packaged within a POL submodule 14 that forms a direct metal connection to the power semiconductor devices 12, wherein the connection is in the form of a low-profile, planar first level interconnect structure, for example.

[0061] Secondary input-output (I / O) connections 16 are provided on the POL submodule 14 to enable surface mounting of the POL structure 10 to an external circuit, such as a printed circuit board (PCB) (not shown). According to an exemplary embodiment, the secondary I / O connections 16 are formed by land grid array (LGA) solder bumps 17 configured to be attached / secured to the PCB to electrically couple the POL structure 10 to the PCB, but other suitable secondary solder interconnects, such as ball grid array (BGA) solder bumps, may also be used. The LGA solder bumps 17 provide a highly reliable interconnect structure that resists failure under high stress conditions.

[0062] like Figure 1 As shown in , the POL structure 10 also includes a multi-layer substrate structure 18 to which the POL submodules 14 are attached. According to an exemplary embodiment, the substrate structure 18 is composed of a ceramic plate (e.g., alumina) 20 with a layer of direct bonded copper (DBC) 22, 24 bonded to both sides thereof by a high temperature bonding process, wherein the top DBC layer 22 forms the "first surface" of the structure 18 and the bottom DBC layer 24 forms the "second surface" of the structure 18. For the bonding process, different brazing and direct bonding techniques may be employed based on, for example, whether the plate 20 is composed of alumina or aluminum nitride and silicon nitride. The top DBC layer 22 or "chip side DBC layer" of the substrate structure 18 is then etched after sintering to pattern the layer as desired based on the number / arrangement of the semiconductor devices 12. The bottom DBC layer 24 or "non-chip side DBC layer" on the back side of the substrate structure 18 is fully or partially exposed to provide efficient heat transfer out of the POL structure 10. Although referred to above and below as a "DBC" layer, it should be appreciated that aluminum may be used as the metal layer in place of copper, and such an embodiment is therefore considered to be within the scope of the present invention. Therefore, the use of the term "DBC layer" hereinafter is intended to encompass a substrate structure 18 comprising sheets of any suitable metal material 22, 24 (such as copper or aluminum) bonded to both sides of a porcelain plate (e.g., alumina) 20. Figure 1As shown in FIG. 1 , a dielectric material 26 (ie, a “dielectric filler material”) is also disposed on the POL structure 10 to fill the gaps in the POL structure 10 so as to provide additional structural integrity to the POL structure 10 . Figure 1 In the embodiment of the POL structure 10 shown in FIG. 1 , the dielectric material 26 is in the form of a polymer underfill (eg, a capillary underfill or a no-flow underfill), an encapsulant, a silicone, or a molding compound. Alternatively, and as will be referred to below, Fig.12 Discussing in more detail, it should be appreciated that dielectric material 26 may be formed from a combination of a ceramic or dielectric sheet and an additional dielectric filler material (underfill, molding compound, silicone, or encapsulant).

[0063] Figure 1 The POL structure 10 is thus formed such that the second level package I / O connections 16 are disposed on the first level interconnect side for second level interconnection to a PCB or other external circuit. The specific construction of the POL structure 10 results in improved thermo-mechanical reliability and more robust second level package I / O connections 16, as well as excellent electrical and thermal performance.

[0064] Now refer to Figures 2 to 11 According to an embodiment of the present invention, there is provided a method for manufacturing Figure 1 A detailed view of the process steps of the POL structure 10 technology. Figures 2 to 9 As shown in FIG. 1 , a process for constructing the POL submodule 14 is provided. Figure 2 , the assembly process of the POL submodule 14 begins by placing and attaching a dielectric layer 30 or "flex layer" to a frame structure 32. The dielectric layer 30 is in the form of a laminate or film and is placed on the frame structure 32 to provide stability during the assembly process of the POL submodule 14. According to an embodiment of the present invention, the dielectric layer 30 can be formed of one of a variety of dielectric materials, such as Kapton®, Ultem®, polytetrafluoroethylene (PTFE), Upilex®, a polysulfone material (e.g., Udel®, Radel®), or another polymer film (such as a liquid crystal polymer (LCP) or a polyimide material).

[0065] like Figure 3 As shown in FIG. 1 , after the dielectric layer 30 is fixed to the frame structure 32, an adhesive layer 34 is deposited onto the dielectric layer 30. A plurality of through holes 36 are then formed through the adhesive layer 34 and the dielectric layer 30, as shown in FIG. Figure 4 According to an embodiment of the present invention, the through hole 36 may be formed by laser ablation or laser drilling process, plasma etching, photodefinition or mechanical drilling process. In the next technical step, one or more semiconductor devices 12 (for example, three semiconductor devices) are fixed to the dielectric layer 30 via an adhesive layer 34, such as Figure 5In order to fix the semiconductor device 12 to the dielectric layer 30, the semiconductor device 12 is placed on the adhesive layer 34 and then the adhesive 34 is cured to fix the semiconductor device 12 to the dielectric layer 30. According to one embodiment of the present invention and as Figure 5 As shown in , the semiconductor devices 12 may have different thicknesses / heights. To increase the thickness / height of the semiconductor devices 12, a copper pad 37 may be soldered to one or more of the semiconductor devices 12 to increase their thickness / height, so that the thickness / height of all semiconductor devices 12 is equal and the backside of the semiconductor devices 12 is "flattened".

[0066] Although the through hole 36 is formed through the adhesive layer 34 and the dielectric stack 30, Figure 4 34, but it is recognized that the placement of semiconductor device 12 may occur before the formation of the vias. That is, depending on the constraints imposed by the via size, semiconductor device 12 may be first placed on adhesive layer 34 and dielectric layer 30, and vias 36 may be subsequently formed at locations corresponding to a plurality of metal circuits and / or connection pads (not shown) formed on semiconductor device 12. Moreover, a combination of pre-drilled vias and post-drilled vias may be employed as desired.

[0067] Now refer to Figure 6 and Figure 7 After the semiconductor device 12 is secured to the dielectric layer 30 and the vias 36 are formed, the vias 36 are cleaned (such as by a reactive ion etching (RIE) dust removal process) and then metalized to form a first level interconnect 38. The first level metal interconnect 38 is typically formed by a combination of sputtering and electroplating applications, but it is recognized that other non-electrolytic methods of metal deposition may also be used. For example, a titanium adhesion layer and a copper seed layer may first be applied via a sputtering process, followed by an electroplating process to increase the thickness of the copper to a desired level. The applied metal material is then patterned into a metal interconnect 38 (i.e., a first level interconnect) having a desired shape and which acts as a vertical feedthrough formed through the dielectric layer 30 and the adhesive layer 30. The metal interconnect 38 extends from the circuit and / or connection pad (not shown) of the semiconductor device 12, through the via / opening 36 and out across the top surface 39 of the dielectric layer 30.

[0068] like Figure 8 As shown in FIG. 1 , a solder mask layer 40 is applied over the patterned metal interconnects 38 to provide a protective coating for the copper pads thereof. In addition to solder, it is recognized that this layer 40 may be composed of some metallic material other than solder (such as Ni or Ni / Au). Figure 8As further shown in FIG. 1 , the second level I / O interconnect 16 is applied to a solder mask layer 40 on top of the dielectric layer 30. In one embodiment, the I / O interconnect 16 is formed as an LGA or BGA solder bump 17 that is soldered to the solder mask 40 to enable surface mounting of the POL structure 10 to an external circuit. The solder bump 17 provides a highly reliable second level interconnect structure that resists failure under high stress conditions.

[0069] When the POL submodule 14 is assembled, the POL submodule 14 is segmented and removed from the frame structure 32, as shown in FIG. Fig. 9 Thus, a completed POL submodule 14 is provided, which includes the semiconductor device 12, the first level metal interconnect 38 acting as a metal vertical feedthrough, and the second level I / O interconnect 16 for surface mounting the POL submodule 14 to an external circuit (such as a PCB). The POL submodule 14 is handled as a component or a multi-chip module.

[0070] Now refer to Fig.10 The technique for manufacturing the POL structure 10 continues with forming a substrate structure 18 to be bonded to the POL submodule 14. The substrate structure 18 is composed of a ceramic plate (e.g., alumina) 20 with a chip-side DBC layer 22 and a non-chip-side DBC layer 24 bonded to both sides thereof by a high temperature bonding process. Fig.10 As shown in FIG, the chip-side DCB layer 22 of the substrate structure 18 is patterned, for example, via an etching process, to correlate with the number / arrangement of the semiconductor devices 12 of the POL submodule 14. According to an exemplary embodiment, the non-chip-side DBC layer 24 on the back side of the substrate structure 18 is not patterned as a continuous layer in order to provide greater bending strength of the substrate structure 18. In addition, the entire surface of the non-chip-side DBC layer 24 can be used for thermal connection (i.e., heat sink attachment).

[0071] like Fig.11 As shown in , the technique for manufacturing the POL structure 10 continues with attaching the POL submodule 14 to the substrate structure 18. According to one embodiment of the present invention, the POL submodule 14 is attached to the substrate structure 18 via a solder material 42 so as to fix the POL submodule 14 and the substrate structure 18 together. That is, each semiconductor device 12 is soldered to the chip-side DBC layer 22. However, it is recognized that a conductive adhesive or sintered silver may also be used instead of a solder material to fix the POL submodule 14 and the substrate structure 18 together. A polymer underfill, sealant or molding compound 26 (e.g., epoxy resin or other organic filling material) is then provided on the POL structure 10, which fills the gaps in the POL structure 10, such as Fig.11 , so as to constrain the dielectric layer 30 and provide additional electrical insulation and structural integrity to the POL structure 10 .

[0072] like Fig.10and Fig.11 As shown in , according to an exemplary embodiment of the present invention, the formation of the substrate structure 18 is selectively performed to optimize the thermal performance of the POL structure 10. That is, it is recognized that there is a mismatch between the coefficient of thermal expansion (CTE) of the ceramic substrate 20 (which generally has a low CTE) and the underfill 26 and copper pads / connections 22, 24, 38 (which generally have a high CTE) in the substrate structure 18, and this CTE mismatch may cause unbalanced thermal stress in the POL structure 10, and thereby cause module warpage, bending stress and cracking in the ceramic / insulating substrate 20, the underfill material 26 and / or the secondary I / O interconnect 16 (i.e., the BGA / LGA solder bump 17). The unbalanced thermal stress in the POL structure 10 and the resulting warpage, bending stress and cracking may be reduced by the selective formation of the substrate structure 18. When forming the substrate structure 18, the thickness (labeled as 44) and the coverage area (labeled as 46) of the non-chip side DBC layer 24 are selectively controlled to optimize the thermal performance of the POL structure 10. More specifically, the ratio of the volume of the non-chip side DBC layer 24 to the volume of the chip side DBC layer 22 is selected / controlled so that the thermal / bending stresses in both the bottom filler 26 and the ceramic substrate 20 are reduced to acceptable levels. By providing additional DBC volume to the layer 24 on the back side (i.e., the non-chip side) of the substrate, the thermal expansion of the DBC layer 24 on the non-chip side can offset the expansion of the bottom filler / sealant 26 on the chip side of the ceramic substrate 20, so that the thermal / bending stresses are reduced.

[0073] In determining the appropriate volume ratio / volume imbalance of the non-chip-side DBC 24 to the chip-side DBC 22 and the corresponding thickness 44 and footprint 46 of the DBC layer 24, the following factors are considered: (1) the volume of the underfill 26 and its known material properties, including the elastic modulus, coefficient of thermal expansion (CTE), and fracture stress and toughness of the underfill material; (2) the density, thickness, and spacing of the chips 12 within the POL submodule 14; and (3) the thickness and material properties of the ceramic substrate 20, including the elastic modulus and CTE of the ceramic substrate. In general, a stiffer underfill material 26 requires a larger DBC volume imbalance between the DBC layers 22, 24 to reduce module warpage and bending stress, while a compliant underfill material requires a smaller volume imbalance.

[0074] According to an exemplary embodiment of the present invention, for a typical organic underfill material 26 for electronic component packaging, the DBC volume ratio / volume imbalance of the non-chip side DBC 24 and the chip side DBC 22 will be greater than 1 and less than 2.5. That is, it is desirable that the DBC volume ratio / volume imbalance is within this range because a balanced ceramic substrate (i.e., a DBC ratio of about 1) will exhibit high imbalance thermal stress during thermal cycling and a larger package curvature (warpage) due to the high CTE mismatch between the ceramic 20 (3-9 ppm / C) and the typical organic underfill 26 (9-50 ppm / C). By increasing the DBC volume ratio of the non-chip side DBC 24 to the chip side DBC 22 to between 1 and 2.5, a stress balance is provided, which reduces the POL package curvature and achieves a more robust second-level module interconnect 16. With respect to the range of 1 to 2.5 listed above, it is recognized that if the CTE of underfill 26 is low, the DBC volume ratio / volume imbalance of non-chip side DBC 24 and chip side DBC 22 may be less than 1, resulting in a reduced CTE mismatch.

[0075] Now refer to Fig.12 , a POL structure 50 is shown according to another embodiment of the present invention, wherein a separate dielectric element is used to fill the gap in the POL structure 50 between the dielectric layer 30 and the substrate structure 18 in the area occupied by the chip 12. Fig.12 As shown in FIG, a ceramic or dielectric sheet 52 is positioned adjacent to the dielectric layer 30 between the dielectric layer 30 and the multi-layer substrate structure 18. The ceramic / dielectric sheet 52 includes a cutout 54 formed therein to receive the chip 12 therein. A polymer underfill material or molding compound 56 is then positioned between the ceramic / dielectric sheet 52 and the multi-layer substrate structure 18 to fill a gap 58 between the ceramic / dielectric sheet 52 and the porcelain / alumina 20 of the multi-layer substrate structure 18. Employing the ceramic / dielectric sheet 52 to fill a portion of the volume in the POL structure 50 between the dielectric layer 30 and the substrate structure 18, as opposed to using only the dielectric fill material 56 entirely, beneficially makes the POL structure 50 less susceptible to moisture absorption, and may further reduce thermo-mechanical stresses in the POL structure 50 to reduce cracking, delamination, etc.

[0076] With respect to the POL structure 50, it is recognized that the volume and known thermo-mechanical material properties of each of the ceramic / dielectric sheet 52 and the underfill material 56 are considered in determining the appropriate volume ratio / volume imbalance of the non-chip-side DBC 24 to the chip-side DBC 22 and the corresponding thickness 44 and footprint 46 of the DBC layer 24. The elastic modulus, coefficient of thermal expansion (CTE), and fracture stress and toughness of each of the ceramic / dielectric sheet 52 and the underfill material 56 may differ from one another, and therefore these material properties of each individual element are considered in determining the volume ratio / volume imbalance.

[0077] Beneficially, embodiments of the present invention thus provide a POL package and interconnect structure 10 having a secondary package I / O' 16 disposed on the flexible side (i.e., the top of the dielectric layer 30) of the POL submodule 14 for secondary interconnection to external circuits, and the entire non-chip side DBC layer 24 can be used for thermal connection. The POL structure 10 incorporates a stress balance-based design strategy that reduces package warpage and thermal stress, so that package reliability during thermal cycling can be improved. The thermal expansion of the non-chip side DBC layer 24 offsets the bottom filler / sealant expansion on the chip side of the ceramic substrate 20, and the resulting stress balance reduces package curvature and achieves a more reliable secondary module interconnect 16. The non-chip side DBC layer 24 can be formed to provide an optimal DBC volume ratio / volume imbalance for a specific package design (device size, density, etc.), wherein the volume of the non-chip side DBC layer 24 is determined based on the package curvature requirements of the secondary assembly, as well as the bending strength and toughness of the dielectric material and the insulating material.

[0078] Thus, according to one embodiment of the present invention, a surface mount structure includes a submodule having a dielectric layer and at least one semiconductor device attached to the dielectric layer, wherein each of the at least one semiconductor device includes a substrate composed of a semiconductor material. The submodule also includes: a primary metal interconnect structure electrically coupled to the at least one semiconductor device, which extends through a via formed through the dielectric layer so as to connect to the at least one semiconductor device; and a secondary input / output (I / O) connection electrically coupled to the primary metal interconnect structure and formed on the dielectric layer on a side opposite to the at least one semiconductor device, the secondary I / O connection being configured to connect the submodule to an external circuit. The surface mount structure also includes a multilayer substrate having a first surface and a second surface, wherein the at least one semiconductor device of the submodule is attached to the first surface of the multilayer substrate. The surface mount structure also includes one or more dielectric materials positioned between the dielectric layer and the first surface of the multilayer substrate structure and at least partially surrounding the at least one semiconductor device of the submodule, the one or more dielectric materials being configured to fill gaps in the surface mount structure and provide additional structural integrity thereto.

[0079] According to another embodiment of the present invention, a method for manufacturing a surface mount package and interconnect structure includes the steps of forming a submodule, the submodule including at least one semiconductor device and a package structure formed thereabout, wherein the step of forming the submodule further includes: attaching the at least one semiconductor device to a dielectric layer; forming a first level metal interconnect structure above the dielectric layer, which extends through a through hole in the dielectric layer to electrically connect to the at least one semiconductor device; and forming a second level input / output (I / O) connection on the dielectric layer on a side opposite to the at least one semiconductor device, wherein the second level I / O connection is configured to connect the submodule to an external circuit. The method also includes the steps of forming a substrate structure, the substrate structure including a central substrate layer and first and second metal layers located on opposite sides of the central substrate layer, so that the first and second metal layers form a first surface and a second surface of the substrate structure, respectively. The method also includes the steps of attaching the submodule to the first surface of the substrate structure and providing a dielectric fill material between the dielectric layer and the first surface of the substrate structure, the dielectric fill material at least partially encapsulating the at least one semiconductor device of the submodule.

[0080] According to another embodiment of the present invention, a power overlay (POL) package structure includes a POL submodule, the POL submodule having: a dielectric layer; a plurality of semiconductor devices attached to the dielectric layer; a primary interconnect structure electrically connected to the plurality of semiconductor devices and extending through a through hole formed through the dielectric layer so as to be connected to the plurality of semiconductor devices; and a secondary interconnect structure for electrically connecting the POL submodule to an external circuit structure, wherein the secondary interconnect structure includes a plurality of solder bumps formed over the dielectric layer and the primary interconnect structure and configured to establish interconnections to the external circuit structure. The POL package structure also includes a multilayer substrate structure having a first surface and a second surface, wherein the plurality of semiconductor devices of the POL submodule are attached to the first surface of the multilayer substrate structure. The multilayer substrate structure of the POL package structure also includes a first direct bonded copper (DBC) layer forming the first surface of the multilayer substrate structure, a second DBC layer forming the second surface of the multilayer substrate structure, and a ceramic layer sandwiched between the first and second DBC layers. The POL package structure also includes an encapsulant positioned between the dielectric layer and the first surface of the multilayer substrate structure and at least partially surrounding the plurality of semiconductor devices of the submodule.

[0081] Although the present invention has been described in detail in conjunction with only a limited number of embodiments, it should be readily understood that the present invention is not limited to such disclosed embodiments. Rather, the present invention may be modified to incorporate any number of variations, alterations, substitutions, or equivalent arrangements not previously described but commensurate with the spirit and scope of the present invention. Furthermore, although various embodiments of the present invention have been described, it should be understood that aspects of the present invention may include only some of the described embodiments. Therefore, the present invention should not be considered to be limited by the foregoing description, but only by the scope of the appended claims.

Claims

1. A power covering packaging structure, comprising: A power coverage submodule, the power coverage submodule comprising: Dielectric layer; a plurality of semiconductor devices attached to the dielectric layer; a first level interconnect structure electrically coupled to the plurality of semiconductor devices, the first level interconnect structure extending through vias formed through the dielectric layer so as to connect to the plurality of semiconductor devices; and a second level interconnect structure to electrically couple the power cover submodule to an external circuit structure, the second level interconnect structure comprising a plurality of solder bumps formed over the dielectric layer and the first level interconnect structure and configured to establish interconnections to the external circuit structure; A multi-layer substrate structure having a first surface and a second surface, wherein a plurality of semiconductor devices of the power cover submodule are attached to the first surface of the multi-layer substrate structure, and wherein the multi-layer substrate structure comprises: forming a first direct copper cladding layer on a first surface of the multi-layer substrate structure; forming a second direct copper coating layer on a second surface of the multi-layer substrate structure; and a ceramic layer sandwiched between the first direct copper cladding layer and the second direct copper cladding layer; and a dielectric fill material positioned between the dielectric layer and the first surface of the multi-layer substrate structure and at least partially surrounding at least one semiconductor device of the submodule, The second direct copper cladding layer has a larger volume than the first direct copper cladding layer, and the volume ratio between the second direct copper cladding layer and the first direct copper cladding layer provides a stress-balanced surface mount package and an interconnect structure with reduced warpage and thermal stress.

2. The power covering packaging structure according to claim 1, The volume of the second direct copper clad layer is determined based on the thickness and material properties of the dielectric filling material, the density, thickness and spacing of the multiple semiconductor devices, and at least one of the thickness and material properties of the ceramic layer, wherein the material properties of the dielectric filling material and the ceramic layer include at least one of elastic modulus, coefficient of thermal expansion (CTE), fracture stress and toughness.

3. The power covering package structure according to claim 2, wherein: The volume imbalance between the first direct copper layer and the second direct copper layer is between 1 and 2.

5.

4. The power covering package structure according to claim 1, wherein: The dielectric filling material includes an underfill material, a sealant, a silicone or a molding compound, or a combination of a ceramic or dielectric sheet and a dielectric filling material.

5. The power covering packaging structure according to claim 1, characterized in that: The first direct copper coating layer includes a patterned direct copper coating layer, and the second direct copper coating layer includes a patterned or unpatterned direct copper coating layer.

6. The power covering packaging structure according to claim 1, characterized in that: The solder bump includes one of a land grid array (LGA) solder bump and a ball grid array (BGA) solder bump.

7. The power covering packaging structure according to claim 6, characterized in that: The power cover package structure also includes one of a solder material, a conductive adhesive, or a sintered metal joint positioned between the multi-layer substrate structure and the power cover sub-module to secure the power cover sub-module to the multi-layer substrate structure.

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