A high-speed switching circuit that eliminates parasitic capacitance of electrostatic discharge devices

Abstract

The present invention discloses a high-speed switching circuit for eliminating parasitic capacitance of an electrostatic discharge device, comprising: a first switching tube, a second switching tube, a first protective tube, and a second protective tube; the first switching tube and the second switching tube are connected in parallel, the first protective tube is arranged at a body region node of the first switching tube, the second protective tube is arranged at a body region node of the second switching tube, and the first protective tube and the second protective tube are connected; the present invention completely eliminates the parasitic capacitance to ground caused by the electrostatic discharge device part, thereby greatly reducing the attenuation of high-frequency signal transmission.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuit devices, and more particularly to a high-speed switching circuit for eliminating parasitic capacitance of an electrostatic discharge device. Background Art

[0002] Currently, high-speed switch integrated circuits (ICs) are widely used in mobile portable devices, such as mobile industry processor interface switches, USB 2.0, USB 3.0 switches, and the like.

[0003] However, the electrostatic discharge device protection solution for high-speed switch channels is usually a diode protection solution. For the protection solution of the prior art, see the attached Figure 1 As shown, 1 is the input node of the high-speed switch, 2 is the output node, 5 is the NMOS switch tube, 6 is the PMOS switch tube connected in parallel with the NMOS switch tube 5, and their source and drain terminals are connected to the circuit nodes 1 and 2 respectively. 3 is the electrostatic discharge device protection device at the input terminal, 4 is the electrostatic discharge device protection device at the output terminal, 7 and 8 are the parasitic diodes from the NMOS source and drain terminals to the NMOS body terminal, and 9 is the NMOS body terminal node. 10 and 11 are the parasitic diodes from the NMOS source and drain terminals to the PMOS body terminal, and 12 is the PMOS body terminal node. When working normally, the high-speed signal passes through Figure 1 When the switch path is switched, the path from the input node to the output node will directly generate the parasitic capacitance of the switch tube to the ground and the additional parasitic capacitance of the electrostatic discharge device protection device 3 and 4, thereby affecting the overall performance of the circuit.

[0004] Therefore, how to provide a high-speed switching circuit that can completely eliminate the parasitic capacitance of the electrostatic discharge device is a problem that those skilled in the art urgently need to solve. Summary of the Invention

[0005] In view of this, the present invention provides a high-speed switching circuit that eliminates the parasitic capacitance of the electrostatic discharge device, so that the parasitic capacitance of the electrostatic discharge device is completely invisible to the input and output pins of the high-speed channel, and the parasitic capacitance to the ground caused by the electrostatic discharge device is completely eliminated, thereby greatly reducing the attenuation of high-frequency signal transmission and improving the bandwidth of the high-speed switch.

[0006] In order to achieve the above object, the present invention adopts the following technical solutions:

[0007] A high-speed switching circuit for eliminating parasitic capacitance of an electrostatic discharge device, comprising: a first switching tube, a second switching tube, a first protection tube, and a second protection tube;

[0008] The first switching tube and the second switching tube are connected in parallel, the first protection tube is set at the body node of the first switching tube, the second protection tube is set at the body node of the second switching tube, and the first protection tube is connected to the second protection tube.

[0009] The beneficial effects of using the above device are: a first protection tube is added to the body node of the first switching tube, and a second protection tube is added to the body node of the second switching tube; when the circuit is operating normally, the parasitic capacitance caused by the additional protection devices is eliminated on the path of the high-speed signal from the input node to the output node.

[0010] Preferably, it also includes: a first parasitic transistor and a second parasitic transistor, which are located between the source and body region nodes and between the drain and body region nodes of the first switching transistor, and are parasitic diodes between the source and body region and between the drain and body region of the first switching transistor itself.

[0011] Preferably, it also includes: a third parasitic transistor and a fourth parasitic transistor, which are located between the source and body region nodes and between the drain and body region nodes of the second switch tube, and are parasitic diodes between the source and body region and between the drain and body region of the second switch tube itself.

[0012] Through the above technical solution, it can be seen that compared with the prior art, the present invention discloses a high-speed switching circuit that eliminates the parasitic capacitance of the electrostatic discharge device. By utilizing the inherent body region and source, as well as the parasitic diodes between the body region and the drain of the switch, an electrostatic discharge device protection device is added to the body region, so that the input node and the output node on the high-speed channel do not need to be directly connected to any electrostatic discharge device tube, and bidirectional protection can be achieved. The additional electrostatic discharge device parasitic capacitance is eliminated at both the input and output ends. Since the electrostatic discharge device capacitance is one of the main factors affecting the bandwidth of the high-speed switch, the parasitic capacitance of the switch channel to the ground can be greatly reduced, thereby effectively improving the signal bandwidth of the channel without increasing the process and circuit difficulty. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0014] Figure 1 The accompanying drawing is a protection circuit diagram of the prior art in the present invention;

[0015] Figure 2 The accompanying drawing is a schematic diagram of a high-speed switching circuit for eliminating parasitic capacitance of an electrostatic discharge device provided by the present invention. DETAILED DESCRIPTION

[0016] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0017] Example 1

[0018] See attached Figure 2 As shown, embodiment 1 of the present invention discloses a high-speed switch circuit for eliminating parasitic capacitance of an electrostatic discharge device, wherein 1 is an input node of the high-speed switch, 2 is an output node, and specifically includes: a first switch tube 5, a second switch tube 6, a first protection tube 14, and a second protection tube 13. The first switch tube 5 can be an NMOS switch tube, the second switch tube 6 can be a PMOS switch tube, 9 can be an NMOS body region node, and 12 can be a PMOS body region node;

[0019] The first switching transistor 5 and the second switching transistor 6 are connected in parallel, specifically, the source of the first switching transistor 5 is connected to the drain of the second switching transistor 6, and the drain of the first switching transistor 5 is connected to the source of the second switching transistor 6; one end of the first protection transistor 14 is set on the body region node 9 of the first switching transistor 5, one end of the second protection transistor 13 is set on the body region node 12 of the second switching transistor, and the other end of the first protection transistor 14 is connected to the other end of the second protection transistor 13.

[0020] Specifically, the other end of the first protection tube 14 is grounded, and the other end of the second protection tube 13 is also connected to a power supply voltage.

[0021] Specifically, the second protection tube 13 can also be one or more ESD protection tubes connected in series in the same direction, with the positive electrode of the ESD protection tube connected to the body node 12 of the second switch tube 6 and the cathode connected to the power supply voltage.

[0022] Specifically, the first protection tube 14 can also be an ESD protection tube with a forward diode or multiple forward diodes connected in series, and the connection mode is that the anode of the ESD protection tube is connected to the body node 9 of the first switch tube 5 and the cathode is grounded.

[0023] Specifically, a power-to-ground ESD clamping tube may be provided between the other end of the first protection tube 14 and the other end of the second protection tube 13 to protect the circuit.

[0024] In a specific embodiment, it also includes: a gate control circuit 15, one end of the gate control circuit 15 is connected to the gate of the first switch tube 5, and the other end is connected to the gate of the second switch tube 6, and the gate control circuit 15 is used to control the opening and closing of the N-type and P-type switch tubes.

[0025] In a specific embodiment, it further includes: a first parasitic transistor 7 and a second parasitic transistor 8, which are arranged between the source and the drain of the first switching transistor 5. The specific connection method is: the cathode of the first parasitic transistor 7 is connected to the source of the first switching transistor 5, the anode of the first parasitic transistor 7 is connected to the positive electrode of the second parasitic transistor 8, and the cathode of the second parasitic transistor 8 is connected to the drain of the first switching transistor 5.

[0026] In a specific embodiment, the device further includes: a third parasitic transistor 10 and a fourth parasitic transistor 11. The third parasitic transistor 10 and the fourth parasitic transistor 11 are arranged between the drain and the source of the second switch transistor 6. The specific connection method is: the positive electrode of the third parasitic transistor 10 is connected to the drain of the second switch transistor 6, the negative electrode of the third parasitic transistor 10 is connected to the negative electrode of the fourth parasitic transistor 11, and the positive electrode of the fourth parasitic transistor 11 is connected to the source of the second switch transistor 6.

[0027] In a specific embodiment, it further includes: a first switch tube body region bias circuit 16, which is arranged on the body region node 9 of the first switch tube 5, wherein the first switch tube body region bias circuit 16 can specifically be an N-type switch tube body region bias circuit.

[0028] In a specific embodiment, it further includes: a second switch tube body region bias circuit 17, which is arranged on the body region node 12 of the second switch tube 6, wherein the first switch tube body region bias circuit 17 can specifically be a P-type switch tube body region bias circuit, and the body region bias circuit provides a body region bias voltage according to the input and output signal potential.

[0029] Specifically, the gate control circuit 15 , the first switch tube body region bias circuit 16 , and the second switch tube body region bias circuit 17 are all common circuits in the prior art.

[0030] When the high-speed switching circuit disclosed in the present invention is used to eliminate the parasitic capacitance of the electrostatic discharge device, the ESD discharge path of its output or output pin to the ground flows as follows: Since the source and drain regions of the first switching tube 5 have a reverse-biased PN junction with its own body region, when one or more protection tubes equivalent to reverse-biased diode protection are connected in series between the body region P well and the ground, it is equivalent to having an ESD unidirectional discharge path composed of series diodes between the substrate ground and the source and drain. When a negative ESD occurs between the input or output pin and the ground, the ESD discharge current will first flow from the ground through the first protection tube 14 between the body region of the first switching tube 5 and the ground to the body region node 9, and then flow through the first parasitic tube 7 between the body region and the drain or source to the input pin 1. Since the entire discharge path is a series of forward-biased diodes, the conduction voltage drop is also very low, so its ESD discharge capability is also very strong, and effective negative ESD protection to the ground can be achieved.

[0031] The forward ESD current discharge path from the input or output pin to the ground is a dotted line starting from the input terminal 1. When a forward ESD occurs from the input pin to the ground, the ESD discharge current will first flow from the input pin 1 through the source or drain in the second switching tube 6 and the parasitic forward-biased PN junction of the body region, the third parasitic tube 10, to the body region 12, and then from the body region through the second protection tube 13 between the body region and the power supply added by this patent to the power supply, and finally flow from the ESD protection tube from the power supply to the ground to the ground.

[0032] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Reference can be made to the common and similar parts between the various embodiments. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the method description.

[0033] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A high-speed switching circuit for eliminating parasitic capacitance of an electrostatic discharge device, characterized in that: include: a first switching tube, a second switching tube, a first protection tube, and a second protection tube; The first switching transistor and the second switching transistor are connected in parallel, the first protection transistor is arranged at a body region node of the first switching transistor, the second protection transistor is arranged at a body region node of the second switching transistor, and the first protection transistor is connected to the second protection transistor; It also includes: a first switch tube body region bias circuit, wherein the first switch tube body region bias circuit is arranged on the body region node of the first switch tube.

2. A high-speed switching circuit for eliminating parasitic capacitance of an electrostatic discharge device according to claim 1, characterized in that: Also includes: A first parasitic transistor and a second parasitic transistor are located between the source and the body node and between the drain and the body node of the first switch transistor.

3. The high-speed switching circuit for eliminating parasitic capacitance of an electrostatic discharge device according to claim 1, characterized in that: Also includes: The third parasitic transistor and the fourth parasitic transistor are located between the source and the body node and between the drain and the body node of the second switch transistor.

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