Method for manufacturing semiconductor integrated circuit

Abstract

The present invention provides a method for manufacturing a semiconductor integrated circuit. The method for manufacturing a semiconductor integrated circuit comprises the following steps: ‑ A portion of an upper portion of a semiconductor layer (12) of the type is multi-stage injected with p-type impurity ions by changing the injection position to form a first ion injection region; another portion of the upper portion is multi-stage injected with p-type impurity ions by changing the injection position to form a second ion injection region; the impurity ions in the first ion injection region are activated to form a well region (22, 23) of the second conductivity type, and the impurity ions in the second ion injection region are activated to form a p-type body region (13); a n-type body region is formed on the upper portion of the well region (22); + A control element (201) having a first terminal region and a second terminal region (25a, 25b) of the type; and a control element (201) having an n-type first terminal region and a second terminal region (25a, 25b) formed on the upper portion of the body region (13) + An output stage element (101) having an output terminal area (15a, 15b) of a type and controlled by a control element (201).

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly to a method for manufacturing a power semiconductor integrated circuit (power IC) in which a vertical power semiconductor element of an output stage and a lateral semiconductor element (control element) for controlling the power semiconductor element are monolithically integrated into the same semiconductor chip. Background Art

[0002] A power IC is proposed in which a vertical MOSFET of an output stage and a lateral MOSFET for controlling the vertical MOSFET are monolithically integrated (hybridly mounted) on the same semiconductor chip (see patent documents 1 to 3). In the manufacturing method of the power IC described in patent documents 1 to 3, after impurity ions are injected into the surface of the semiconductor substrate, a high-temperature and long-term heat treatment is performed to form a body region for forming a vertical output stage element. In addition, after impurity ions are injected into a specified position on the surface of the semiconductor substrate, a high-temperature and long-term heat treatment is performed to form a well region for forming a lateral control element. Since high-temperature and long-term heat treatment is performed multiple times in this way, the manufacturing time is long. In addition, multiple heat treatments cause deviations in the impurity concentration of the diffusion layer and deviations in the device characteristics.

[0003] Patent documents 4 to 6 propose a technology for forming a diffusion layer associated with a vertical output stage element and a lateral control element without relying on high temperature and long time heat treatment. Patent documents 4 and 5 disclose a technology for forming a body region of a trench MOSFET using an ion implantation device with a high acceleration voltage. Patent document 6 discloses a technology related to a method for forming a separation diffusion layer that suppresses the amount of heat treatment and prevents impurities from excessively diffusing.

[0004] However, Patent Documents 1 to 6 do not disclose improving the integration density of a semiconductor integrated circuit in which vertical output stage elements and lateral control elements are integrated into the same semiconductor chip, or shortening the manufacturing time.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent Application Publication No. 2000-91344

[0008] Patent Document 2: Japanese Patent No. 5641131

[0009] Patent Document 3: Japanese Patent No. 6037085

[0010] Patent Document 4: Japanese Patent Application Publication No. 2006-80177

[0011] Patent Document 5: Japanese Patent Application Publication No. 2001-339063

[0012] Patent Document 6: Japanese Patent Application Publication No. 2012-80117 Summary of the invention

[0013] Problem that the invention aims to solve

[0014] In view of the above problems, an object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit having a high integration density structure with improved electrical characteristics and high area utilization efficiency, which can be manufactured in a short time.

[0015] Solutions for solving problems

[0016] The purpose of one embodiment of the present invention is a method for manufacturing a semiconductor integrated circuit, comprising the following steps: (a) multi-stage injection of impurity ions of a second conductivity type into a portion of an upper portion of a semiconductor layer of a first conductivity type by changing the injection position, thereby selectively forming a first ion injection region; (b) multi-stage injection of impurity ions of the second conductivity type into another portion of the upper portion of the semiconductor layer by changing the injection position, thereby selectively forming a second ion injection region; (c) activating the impurity ions in the first ion injection region to form a well region of the second conductivity type, and at the same time activating the impurity ions in the second ion injection region to form a body region of the second conductivity type; (d) forming a control element having a first terminal region and a second terminal region of the first conductivity type facing each other in the upper portion of the well region; and (e) forming an output stage element having an output terminal region of the first conductivity type and controlled by the control element in the upper portion of the body region.

[0017] Effects of the Invention

[0018] According to the present invention, it is possible to provide a method for manufacturing a semiconductor integrated circuit having a high integration density structure with improved electrical characteristics and high area utilization efficiency, which can be manufactured in a short time. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a cross-sectional view of a main part showing an example of a semiconductor integrated circuit according to an embodiment of the present invention.

[0020] Figure 2 1 is an equivalent circuit diagram showing an example of a semiconductor integrated circuit according to an embodiment of the present invention.

[0021] Figure 3 The present invention is a process cross-sectional view showing an example of a method for manufacturing a semiconductor integrated circuit according to an embodiment of the present invention.

[0022] Figure 4 Then Figure 3 1 is a cross-sectional view showing a process of an example of a method for manufacturing a semiconductor integrated circuit according to an embodiment of the present invention.

[0023] Figure 5 Then Figure 4 1 is a cross-sectional view showing a process of an example of a method for manufacturing a semiconductor integrated circuit according to an embodiment of the present invention.

[0024] Figure 6 Then Figure 5 1 is a cross-sectional view showing a process of an example of a method for manufacturing a semiconductor integrated circuit according to an embodiment of the present invention.

[0025] Figure 7 Then Figure 6 1 is a cross-sectional view showing a process of an example of a method for manufacturing a semiconductor integrated circuit according to an embodiment of the present invention.

[0026] Figure 8 Then Figure 7 1 is a cross-sectional view showing a process of an example of a method for manufacturing a semiconductor integrated circuit according to an embodiment of the present invention.

[0027] Fig. 9A Then Figure 8 1 is a cross-sectional view showing a process of an example of a method for manufacturing a semiconductor integrated circuit according to an embodiment of the present invention.

[0028] Fig. 9B This is a graph showing the impurity concentration distribution in the depth direction from the surface of a lateral semiconductor device constituting a control element according to an embodiment of the present invention.

[0029] Fig.10 Then Fig. 9A 1 is a cross-sectional view showing a process of an example of a method for manufacturing a semiconductor integrated circuit according to an embodiment of the present invention.

[0030] Fig.11 Then Fig.10 1 is a cross-sectional view showing a process of an example of a method for manufacturing a semiconductor integrated circuit according to an embodiment of the present invention.

[0031] Fig.12 Then Fig.11 1 is a cross-sectional view showing a process of an example of a method for manufacturing a semiconductor integrated circuit according to an embodiment of the present invention.

[0032] Fig.13 Then Fig.12 1 is a cross-sectional view showing a process of an example of a method for manufacturing a semiconductor integrated circuit according to an embodiment of the present invention.

[0033] Fig.14 Then Fig.13 1 is a cross-sectional view showing a process of an example of a method for manufacturing a semiconductor integrated circuit according to an embodiment of the present invention.

[0034] Fig.15 Then Fig.14 1 is a cross-sectional view showing a process of an example of a method for manufacturing a semiconductor integrated circuit according to an embodiment of the present invention.

[0035] Fig.16 Then Fig.15 1 is a cross-sectional view showing a process of an example of a method for manufacturing a semiconductor integrated circuit according to an embodiment of the present invention.

[0036] Fig.17 Then Fig.16 1 is a cross-sectional view showing a process of an example of a method for manufacturing a semiconductor integrated circuit according to an embodiment of the present invention.

[0037] Fig.18 It is a cross-sectional view showing a main part of a semiconductor integrated circuit according to a comparative example.

[0038] Fig.19 The diagram is a cross-sectional view showing the steps of a method for manufacturing a semiconductor integrated circuit according to a comparative example.

[0039] Fig. 20 Then Fig.19 4 is a cross-sectional view showing a process of a method for manufacturing a semiconductor integrated circuit according to a comparative example.

[0040] Fig.21 Then Fig. 20 4 is a cross-sectional view showing a process of a method for manufacturing a semiconductor integrated circuit according to a comparative example.

[0041] Fig. 22 Then Fig.21 4 is a cross-sectional view showing a process of a method for manufacturing a semiconductor integrated circuit according to a comparative example.

[0042] Fig.23 Then Fig. 22 4 is a cross-sectional view showing a process of a method for manufacturing a semiconductor integrated circuit according to a comparative example.

[0043] Fig.24 Then Fig.23 4 is a cross-sectional view showing a process of a method for manufacturing a semiconductor integrated circuit according to a comparative example.

[0044] Fig.25 Then Fig.24 4 is a cross-sectional view showing a process of a method for manufacturing a semiconductor integrated circuit according to a comparative example.

[0045] Fig.26 Then Fig.25 4 is a cross-sectional view showing a process of a method for manufacturing a semiconductor integrated circuit according to a comparative example.

[0046] Fig. 27 The diagram is a cross-sectional view showing a process step of an example of a method for manufacturing a semiconductor integrated circuit according to a first modified example of the embodiment of the present invention.

[0047] Fig.28 Then Fig. 27 1 is a cross-sectional view showing a process of an example of a method for manufacturing a semiconductor integrated circuit according to a first variation of an embodiment of the present invention.

[0048] Fig.29 The diagram is a cross-sectional view showing a process step of an example of a method for manufacturing a semiconductor integrated circuit according to a second modification example of the embodiment of the present invention.

[0049] Fig.30 Then Fig.29 2 is a cross-sectional view showing a process of an example of a method for manufacturing a semiconductor integrated circuit according to a second modification example of an embodiment of the present invention.

[0050] Fig.31 Then Fig.30 2 is a cross-sectional view showing a process of an example of a method for manufacturing a semiconductor integrated circuit according to a second modification example of an embodiment of the present invention.

[0051] Fig.32 The diagram is a cross-sectional view showing a process step of an example of a method for manufacturing a semiconductor integrated circuit according to a third modified example of the embodiment of the present invention.

[0052] Fig.33 The fourth embodiment of the present invention is a process cross-sectional view showing an example of a method for manufacturing a semiconductor integrated circuit according to a fourth modification example of the embodiment of the present invention.

[0053] Fig.34 Then Fig.33 4 is a cross-sectional view showing a process step of an example of a method for manufacturing a semiconductor integrated circuit according to a fourth modified example of an embodiment of the present invention.

[0054] Fig.35 Then Fig.34 4 is a cross-sectional view showing a process step of an example of a method for manufacturing a semiconductor integrated circuit according to a fourth modified example of an embodiment of the present invention.

[0055] Fig.36 Then Fig.35 4 is a cross-sectional view showing a process step of an example of a method for manufacturing a semiconductor integrated circuit according to a fourth modified example of an embodiment of the present invention.

[0056] Fig.37 The diagram is a cross-sectional view showing a process step of an example of a method for manufacturing a semiconductor integrated circuit according to a fifth modification example of the embodiment of the present invention.

[0057] Fig.38 Then Fig.37 4 is a cross-sectional view showing a process step of an example of a method for manufacturing a semiconductor integrated circuit according to a fifth modification example of an embodiment of the present invention.

[0058] Fig.39 Then Fig.38 4 is a cross-sectional view showing a process of an example of a method for manufacturing a semiconductor integrated circuit according to a fifth variation of the embodiment of the present invention.

[0059] Fig.40 Then Fig.39 4 is a cross-sectional view showing a process of an example of a method for manufacturing a semiconductor integrated circuit according to a fifth variation of the embodiment of the present invention.

[0060] Fig.41 Then Fig.40 4 is a cross-sectional view showing a process of an example of a method for manufacturing a semiconductor integrated circuit according to a fifth variation of the embodiment of the present invention.

[0061] Description of Reference Numerals

[0062] 10: back electrode; 11: back contact layer; 12: semiconductor layer; 13, 13x: body region; 13a, 13b: second ion implantation region; 15a, 15b: main electrode region; 16: base contact region; 17a, 17b: trench; 17c, 17d: element separation groove; 18, 27: gate insulating film; 18p, 18q: element separation insulating film; 19a, 19b, 28: gate electrode; 19p, 19q: dummy electrode; 20: interlayer insulating film; 21: output terminal wiring; 22, 22x: first well region; 22a, 22b, 22c, 22d, 22e, 23a, 23b, 23q 3c: first ion implantation region; 23, 23x: second well region; 25a: first terminal region; 25b: second terminal region; 30: field oxide film; 31: first circuit terminal wiring; 32: second circuit terminal wiring; 34, 43, 44, 47, 50, 51, 52, 53, 54, 55, 56, 59, 60: photoresist film; 41, 48, 57, 58: etching protection film; 42, 42a, 42b, 49: oxidation-resistant film (silicon nitride film); 45, 46: mask for selective ion implantation; 100: output section; 101: output stage element; 200: circuit section; 201: control element. DETAILED DESCRIPTION

[0063] The following is an explanation of the embodiments of the present invention with reference to the accompanying drawings. In the description of the accompanying drawings referred to in the following description, the same or similar parts are marked with the same or similar symbols. However, it should be noted that the accompanying drawings are schematic, and the relationship between thickness and plane size, the ratio of thickness of each layer, etc. are different from the actual situation. Therefore, the specific thickness and size should be determined with reference to the following description. In addition, it goes without saying that the drawings also include parts with different size relationships and ratios.

[0064] In the semiconductor integrated circuit involved in the embodiment of the present invention, various semiconductor elements are monolithically integrated on the same semiconductor chip. In the embodiment of the present invention, regarding the "first terminal area" and "second terminal area" of the control element (semiconductor element) integrated in the circuit part, when the integrated semiconductor element is a field effect transistor (FET) or a static induction transistor (SIT), it refers to a semiconductor area that becomes either the source area or the drain area for the main current to flow in or out. In the case of a semiconductor element with a symmetrical structure such as MISFET, it is sometimes possible to exchange the function of the "first terminal area" and the function of the "second terminal area" by exchanging the bias relationship.

[0065] In this specification, the terms "first main electrode region" and "second main electrode region" are used for output-stage elements. The relationship between the "first main electrode region" and the "second main electrode region" is the same as the relationship between the "first terminal region" and the "second terminal region" described above, and they are main electrode regions for the main current to flow in or out of the output-stage element (semiconductor element). When the semiconductor element integrated as the output-stage element is an insulated gate bipolar transistor (IGBT), the "first main electrode region" refers to a semiconductor region that becomes either the emitter region or the collector region. In addition, when the integrated output-stage element is an electrostatic induction thyristor (SI thyristor) or a gate turn-off thyristor (GTO), the "first main electrode region" refers to a semiconductor region that becomes either the anode region or the cathode region. Regarding the "second main electrode region", if the integrated output-stage element is a FET or a SIT, it refers to a semiconductor region that becomes either the source region or the drain region and does not become either the first main electrode region described above. In an IGBT, it refers to a region that becomes either the emitter region or the collector region and does not become either the first main electrode region described above. In the SI thyristor and the GTO, it refers to a region that serves as an anode region or a cathode region but does not serve as the first main electrode region.

[0066] Like this, if the "first main electrode region" of the output-stage element integrated in the semiconductor chip is the source region, the "second main electrode region" refers to the drain region. If the "first main electrode region" is the emitter region, the "second main electrode region" refers to the collector region. If the "first main electrode region" is the anode region, the "second main electrode region" refers to the cathode region. In addition, in this specification, when it is recorded only as "main electrode region", it generally refers to either the first main electrode region or the second main electrode region, which is technically and logically appropriate.

[0067] In addition, the definitions of up and down directions in the following description are only for convenience of explanation and are not intended to limit the technical concept of the present invention. For example, if the object is rotated 90° to observe, up and down are converted to left and right to read, and if it is rotated 180° to observe, up and down are reversed to read, which is self-evident.

[0068] In addition, in the following description, the case where the first conductivity type is n-type and the second conductivity type is p-type is exemplified. However, the conductivity type can also be selected to be in an opposite relationship, with the first conductivity type being set to p-type and the second conductivity type being set to n-type. In addition, the "+" and "-" attached to "n" and "p" respectively refer to semiconductor regions with relatively high or relatively low impurity concentrations compared to semiconductor regions without "+" and "-". However, in the representation of the accompanying drawings, even if the semiconductor regions are marked with the same "n" and "n", it does not mean that the impurity concentrations of the respective semiconductor regions are strictly the same.

[0069] <Semiconductor Integrated Circuits>

[0070] As an example of a semiconductor integrated circuit according to an embodiment of the present invention, a high-side power IC is described. Figure 1 As exemplarily shown, the power IC is one in which the output unit 100 and the circuit unit 200 are monolithically integrated on the right and left sides of the same semiconductor chip.

[0071] The output section 100 has an output stage element 101 which is a vertical power semiconductor element. In the semiconductor integrated circuit involved in the embodiment of the present invention, for convenience, the case where the output stage element 101 is a trench gate type vertical nMOSFET is exemplified. In the output stage element 101, the main current flows between the first main electrode region (source region) 15a, 15b on the upper surface (front) side and the second main electrode region (drain region) on the lower surface (back) side via the semiconductor region that becomes the channel. Therefore, the back contact layer 11 functions as a drain region (second main electrode region), and the semiconductor layer 12 functions as a drift layer. A back electrode 10 that becomes a drain electrode is arranged on the back side of the back contact layer 11, and the back electrode 10 is connected to the power supply voltage terminal.

[0072] In the semiconductor integrated circuit according to the embodiment of the present invention, the semiconductor substrate (11, 12) constituting the semiconductor chip is described as an example in which the semiconductor material composed of silicon (Si) is used as the base material, but the base material is not limited to Si. Figure 1 In the embodiment, the semiconductor substrate (11, 12) is exemplified by a structure in which a semiconductor layer 12 is epitaxially grown on a back contact layer 11, wherein the back contact layer 11 is composed of a first conductivity type (n + The semiconductor layer 12 is a first conductivity type (n - Alternatively, the semiconductor layer 12 may be formed by ion implantation or thermal diffusion. - The back side of the semiconductor substrate (Si wafer) is formed by n + A back contact layer 11 is formed of a diffusion layer of the type, thereby forming a semiconductor substrate (11, 12).

[0073] When the semiconductor substrate is used as the back contact layer 11, the impurity concentration of the back contact layer 11 is, for example, 2×10 18 cm -3 ~1×10 19 cm -3 In this case, the impurity concentration of the semiconductor layer 12 can be selected to be, for example, 1×10 12 cm -3 ~1×10 16 cm -3 About, here for example 1×10 15 cm -3 ~1×10 16 cm -3 Around. - The back side of the semiconductor layer 12 formed of a semiconductor substrate of type n + When the back contact layer 11 is formed of a diffusion layer of the type, the impurity concentration of the back contact layer 11 can be set to 5×10 18 cm -3 ~1×10 21 cm -3 In addition, the impurity concentration of the back contact layer 11 may not be constant, and may be as high as 1×10 21 cm -3 For example, the semiconductor layer 12 side may have a high impurity concentration of 5×10 18 cm -3 ~2×1019 cm -3 The left and right layers are 3×10 19 cm -3 ~1×10 21 cm -3 Composite structure of left and right layers.

[0074] In the output portion 100, a body region (base region) 13 of the second conductivity type (p-type) is provided on the upper portion of the semiconductor layer 12. The body region 13 of the semiconductor integrated circuit according to the embodiment of the present invention is formed by multi-stage ion implantation with different acceleration voltages and a short-time heat treatment. By appropriately adjusting the number of ion implantations and the acceleration voltage in the multi-stage implantation, it is possible to achieve a doping distribution that matches the required performance in the depth direction of the body region 13, such as a step-shaped doping distribution, a distribution in which the impurity concentration in the deep part is higher than that in the shallow part (flip-chip well), a distribution close to a Gaussian distribution shape, etc.

[0075] In the upper part of the body region 13, n-type semiconductor layers having an impurity concentration higher than that of the semiconductor layer 12 are selectively provided in pairs. + In the upper part of the body region 13, between the paired first main electrode regions 15a and 15b, a p-type first main electrode region 15a and 15b is selectively provided in a manner of contacting the first main electrode regions 15a and 15b. + The base contact region 16 of the type is formed. Output terminal wiring (source electrode wiring) 21 is arranged on the base contact region 16 and the first main electrode regions 15a and 15b, and the output terminal wiring 21 is connected to the output terminal. Therefore, in the semiconductor integrated circuit involved in the embodiment of the present invention, the first main electrode regions 15a and 15b are defined as "output terminal regions".

[0076] A pair of trenches 17a and 17b are provided, which are dug from the upper surface of the semiconductor layer 12, at least a portion of the side surface is in contact with the body region 13 and are deeper than the body region 13. In each of the paired trenches 17a and 17b, gate electrodes 19a and 19b are embedded via a gate insulating film 18 provided along the inner surface of the trenches 17a and 17b, thereby forming a trench-type control electrode structure (18, 19a, 19b).

[0077] As the gate insulating film 18, for example, a SiO2 film or the like can be used, but in addition to the SiO2 film, a silicon oxynitride (SiON) film, a strontium oxide (SrO) film, a silicon nitride (Si3N4) film, or an aluminum oxide (Al2O3) film can also be used. Alternatively, a magnesium oxide (MgO) film, an yttrium oxide (Y2O3) film, a hafnium oxide (HfO2) film, a zirconium oxide (ZrO2) film, a tantalum oxide (Ta2O5) film, or a bismuth oxide (Bi2O3) film can also be used. Furthermore, several single-layer films can be selected from these single-layer films, and a composite film formed by stacking multiple single-layer films can be used.

[0078] The gate electrodes 19a and 19b electrostatically control the surface potential (Japanese: surface potential) of the semiconductor region on the side of the body region 13 near the grooves 17a and 17b through the gate insulating film 18, thereby forming an inversion channel on the side of the body region 13 near the grooves 17a and 17b. As the material of the gate electrodes 19a and 19b, for example, polysilicon (doped polysilicon) into which a high concentration of n-type impurities is introduced can be used, but in addition to doped polysilicon (DOPOS), high melting point metals such as tungsten (W), molybdenum (Mo), titanium (Ti), or silicides of high melting point metals and polysilicon can also be used. In addition, the material of the gate electrodes 19a and 19b can also be a composite film of polysilicon and silicide of high melting point metal, that is, polysilicon-metal silicide (polycide).

[0079] An interlayer insulating film 20 is disposed on the gate electrodes 19a and 19b. For example, a silicon oxide film (BPSG film) to which phosphorus and boron are added can be used as the interlayer insulating film 20. The trenches 17a and 17b may be a single trench having a ring-shaped planar shape.

[0080] On the other hand, the circuit unit 200 includes a control element 201 for controlling the output stage element 101. The control element 201 is a lateral nMOSFET, and may also be a pMOSFET (not shown) or a complementary MOS (CMOS). The control element 201 is provided in a second conductivity type (p-type) region (first well region) 22 provided on the upper portion of the semiconductor layer 12.

[0081] A well region (second well region) 23 of a second conductivity type (p-type) is provided in an upper portion of the semiconductor layer 12 in a manner separated from the first well region 22. The second well region 23 is formed in the terminal region of the output stage element 101 to relax the electric field. The depths of the first well region 22 and the second well region 23 are, for example, deeper than the depth of the body region 13 and deeper than the depths of the trenches 17a and 17b. The impurity concentrations of the first well region 22 and the second well region 23 are substantially the same as each other, and are set to substantially the same depth. In addition, the impurity concentrations of the first well region 22 and the second well region 23 may be different from each other, and the depths of the first well region 22 and the second well region 23 may be different from each other. The first well region 22 and the second well region 23 can be formed in the same process, thereby suppressing an increase in the number of processes.

[0082] The first well region 22 and the second well region 23 are formed by multi-stage ion implantation with different acceleration voltages and short-time heat treatment, similarly to the body region 13 of the output portion 100. By appropriately adjusting the number of ion implantations and the acceleration voltage in the multi-stage implantation, it is possible to achieve a doping distribution that matches the required performance in the depth direction of the first well region 22 and the second well region 23, such as a step-shaped doping distribution, a distribution in which the impurity concentration in the deep part is higher than the impurity concentration in the shallow part (flip-chip well), a distribution close to a Gaussian distribution, etc. In addition, the cross-sectional shape of the first well region 22 and the second well region 23 is not limited to Figure 1 The shape shown in FIG. 1 can be appropriately changed according to the number of ion implantations and the acceleration voltage.

[0083] like Figure 1 As shown, in the control element 201 of the circuit unit 200, the first conductivity type (n + The first terminal region (source region) 25a and the second terminal region (drain region) 25b of the semiconductor layer 12 are opposite to each other at the upper part of the first well region 22. The first terminal region 25a and the second terminal region 25b are selectively provided at the upper part of the first well region 22 in a manner separated from each other and have an impurity concentration higher than that of the semiconductor layer 12. + type semiconductor region. In the semiconductor integrated circuit involved in the embodiment of the present invention, the first terminal region 25a and the second terminal region 25b have substantially the same impurity concentration as the first main electrode regions 15a and 15b on the output portion 100 side, and are set to substantially the same depth. In addition, the first terminal region 25a and the second terminal region 25b may have different impurity concentrations from the first main electrode regions 15a and 15b, and their depths may also be different. The first terminal region 25a and the second terminal region 25b and the first main electrode regions 15a and 15b on the output portion 100 side can be formed in the same process, thereby suppressing the increase in the number of processes.

[0084] A planar control electrode structure (27, 28) extends laterally on the first well region 22. The control electrode structure (27, 28) includes a gate insulating film 27 disposed on the first well region 22 between the first terminal region 25a and the second terminal region 25b and a control electrode (gate electrode) 28 disposed on the gate insulating film 27.

[0085] The gate insulating film 27 may be made of the same material as the gate insulating film 18, such as a SiO2 film. The gate electrode 28 electrostatically controls the surface potential of the first well region 22 via the gate insulating film 27, thereby forming an inversion channel on the surface of the first well region 22. The gate electrode 28 may be made of the same material as the gate electrodes 19a and 19b, such as DOPOS.

[0086] A first circuit terminal wiring (source electrode wiring) 31 made of a metal material such as Al is disposed on the first terminal region 25a. A second circuit terminal wiring (drain electrode wiring) 32 made of a metal material such as Al is disposed on the second terminal region 25b. A field oxide film 30 is selectively provided between the control element 201 and the output stage element 101 on the upper surface of the semiconductor layer 12.

[0087] Figure 2 FIG. 2 shows an equivalent circuit diagram of a semiconductor integrated circuit according to an embodiment of the present invention. Figure 2 It can be understood that the semiconductor integrated circuit according to the embodiment of the present invention includes the output unit 100 and the circuit unit 200 . Figure 1 The control element 201 shown in FIG. Figure 2 MOS transistors T1 and T2 constitute a CMOS circuit, and correspond to a part of a control circuit of the control output unit 100, for example. Figure 1 The output stage components 101 shown in FIG. Figure 2 1 corresponds to the MOS transistor T0 of the output unit 100 shown in FIG. A freewheeling diode D0 is connected to the MOS transistor T0. A source terminal of the MOS transistor T0 is connected to the output terminal OUT, and a drain terminal of the MOS transistor T0 is connected to the power supply voltage terminal VCC.

[0088] <Method for manufacturing semiconductor integrated circuit>

[0089] Next, refer to Figure 3 to Figure 17 An example of a method for manufacturing a semiconductor integrated circuit according to an embodiment of the present invention will be described.

[0090] First, prepare n + A semiconductor substrate (Si wafer) composed of a type of silicon (Si) is used, and n is epitaxially grown on the semiconductor substrate.- Then, the thickness of the semiconductor substrate is adjusted, such as Figure 3 As shown, the semiconductor substrate is formed as a back contact layer 11, and n is epitaxially grown on the back contact layer 11. - The semiconductor substrate (11, 12) has a two-layer structure and a semiconductor layer 12 of the type. In addition, the thickness adjustment of the semiconductor substrate can also be implemented in the latter stage of the series of steps shown below, and is usually implemented in the latter stage of the series of steps.

[0091] On the other hand, the n-type semiconductor layer 12 may be formed by ion implantation or thermal diffusion. - The back side of the semiconductor substrate (Si wafer) is formed by n + In the case where the semiconductor layer 12 is formed using a semiconductor substrate, if the thickness of the semiconductor substrate becomes a problem, in the latter stage of the process, after the thickness of the semiconductor substrate that becomes the semiconductor layer 12 is adjusted, an n type diffusion layer is formed on the back side of the semiconductor substrate by ion implantation and thermal diffusion. + In this case, the back contact layer 11 of the type can be formed. At this time, the thickness can be adjusted after the Si wafer is attached to the upper surface side of the semiconductor layer 12 for reinforcement. Even in the case of epitaxially growing the semiconductor layer 12 on the back contact layer 11, the thickness of the semiconductor substrate that becomes the back contact layer 11 can be adjusted in the later stage of the process.

[0092] Next, an etching protection film 41 composed of an oxide film or the like is formed on the semiconductor layer 12 by a CVD method or the like, and the etching protection film 41 is patterned by photolithography and dry etching such as reactive ion etching (RIE). The patterned etching protection film 41 is used as an etching mask, such as Figure 4 As shown, trenches 17a and 17b are selectively formed in the upper portion of the semiconductor layer 12 by dry etching such as RIE. Thereafter, the etching protection film 41 used as an etching mask is removed.

[0093] Next, after forming a buffer oxide film (not shown) on the semiconductor layer 12 by thermal oxidation or the like, an oxidation resistant film 42 such as a silicon nitride film (Si3N4 film) is deposited on the buffer oxide film (not shown) by CVD or the like. Considering the groove width of the grooves 17a and 17b, the thickness of the oxidation resistant film is set so as to completely bury the grooves 17a and 17b. Specifically, the oxidation resistant film is formed under the condition that the thickness of the oxidation resistant film is at least 1 / 2 of the groove width of the grooves 17a and 17b. Then, photolithography technology and dry etching such as RIE are used to perform the oxidation resistant film. Figure 5The oxidation resistant film is patterned as shown in FIG. By using the patterned oxidation resistant films 42a and 42b as an oxidation resistant mask, a local oxidation of silicon (LOCOS) method is performed. Figure 6 As shown, a field oxide film (LOCOS film) 30 serving as an element isolation region is selectively (partially) formed in the openings of the oxidation-resistant films 42 a and 42 b on the semiconductor layer 12 .

[0094] Next, a photoresist film 43 is coated on the oxidation-resistant films 42a, 42b and the field oxide film 30, and a photolithography process of patterning the photoresist film 43 is performed using a photolithography technique. The patterned photoresist film 43 is used as a mask for selective ion implantation, and p-type impurity ions such as boron (B) ions and aluminum (Al) ions for forming the first well region 22 and the second well region 23 are selectively implanted in multiple stages (multi-stage implantation) on the upper surface of the semiconductor layer 12. Multiple multi-stage implantations are performed under different implantation conditions such as changing the implantation position. Here, the implantation position is set to the peak position of the chemical concentration distribution of the p-type impurities implanted into the semiconductor layer 12 by ion implantation.

[0095] As an example of the ion implantation process for forming the first well region 22 and the second well region 23, a case where three stages (three times) of ion implantation are performed is exemplified. Figure 7 As shown, the photoresist film 43 is used as a mask for selective ion implantation to form the first ion implantation regions 22a and 23a of the lower layer (lower side). The ion implantation is performed at a high acceleration voltage (e.g., about 1 to 4 MeV) that penetrates the oxidation-resistant films 42a and 42b and the field oxide film 30, so that the deep position of the lower part of the semiconductor layer 12 is set as the implantation position. The well withstand voltage (parasitic structure withstand voltage) of the control element 201 can be adjusted by the first ion implantation region 22a of the lower layer, for example.

[0096] Then, if Figure 8 As shown, the same photoresist film 43 is used as a mask for selective ion implantation to form the first ion implantation regions 22b and 23b in the middle layer (central region side). The ion implantation is performed at a medium acceleration voltage (e.g., about 0.3 MeV to 1 MeV) that penetrates the oxidation-resistant film 42b and the field oxide film 30 but does not penetrate the oxidation-resistant film 42a, so that the position above the first ion implantation regions 22a and 23a of the semiconductor layer 12 is set as the implantation position. The doping distribution under the field oxide film 30 can be adjusted by the first ion implantation region 22b in the middle layer.

[0097] Then, if Fig. 9AAs shown, the same photoresist film 43 is used as a mask for selective ion implantation to form the first ion implantation regions 22c and 23c of the upper layer (upper side). The ion implantation is performed at a low acceleration voltage (e.g., about 300 keV or less) that penetrates the oxidation-resistant film 42b but does not penetrate the field oxide film 30 and the oxidation-resistant film 42a, so that a shallow position near the upper surface of the semiconductor layer 12 is set as the implantation position. The threshold voltage of the control element 201 can be adjusted by the first ion implantation region 22c of the upper layer.

[0098] In addition, as an example of the ion implantation process for forming the first well region 22 and the second well region 23, a case of performing three-stage (three times) ion implantation is illustrated, but the number of stages (number of times) of multi-stage implantation is not limited to this. For example, two-stage (two times) ion implantation may be performed, and four-stage (four times) or more ion implantation may be performed. Thereafter, the photoresist film 43 used as a mask for selective ion implantation is removed.

[0099] Next, a photoresist film 44 is coated on the oxidation-resistant films 42a, 42b and the field oxide film 30, and a photolithography process is performed to pattern the photoresist film 44 using a photolithography technique. The patterned photoresist film 44 is used as a mask for selective ion implantation, and p-type impurity ions such as boron (B) ions and aluminum (Al) ions for forming the body region 13 are selectively implanted in multiple stages on the upper surface of the semiconductor layer 12 at an acceleration voltage that penetrates the oxidation-resistant film 42b but does not penetrate the oxidation-resistant film 42a. The ion implantation process for forming the body region 13 is similar to the ion implantation process for forming the first well region 22 and the second well region 23, and multiple ion implantations are performed under different implantation conditions. For example, in the ion implantation process for forming the body region 13, multi-stage implantation is performed in a manner that the deepest implantation position is different from the deepest implantation position of the first ion implantation regions 22a and 23a.

[0100] For example Fig.10 As shown, ion implantation is performed using the photoresist film 44 as a mask for selective ion implantation, thereby forming a second ion implantation region 13a. The ion implantation is performed by adjusting the high acceleration voltage of about 1MeV to 4MeV so that the ion implantation penetrates the oxidation-resistant film 42b but not the oxidation-resistant film 42a, and the implantation position reaches a relatively deep position inside the semiconductor layer 12. The second ion implantation region 13a of the lower layer is formed so that the implantation position is shallower than the bottom of the trenches 17a and 17b. The withstand voltage of the output stage element 101 can be adjusted by the second ion implantation region 13a of the lower layer.

[0101] Then, if Fig.11As shown, the same photoresist film 44 is used as a mask for selective ion implantation to perform ion implantation, thereby forming a second ion implantation region 13b in the upper layer. The ion implantation is performed by adjusting the medium acceleration voltage to about 0.3MeV to 1MeV so that the ion implantation penetrates the oxidation-resistant film 42b but does not penetrate the oxidation-resistant film 42a, and a shallow position near the upper surface of the semiconductor layer 12 is set as the implantation position. The threshold voltage of the output-stage element 101 can be adjusted by the second ion implantation region 13b in the upper layer. In addition, as an example of the ion implantation process for forming the body region 13 of the output-stage element 101, a case where two stages (two times) of ion implantation are performed as a multi-stage implantation is illustrated, and the number of stages (number of times) of the multi-stage implantation is not limited to this. For example, three stages (three times) or more of ion implantation can also be performed.

[0102] At this time, in terms of forming the output stage element 101, it is necessary to form the body region 13 to be shallower than the depth of the grooves 17a and 17b, and the body region 13 is not formed at the bottom of the grooves 17a and 17b. Therefore, in the case where ion implantation is performed after the oxidation-resistant films 42a and 42b are removed, it is necessary to perform ion implantation in a state where the grooves 17a and 17b are protected by a photoresist film. In this case, the thickness of the photoresist film is about several μm so that impurities do not penetrate the photoresist film during ion implantation at a high acceleration voltage. On the other hand, if a photoresist film is formed only on the grooves 17a and 17b, it is difficult to perform processing due to the aspect ratio problem.

[0103] In contrast, in the method for manufacturing a semiconductor integrated circuit according to the embodiment, Fig.10 and Fig.11 As shown in FIG. 1 , since ion implantation is performed before removing the oxidation-resistant films 42a and 42b, the inside of the grooves 17a and 17b is completely filled with the oxidation-resistant films 42a. Therefore, the oxidation-resistant films 42a that are effectively thickened in the grooves 17a and 17b can be used as a mask for selective ion implantation. Therefore, an acceleration voltage is set so as not to penetrate the oxidation-resistant films 42a that are effectively thickened in the grooves 17a and 17b and penetrate the oxidation-resistant films 42b on the semiconductor layer 12. By selecting the acceleration voltage, impurities can be implanted in a portion other than the bottom of the grooves 17a and 17b in a matching manner through the photoresist film 44 that has a large opening formed in the formation region of the grooves 17a and 17b.

[0104] Thereafter, the photoresist film 44 used as a mask for the selective ion implantation is removed. In addition, the multi-stage implantation for forming the body region 13 may be performed before the multi-stage implantation for forming the first well region 22 and the second well region 23 .

[0105] Next, the oxidation resistant films 42 a and 42 b are removed. Alternatively, the oxidation resistant films 42 a and 42 b may be removed before the multi-stage ion implantation step for forming the first well region 22 and the second well region 23 and the multi-stage ion implantation step for forming the body region 13 .

[0106] Then, the impurity ions in the lower first ion implantation region 22a, the middle first ion implantation region 22b and the upper first ion implantation region 22c are activated by a short-time heat treatment. Fig.12 As shown, the first well region 22 is formed. In addition, the impurity ions of the lower first ion implantation region 23a, the middle first ion implantation region 23b, and the upper first ion implantation region 23c are activated to form the second well region 23. In addition, the impurity ions of the lower second ion implantation region 13a and the upper second ion implantation region 13b are activated to form the body region 13. At this time, by setting the heat treatment conditions of temperature and time to such a temperature that does not cause the redispersion of impurities to avoid the destruction of the impurity distribution during ion implantation, it is possible to reduce characteristic deviation and suppress lateral diffusion, thereby achieving miniaturization.

[0107] Fig. 9B Show Fig. 9A The doping distribution of p-type impurities in the shallow first ion implantation region 22c of the upper layer of the semiconductor layer 12 (solid line), the doping distribution of p-type impurities in the first ion implantation region 22b of the middle layer (dotted line), and the doping distribution of p-type impurities in the deep first ion implantation region 22a of the lower layer (dashed line) are shown by line AA. In addition, the injection positions of the upper layer, the middle layer, and the lower layer during ion implantation are consistent with the peak positions of the doping distribution.

[0108] like Fig. 9B As shown, the position of the peak concentration of the p-type impurity in the first ion implantation region 22a of the lower layer is deeper than the peak concentration of the p-type impurity in the first ion implantation region 22b of the middle layer. In addition, the position of the peak concentration of the p-type impurity in the first ion implantation region 22b of the middle layer is deeper than the peak concentration of the p-type impurity in the first ion implantation region 22c of the upper layer. The peak concentration of the p-type impurity in the first ion implantation region 22a of the lower layer is higher than the peak concentration of the p-type impurity in the first ion implantation region 22b of the middle layer. In addition, the peak concentration of the p-type impurity in the first ion implantation region 22b of the middle layer is higher than the peak concentration of the p-type impurity in the first ion implantation region 22c of the upper layer.

[0109] Next, a gate insulating film 27 is formed on the first well region 22 exposed between the field oxide films 30 by a thermal oxidation method, and a gate insulating film 18 is formed on the body region 13 and the inner walls of the trenches 17a and 17b. Next, a DOPOS layer is deposited on the field oxide film 30, on the gate insulating film 27, on the gate insulating film 18, and in the trenches 17a and 17b by a CVD method or the like. A photoresist film is applied on the DOPOS layer, and the photoresist film is patterned using a photolithography technique. The patterned photoresist film is used as an etching mask, and the DOPOS layer, the gate insulating film 27, and the gate insulating film 18 are patterned by dry etching such as RIE or the like. Thereafter, the photoresist film used as an etching mask is removed. As a result, as shown in FIG. Fig.13 As shown, a gate electrode 28 and gate electrodes 19a and 19b made of a DOPOS layer are formed.

[0110] Then, if Fig.14 As shown in FIG. 1 , a selective ion implantation mask 45 having openings is formed on the body region 13 of the output stage element 101 and the first well region 22 of the control element 201 using photolithography technology. Then, the gate electrode 28 exposed in the opening of the selective ion implantation mask 45 is used as a self-matching mask to selectively implant n-type impurity ions such as arsenic (As) ions and phosphorus (P) ions into the upper surface of the body region 13. Next, as shown in FIG. Fig.15 As shown, a selective ion implantation mask 46 having an opening is formed on the body region 13 of the output stage element 101 using photolithography. Then, p-type impurity ions such as boron (B) ions and aluminum (Al) ions are selectively implanted into the upper surface of the body region 13 using the selective ion implantation mask 46.

[0111] After removing the selective ion implantation mask 46, the p-type and n-type impurity ions are activated and thermally diffused by heat treatment. Fig.16 As shown, in the output section 100, the output stage element 101 is formed by n + The first main electrode regions 15a, 15b and p + In addition, in the circuit portion 200, the control element 201 is formed with an n-type base contact region 16. + The first terminal area 25a and the second terminal area 25b of the type. + The depth of the first main electrode regions 15a and 15b of the type is formed shallower than the implantation position of the second ion implantation region 13b in the upper layer of the body region 13. Fig.12 The heat treatment shown, through Fig.16 The heat treatment shown is used to form the first well region 22 , the second well region 23 and the body region 13 .

[0112] In addition, here, the first main electrode regions 15a, 15b and the base contact region 16 are formed after the grooves 17a, 17b are formed and buried by the DOPOS layer, but this is only an example. For example, the grooves 17a, 17b may be formed after the first main electrode regions 15a, 15b and the base contact region 16 are formed. In addition, the first main electrode regions 15a, 15b and the first terminal region 25a and the second terminal region 25b may also be formed independently.

[0113] Next, the interlayer insulating film 20 is deposited by a CVD method or the like. The surface of the interlayer insulating film 20 is flattened by a method such as chemical mechanical polishing (CMP). A photoresist film is applied on the flattened interlayer insulating film 20, and the photoresist film is patterned using a photolithography technique. The patterned photoresist film is used as an etching mask, and the interlayer insulating film 20 is patterned by dry etching such as RIE, etc., to open contact holes.

[0114] After that, a metal film such as Al is deposited by sputtering or evaporation. A photoresist film is applied on the metal film, and the photoresist film is patterned using photolithography. The patterned photoresist film is used as an etching mask, and the metal film is patterned by dry etching such as RIE. As a result, Fig.17 As shown, a gate electrode wiring (not shown), a first circuit terminal wiring 31 and a second circuit terminal wiring 32 are formed. Alternatively, a gate electrode wiring (not shown), a first circuit terminal wiring 31 and a second circuit terminal wiring 32 may be formed in a self-aligned silicide process using a silicide of a high melting point metal such as W, Mo, or Ti. Thereafter, if necessary, the thickness of the back contact layer 11 is adjusted. Then, a back electrode 10 composed of Al or the like is deposited on the back side of the back contact layer 11 by a sputtering method or an evaporation method, thereby Figure 1 The semiconductor integrated circuit shown is completed.

[0115] <Comparative Example>

[0116] Here, a semiconductor integrated circuit according to a comparative example is described. In the semiconductor integrated circuit according to the comparative example, Fig.18 As shown, the semiconductor integrated circuit according to the embodiment of the present invention is different in that the body region 13x of the output portion 100 and the first well region 22x and the second well region 23x of the circuit portion 200 are formed by a single ion implantation and a high-temperature and long-term heat treatment. The body region 13x, the first well region 22x, and the second well region 23x each have a simple Gaussian doping profile in the depth direction.

[0117] Next, refer to Figure 19 to Figure 26The following will describe a method for manufacturing a semiconductor integrated circuit according to a comparative example. Figure 3 The process is the same, in n + The n-type back contact layer 11 is epitaxially grown - The semiconductor layer 12 of the type is formed, thereby forming a semiconductor substrate (11, 12) with a two-layer structure.

[0118] Then, if Fig.19 As shown in FIG. 1 , a photoresist film 47 is coated on the semiconductor layer 12, and the photoresist film 47 is patterned using photolithography. The patterned photoresist film 47 is used as a mask for selective ion implantation, and p-type impurity ions are selectively implanted on the upper surface of the semiconductor layer 12. The photoresist film 47 is then removed. After that, the impurity ions are activated and thermally diffused by heat treatment. This thermal diffusion is used to form Fig. 20 A high temperature and long time drive-in process is performed to form the p-type first well region 22 x and the p-type second well region 23 x with the depth shown.

[0119] Next, an etching protection film 48 such as an oxide film is deposited on the semiconductor layer 12 by a CVD method or the like, and the etching protection film 48 is patterned using photolithography and dry etching such as RIE. The patterned etching protection film 48 is used as an etching mask (etching mask), such as Fig.21 As shown, trenches 17a and 17b are formed in the upper part of the semiconductor layer 12 by dry etching such as RIE. Thereafter, the etching protection film 48 is removed.

[0120] Next, an oxidation resistant film 49 composed of a Si3N4 film or the like is deposited on the semiconductor layer 12 by a CVD method or the like. Then, by photolithography and dry etching, the Fig. 22 The oxidation resistant film 49 is patterned as shown. By using the patterned oxidation resistant film 49 as an oxidation resistant mask in a LOCOS method, as shown in FIG. Fig.23 As shown, the field oxide film 30 is selectively formed on the semiconductor layer 12. Thereafter, the oxidation resistant film 49 is removed.

[0121] Next, a gate insulating film 27 is formed on the first well region 22x exposed between the field oxide films 30 by thermal oxidation, and a gate insulating film 18 is formed on the inner walls of the trenches 17a and 17b. Next, a DOPOS layer is deposited on the field oxide film 30, the gate insulating film 27, the gate insulating film 18, and in the trenches 17a and 17b by CVD or the like. Then, the DOPOS layer, the gate insulating film 27, and the gate insulating film 18 are patterned by photolithography and dry etching or the like. As a result, as shown in FIG. Fig.24As shown, a gate electrode 28 and gate electrodes 19a and 19b made of a DOPOS layer are formed.

[0122] Then, if Fig.25 As shown, a photoresist film 50 is coated on the semiconductor layer 12, and the photoresist film 50 is patterned using photolithography. The patterned photoresist film 50 is used as a mask for selective ion implantation, and p-type impurity ions are selectively implanted on the upper surface of the semiconductor layer 12. Next, the photoresist film 50 used as a mask for selective ion implantation is removed. After that, a high-temperature and long-term heat treatment is performed to activate and thermally diffuse the impurity ions. As a result, as shown in FIG. Fig.26 As shown, a p-type body region 13x is formed. Fig.14 The subsequent process is the same, so repeated explanation is omitted.

[0123] In the manufacturing method of the semiconductor integrated circuit according to the comparative example, after the ion implantation for forming the first well region 22x and the p-type second well region 23x and after the ion implantation for forming the body region 13x, a plurality of high-temperature and long-term heat treatments are performed, so the manufacturing time is long. In addition, the plurality of heat treatments cause variations in the impurity concentrations of the first well region 22x, the second well region 23x, and the body region 13x, and thus causes variations in device characteristics.

[0124] In contrast, according to the method for manufacturing a semiconductor integrated circuit involved in the embodiment, since a high-temperature and long-term heat treatment (driving) is not performed, the manufacturing time can be shortened and lateral diffusion can be suppressed. For example, a 1150°C, 3-hour driving process can be cooled to 800°C and the time can be shortened to about 30 minutes. The heating time and cooling time of the high-temperature driving process are also longer, so the actual time reduction effect is greater. By being able to suppress lateral diffusion, the aspect ratio of the first well region 22, the second well region 23, the body region 13, etc., which are defined by the size in the depth direction relative to the plane size, can be increased. As a result of the increase in the aspect ratio, the area utilization efficiency of the output stage element 101 and the control element 201, etc. is improved, so a semiconductor integrated circuit in which the output stage element 101 and the control element 201, etc. are integrated into the same semiconductor chip can be manufactured through a high integration density structure. Furthermore, since there is no high-temperature and long-term push process, the generation of process-induced stacking faults and the like caused by thermal strain and the like is suppressed, and the deviation of the impurity concentrations of the first well region 22, the second well region 23, and the body region 13 can be suppressed. In addition, by suppressing the generation of process-induced stacking faults and the like, the generation of leakage current can be suppressed, and the electrical characteristics of the semiconductor integrated circuit can be improved.

[0125] (First Modification)

[0126] In the method for manufacturing a semiconductor integrated circuit according to the first modification of the embodiment of the present invention, an example is given in which, in the ion implantation step for forming the first well region 22 and the second well region 23 , ion implantation is also selectively performed under the field oxide film 30 .

[0127] In the method for manufacturing a semiconductor integrated circuit according to the first variant of the embodiment of the present invention, the method for manufacturing a semiconductor integrated circuit according to the embodiment of the present invention is different from the method for manufacturing a semiconductor integrated circuit according to the embodiment of the present invention. Fig. 9A After the ion implantation is performed three times, the photoresist film 43 is removed. Then, a photoresist film 51 is applied on the semiconductor layer 12, and the photoresist film 51 is patterned using photolithography. The patterned photoresist film 51 is used as a mask for selective ion implantation, such as Fig. 27 As shown in FIG. 1 , p-type impurity ions are selectively implanted on the upper surface of the semiconductor layer 12 in a manner that penetrates the field oxide film 30, thereby forming first ion implantation regions 22d and 22e on the sides of the first ion implantation region 22b under the field oxide film 30. Furthermore, a first ion implantation region 23d is formed on the sides of the first ion implantation region 23b under the field oxide film 30. Furthermore, in the method for manufacturing a semiconductor integrated circuit according to the embodiment, Fig.10 and Fig.11 In the same manner as in the process of FIG. 1 , a multi-stage implantation for forming the body region 13 is performed. Then, a short-term heat treatment is performed, such as Fig.28 As shown, a first well region 22 , a second well region 23 and a body region 13 are formed.

[0128] According to the manufacturing method of the semiconductor integrated circuit involved in the first variant of the embodiment of the present invention, by increasing the impurity concentration under the field oxide film 30, it is possible to suppress the situation in which an inversion layer (Inversion layer) is formed due to the potential of the wiring formed on the field oxide film 30 when the impurity concentration under the field oxide film 30 is low, thereby generating leakage current.

[0129] (Second Modification)

[0130] In the method for manufacturing the semiconductor integrated circuit according to the embodiment, the case where the oxidation resistant films 42a and 42b are removed after the multi-stage ion implantation step for forming the first well region 22 and the second well region 23 and the multi-stage ion implantation step for forming the body region 13 is exemplified. In contrast, in the method for manufacturing the semiconductor integrated circuit according to the second modified example of the embodiment of the present invention, the case where the oxidation resistant films 42a and 42b are removed before the multi-stage ion implantation step for forming the first well region 22 and the second well region 23 and the multi-stage ion implantation step for forming the body region 13 is exemplified.

[0131] In a method for manufacturing a semiconductor integrated circuit according to a second variation of the embodiment of the present invention, similarly to the method for manufacturing a semiconductor integrated circuit according to the embodiment of the present invention, Figure 6 As shown, a field oxide film 30 is formed. Fig.29 As shown in FIG. 4 , the oxidation resistant films 42a and 42b are removed. Fig.30 As shown, a photoresist film 52 is applied on the semiconductor layer 12, and the photoresist film 52 is patterned using a photolithography technique. The patterned photoresist film 52 is used as a mask for selective ion implantation, and p-type impurity ions are selectively implanted in multiple stages on the upper surface of the semiconductor layer 12. Next, the photoresist film 52 used as a mask for selective ion implantation is removed.

[0132] Next, a photoresist film 53 is coated on the semiconductor layer 12. Fig.31 As shown, the photoresist film 53 is patterned using photolithography technology. The patterned photoresist film 53 is used as a mask for selective ion implantation to selectively implant p-type impurity ions on the upper surface of the semiconductor layer 12. Next, the photoresist film 53 used as a mask for selective ion implantation is removed. After that, a short-time heat treatment is performed to activate and thermally diffuse the impurity ions. The following is a method for manufacturing a semiconductor integrated circuit according to the embodiment. Fig.12 The process shown later is the same, so repeated description is omitted.

[0133] (Third Modification)

[0134] In the method for manufacturing a semiconductor integrated circuit according to the embodiment of the present invention, the following case is exemplified: the multi-stage ion implantation process for forming the first well region 22 and the second well region 23 and the multi-stage ion implantation process for forming the body region 13 are performed independently. In contrast, in the method for manufacturing a semiconductor integrated circuit according to the third variant of the embodiment of the present invention, the following case is exemplified: the multi-stage ion implantation process for forming the first well region 22 and the second well region 23 and the multi-stage ion implantation process for forming the body region 13 include a common stage in which at least one ion implantation is performed simultaneously.

[0135] In a semiconductor integrated circuit according to a third variation of the embodiment of the present invention, similarly to the method for manufacturing the semiconductor integrated circuit according to the embodiment of the present invention, Figure 7 As shown, the first ion implantation regions 22a and 23a of the lower layer are formed by performing ion implantation at a high acceleration voltage (eg, about 1 MeV to 4 MeV) so as to penetrate the oxidation resistant films 42a and 42b and the field oxide film 30. Thereafter, the photoresist film 43 is removed.

[0136] Then, if Fig.32As shown, after the photoresist film 54 is newly patterned, ion implantation is performed at a medium acceleration voltage (e.g., about 0.3 MeV to 1 MeV) that penetrates the oxidation-resistant film 42b but does not penetrate the field oxide film 30 and the oxidation-resistant film 42a, thereby simultaneously forming the first ion implantation regions 22b, 23b and the second ion implantation region 13a of the middle layer. Next, ion implantation is performed at a low acceleration voltage (e.g., about 300 keV or less) that penetrates the oxidation-resistant film 42b but does not penetrate the field oxide film 30, thereby simultaneously forming the first ion implantation regions 22c, 23c and the second ion implantation region 13b of the upper layer. Thereafter, after removing the photoresist film 54, a short-time heat treatment is performed to activate and thermally diffuse the impurity ions. The following is related to the method for manufacturing a semiconductor integrated circuit according to the embodiment of the present invention. Fig.12 The process shown later is the same, so repeated description is omitted.

[0137] (Fourth Modification)

[0138] In the method for manufacturing a semiconductor integrated circuit according to the embodiment of the present invention, the following case is exemplified: the field oxide film 30 is formed after the trenches 17a and 17b are formed. In contrast, in the method for manufacturing a semiconductor integrated circuit according to the fourth variation of the embodiment of the present invention, the following case is exemplified: the trenches 17a and 17b are formed after the field oxide film 30 is formed.

[0139] In a semiconductor integrated circuit according to a fourth variation of the embodiment of the present invention, the method for manufacturing a semiconductor integrated circuit according to the embodiment of the present invention is as follows: Figure 3 The same process is used to form a two-layer semiconductor substrate (11, 12). Fig.33 As shown in FIG. 4 , an oxidation resistant mask composed of an oxidation resistant film 42 is formed, and a field oxide film 30 is formed in the opening of the oxidation resistant film 42. Fig.34 As shown, after the photoresist film 55 is patterned, multi-stage implantation with different acceleration voltages is performed to form the first ion implantation regions 22a, 23a of the lower layer, the first ion implantation regions 22b, 23b of the middle layer, and the first ion implantation regions 22c, 23c of the upper layer.

[0140] Then, if Fig.35 As shown, after the photoresist film 56 is patterned, multi-stage implantation with different acceleration voltages is performed, thereby forming the lower second ion implantation region 13a and the upper second ion implantation region 13b. Fig.36As shown in FIG. 1 , an etching protection film 57 such as an oxide film is patterned, and the patterned etching protection film 57 is used as an etching mask to form trenches 17a and 17b by dry etching such as RIE. The following process is similar to the method for manufacturing a semiconductor integrated circuit according to the embodiment of the present invention. Fig.12 The process shown later is the same, so repeated description is omitted.

[0141] (Fifth Modification)

[0142] In the method for manufacturing a semiconductor integrated circuit according to the embodiment of the present invention, the following case is exemplified: the field oxide film 30 is formed by the LOCOS method. In contrast, in the method for manufacturing a semiconductor integrated circuit according to the fifth variation of the embodiment of the present invention, the following case is exemplified: the output stage element 101 and the control element 201 are separated by an element separation trench based on shallow trench isolation (STI).

[0143] In a method for manufacturing a semiconductor integrated circuit according to a fifth variation of the embodiment of the present invention, the method for manufacturing a semiconductor integrated circuit according to the embodiment Figure 3 The process shown in the figure is the same as that of the semiconductor substrate (11, 12) with a two-layer structure. Next, an etching protection film 58 such as an oxide film is deposited on the semiconductor layer 12 by a CVD method or the like, and the etching protection film 58 is patterned by photolithography and dry etching such as RIE. The patterned etching protection film 58 is used as an etching mask, such as Fig.37 As shown, trenches 17a, 17b and element isolation grooves 17c, 17d are selectively formed in the upper part of the semiconductor substrate (11, 12) by dry etching such as RIE, etc. Thereafter, the etching protection film 58 used as an etching mask is removed.

[0144] Next, a photoresist film 59 is applied on the semiconductor layer 12, and the photoresist film 59 is patterned using a photolithography technique. The patterned photoresist film 59 is used as a mask for selective ion implantation, such as Fig.38 As shown, p-type impurity ions are selectively implanted in multiple stages on the upper surface of the semiconductor layer 12. Thereafter, the photoresist film 59 used as a mask for selective ion implantation is removed.

[0145] Next, a photoresist film 60 is applied on the semiconductor layer 12, and the photoresist film 60 is patterned using a photolithography technique. The patterned photoresist film 60 is used as a mask for selective ion implantation, such as Fig.39 As shown in FIG. 1 , p-type impurity ions are selectively implanted in multiple stages on the upper surface of the semiconductor layer 12. Next, the photoresist film 60 used as a mask for selective ion implantation is removed. By a short-term heat treatment, as shown in FIG. Fig.40As shown, a first well region 22 , a second well region 23 and a body region 13 are formed.

[0146] Next, an insulating film is formed on the semiconductor layer 12 and on the inner walls of the grooves 17a, 17b and the element separation grooves 17c, 17d by a thermal oxidation method or the like. Next, a DOPOS layer is deposited on the insulating film and in the grooves 17a, 17b and the element separation grooves 17c, 17d by a CVD method or the like. A photoresist film is applied on the DOPOS layer, and a pattern is formed on the photoresist film using a photolithography technique. The patterned photoresist film is used as an etching mask, and the DOPOS layer and the insulating film are patterned by dry etching such as RIE or the like. Thereafter, the photoresist film used as the etching mask is removed. As a result, as shown in FIG. Fig.41 As shown, gate insulating films 18, 27 and element isolation insulating films 18p, 18q formed of insulating films, and gate electrodes 28, gate electrodes 19a, 19b and dummy electrodes 19p, 19q formed of DOPOS layers are formed. The dummy electrodes 19p, 19q may be in a floating state, or may be connected to the lowest potential (for example, ground potential) of the connection control element 201. The following process is substantially the same as the process of the method for manufacturing the semiconductor integrated circuit involved in the embodiment, so repeated description is omitted.

[0147] (Other embodiments)

[0148] As described above, the present invention is described through the embodiments, but it should not be understood that the discussion and drawings constituting part of the present disclosure are used to limit the present invention. Based on the present disclosure, various alternative embodiments, examples, and application technologies can be clearly identified by those skilled in the art.

[0149] For example, in the embodiment of the present invention, a trench gate MOSFET is exemplified as the output stage element 101 of the output unit 100, but the present invention is not limited thereto. For example, the output stage element may also be a trench gate IGBT. When the output stage element is an IGBT, for example, Figure 1 The back contact layer 11 is set to p + In addition, although the control element 201 of the circuit unit 200 is constituted by CMOS, the present invention is not limited to CMOS and may be a control circuit constituted by other semiconductor elements.

[0150] In the embodiment of the present invention, Si is used as the semiconductor substrate (11, 12). However, in addition to Si, it is also applicable to the case of using a semiconductor material (wide bandgap semiconductor) having a wider bandgap than Si, such as silicon carbide (SiC), gallium nitride (GaN), diamond or aluminum nitride (AlN).

[0151] In addition, Figure 1 In the example, the semiconductor substrate (11, 12) is shown as being composed of n + The back contact layer 11 is epitaxially grown on the semiconductor substrate of the type - For example, an n-type semiconductor layer 12 epitaxially grown on a p-type supporting substrate (semiconductor wafer) may be used. + The buried layer of the type is used to replace the back contact layer 11. + n - The semiconductor layer 12 of the type is formed to form a semiconductor substrate with a three-layer structure. + In the case of a three-layer semiconductor substrate having a buried epitaxial layer of the type replacing the back contact layer 11, a sinker region extending from the upper surface of the semiconductor layer 12 to the buried epitaxial layer may be provided. That is, the upper surface side of the semiconductor layer 12 may be connected to the n electrode functioning as a drain region via the sinker region. + In this case, the drain electrode wiring is provided on the upper surface side of the semiconductor layer 12. + When a buried epitaxial layer of the SOI type is used instead of the back contact layer 11, the support substrate on the back side may be an insulator substrate to form an SOI structure.

[0152] As described above, it is needless to say that the present invention includes various embodiments and the like that are not described here. Therefore, the technical scope of the present invention is determined only by the specific features of the invention according to the claims that are appropriately derived from the above description.

Claims

1. A method for manufacturing a semiconductor integrated circuit, characterized in that: Including the following processes: Injecting impurity ions of the second conductivity type into a portion of an upper portion of the semiconductor layer of the first conductivity type in multiple stages while changing the implantation position, thereby selectively forming a first ion implantation region; Injecting impurity ions of the second conductivity type in multiple stages at other parts of the upper portion while changing the implantation position, thereby selectively forming a second ion implantation region; activating the impurity ions in the first ion implantation region to form a well region of the second conductivity type, and activating the impurity ions in the second ion implantation region to form a body region of the second conductivity type; forming a control element having a first terminal region and a second terminal region of a first conductivity type facing each other on an upper portion of the well region; as well as An output stage element having an output terminal region of the first conductivity type and controlled by the control element is formed on the upper portion of the body region, Before the process of selectively forming the first ion implantation region and the process of selectively forming the second ion implantation region, a process of digging a groove in another part of the upper portion is also included. Before the step of selectively forming the first ion implantation region and the step of selectively forming the second ion implantation region, the method further includes forming an oxidation resistant film on the semiconductor layer so as to fill the trench.

2. The method for manufacturing a semiconductor integrated circuit according to claim 1, wherein: In the step of selectively forming the second ion implantation region, multi-stage implantation is performed so that the deepest implantation position is different from the deepest implantation position of the first ion implantation region.

3. The method for manufacturing a semiconductor integrated circuit according to claim 1, wherein: It also includes the following processes: patterning the oxidation resistant film to form an oxidation resistant mask; thermally oxidizing the opening of the oxidation-resistant mask to locally form a field oxide film; as well as After the process of selectively forming the first ion implantation region and the process of selectively forming the second ion implantation region, the oxidation resistant mask is removed.

4. The method for manufacturing a semiconductor integrated circuit according to claim 3, wherein: After the step of locally forming the field oxide film, the method further includes the following steps: a photolithography step of patterning a first selective ion implantation mask for selectively forming the first ion implantation region; and A photolithography step of patterning a second selective ion implantation mask for selectively forming the second ion implantation region.

5. The method for manufacturing a semiconductor integrated circuit according to claim 4, wherein: Respective acceleration voltages of the multi-stage implantation forming the first ion implantation region and the multi-stage implantation forming the second ion implantation region are selected to be values ​​that penetrate the oxidation resistant mask.

6. The method for manufacturing a semiconductor integrated circuit according to claim 4 or 5, characterized in that: An acceleration voltage of at least one of the multi-stage implantation for forming the first ion implantation region and the multi-stage implantation for forming the second ion implantation region is selected to have a value that penetrates the field oxide film.

7. The method for manufacturing a semiconductor integrated circuit according to claim 4 or 5, characterized in that: An acceleration voltage of at least one of the multi-stage implantation for forming the first ion implantation region and the multi-stage implantation for forming the second ion implantation region is selected to be a value that does not penetrate the field oxide film.

8. The method for manufacturing a semiconductor integrated circuit according to claim 4 or 5, characterized in that: Each acceleration voltage of the multi-stage implantation for forming the second ion implantation region is selected to be a value that does not penetrate the oxidation resistant film buried in the trench.

9. The method for manufacturing a semiconductor integrated circuit according to claim 4 or 5, characterized in that: The method further includes a photolithography step of patterning a third selective ion implantation mask different from the first selective ion implantation mask for selectively forming the first ion implantation region. In the step of selectively forming the first ion implantation region, the first ion implantation region is selectively formed using the first selective ion implantation mask and the third selective ion implantation mask, respectively.

10. The method for manufacturing a semiconductor integrated circuit according to any one of claims 3 to 5, characterized in that: After the step of removing the oxidation resistant mask, the method further includes the step of embedding a control electrode structure of the output stage element in the trench.

11. The method for manufacturing a semiconductor integrated circuit according to any one of claims 1 to 5, characterized in that: The step of selectively forming the first ion implantation region and the step of selectively forming the second ion implantation region include a common stage of simultaneously performing at least one ion implantation.

Images