Light Sensor

Abstract

Embodiments of the present disclosure relate to a light sensor. A sensor having a plurality of pixels arranged in a plurality of rows and a plurality of columns, the sensor having a row control circuit device for controlling which of the rows is activated, and having a column control circuit device for controlling which of the pixels in the activated rows is to be activated. The column circuit device has a memory configured to store information indicating which pixels are defective, wherein each of the pixels has a photodiode and a plurality of transistors controlling activation of the photodiode. The first transistor is configured to be controlled by a column enable signal, and the second transistor is configured to be controlled by a row select signal.

Description

Technical Field

[0001] Some embodiments relate to an apparatus, and particularly, but not exclusively, to an apparatus having an array of photosensors. Background Art

[0002] Range and distance detection using light is known. Systems known as LIDAR (Light Detection and Ranging) have many applications including consumer electronics, automotive, robotics, surveying, and more.

[0003] Example LIDAR systems use a light source, such as a vertical cavity surface emitting laser (VCSEL), to generate light pulses that reflect from a surface and are detected at a receiver or detector, such as a photodiode or a single photon avalanche diode (SPAD) array.

[0004] The time difference between the transmitted and received light provides a distance or range value using the formula D = 0.5 x S * T, where T is the time difference, S is the speed of light, and D is the distance from the transmitter to the reflecting object. Summary of the invention

[0005] According to some embodiments, a sensor is provided, comprising: a plurality of pixels arranged in a plurality of rows and a plurality of columns; a row control circuit device for controlling which of the rows is activated; and a column control circuit device for controlling which of the pixels in the activated rows is to be activated, the column circuit device comprising a memory configured to store information indicating which of the pixels are defective, wherein each of the pixels comprises a photodiode and a plurality of transistors configured to control activation of the photodiode, wherein a first transistor is configured to be controlled by a column enable signal, and a second transistor is configured to be controlled by a row select signal.

[0006] The photodiode may include a single photon avalanche diode.

[0007] The row control circuitry may be configured to provide a control signal in dependence on the row select signal, the control signal being provided to each of the pixels, the control signal being configured to control quenching of a photodiode in each respective pixel.

[0008] The memory may be configured to output a column enable signal.

[0009] The memory may include a state machine, a defect memory connected to the state machine, and an active memory, wherein the defect memory will indicate which pixels of the plurality of pixels are faulty, and wherein the active memory defines which pixels of the plurality of pixels are active in a given read operation.

[0010] The control signal may only quench the photodiode in each corresponding pixel when the column enable signal provided to the first transistor is also high.

[0011] The sensor can be configured such that if the column enable signal is low, the column disable transistor will conduct and the first transistor will not conduct, which will reduce the voltage across the photodiode in each pixel to below the breakdown voltage.

[0012] The sensor can be configured so that if the row select signal is high, the row disable transistor will turn on, which will reduce the voltage across the photodiode in each pixel to below the breakdown voltage.

[0013] Each of the pixels in the plurality of pixels may include a buffer including two inverters arranged in series.

[0014] The sensor may include a plurality of photon counting circuits configured to count an amount of photons detected by each of the plurality of pixels.

[0015] The plurality of photon counting circuits may be shared by two or more of the pixels in the plurality of pixels.

[0016] The sensor can be configured to activate a single row of pixels at a time, such that the row activation can be sequential and / or the row activation can be random.

[0017] The plurality of transistors may include MOSFET transistors.

[0018] The first transistor and the second transistor may be NMOS transistors, and the column disable transistor and the row disable transistor may be PMOS transistors.

[0019] According to some embodiments, a method is provided, comprising: providing a plurality of pixels arranged in a plurality of rows and a plurality of columns, wherein each of the above-mentioned pixels comprises a photodiode and a plurality of transistors configured to control activation of the above-mentioned photodiode; controlling which one of the above-mentioned rows is activated using a row selection signal; controlling which one of the above-mentioned pixels in the above-mentioned activated rows is to be activated using a column enable signal; and storing information indicating which of the above-mentioned plurality of pixels are defective when the above-mentioned plurality of rows and columns of pixels are activated.

[0020] The photodiode may include a single photon avalanche diode.

[0021] The method may include providing a control signal in dependence on a row select signal, the control signal being provided to each of the pixels, the control signal controlling quenching of a photodiode in each respective pixel.

[0022] A column enable signal may be output by the memory.

[0023] The method may include indicating, by a defect memory, which pixels of the plurality of pixels are active in a given read operation.

[0024] The method may include quenching the photodiode in each respective pixel when the column enable signal provided to the first transistor is also high.

[0025] The method may include turning on a column disable transistor when the column enable signal is low, which reduces the voltage across the photodiode in each pixel to below a breakdown voltage.

[0026] The method may include turning on a row disable transistor if the row select signal is high, which reduces the voltage across the photodiode in each pixel to below a breakdown voltage.

[0027] Each of the pixels in the plurality of pixels may include a buffer including two inverters arranged in series.

[0028] The method may include counting, by a photon counting circuit, an amount of photons detected by each pixel of the plurality of pixels.

[0029] The photon counting circuit may be shared by two or more of the pixels in the plurality of pixels.

[0030] The method may include activating a single row of pixels at a time, such that the row activation may be sequential and / or the row activation may be random.

[0031] The plurality of transistors may include MOSFET transistors.

[0032] The first transistor and the second transistor may be NMOS transistors, and the column disable transistor and the row disable transistor may be PMOS transistors.

[0033] According to some embodiments, a device is provided, comprising: a component for providing a plurality of pixels arranged in a plurality of rows and a plurality of columns, wherein each of the above-mentioned pixels includes a photodiode and a plurality of transistors configured to control activation of the above-mentioned photodiode; controlling which of the above-mentioned rows is activated using a row selection signal; controlling which of the above-mentioned pixels in the above-mentioned activated rows is to be activated using a column enable signal; and storing information indicating which of the above-mentioned pixels are defective when the pixels of the above-mentioned plurality of rows and columns are activated.

[0034] The photodiode may include a single photon avalanche diode.

[0035] The apparatus may comprise means for providing a control signal in dependence on a row select signal, said control signal being provided to each of said pixels, said control signal controlling the quenching of a photodiode in each respective pixel.

[0036] A column enable signal may be output by the memory.

[0037] The method may include indicating, by a defect memory, which pixels of the plurality of pixels are active in a given read operation.

[0038] The apparatus may include means for quenching the photodiode in each respective pixel when the column enable signal provided to the first transistor is also high.

[0039] The apparatus may include means for turning on a column disable transistor when the column enable signal is low, which reduces the voltage across the photodiode in each pixel to below a breakdown voltage.

[0040] The apparatus may include means for turning on a row disable transistor if the row select signal is high, which reduces the voltage across the photodiode in each pixel to below the breakdown voltage.

[0041] Each of the pixels in the plurality of pixels may include a buffer including two inverters arranged in series. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 schematically illustrates an example LIDAR system according to some embodiments, in which embodiments may be implemented;

[0043] Figure 2 An image sensor is schematically shown;

[0044] Figure 3A The sensor array is schematically shown;

[0045] Figure 3B An alternative sensor array is schematically shown;

[0046] Figure 4 Pixels of some embodiments are shown;

[0047] Figure 5 A schematic diagram showing a sensor array of some embodiments;

[0048] Figure 6 A schematic representation of row activation with respect to time is shown;

[0049] Figure 7 Another schematic representation of row activation with respect to time is shown;

[0050] Figure 8 shows the arrangement of pixel circuit devices in some embodiments;

[0051] Fig. 9Another example of a pixel circuit arrangement in some embodiments is shown. DETAILED DESCRIPTION

[0052] about Figure 1 , further details an example range or distance measurement system 100 suitable for implementing some embodiments. System 100 includes a light source 103. The light source can be considered as an emitter of light used in distance detection. The light source can be any suitable pulse (or wave) light source. For example, in some embodiments, the light source can be one or more vertical cavity surface emitting laser light sources. The vertical cavity surface emitting laser is suitable because it can produce pulses of suitable short duration that are appropriately defined. The light source 103 can further include or be coupled to various optical devices configured to collimate and / or focus the light source to a specific area or area. In some embodiments, the light source includes a mechanical or beam guide that is configured to direct light to a target or surface 104 according to a defined pattern. The emitted light 102 can then be incident on the surface 104, and the reflected light 106 is received at the detector 105 of the system 100.

[0053] The detector 105 may include or be coupled to various optical devices configured to focus the returned light to a specific photosensitive region or area within the detector. The detector may be considered a receiver of light used in distance detection. In some embodiments, the detector includes or is associated with a mechanical or beam guide (in some embodiments, the same mechanical or beam guide as used by the light source 103) that is configured to direct the returned light to a specific photosensitive region or area within the detector (according to a defined pattern). In some embodiments, the detector 105 includes a photosensitive region, such as an array of single photon avalanche diodes configured to convert the received light into an electronic signal suitable for output.

[0054] A single photon avalanche diode (SPAD) is a semiconductor device capable of detecting light. Photons impinging on the detection region of the SPAD generate electron and hole pairs via the photoelectric effect. The SPAD is reverse biased with a high voltage amplitude so that when electron / hole carriers are generated, the electric field applied across the detection region causes the carriers to be accelerated to relatively high velocities depending on the strength and direction of the applied field. If the kinetic energy of the accelerated carriers is sufficient, additional carriers will be generated from the semiconductor lattice, which are in turn accelerated by the electric field and may release additional carriers in an exponentially increasing manner. Therefore, when a sufficiently high electric field is applied across the detection region, a single impinging photon can generate an avalanche of carriers, resulting in an output current "pulse", where the current output is proportional to the number of photons detected.

[0055] The minimum voltage that causes an avalanche of carriers, thus allowing the device to operate as a SPAD, is called the breakdown voltage. If the applied voltage is too low, i.e., below the breakdown voltage, the device will not produce any output. However, if the applied voltage is too high, the electric field generated can be sufficient to cause an avalanche of carriers, even if no photons hit the SPAD, resulting in an erroneous output current. This erroneous output is called "dark current."

[0056] The system may include a timing generator (or controller) 113. In some embodiments, the timing generator 113 may be used to control the detector 105 and the light source 103. The timing generator 113 may be configured to generate various timing or control pulses to control the light source, such as controlling when and where light is emitted. The timing generator 113 may be configured to further control the detector to activate some areas as being photosensitive or active and activate some other areas as being inactive.

[0057] The system may include a distance measurement / distance mapping unit 115. In some embodiments, the distance measurement / distance mapping unit 115 may be configured to receive timing control information from the timing generator 113 and from the detector 105 (and in some embodiments, the light source 103), and determine the distance between the system 100 and the surface 104 based on the time it takes for light to travel from the light source 103 to the surface 104 and from the surface 104 to the detector 105. For example, the distance measurement / distance mapping unit 115 may be configured to generate a histogram of detected events (with respect to time) and determine the distance based on the histogram. In some embodiments, the distance measurement / distance mapping unit 115 is configured to determine the distance of more than one point or area, and thus determine a distance map.

[0058] In some embodiments, the system 100 may include a suitable application 111 configured to interface with the timing generator 113 and the distance measurement / distance mapping unit 115. For example, the application may be a motor vehicle braking decision unit, a motor vehicle navigation unit, a computer vision unit, or other application. For example, the application 111 may receive a distance map or distance value and perform a decision or determination based on the distance information to control another device. In some further embodiments, the application 111 may also be configured to control the timing generator to change the distance measurement parameters.

[0059] In some embodiments, the timing generator 113, distance measurement / mapping 115 and application 111 may be implemented within a computer (running appropriate software stored on at least one memory and at least one processor), a mobile device, or alternatively within a specific device utilizing, for example, an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit).

[0060] about Figure 2 , schematically showing a detector (receiver) configuration. Image sensor 225 includes a sensitive region or detection region 226. The sensing region is composed of an array of photodiodes (such as SPAD 224) forming a sensitive region. The array is configured with multiple rows and multiple columns of SPAD 224.

[0061] refer to Figure 3A , which shows a sensor 300 that can be used to implement the detector 105. The sensor 300 has an array 301 of macropixels 302 arranged in X rows and Y columns, a control circuit device 304, and a row control circuit device 306. In this embodiment, one row can be activated at a time. This is controlled by the row control 306. Figure 3A Macropixel 302 is shown in more detail in FIG.

[0062] The macropixel 302 has four wells 308. Each well 308 has N SPADs. By way of example only, the value of N may be between 4 and 560. Preferably, the value of N may be between 8 and 112. More preferably, the value of N may be 28. In other examples, the value of N may be higher or lower than 28. The four wells are arranged in a 2x2 arrangement. Figure 3A In an alternative embodiment, the two upper wells are directly above the two lower wells. Figure 3B As shown in , the two upper wells are offset by a quarter macro-pixel 302. As shown in Figure 3B As you can see in the figure, the middle of the lower left well is aligned with the left end of the well above it. Figure 3A and Figure 3B Four wells 308 are shown for each macropixel 302 , but in other examples, the number of wells provided per macropixel may be higher or lower than four.

[0063] The macropixels 302 each have clock and signal buffer circuitry 310 along the lower edge of the two wells in the bottom row. TDC (time to digital converter) circuitry 312 is provided between the first and second wells of the first row and between the first and second wells of the second row. SPAD pixel circuitry 314 is arranged between the first and second rows of macropixels 302. TDC circuitry can be used to increase timing resolution.

[0064] A portion of the well 308 and associated SPAD pixel circuitry 314 (shown by the dashed box with reference numeral 316) is shown in more detail in FIG3 . In this detail, three SPADs 320 are shown in a column and they share a cathode. A SPAD pixel circuit 314 is provided for each SPAD 320. Each SPAD pixel circuit will control readout, charge storage, quenching, resetting, activation, and deactivation of the corresponding SPAD.

[0065] In some cases, it may be desirable to provide a relatively high fill factor. To this end, some embodiments may be configured to provide a more compact SPAD pixel circuit to reduce the area occupied thereby. This means that the proportion of the macro pixel occupied by the SPAD can be increased.

[0066] In some embodiments, some SPADs can provide a relatively high DCR (dark count rate). This is the number of output pulses counted when the SPAD is not illuminated (i.e. no photons are received, but avalanche breakdown is still triggered). SPADs with high DCR themselves are generally not desired, but being able to manage SPADs with high DCR means that the array can be less sensitive to problems caused by higher DCR. Reducing the DCR has an associated cost, which can be avoided or reduced if the array is not sensitive to high DCR SPADs. The reduced cost can be, for example, a reduction in spatial sampling. If a pixel is turned off, it cannot be detected or sampled.

[0067] It will be appreciated that embodiments may be used with arrays of any suitable size, from arrays of only a few pixels to very large arrays. It will be appreciated that some embodiments may be used with arrays having, for example, hundreds of thousands, millions, or tens of millions of SPADs.

[0068] In some embodiments, power consumption can be managed. For example, a high DCR SPAD can be gated. For example, rows of SPADs can be enabled sequentially. In particular, a memory that defines defective SPADs (e.g., SPADs with high DCR) is not provided in the pixel itself, but is provided in a column control circuit device. The column control circuit device is used to control whether the SPAD is active (assuming that the SPAD is in an activated row). The column control circuit device will provide an enable signal (which can be turned on or off) and a disable signal (which can be turned on or off). These signals are used to control whether a specific SPAD in an activated row is activated. Although this technique is used to avoid the use of defective SPADs, if there is a specific area of ​​interest, the technique can also be used to select pixels of a subgroup in a row.

[0069] Some embodiments make it possible to activate a region of interest (ROI) of the array, thereby allowing random access across the array. The ROI may be any suitable ROI, and may be, for example, one or more rows of a SPAD. For example, a range of rows may be selected to obtain the ROI, while all other rows above and below the range are deactivated.

[0070] refer to Figure 4 , which shows a pixel 400 of some embodiments. The pixel may be used in an array such as described previously.

[0071] A row controller 440 and a column controller 480 are provided separately from the pixels 400 .

[0072] Pixel 400 has a sensing stage including SPAD 401, column enable MOSFET 402 and quenching / reset device 403. SPAD 401, column enable MOSFET 402 and quenching / reset device 403 are arranged in series between VHV (i.e. power supply) and AVSS (i.e. ground). SPAD 401 can detect photons and trigger avalanche current.

[0073] Column enable MOSFET 402 may receive a signal from column controller 480. In this example, column enable MOSFET 402 is an NMOS transistor. If the signal received at the gate of column enable MOSFET 402 is high, column enable MOSFET 402 will turn on and enable the pixel. In this example, quencher / reset device 403 is also an NMOS transistor. Quencher / reset device 403 may receive a SPAD reset signal (row VQ) from row controller 440, which, when high, causes quencher / reset device 403 to turn on and cause the avalanche to be quenched.

[0074] Pixel 400 includes MOSFET devices 405, 407, which are arranged in parallel between the voltage terminal VSPADOFF and the node between SPAD 401 and the column enable MOSFET 402. In this example, MOSFET devices 405, 407 are PMOS transistors. MOSFET device 405 can receive a row disable signal that will disable the pixel. If the row disable signal is low, MOSFET device 405 will turn on and pixel 400 will be disabled. The row disable signal can be sent by row controller 440. MOSFET device 407 can receive a column disable signal that will disable the pixel. If the column disable signal is low, MOSFET device 407 will turn on and pixel 400 will be disabled. The column disable signal can be sent by column controller 480. When MOSFET devices 405, 407 are turned off (i.e., the disable signal to MOSFET 405, 407 is high), the avalanche current from the sensing stage passes into inverter 409.

[0075] The row controller 440 includes a second inverter 441 having a row select signal input labeled ROWSEL. The second inverter 441 is connected to the gate of the first MOSFET 405. In this way, the row controller can provide a row disable signal to the pixel 400, and when ROWSEL is high (due to the inverter), the row disable signal will disable the pixel. The row controller has a quenching trigger circuit including MOSFET devices 443 and 445. In this example, MOSFET device 443 is a PMOS transistor and MOSFET device 445 is an NMOS transistor. The ROWSEL signal is input to the gates of MOSFET devices 443 and 445. The drain of MOSFET device 443 is connected to the drain of MOSFET device 445, which in turn is connected to the gate of the quenching / reset device 403 in the pixel 400. The source of MOSFET device 443 is connected to the global VQ (i.e., the global reference voltage). The source of MOSFET device 445 is connected to AVSS (i.e., ground). When the ROWSEL signal is high, MOSFET device 443 will not conduct, and MOSFET device 445 will conduct. In this case, the gate to the quench / reset device 403 will be a low input, which will cause the quench / reset device 403 to not conduct. When the ROWSEL signal is low, MOSFET device 443 will conduct, and MOSFET device 445 will not conduct. In this case, the gate to the quench / reset device 403 will be a high input, which will cause the quench / reset device 403 to conduct. If the quench / reset device 403 is turned on and the column enable MOSFET 402 is also turned on, this will allow avalanche quenching / resetting.

[0076] The column controller 480 includes a memory 481. The memory 481 can be any kind of suitable memory. The row data and column data for the pixel will be input into the memory 481 for storage. The memory 481 can output a high output or a low output (enable signal (EN) and / or disable signal (DIS)) to the buffer gates 483 and 485, respectively. The output of the buffer gate 483 is connected to the gate of the column enable MOSFET 402. If the EN signal and the DIS signal are high, the column enable MOSFET 402 will be turned on. The output of the buffer gate 485 is connected to the gate of the MOSFET device 407. If the EN and DIS signals are low, the MOSFET device 407 will be turned on and the MOSFET 402 will stop conducting. This reduces the voltage across the SPAD 401, making the SPAD 401 below the breakdown voltage, thereby preventing the occurrence of avalanche. When the ROWSEL signal is high, the same effect occurs, when MOSFET 403 stops conducting and MOSFET 405 turns on, bringing SPAD 401 below breakdown voltage and preventing operation. MOSFET devices 402, 403, 405, 407 form a NAND gate. If ROWSEL, global VQ, and column EN are all high, the NAND gate in the pixel provides the function of activating the pixel.

[0077] Figure 4 Only a single pixel 400 is shown with a row controller 440 and a column controller 480. However, the row controller 440 will be connected to multiple pixels and will control the pixels as a row. The column controller 480 will be connected to multiple pixels and will control the pixels as a column.

[0078] The row controller 440 and column controller 480 separated from the pixel 400 can allow a high resolution SPAD array with a high fill factor. This pixel layout provides a high resolution SPAD array with integrated timing. The system can be suitable for LIDAR. The layout allows the use of the row controller 440 or the column controller 480 to turn off or on individual rows and columns of pixels. In addition, the layout can be more compact because the PMOS has a maximum of 2 N wells (instead of 4).

[0079] In conventional systems, memory, row controllers, and column controllers would be provided for each individual pixel. This reduces the resolution of the SPAD array because fewer pixels can be arranged in space. For example, in some previous proposals, transistors 443 and 440 would be provided in each pixel. In some previous proposals, each pixel would be provided with a memory to indicate whether the pixel was defective.

[0080] refer to Figure 5, which schematically illustrates the sensor array architecture of some embodiments, a state machine and random access control 501 is provided. A defect memory 503 for the entire SPAD array is connected to the state machine and random access control 501. The defect memory 503 will indicate which of the SPADs in the array are faulty and should not be used. The state machine and random access control 501 and the defect memory 503 are both connected to an active SPAD memory 505, which defines which SPADs are active in a given read operation. The state machine and random access control 501, the defect memory 503 and the active SPAD memory 505 are connected to an active SPAD memory 505 via Figure 4 The column controller 480 is connected to the SPAD array 507. The state machine and random access control 501 may also be connected to the row control 509.

[0081] The active SPAD memory 505 is connected to the SPAD array 507. The active SPAD memory may be connected to the SPAD array 507 via a parallel data interface (1 bit per SPAD). Any other suitable connection may also be used.

[0082] A row control 509 is provided that is connected to the SPAD array 507. The row control 509 may be connected to the SPAD array 507 via a parallel data interface. In this arrangement, only one row is activated at a time. Any other suitable connection may also be used. The column controller is used to select which SPADs in the array are active for sensing. In some embodiments, this may be the entire row except for the defective SPAD.

[0083] like Figure 5 As shown in , the memories (ie, state machine and random access control 501, defect memory 503 and active SPAD memory 505) are provided at the edge of the array. This can allow higher image resolution since there are more SPADs in the sensing part of the array.

[0084] The SPAD array 507 can be activated one row at a time. Figure 6 , which shows a schematic representation of row activations with respect to time. Figure 6 As shown in , row accesses can be sequential accesses, where row 0 is accessed first, row 1 is accessed next, and so on.

[0085] refer to Figure 7 , which shows another schematic representation of row activation with respect to time. Figure 7 As shown in , row accesses can be random row accesses, where row 0 is accessed first, row 11 is accessed next, row 2 is accessed next, and so on.

[0086] It will be appreciated that in other embodiments any suitable pattern of row access may be used.

[0087] In an embodiment, row access may be changed from sequential access to random access, or vice versa, at any time.Alternatively or additionally, any other suitable access mode may be used.

[0088] Reference again Figure 5 , the defect memory can be accessed by the state machine and random access control 501 to control which SPADs in the activated row will be active (so defective SPADs are not activated). The state machine and random access control 501 can activate the SPADs at any time during the LIDAR frame.

[0089] refer to Figure 8 , a pixel 701 including a SPAD 703 is provided. The layout of the pixel 701 is similar to Figure 4 4, but the readout aspects of the pixel are shown in more detail. Pixel 701 has a sensing stage, which includes SPAD 703, column enable MOSFET 705 and quenching / reset device 707. SPAD703, column enable MOSFET 705 and quenching / reset device 707 are arranged in series between VHV (i.e., power supply) and AVSS (i.e., ground). SPAD703 can detect photons and trigger avalanche current. In this example, column enable MOSFET 705 is an NMOS transistor. Column enable MOSFET 705 can receive a gate signal from an input marked as column [Y, SPAD] SPAD PD (COL [Y, SPAD] SPAD PD). If column [Y, SPAD] SPAD PD (COL [Y, SPAD] SPAD PD) is high, column enable MOSFET 705 will be turned on. The quenching / resetting device 707 can receive a signal on its gate from an input labeled ROW[x]VRECHARGE. If this signal is high, the quenching / resetting device 707 will turn on. If both the column-enable MOSFET 705 and the quenching / resetting device 707 are turned on, this will cause the avalanche current to be quenched / reset.

[0090] Pixel 701 includes MOSFET devices 709, 711, which are arranged in parallel between VSPADOFF and a node between SPAD 703 and column enable MOSFET 705. In this example, MOSFET devices 709, 711 are PMOS transistors. MOSFET device 709 can receive a gate signal from an input labeled as COL[Y, SPAD]] PULL UP. If COL[Y, SPAD]] PULL UP is low, MOSFET device 709 will turn on and pull up the output signal from SPAD 703. This can disable pixel 701. MOSFET device 711 can receive a gate signal from an input labeled as ROW[X] PULL UP. If ROW[X] PULL UP is low, the MOSFET device 711 will turn on and pull up the output signal from the SPAD 703. This can disable the pixel 701. The outputs from the MOSFETs 709, 711 are fed into a pair of CMOS inverters 713, 715 arranged in series. The two series CMOS inverters 713, 715 form a buffer.

[0091] The output of the buffer is connected to a multiplexer 719 of a pixel output circuit 717. The pixel output circuit 717 can be shared by two pixels 701 having corresponding SPADs. In other examples, the pixel output circuit 717 can be shared by more than two pixels 701. The multiplexer 719 has a second input from the output of the buffer of another pixel 701. The multiplexer 719 has a select input from an input labeled ROW[X]SELECT, which determines which output the multiplexer 719 will forward. The output of the multiplexer 719 is input to AND gates 721, 723. Each set of AND gates 721, 723 has a second input from an input labeled COLUMN[Y, SPAD]TIME GATE. The AND gate 721 also has an input from a pulse shaper 725. The AND gate 721 and the pulse shaper 725 form an integrated time gate and pulse shaper.

[0092] AND gate 721 outputs to an OR tree to a time to digital converter. AND gate 723 outputs to an OR tree to a counter. The value provided by the counter represents the photons collected by the corresponding SPAD.

[0093] The secondary output from AND gate 723 is provided to a monitoring counter, which can be matched with a dynamic enable / disable scheme. The monitoring counter allows checking whether the SPAD has too much light on it. In this case, the SPAD may be stuck high and always output "1" (high output). The pulse shaper 725 always outputs "0" to the OR tree, so the AND gate 723 without the pulse shaper 725 is configured to determine whether the SPAD is under very high light conditions.

[0094] Fig. 9 Schematically shows a similar Figure 8 Circuit 800 described in . Circuit 800 has a pixel 806, which includes a SPAD 801, a column enable MOSFET 803, a row enable MOSFET 805 and a quenching / reset device 807. SPAD 801, column enable MOSFET 803, row enable MOSFET 805 and quenching / reset device 807 are arranged in series between VHV (i.e., power supply) and ground. SPAD 801 can detect photons and trigger avalanche current. In this example, column enable MOSFET 803, row enable MOSFET 805 and quenching / reset device 807 are NMOS transistors. In other examples, any other suitable transistor or switch can be used. Column enable MOSFET 803 can receive a gate signal from an input labeled SPAD_COL_EN_GO2. Row enable MOSFET 805 can receive a gate signal from an input labeled SPAD_ROW_EN_GO2. Column enable MOSFET 803 can be connected in series with Figure 7 The row enable MOSFET 805 can function in a similar manner to the column enable MOSFET 803. The quencher / reset device 807 can receive a gate signal from an input labeled VRECHARGE. The quencher / reset device 807 can function in a similar manner to the column enable MOSFET 803. Figure 7 A similar approach as described above works.

[0095] In an embodiment, this configuration of the pixel circuit device allows a single row activation of SPAD / pixel. Therefore, SPAD can be enabled or disabled to mask high DCR devices. Once a high DCR SPAD is identified in the array, the corresponding row controller and column controller can selectively disable the high DCR SPAD. In other examples, SPAD can be enabled or disabled based on other metrics. In some examples, this allows dynamic enabling / disabling of pixels to manage the dynamic range in laser emission timing. Turning on SPAD can mean more SPAD avalanches, and therefore more SPAD events. Turning off SPAD can mean fewer SPAD avalanches, and therefore fewer SPAD events. Therefore, turning on more SPADs allows higher signals, and turning off SPADs allows smaller signals, which gives a relatively high dynamic range (signal count). By dynamically changing the SPAD that is turned on or off, the signal rate can be controlled over a relatively large range.

[0096] In some examples, this pixel configuration allows comprehensive testing of all transistors in all pixels for automated testing. For example, all electrical testing of a pixel can be performed without using any SPADs.

[0097] Pixel 806 includes MOSFET devices 809, 811, which are arranged in parallel between AVDD (i.e., power supply) and a node between SPAD 801 and column enable MOSFET 803. In this example, MOSFET devices 809, 811 are PMOS transistors. MOSFET device 809 can receive a gate signal from an input labeled SPAD_ROW_EN_GO2. If SPAD_ROW_EN_GO2 is low, MOSFET device 809 can be turned on and pull up the output signal from SPAD 801. MOSFET device 811 can receive a gate signal from an input labeled SPAD_COL_EN_GO2. If SPAD_COL_EN_GO2 is low, MOSFET device 811 can be turned on and pull up the output signal from SPAD 801. The outputs from MOSFET devices 809, 811 are fed to a pair of inverters 813, 815 arranged in series. The two inverters 813, 815 in series form a buffer. The output from the buffer is connected to the input of the multiplexer 817. Another input to the multiplexer 817 is received from the pixel of the adjacent row. Therefore, the multiplexer 817 can be considered as a shared multiplexer. In this example, the multiplexer 817 is shared by two pixels. In other examples, the multiplexer 817 can be shared by more pixels. The multiplexer has a selection input from the input marked as SPAD_SEL_PS_INPUT_GO1. The SPAD_SEL_PS_INPUT_GO1 signal will determine which multiplexer input is selected for output.

[0098] The output of multiplexer 817 is connected to pulse shaper 819. Pulse shaper 819 can be enabled to reshape the pulse generated by SPAD801. Pulse shaper 819 can be configured to shape the output from SPAD801 in normal operation mode and to shape the calibration signal in calibration operation mode. For a given SPAD count rate, pulse shaper 819 can be used to shorten the pulse length and reduce the effect of pile-up. The input signal SPAD_PSINPUT_GO1 will be shortened or truncated by pixel shaper 819 to produce a useful output signal marked as SPAD_PS_SLEW_GO1. The output of multiplexer 817 is also connected to the input of AND gates 821, 823. The second input to AND gates 821, 823 is received from the input marked as SPAD_COLLEGIC_EN_GO1. The output of AND gate 821 (SPAD_PIX_TDC_OUT_GO1) is connected to a pile-up NOR tree 825. In other examples, this can be a pile-up OR tree. Each of the NOR gates of the stacked NOR tree 825 is connected to a NAND gate 827. Each NAND gate is connected to an input of an OR gate 829. The output (SPAD_PIX_PILEUP_OUT_GO1) of AND gate 823 is connected to a stacked NOR tree 831. In other examples, this can be a stacked OR tree. Each of the NOR gates of the stacked NOR tree 831 is connected to a NAND gate 833. Each NAND gate is connected to an input of an OR gate 835.

[0099] In some applications, such as optical communications or light detection and ranging (LIDAR), the device includes both a light emitter and a SPAD detector. The light emitter may be, for example, a vertical cavity surface emitting laser (VCSEL). Other embodiments may use other suitable light sources.

[0100] In the example of a LIDAR system, light can be emitted by a VCSEL. When the emitted light reaches a target within the field of view of the device, a portion of the light can be reflected back to the SPAD detector. If the voltage applied to the SPAD is too low, it is impossible to determine whether no light is being received because the SPAD is improperly biased, or if there is no target within the field of view.

[0101] It should be understood that the use of various transistors in the above-described embodiments is only one example of such possible devices. Those skilled in the art will appreciate that any other suitable transistors may be used. For example, p-type FETs may be used instead of n-type FETs, etc. It should be understood that, alternatively or additionally, different types of transistors may be used, such as bipolar transistors or MOSFETs.

[0102] The above device can be implemented in any device or apparatus utilizing SPAD. For example, the above device and method can be implemented in a LIDAR system. It should be understood that this non-limiting embodiment is merely exemplary and the device and method can be implemented in any manner for other light detection applications.

[0103] It should be understood that the above-described arrangements may be implemented at least in part by an integrated circuit, a chipset, one or more bare dies packaged together or in different packages, discrete circuit devices, or any combination of these options.

[0104] Various embodiments with different variations have been described above. It should be noted that those skilled in the art can combine various elements of these various embodiments and variations.

[0105] Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the scope of this disclosure.Accordingly, the foregoing description is by way of example only, and is not intended to be limiting.

[0106] The various embodiments described above can be combined to provide additional embodiments. These and other changes can be made to the embodiments in light of the above detailed description. Generally, in the claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted as including all possible embodiments and the full range of equivalents to these claims. Therefore, the claims are not limited by the disclosure.

Claims

1. A sensor, comprising: a plurality of pixels arranged in a plurality of rows and a plurality of columns; row control circuit means for selectively controlling which of said rows is activated; as well as A column control circuit device selectively controls which of the pixels in the activated row is to be activated, the column control circuit device comprising a memory configured to store information indicating which of the pixels are defective, wherein each of the pixels comprises a photodiode and a plurality of transistors configured to control activation of the photodiode, the plurality of transistors comprising a first transistor and a second transistor, the first transistor being configured to be controlled by a column enable signal from the column control circuit device based at least in part on the memory, and the second transistor being configured to be controlled by a row select signal from the row control circuit device.

2. The sensor of claim 1, wherein the photodiode comprises a single photon avalanche diode.

3. A sensor according to claim 1, wherein the row control circuit device is configured to provide a control signal to each of the pixels in the activated row according to the row selection signal, and the control signal is configured to control the quenching of the photodiode in each corresponding pixel.

4. The sensor of claim 3, wherein the control signal will only quench the photodiode in each respective pixel when the column enable signal provided to the first transistor of the pixel is also high. The sensor of claim 1 , wherein the memory is configured to output the column enable signal.

6. The sensor of claim 1 , wherein the memory comprises a state machine, a defect memory connected to the state machine, and an activity memory, wherein the defect memory indicates which pixels of the plurality of pixels are faulty, and wherein the activity memory defines which pixels of the plurality of pixels are active in a given read operation.

7. A sensor according to claim 1, wherein for each pixel, the plurality of transistors of the pixel include a column disable transistor, wherein when the column enable signal is low, the column disable transistor will turn on and the first transistor will not turn on, which will reduce the voltage across the photodiode in the pixel to below a breakdown voltage.

8. The sensor of claim 1 , wherein for each pixel, the plurality of transistors of the pixel include a row disable transistor configured to turn on if the row select signal is high, which reduces the voltage across the photodiode in the pixel to below a breakdown voltage. 9 . The sensor of claim 1 , wherein each of the pixels in the plurality of pixels comprises a buffer comprising two inverters arranged in series.

10. The sensor of claim 1, wherein the sensor comprises a plurality of photon counting circuits configured to count photons detected by each of the plurality of pixels.

11. The sensor of claim 10, wherein each of the plurality of photon counting circuits is shared by two or more of the pixels of the plurality of pixels.

12. The sensor of claim 1, wherein the row control circuitry is configured to activate a single row of pixels at a time, such that row activation can be sequential or the row activation can be random.

13. The sensor of claim 1, wherein the plurality of transistors comprises MOSFET transistors.

14. The sensor of claim 12, wherein for each pixel: the plurality of transistors of the pixel include a column disable transistor, wherein when the column enable signal is low, the column disable transistor will conduct and the first transistor will not conduct, which will reduce the voltage across the photodiode in the pixel below a breakdown voltage; and The plurality of transistors of the pixel includes a row disable transistor configured to turn on if the row select signal is high, which reduces a voltage across the photodiode in the pixel below the breakdown voltage.

15. A method performed at a sensor, comprising: controlling which of a plurality of rows of pixels arranged in a plurality of columns is activated using a row selection signal, wherein each of the pixels includes a photodiode and a plurality of transistors configured to control activation of the photodiode; storing, in a memory, information indicating which of the pixels are defective; as well as Based at least in part on the stored information, a column enable signal is utilized to control which of the pixels in the activated row is to be activated.

16. The method according to claim 15, further comprising: row control circuit means providing a control signal to each of said pixels in accordance with said row selection signal; as well as The photodiode in a selected one of the pixels is quenched based on the control signal and based on the column enable signal provided to the first transistor of the selected one of the pixels. The method of claim 15 , wherein the memory outputs the column enable signal.

18. A sensor comprising: a plurality of pixels arranged in a plurality of rows and a plurality of columns, wherein each of the pixels comprises a single photon avalanche diode and a plurality of transistors configured to control activation of the single photon avalanche diode, the plurality of transistors comprising a first transistor; row control circuitry configured to selectively control activation of the rows using row select lines respectively coupled to control terminals of the pixels; as well as A column control circuit device selectively controls which pixel of the pixels in the activated row is to be activated, the column control circuit device comprising a memory configured to store information indicating which pixels of the plurality of pixels are defective, wherein the column control circuit device is configured to: based on the information in the memory, disable the defective pixel by sending a column disable signal to the first transistor of the defective pixel in the activated row.

19. A sensor according to claim 18, wherein the multiple transistors of each pixel include a second transistor, and the column control circuit device is configured to: activate the selected pixel by sending a column enable signal to the second transistor of the selected pixel of the activated row based on the information in the memory.

20. A sensor according to claim 19, wherein the multiple transistors of each pixel include a third transistor, and the row control circuit device is configured to provide a row control signal to the third transistor of each pixel in the activated row of pixels, and the second transistor and the third transistor are configured to control the quenching of the selected pixel based on the column enable signal and the row enable signal, respectively.

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