Display panel

Abstract

A display panel includes an upper display substrate, a lower display substrate, and a partition wall. The upper display substrate includes a display area and a non-display area adjacent to the display area. The display area includes a pixel area and a light-shielding area adjacent to the pixel area. The lower display substrate includes display elements configured to emit light having a first color and overlapping with the pixel areas, respectively. The partition wall includes a partition wall portion overlapping with the light-shielding area and a reflective portion arranged on the partition wall portion. The upper display substrate includes a base substrate, a color filter layer arranged on the base substrate, and a light control layer arranged on the color filter layer. The light control layer is configured to control light having the first color. The partition wall is arranged on the light control layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0023273, filed on February 27, 2019, which is hereby incorporated by reference in its entirety for all purposes as if fully set forth herein. Technical Field

[0003] Example embodiments relate generally to a display panel, and more particularly, to a display panel configured to prevent (or at least reduce) color mixing. Background Art

[0004] Various display devices can be used in conjunction with multimedia equipment such as televisions, mobile phones, tablet computers, navigation devices, and game consoles. The display device may be a transmissive display panel that selectively transmits source light generated from a light source, or an emissive display panel that generates source light within the display panel itself. When the display device is used in an outdoor space, reflection and scattering may occur on the display surface on which an image is visible due to external light.

[0005] The above information disclosed in this section is only for background understanding of the present inventive concept and therefore it may contain information that does not form the prior art. Summary of the Invention

[0006] Some example embodiments provide a display panel capable of preventing (or at least reducing) color mixing.

[0007] Additional aspects will be set forth in the detailed description which follows, and in part will be apparent from the disclosure, or may be learned by practice of the inventive concepts.

[0008] According to some exemplary embodiments, a display panel includes: an upper display substrate, a lower display substrate, and a partition wall. The upper display substrate includes a display area and a non-display area adjacent to the display area. The display area includes a pixel area and a light-shielding area adjacent to the pixel area. The lower display substrate includes display elements configured to emit light having a first color and overlapping with the pixel areas, respectively. The partition wall includes a partition wall portion overlapping with the light-shielding area and a reflective portion arranged on the partition wall portion. The upper display substrate includes a base substrate, a color filter layer arranged on the base substrate, and a light control layer arranged on the color filter layer. The light control layer is configured to control light having the first color. The partition wall is arranged on the light control layer.

[0009] According to some exemplary embodiments, a display panel includes: an upper display substrate, a lower display substrate, and a partition wall. The upper display substrate includes a display area and a non-display area adjacent to the display area. The display area includes a pixel area and a light-shielding area adjacent to the pixel area. The lower display substrate includes display elements that overlap with the pixel areas, respectively. The partition wall is arranged between the upper display substrate and the lower display substrate. The partition wall includes a partition wall portion overlapping with the light-shielding area and a reflective portion covering the partition wall portion. The height between the upper display substrate and the lower display substrate is defined as a first length in the thickness direction of the upper display substrate. The height of the partition wall is defined as a second length in the thickness direction. The second length is 0.6 to 0.95 times the first length.

[0010] The foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings, which are included to provide a further understanding of the inventive concept and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the inventive concept and, together with the description, serve to explain the principles of the inventive concept. In the drawings:

[0012] Figure 1 is a perspective view of a display panel according to some exemplary embodiments;

[0013] Figure 2 According to some exemplary embodiments Figure 1 a cross-sectional view of a display panel;

[0014] Figure 3A is a diagram illustrating a method according to some exemplary embodiments Figure 1 a plan view of a display panel;

[0015] Figure 3B is an equivalent circuit diagram of a pixel according to some exemplary embodiments;

[0016] Figure 4 According to some exemplary embodiments, Figure 1 a plan view of a pixel area in a display area of ​​a display panel;

[0017] Figure 5 According to some exemplary embodiments Figure 1 A cross-sectional view of a portion of a pixel region of a display panel;

[0018] Figure 6 According to some exemplary embodiments Figure 1 a cross-sectional view of an upper display substrate of a display panel;

[0019] Figure 7Ais a diagram illustrating a method according to some exemplary embodiments Figure 6 A plan view of a stacked structure of a display substrate;

[0020] Figure 7B is a diagram illustrating a method according to some exemplary embodiments Figure 6 A plan view of a stacked structure of a display substrate;

[0021] Figure 7C is a schematic diagram illustrating light characteristics of a light control layer according to some exemplary embodiments;

[0022] Figure 8 is a perspective view of a partition wall according to some exemplary embodiments;

[0023] Figure 9 is a diagram illustrating a method according to some exemplary embodiments Figure 6 a cross-sectional view of a portion of a display panel;

[0024] Figure 10 is a cross-sectional view of a display panel according to some exemplary embodiments;

[0025] Figure 11A is a cross-sectional view of a display panel according to some exemplary embodiments; and

[0026] Figure 11B is a cross-sectional view of a display panel according to some exemplary embodiments. DETAILED DESCRIPTION

[0027] In the following description, for the purpose of explanation, many specific details are set forth in order to provide a comprehensive understanding of each exemplary embodiment. As used herein, the terms "embodiment" and "implementation method" are used interchangeably and are non-limiting examples of one or more of the inventive concepts disclosed herein. However, it is apparent that each exemplary embodiment can be practiced without these specific details or with one or more equivalent settings. In other cases, well-known structures and devices are shown in block diagram form in order to avoid making each exemplary embodiment unnecessarily vague. Further, each exemplary embodiment can be different, but does not have to be exclusive. For example, the specific shape, configuration and characteristics of an exemplary embodiment can be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0028] Unless otherwise specified, the illustrated exemplary embodiments are to be understood as providing exemplary features of varying details of some exemplary embodiments. Therefore, unless otherwise specified, the various illustrated features, parts, modules, layers, films, panels, regions, aspects, etc. (hereinafter individually or collectively referred to as "elements") may be further combined, separated, interchanged, and / or rearranged without departing from the present inventive concept.

[0029] The use of cross hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Therefore, unless so specified, the presence or absence of cross hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, proportion, commonality between the illustrated elements and / or any other characteristics, properties, attributes, etc. of the elements. Further, in the drawings, the sizes and relative sizes of the elements may be exaggerated for clarity and / or descriptive purposes. Therefore, the sizes and relative sizes of the various elements are not necessarily limited to those shown in the drawings. When the exemplary embodiments can be implemented differently, a particular process order can be performed differently from the described order. For example, two consecutively described processes can be performed substantially simultaneously, or in an order opposite to the described order. In addition, the same reference numerals represent the same elements.

[0030] When an element, such as a layer, is referred to as being "on," "connected to," or "coupled to" another element, it can be directly on, directly connected to, or directly coupled to the other element, or there can be intervening elements. However, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element, there are no intervening elements. Other terms and / or phrases used to describe the relationship between elements should be interpreted in a similar manner, such as "between" versus "directly between," "adjacent" versus "immediately adjacent," "on" versus "directly on," etc. Further, the term "connected" can refer to a physical connection, an electrical connection, and / or a fluid connection. In addition, the DR1 axis, the DR2 axis, and the DR3 axis are not limited to the three axes of a rectangular coordinate system, and can be interpreted in a broader manner. For example, the DR1 axis, the DR2 axis, and the DR3 axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as, for example, XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0031] Although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, the first element discussed below may be referred to as the second element without departing from the teachings of the present disclosure.

[0032] Spatially relative terms such as "below," "beneath," "lower," "above," "upper," "above," "above," "side" (e.g., as in "sidewall"), etc. may be used herein for descriptive purposes and, therefore, describe the relationship of one element to another element as illustrated in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the accompanying drawings. For example, if the device in the drawings is flipped, an element described as "below" or "beneath" other elements or features would subsequently be oriented "above" the other elements or features. Thus, the exemplary term "below" can include both above and below orientations. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and, therefore, the spatially relative descriptors used herein are interpreted accordingly.

[0033] The terms used herein are for the purpose of describing specific embodiments and are not intended to be limiting. As used herein, the singular "a" and "the" are intended to also include the plural form, unless the context clearly indicates otherwise. In addition, when used in this specification, the terms "comprise" and / or "include" specify the presence of the features, integers, steps, operations, elements, parts and / or groups thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups thereof. It should also be noted that, as used herein, the terms "substantially", "approximately" and other similar terms are used as approximate terms and not as terms of degree, and therefore, are utilized to consider the inherent deviations in the numerical values ​​measured, calculated and / or provided that should be recognized by those of ordinary skill in the art.

[0034] Various exemplary embodiments are described herein with reference to cross-sectional views, isometric views, perspective views, plan views, and / or exploded views that are schematic illustrations of idealized exemplary embodiments and / or intermediate structures. Thus, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments disclosed herein should not be construed as limited to specific illustrated shapes of regions, but rather are intended to include deviations in shapes resulting, for example, from manufacturing. To this end, the regions illustrated in the accompanying drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of regions of the device and, therefore, are not intended to be limiting.

[0035] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly defined as such herein.

[0036] According to the convention of this field, some exemplary embodiments are described and illustrated according to functional blocks, units and / or modules. It will be understood by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits, such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, etc., which can be formed using semiconductor-based manufacturing technology or other manufacturing technology. In the case where blocks, units and / or modules are implemented by microprocessors or other similar hardware, software (such as microcode) can be used to program and control them to perform the various functions discussed herein, and they can be selectively driven by firmware and / or software. It should also be considered that each block, unit and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware that performs some functions and a processor (such as one or more programmed microprocessors and associated circuits) that performs other functions. In addition, each block, unit and / or module of some exemplary embodiments can be physically separated into two or more interacting and discrete blocks, units and / or modules without departing from the present invention. Further, the blocks, units and / or modules of some exemplary embodiments can be physically composed into more complex blocks, units and / or modules without departing from the present invention.

[0037] Hereinafter, various exemplary embodiments will be explained in detail with reference to the accompanying drawings.

[0038] Figure 1 is a perspective view of a display panel according to some exemplary embodiments. Figure 2 According to some exemplary embodiments Figure 1 A cross-sectional view of a display panel.

[0039] The display panel DP according to some exemplary embodiments may be applied to large-sized electronic devices such as monitors, outdoor billboards, etc., as well as small-sized and medium-sized electronic devices such as personal computers, notebook computers, personal digital terminals, car navigation units, game consoles, smartphones, tablet computers, cameras, etc. In addition, the above-mentioned devices are merely exemplified as some exemplary embodiments, and thus, the display panel DP may be used for other electronic devices.

[0040] According to some exemplary embodiments, the display panel DP may be at least one of a liquid crystal display panel, an electrophoretic display panel, a microelectromechanical system (MEMS) display panel, an electrowetting display panel, and an organic light emitting display panel, but exemplary embodiments are not limited thereto.

[0041] Although not shown separately, the display panel DP may further include a chassis member or a molding member, and when the display panel DP is, for example, a liquid crystal display panel, may further include a backlight unit. Hereinafter, the display panel DP will be described as an organic light emitting display panel.

[0042] Reference Figure 1 , the display panel DP may include a lower display substrate 100 and an upper display substrate 200 facing the lower display substrate 100 and spaced apart from the lower display substrate 100. Figure 1 As illustrated in FIG. 4 , the display panel DP may display an image through the display surface DP-IS. The display surface DP-IS is parallel to a surface defined by the first direction DR1 and the second direction DR2.

[0043] The display surface DP-IS may include a display area DA and a non-display area NDA. Pixels PX are arranged in the display area DA and not in the non-display area NDA. The non-display area NDA may be defined externally, for example, along an edge of the display surface DP-IS. According to some exemplary embodiments, the display area DA may be surrounded by the non-display area NDA. However, exemplary embodiments are not limited thereto. For example, the non-display area NDA may be adjacent to one side of the display area DA, or the non-display area NDA may be omitted.

[0044] The normal direction of the display surface DP-IS (for example, the thickness direction of the display panel DP) is indicated as a third direction DR3. In this specification, "when viewed on a plane", "when viewed on the plane", or "when viewed in a plan view" may mean viewing in the third direction DR3. The front side (or top surface) and the back side (or bottom surface) of each of the layers or units to be described below are distinguished by the third direction DR3. However, the directions indicated as the first direction to the third direction DR1, DR2, and DR3 as relative concepts may be changed to different directions, for example, opposite directions.

[0045] Although the display panel DP having a flat display surface DP-IS is illustrated as an example, exemplary embodiments are not limited thereto. The display panel DP may include a display surface having at least a portion thereof having a curved shape, or a display surface having a three-dimensional shape on a plane. The three-dimensional display surface may include a plurality of display areas indicating different directions.

[0046] Reference Figure 2 , an internal space GP may be defined between the upper display substrate 200 and the lower display substrate 100. The internal space GP may be maintained by an adhesive member SLM disposed between the upper display substrate 200 and the lower display substrate 100. For example, the adhesive member SLM may include at least one of an organic adhesive member and an inorganic adhesive member.

[0047] Figure 3A is a diagram illustrating a method according to some exemplary embodiments Figure 1 A plan view of the display panel. Figure 3B is an equivalent circuit diagram of a pixel according to some example embodiments.

[0048] Reference Figure 3A , which illustrates an arrangement relationship between the signal lines GL1 to GLn and DL1 to DLm and the pixels PX11 to PXnm on a plane. The signal lines GL1 to GLn and DL1 to DLm may include a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm.

[0049] Each of the pixels PX11 to PXnm is connected to a corresponding gate line among a plurality of gate lines GL1 to GLn and a corresponding data line among a plurality of data lines DL1 to DLm. As will become more apparent below, each of the pixels PX11 to PXnm may include a pixel drive circuit and a display element. Other and / or alternative types of signal lines may be provided in the display panel DP depending on the configuration of the pixel drive circuit.

[0050] The pixels PX11 to PXnm may be arranged in a matrix, but the exemplary embodiment is not limited thereto. The pixels PX11 to PXnm may be arranged in a honeycomb arrangement or any other suitable arrangement. For example, the pixels PX11 to PXnm may be arranged in a diamond shape.

[0051] The gate driving circuit GDC may be disposed in the non-display area NDA and may be integrated with the display panel DP through an oxide silicon gate driving circuit (OSG) process or an amorphous silicon gate driving circuit (ASG) process.

[0052] Reference Figure 3B , Figure 3A The pixel PX connected to one gate line GL, one data line DL, and the power line PL among the pixels PX11 to PXnm is illustrated as an example. However, the exemplary embodiment is not limited to the example shown in FIG. Figure 3B For example, the pixels PX may be formed differently in alternative and / or other configurations.

[0053] According to some exemplary embodiments, a pixel PX includes a light-emitting element OLED, a first electrode AE, a second electrode CE, and a pixel circuit PXC. According to some exemplary embodiments, the light-emitting element OLED can emit a first color light. Hereinafter, in this specification, the first color light is defined as blue light, but exemplary embodiments are not limited thereto. In addition, the light-emitting element OLED can include a light-emitting layer that generates its own light. Hereinafter, the light-emitting element OLED is described as an organic light-emitting element, but exemplary embodiments are not limited thereto.

[0054] The light emitting element OLED, the first electrode AE ​​and the second electrode CE may be provided in the display element layer DP-OLED (see Figure 5). The pixel PX includes a first transistor T1 (eg, a switching transistor), a second transistor T2 (eg, a driving transistor), and a capacitor Cap as a pixel circuit PXC for driving the light emitting element OLED. The pixel circuit PXC may be provided in the circuit element layer DP-CL (see Figure 5 ).

[0055] The light emitting element OLED generates first color light by an electrical signal supplied from the first transistor T1 and the second transistor T2.

[0056] The first transistor T1 outputs a data signal applied to the data line DL in response to a gate signal applied to the gate line GL. The capacitor Cap charges a voltage corresponding to the data signal received from the first transistor T1. A first power supply voltage ELVDD is supplied to the first electrode AE ​​through the second transistor T2, and a second power supply voltage ELVSS is supplied to the second electrode CE. The second power supply voltage ELVSS may be lower than the first power supply voltage ELVDD.

[0057] The second transistor T2 is electrically connected to the light emitting element OLED through the first electrode AE. The second transistor T2 controls the driving current ID flowing through the light emitting element OLED in response to the amount of charge stored in the capacitor Cap. The light emitting element OLED emits light during the on period of the second transistor T2.

[0058] Figure 4 According to some exemplary embodiments, Figure 1 A plan view of a pixel area in a display area of ​​a display panel. Figure 5 According to some exemplary embodiments Figure 1 A cross-sectional view of a portion of a pixel area of ​​a display panel.

[0059] For example, Figure 4 It is an icon Figure 1 The display area DA may include a plurality of pixel areas PXA and a light shielding area NPXA adjacent to the plurality of pixel areas PXA. Figure 4 The figure mainly illustrates three pixel areas PXA-R, PXA-G and PXA-B. Figure 4 The three pixel areas PXA-R, PXA-G, and PXA-B may be repeatedly arranged throughout the display area DA.

[0060] The light shielding area NPXA is arranged outside (e.g., around) the first to third pixel areas PXA-R, PXA-G, and PXA-B. The first to third pixel areas PXA-R, PXA-G, and PXA-B and the light shielding area NPXA may be substantially defined on the upper display substrate 200. In this specification, a pixel area means a region through which light actually passes as shown in FIG. Figure 1 The described display surface DP-IS is emitted to the area outside.

[0061] Although the first to third pixel regions PXA-R, PXA-G, and PXA-B having the same surface area on a plane are illustrated as an example Figure 4 The first to third pixel regions PXA-R, PXA-G, and PXA-B may have surface areas different from each other, or have at least two or more areas different from each other.

[0062] In addition, although each of the first to third pixel regions PXA-R, PXA-G, and PXA-B is shown as having a rectangular shape with rounded corners in a plane, exemplary embodiments are not limited thereto. The first to third pixel regions PXA-R, PXA-G, and PXA-B may have other polygonal shapes in a plane. Alternatively, each of the first to third pixel regions PXA-R, PXA-G, and PXA-B may have a square shape with rounded corners.

[0063] One pixel area among the first to third pixel areas PXA-R, PXA-G, and PXA-B may provide a user with first color light having a wavelength band of a first color, another pixel area among the first to third pixel areas PXA-R, PXA-G, and PXA-B may provide a user with second color light having a wavelength band of a second color different from the first color, and the remaining pixel areas may provide a user with third color light having a wavelength band of a third color different from the first and second colors.

[0064] For example, the first pixel region PXA-R may emit red light, the second pixel region PXA-G may emit green light, and the third pixel region PXA-B may emit blue light. According to some exemplary embodiments, the source light may be blue light as the first color light. The source light may be generated in a light source such as a backlight unit (not shown) or in a display element such as a light emitting diode.

[0065] The light blocking area NPXA may be provided at the boundaries between the first to third pixel areas PXA-R, PXA-G, and PXA-B to prevent or at least reduce (hereinafter collectively referred to as "prevent") colors from mixing with each other between the first to third pixel areas PXA-R, PXA-G, and PXA-B. Furthermore, the light blocking area NPXA may block source light so that the source light is not provided to the user.

[0066] For example, the display panel DP according to some exemplary embodiments may include a partition wall overlapping the light shielding area NPXA. The partition wall may prevent light output from two pixel areas adjacent to each other from mixing, and may improve the luminous efficiency of light emitted from each of the pixel areas. This will be referred to Figure 6 Describe in more detail.

[0067] Figure 5 The figure shows a cross-sectional view of the display panel DP corresponding to the second pixel region PXA-G and a cross-sectional view corresponding to the driving transistor TD and the light emitting element OLED. Figure 5 , a substrate 200 is shown schematically.

[0068] Reference Figure 5 , the lower display substrate 100 includes a first base substrate BS1, a circuit element layer DP-CL disposed on the first base substrate BS1, and a display element layer DP-OLED disposed on the circuit element layer DP-CL.

[0069] The first base substrate BS1 may include, for example, a synthetic resin substrate or a glass substrate. The circuit element layer DP-CL includes at least one insulating layer and circuit elements. The circuit elements include pixel signal lines and driver circuits. The circuit element layer DP-CL may be formed by forming at least one insulating layer, a semiconductor layer, and a conductive layer by coating or deposition, and patterning the at least one insulating layer, semiconductor layer, and conductive layer by photolithography.

[0070] In some exemplary embodiments, the circuit element layer DP-CL may include a buffer layer BFL, a first insulating layer 10, a second insulating layer 20, and a third insulating layer 30. For example, each of the first insulating layer 10 and the second insulating layer 20 may be an inorganic layer, and the third insulating layer 30 may be an organic layer. However, exemplary embodiments are not limited thereto. For example, each of the first insulating layer 10 and the second insulating layer 20 may be a layer in which an inorganic layer and an organic layer are mixed.

[0071] Figure 5 An example of an arrangement relationship of the semiconductor pattern OSP, the control electrode GE, the input electrode DE, and the output electrode SE constituting the drive transistor TD is illustrated. The first through hole CH1, the second through hole CH2, and the third through hole CH3 are exemplarily illustrated.

[0072] The display element layer DP-OLED includes a light-emitting element OLED as a display element. The light-emitting element OLED can generate the aforementioned source light. The light-emitting element OLED includes a first electrode AE, a second electrode CE, and an emission layer ENL disposed between the first electrode AE ​​and the second electrode CE. In some exemplary embodiments, the light-emitting element OLED may include an organic light-emitting diode. The display element layer DP-OLED includes a pixel-defining layer PDL. For example, the pixel-defining layer PDL may be an organic layer.

[0073] The first electrode AE ​​is disposed on the third insulating layer 30. The first electrode AE ​​is connected to the output electrode SE through a third through hole CH3 passing through the third insulating layer 30. A light emitting opening OP is defined in the pixel defining layer PDL. According to some exemplary embodiments, the light emitting opening OP may be defined as an emission area EA on (or in) which the first color light is emitted from the light emitting layer ENL.

[0074] The light emitting opening OP of (or in) the pixel defining layer PDL exposes at least a portion of the first electrode AE. According to some exemplary embodiments, the light emitting opening OP may be defined as an emission area EA from which actual light is emitted from the light emitting element OLED. A plurality of emission areas EA may be provided, and the plurality of emission areas EA may correspond to pixel areas, respectively.

[0075] The hole control layer HCL, the emission layer ENL, and the electron control layer ECL may be commonly disposed on the first electrode AE ​​and the pixel definition layer PDL. The hole control layer HCL, the emission layer ENL, and the electron control layer ECL may be commonly disposed on the first to third pixel regions PXA-R, PXA-G, and PXA-B (see Figure 4 ).

[0076] The hole control layer (HCL) may include a hole transport layer and may further include a hole injection layer. The light-emitting layer (ENL) may generate blue light. The blue light may have a wavelength of approximately 410 nm to approximately 480 nm. The emission spectrum of the blue light may have a maximum peak within a wavelength range of approximately 440 nm to approximately 460 nm. The electron control layer (ECL) may include an electron transport layer and may further include an electron injection layer. The light-emitting layer (ENL) may have a tandem (or multilayer) structure or a single-layer structure.

[0077] The second electrode CE is disposed on the electronic control layer ECL. The second electrode CE may be disposed collectively on the first to third pixel regions PXA-R, PXA-G, and PXA-B. The second electrode CE may have a surface area larger than that of the first electrode AE. A cover layer CL may be further disposed on the second electrode CE to protect the second electrode CE. The cover layer CL may include at least one of an organic material and an inorganic material. In some exemplary embodiments, the cover layer CL may be omitted.

[0078] Although not separately shown, the lower display substrate 100 may include Figure 4 The first to third light emitting elements corresponding to the first to third pixel regions PXA-R, PXA-G, and PXA-B. The first to third light emitting elements may have the same stacked structure as each other, and may also have the same stacked structure as each other. Figure 5 The light emitting element OLED has the same stacked structure, but the exemplary embodiments are not limited thereto.

[0079] Figure 6 According to some exemplary embodiments Figure 1 A cross-sectional view of an upper display substrate of a display panel. Figure 7A is a plan view illustrating a stacked structure of an upper display substrate according to some example embodiments. Figure 7B is a plan view illustrating a stacked structure of an upper display substrate according to some example embodiments. Figure 7C is a schematic diagram illustrating light characteristics of a light management layer according to some example embodiments. Figure 8 is a perspective view of a partition wall according to some exemplary embodiments. Figure 9 is a diagram illustrating a method according to some exemplary embodiments Figure 6 A cross-sectional view of a portion of a display panel.

[0080] Reference Figure 6 The upper display substrate 200 includes a second base substrate BS2, first to third color filters CF-R, CF-G, and CF-B, a first upper insulating layer IL, a light-control layer CCL, and a second upper insulating layer RL. Although not separately shown, according to some exemplary embodiments, when display elements corresponding to the first to third pixel regions PXA-R, PXA-G, and PXA-B generate light having different colors from each other, the light-control layer CCL may be omitted.

[0081] The first to third color filters CF-R, CF-G, and CF-B may be arranged on the second base substrate BS2. The first to third color filters CF-R, CF-G, and CF-B may be defined as constituent elements provided in the color filter layer. According to some exemplary embodiments, the first to third color filters CF-R, CF-G, and CF-B may be directly arranged on the second base substrate BS2.

[0082] In this specification, “constituent element A is directly disposed on constituent element B” may mean that an adhesive member is not disposed between constituent element A and constituent element B. For example, the first to third color filters CF-R, CF-G, and CF-B may be directly disposed on the second base substrate BS2 without using an adhesive layer.

[0083] The first color filter CF-R may overlap with the first pixel region PXA-R to transmit light having a wavelength range of a second color different from the first color and absorb light having other wavelength ranges. For example, the second color may be red. The second color filter CF-G may overlap with the second pixel region PXA-G to transmit light having a wavelength range of a third color different from the second color and absorb light having other wavelength ranges. For example, the third color may be green. The third color filter CF-B may overlap with the third pixel region PXA-B to transmit light corresponding to the wavelength range of the first color and absorb light having other wavelength ranges.

[0084] According to some exemplary embodiments, the first to third color filters CF-R, CF-G, and CF-B overlapping the display area DA may be separated by the light blocking layer SHD or the light blocking portion BP2.

[0085] According to some exemplary embodiments, the third color filter CF-B may be provided with a refractive index similar to that of the second base substrate BS2, but not similar to the refractive index of each of the first color filter CF-R and the second color filter CF-G. As a result, external light introduced from the outside can pass through the second base substrate BS2 and then be incident on the third color filter CF-B. Therefore, external light reflection occurring at the interface between the second base substrate BS2 and the third color filter CF-B can be reduced. However, exemplary embodiments are not limited thereto. For example, each of the first to third color filters CF-R, CF-G, and CF-B may have a refractive index similar to that of the second base substrate BS2.

[0086] The third color filter CF-B may be divided into a filter portion BP1 serving as a color filter and a light shielding portion BP2 performing a light shielding function. The filter portion BP1 may overlap the third pixel region PXA-B, and the light shielding portion BP2 may overlap the light shielding region NPXA.

[0087] For example, refer to Figure 7A An organic layer having a blue color is formed on one surface of the second base substrate BS, and then the organic layer may be exposed and developed to form a third color filter CF-B having a first opening B-OP1 and a second opening B-OP2. The filter portion BP1 and the light shielding portion BP2 may be provided as a single body.

[0088] Reference Figure 7B , the first color filter CF-R is arranged in the first opening B-OP1 defined in the third color filter CF-B. In a plan view, the first color filter CF-R can completely cover the first opening B-OP1 and can be arranged on at least a portion of the light shielding portion BP2. The second color filter CF-G is arranged in the second opening B-OP2 defined in the third color filter CF-B. In a plan view, the second color filter CF-G can completely cover the second opening B-OP2 and can be arranged on at least a portion of the light shielding portion BP2.

[0089] Refer again Figure 6 , a light shielding layer SHD may be disposed on the light shielding portion BP2 of the third color filter CF-B. A portion of the first color filter CF-R and a portion of the second color filter CF-G may each be disposed on the light shielding layer SHD. The edge of the first color filter CF-R and the light shielding layer SHD may absorb external light transmitted through the light shielding portion BP2 to prevent colors from mixing between the first to third pixel regions PXA-R, PXA-G, and PXA-B. In addition, the light shielding layer SHD may absorb a portion of the light output from the light control layer CCL.

[0090] The first upper insulating layer IL may cover the first to third color filters CF-R, CF-G, and CF-B and may be disposed on the second base substrate BS2. For example, the first upper insulating layer IL may be provided as an inorganic layer.

[0091] The light control layer CCL is disposed on the first upper insulating layer IL. The light control layer CCL can control the light from the display element layer DP-OLED (see Figure 5 For example, the light-controlling layer CCL may convert the first color light into light of a different color or transmit the first color light as it is.

[0092] The light-control layer CCL includes a first conversion portion CCF-R, a second conversion portion CCF-G, and a transmissive portion CCF-B. The first conversion portion CCF-R may overlap with the first pixel region PXA-R to convert the first color light and thereby emit light having a second color different from the first color. The second conversion portion CCF-G may overlap with the second pixel region PXA-R to convert the first color light and thereby emit light having a third color different from the second color. The transmissive portion CCF-B may overlap with the third pixel region PXA-B to transmit the first color light.

[0093] The second upper insulating layer RL may cover the light-control layer CCL and may be disposed on the first upper insulating layer IL. For example, the second upper insulating layer RL may be provided as an inorganic layer.

[0094] For example, refer to Figure 7C The first luminescent material EP-R may absorb the first color light, which is blue light, and emit the second color light, which is red light. The second luminescent material EP-G may absorb the first color light and emit the third color light, which is green light. The transmissive portion CCF-B may be a portion that does not include the luminescent material. The transmissive portion CCF-B may be a portion that transmits the first color light.

[0095] Each of the first conversion part CCF-R, the second conversion part CCF-G, and the transmission part CCF-B may include a base resin BR. The base resin BR may be a polymer resin. For example, the base resin BR may include at least one of an acrylic resin, a polyurethane resin, a silicon resin, and an epoxy resin. The base resin BR may be a transparent resin.

[0096] In some exemplary embodiments, each of the first conversion portion CCF-R, the second conversion portion CCF-G, and the transmissive portion CCF-B may include scattering particles OL. The scattering particles OL may be at least one of titanium dioxide (TiO2) and silicon dioxide-based nanoparticles. The scattering particles OL may scatter light emitted from the luminescent material to the outside of the conversion portion. In addition, when a member such as the transmissive portion CCF-B transmits light as it is, the scattering particles OL may scatter the provided light to emit it to the outside.

[0097] The first luminescent material EP-R and the second luminescent material EP-G (hereinafter referred to as luminescent materials) included in the light-control layer CCL may be at least one of phosphors and quantum dots. For example, according to some exemplary embodiments, the light-control layer CCL may include at least one of phosphors and quantum dots as the luminescent materials EP-R and EP-G.

[0098] For example, the phosphor used as the luminescent materials EP-R and EP-G may be an inorganic phosphor. The phosphor used as the luminescent materials EP-R and EP-G in the display panel DP according to some exemplary embodiments may be at least one of a green phosphor and a red phosphor.

[0099] The kind of phosphor used in the light control layer CCL according to some exemplary embodiments is not limited to the disclosed materials, and thus, well-known phosphor materials may be used instead of or in addition to the above-described phosphors.

[0100] In some exemplary embodiments, the luminescent materials EP-R and EP-G included in the light-control layer CCL may be quantum dots, which may be selected from II-VI compounds, III-V compounds, IV-VI compounds, IV elements, IV compounds, and / or combinations thereof.

[0101] The II-VI compound may be selected from a binary compound, a ternary compound, and a quaternary compound, the binary compound being selected from the group consisting of CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe, MgS, and / or a combination comprising at least one of the binary compounds, and the ternary compound being selected from the group consisting of AgInS, CuInS, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZn Se, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, MgZnSe, MgZnS and / or a combination including at least one of the ternary compounds, and the quaternary compound is selected from the group consisting of HgZnTeS, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, HgZnSTe and / or a combination including at least one of the quaternary compounds.

[0102] The Group I-III-VI compound may be selected from a ternary compound or an elemental compound such as AgInGaS2, CuInGaS2, the ternary compound being selected from the group consisting of AgInS2, CuInS2, AgGaS2, CuGaS2 and mixtures thereof.

[0103] The III-V compound may be selected from a binary compound, a ternary compound, and a quaternary compound, the binary compound being selected from the group consisting of GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb and / or a combination including at least one of the binary compounds, the ternary compound being selected from the group consisting of GaNPs, GaNAs, GaNSb, GaPAs, GaPSb, AlNPs, AlNAs, AlNSb, AlPAs, AlPSb, InGaP, InAlP, InNP, InNAs, InNSb, InPAs, InPSb and / or a combination including at least one of the ternary compounds, the quaternary compound being selected from the group consisting of GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs, InAlPSb and / or a combination including at least one of the quaternary compounds. Meanwhile, the III-V compound may further include a II metal. For example, InZnP or the like may be selected as the III-II-V compound.

[0104] The IV-VI compound may be selected from a binary compound, a ternary compound, and a quaternary compound. The binary compound is selected from the group consisting of SnS, SnSe, SnTe, PbS, PbSe, PbTe, and / or a combination comprising at least one of the binary compounds. The ternary compound is selected from the group consisting of SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, SnPbTe, and / or a combination comprising at least one of the ternary compounds. The quaternary compound is selected from the group consisting of SnPbSSe, SnPbSeTe, SnPbSTe, and / or a combination comprising at least one of the quaternary compounds. The Group IV element may be selected from the group consisting of Si, Ge, and / or a combination thereof. The Group IV compound may be a binary compound selected from the group consisting of SiC, SiGe, and / or a combination thereof.

[0105] Binary, ternary, and quaternary compounds may be present in the particle at a uniform concentration, or in a state where the concentration distribution is partitioned into partially different states. Alternatively, the quantum dot may have a core-shell structure in which one quantum dot surrounds another quantum dot. The interface between the core and the shell may have a concentration gradient in which the concentration of the element present in the shell gradually decreases toward the center.

[0106] In some exemplary embodiments, the quantum dot may have a core-shell structure comprising: a core comprising the above-described nanocrystals and a shell surrounding the core. The shell of the quantum dot may serve as a protective layer to prevent the core from chemically changing to maintain semiconductor properties and / or perform the function of a charging layer for imparting electrophoretic properties to the quantum dot. The shell may be a single-layer or multi-layer structure. The interface between the core and the shell may have a concentration gradient in which the elements present in the shell have a concentration that gradually decreases toward the center. For example, the shell of the quantum dot may include a metal or non-metal oxide, a semiconductor compound, or a combination thereof.

[0107] For example, the oxide of a metal or non-metal may include at least one of a binary compound and a ternary compound, a binary compound such as at least one of SiO2, Al2O3, TiO2, ZnO, MnO, Mn2O3, Mn3O4, CuO, FeO, Fe2O3, Fe3O4, CoO, Co3O4, NiO, etc., and a ternary compound such as at least one of MgAl2O4, CoFe2O4, NiFe2O4, CoMn2O4, etc., but exemplary embodiments are not limited thereto.

[0108] The semiconductor compound may include at least one of CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnSeS, ZnTeS, GaAs, GaP, GaSb, HgS, HgSe, HgTe, InAs, InP, InGaP, InSb, AlAs, AlP, AlSb, etc., but exemplary embodiments are not limited thereto.

[0109] Quantum dots can have an emission wavelength spectrum with a full width at half maximum (FWHM) of about 45 nm or less (such as about 40 nm or less, for example, about 30 nm or less). Within this range, color purity and color reproducibility can be improved. In addition, light emitted by quantum dots can be emitted in all directions to improve the optical viewing angle.

[0110] In some exemplary embodiments, the quantum dots have shapes commonly used in the art and are not particularly limited in shape. For example, the quantum dots may have spherical shapes, conical shapes, multi-arm shapes, three-dimensional nanoparticle shapes, nanotube shapes, nanowire shapes, nanofiber shapes, nanoplate particle shapes, etc.

[0111] Quantum dots can adjust the color of emitted light based on their size. In this way, quantum dots can emit light of various colors, such as blue, red, and green. When each of the first luminescent material EP-R and the second luminescent material EP-G is a quantum dot, the particle size of the first luminescent material EP-R and the particle size of the second luminescent material EP-G can be different. For example, the first luminescent material EP-R can have a larger particle size than the second luminescent material EP-G. The first luminescent material EP-R can emit light having a longer wavelength than the wavelength of light emitted from the second luminescent material EP-G.

[0112] Refer again Figure 6 , as referenced Figure 2 As described above, an inner space GP may be defined between the upper display substrate 200 and the lower display substrate 100. For example, the display element layer DP-OLED and the light control layer CCL may be spaced apart from each other in the third direction DR3 due to the inner space GP between the upper display substrate 200 and the lower display substrate 100.

[0113] It should be noted that the first color light emitted from the display element layer DP-OLED may not be accurately transmitted to the light control layer CCL due to the spacing. As a result, the overall visibility of the display panel DP may deteriorate. For example, light may be emitted from the first pixel area to the second pixel area PXA-G and the third pixel area PXA-B among the third pixel areas PXA-R, PXA-G, and PXA-B. In this case, the first color light may be emitted from each of the two light-emitting elements OLED overlapping with the second pixel area PXA-G and the third pixel area PXA-B, and the first color light may not be emitted from the light-emitting element OLED overlapping with the first pixel area PXA-R. However, a portion of the first color light emitted from each of the two light-emitting elements OLED may be transmitted to the first conversion part CCF-R overlapping with the first pixel area PXA-R due to the spacing. As a result, the second color light can be emitted from the first conversion part CCF-R and visible from the outside through the first pixel area PXA-R.

[0114] According to some exemplary embodiments, the display panel DP may be arranged on (or include) the light control layer CCL and include a partition wall DM overlapping the light shielding area NPXA. The partition wall DM may completely overlap the light shielding area NPXA and have a predetermined height in the third direction DR3. Here, the third direction DR3 may be a thickness direction of the upper display substrate 200.

[0115] Partition walls DM according to some exemplary embodiments can prevent the colors of light emitted to the outside through the upper display substrate 200 from mixing with each other. For example, the first color light emitted from one light-emitting element OLED can be emitted to the outside through the pixel region overlapping with the one light-emitting element OLED in the pixel area PXA. For example, the first color light emitted from one light-emitting element OLED can be prevented from being transmitted through the partition wall DM to other pixel regions in the pixel area PXA that do not overlap with the one light-emitting element OLED. In addition, partition walls DM according to some exemplary embodiments can improve the luminous efficiency of light emitted to the outside through the pixel region.

[0116] Reference Figure 8 , the partition wall DM may be disposed on the second upper insulating layer RL overlapping the light-shielding area NPXA. Hereinafter, for convenience of description and illustration, it is assumed that the second upper insulating layer RL disposed between the partition wall DM and the control layer CCL is omitted, and a structure in which the partition wall DM is disposed on the light-control layer CCL will be described. In practice, the second upper insulating layer RL may be omitted.

[0117] According to some exemplary embodiments, the partition wall DM may include a partition wall portion PC and a reflective portion RC covering the partition wall portion PC.

[0118] The partition wall portion PC may surround the first to third pixel regions PXA-R, PXA-G, and PXA-B on a plane, and may extend from the light control layer CCL at a predetermined height in the third direction DR3. At least a portion of the partition wall portion PC may be arranged on the top surface of the light control layer CCL, and the other portion of the partition wall portion PC may be arranged on the light shielding portion BP2 of the third color filter CF-B. For example, the other portion of the partition wall portion PC may be arranged on the first conversion portion CCF-R, the second conversion portion CCF-G, and the transmission portion CCF-B of the light control layer CCL. In this specification, being arranged on the same layer means that two constituent elements that are different from each other are directly arranged on one constituent element.

[0119] The partition wall portion PC may have a color that absorbs a wavelength range of the first color light. For example, the partition wall portion PC may have a black color.

[0120] The reflective portion RC may overlap with the light shielding area NPXA and cover at least a portion of the partition wall portion PC. Figure 8 As shown in FIG, the reflective portion RC may completely cover the outer surface of the partition wall portion PC and may be disposed on the light control layer CCL. The reflective portion RC may be made of a material having a high reflectivity. For example, the reflective portion RC may be made of a metal material such as aluminum, copper, or the like.

[0121] According to some exemplary embodiments, since the reflective portion RC is made of a metallic material and covers the outer surface of the partition wall portion PC, luminous efficiency of light transmitted to the light-controlling layer CCL may be improved.

[0122] For example, refer to Figure 9 , the lower display substrate 100 includes an emission area EA through which the first color light is emitted and a non-emission area NEA adjacent to the emission area EA. Figure 9 A case where the first color light emitted from the emission area EA is transmitted to a conversion portion CCFz provided in the light control layer CCL.

[0123] As described above, the first color light emitted by one emission area EA can be transmitted not only in a direction facing the conversion part CCFz, but also in a direction facing another conversion part overlapping another pixel area. Hereinafter, the first color light emitted by the emission area EA in a direction facing the conversion part CCFz is defined as first light, and the light emitted in a direction facing another conversion part is defined as second light.

[0124] According to some embodiments, the reflective portion RC of the partition wall DM can reflect the second light to transmit the second light to the conversion portion CCFz. As a result, the amount of light transmitted from the emission area EA to the conversion portion CCFz can be increased. In addition, because the amount of light transmitted to the conversion portion CCFz is increased, the luminous efficiency of light emitted to the outside through the pixel area PXA overlapping with the conversion portion CCFz can be improved. Therefore, the overall visibility of the display panel DP can also be improved.

[0125] According to some exemplary embodiments, Figure 6 and Figure 9 As shown in FIG, the partition wall DM may be spaced apart a predetermined distance from the lower display substrate 100. In addition, the partition wall DM may have a predetermined height from the upper display substrate 200 in the third direction DR3.

[0126] For example, in the third direction DR3, the height between the light control layer CCL of the upper display substrate 200 and the lower display substrate 100 is defined as a first length D1a, and the height of the partition wall DM is defined as a second length D1b. In this case, the second length D1b may be approximately 0.6 to 0.95 times the first length D1a. Because the partition wall DM has the second length D1b, a larger amount of second light can be reflected by the partition wall DM.

[0127] In some exemplary embodiments, the partition wall portion PC includes a first portion PCa and a second portion PCb adjacent to the first portion PCa. The first portion PCa and the second portion PCb may be integrated with each other. That is, the first portion PCa and the second portion PCb may be formed by the same process.

[0128] The first portion PCa may overlap the light shielding area NPXA and be arranged in a space between two adjacent portions of the first conversion portion CCF-R, the second conversion portion CCF-G, and the transmission portion CCF-B. For example, the first portion PCa may be a portion arranged on the color filter layer together with the first conversion portion CCF-R, the second conversion portion CCF-G, and the transmission portion CCF-B. For example, the first portion PCa may overlap the light shielding area NPXA and be arranged in a space between two adjacent portions of the first conversion portion CCF-R, the second conversion portion CCF-G, and the transmission portion CCF-B. Figure 6 The shading layers SHD completely overlap.

[0129] The second portion PCb may be a portion disposed on the bottom surface of each of the first conversion portion CCF-R, the second conversion portion CCF-G, and the transmissive portion CCF-B, facing downwardly from the display substrate 100. The second portion PCb may have a width D2a, in plan view, that is greater than the width D2b of the first portion PCa. In this specification, the outer surface of the partition wall DM refers to the outer surface of the second portion PCb. In other words, the outer surface of the partition wall DM refers to the second portion PCb exposed to the internal space GP.

[0130] According to some exemplary embodiments, the second portion PCb may have a height greater than that of the first portion PCa in the third direction DR3. Figure 9 The described second length D1b of the partition wall DM means the height of the second portion PCb.

[0131] In addition, according to some exemplary embodiments, a filler CPz may be disposed in the inner space GP between the upper display substrate 200 and the lower display substrate 100. In this case, since the partition wall DM is spaced a predetermined distance from the lower display substrate 100, the filler CPz may be completely disposed in the inner space GP. The filler CPz may be provided as a transparent material to constantly maintain the spacing distance between the upper display substrate 200 and the lower display substrate 100.

[0132] Figure 10 is a cross-sectional view of a display panel according to some exemplary embodiments. Figure 10 The display panel DPa is substantially the same as the display panel DP except for the structure of the partition wall DMa. Figure 10 The structure of the partition wall DMa will be mainly described.

[0133] Reference Figure 10, the partition wall DMa includes a partition wall portion PC and reflecting portions RC1a and RC1b spaced apart from each other, with the partition wall portion PC between the reflecting portions RC1a and RC1b.

[0134] According to some exemplary embodiments, the reflective portions RC1a and RC1b may expose at least a portion of the partition wall portion PC. The at least a portion of the partition wall portion PC may be an outer surface of the partition wall portion PC that is exposed to the inner space GP and faces downwardly toward the display substrate 100. The reflective portions RC1a and RC1b may be spaced apart from a partial portion of the partition wall portion PC that is exposed to the inner space GP.

[0135] When the first color light emitted from the display element layer PD-OLED of the lower display substrate 100 is transmitted through the partial portion, the first color light may be absorbed by the partition wall portion PC.

[0136] Figure 11A is a cross-sectional view of a display panel according to some exemplary embodiments. Figure 11B is a cross-sectional view of a display panel according to some exemplary embodiments.

[0137] Figure 11A and Figure 11B The display panel DPb may be substantially similar to Figure 10 The display panel DPa has a structure other than the partition wall DMb. Therefore, for the convenience of description, reference will be made to Figure 11A and Figure 11B The structure of the partition wall DMb will be mainly described.

[0138] Reference Figure 11A and Figure 11B , the partition wall DMb may contact the lower display substrate 100. That is, the plurality of spaces SP may be defined by the partition wall DMb, the upper display substrate 200, and the lower display substrate 100. The plurality of spaces SP may overlap with the plurality of pixels PXA, respectively.

[0139] The partition wall DMb includes a partition wall portion PC and reflective portions RC2a and RC2b spaced apart from each other with the partition wall portion PC between the reflective portions RC2a and RC2b. The reflective portions RC2a and RC2b may expose at least a portion of the partition wall portion PC.

[0140] According to some exemplary embodiments, each of the reflective portions RC2a and RC2b and the partition wall portion PC exposed by the reflective portions RC2a and RC2b may contact the lower display substrate 100. For example, referring to Figure 11A, each of the reflective portions RC2a and RC2b and the partition wall portion PC exposed by the reflective portions RC2a and RC2b may be directly disposed on the cover layer CL of the display element layer DP-OLED.

[0141] In comparison, reference Figure 11B , the reflective portions RC2a and RC2b and the partition wall portion PC exposed by the reflective portions RC2a and RC2b may be directly disposed on the second electrode CE of the display element layer DP-OLED. In this case, the cover layer CL may be omitted.

[0142] Although the reference Figure 11A and Figure 11B A structure in which at least a portion of the partition wall portion PC is exposed by the reflective portions RC2a and RC2b is described, but exemplary embodiments are not limited thereto. For example, the reflective portions RC2a and RC2b may completely cover the outer surface of the partition wall portion PC.

[0143] According to various exemplary embodiments, the partition walls can prevent colors output to the outside through the upper display substrate from mixing with each other. For example, light of a first color emitted from one light-emitting element can be prevented from transmitting to another pixel region that does not overlap with the first light-emitting element. Furthermore, the partition walls according to various exemplary embodiments can improve the luminous efficiency of light emitted to the outside through the pixel region. Thus, the overall display quality of the display panel can be improved.

[0144] Although certain exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concept is not limited to these embodiments, but rather to the broader scope of the appended claims and various obvious modifications and equivalent arrangements that will be apparent to those skilled in the art.

Claims

1. A display panel, comprising: a lower display substrate comprising a display element configured to emit light having a first color; a light control layer overlapping the display element and configured to control the light having the first color to provide the controlled light to a pixel area; as well as a partition wall including a partition wall portion overlapping a light shielding region adjacent to the pixel region and a reflective portion disposed on the partition wall portion and between the lower display substrate and the light control layer, The partition wall is spaced a predetermined distance from the lower display substrate. Wherein, the display panel further comprises: an insulating layer disposed between the light control layer and the partition wall and covering the light control layer, wherein: A height between the insulating layer and the lower display substrate is defined as a first length in a thickness direction of the lower display substrate; The height of the partition wall is defined as a second length in the thickness direction; and The second length is 0.6 to 0.95 times the first length.

2. The display panel according to claim 1, wherein The reflective portion exposes at least a portion of the partition wall portion facing the lower display substrate.

3. The display panel according to claim 1, wherein: The pixel region includes a first pixel region, a second pixel region, and a third pixel region arranged in one direction; and The light control layer comprises: a first conversion portion overlapping the first pixel area and configured to convert the light having the first color so as to emit light having a second color different from the first color; a second conversion portion overlapping the second pixel area and configured to convert the light having the first color so as to emit light having a third color different from the second color; and A transmissive portion overlaps the third pixel region and is configured to transmit the light having the first color.

4. The display panel according to claim 3, wherein: The partition wall portion includes: a first portion disposed in a space between two adjacent portions of the first conversion portion, the second conversion portion, and the transmission portion; and A second portion is adjacent to the first portion and is arranged on bottom surfaces of the two adjacent portions.

5. The display panel according to claim 4, wherein: In a thickness direction of the lower display substrate, a height of the second portion is greater than a height of the first portion. The display panel according to claim 4 , wherein: The width of the second portion is greater than the width of the first portion.

7. The display panel according to claim 1, further comprising: a base substrate disposed on the light control layer; as well as An adhesive member is disposed between the base substrate and the lower display substrate, wherein an inner space is defined between the base substrate and the lower display substrate.

8. The display panel according to claim 7, further comprising: A filler is disposed in the interior space.

9. The display panel according to claim 1, further comprising: a base substrate disposed on the lower display substrate; as well as a color filter layer disposed on a lower surface of the base substrate facing the lower display substrate, The light control layer is disposed on a lower surface of the color filter layer facing the lower display substrate.

10. The display panel according to claim 9, wherein: The pixel region includes a first pixel region, a second pixel region, and a third pixel region arranged in one direction; and The color filter layer includes: a first color filter overlapping the first pixel region and configured to transmit light having a second color different from the first color; a second color filter overlapping the second pixel region and configured to transmit light having a third color different from the second color; and A third color filter overlaps the third pixel region and is configured to transmit the light having the first color.

11. The display panel according to claim 10, wherein: The third color filter includes: a filter portion overlapping the third pixel region; and A light-shielding portion overlapping the light-shielding area.

12. The display panel according to claim 11, wherein: The color filter layer is disposed directly on the lower surface of the base substrate; and At least a portion of the partition wall overlaps with the light shielding region.

13. The display panel according to claim 1, wherein: The color of the partition wall is black.

14. A display panel comprising: a lower display substrate comprising a display element configured to emit light having a first color; a light control layer overlapping the display element and configured to control the light having the first color to provide the controlled light to a pixel area; a partition wall including a partition wall portion overlapping a light shielding region adjacent to the pixel region and a reflective portion disposed on the partition wall portion and between the lower display substrate and the light control layer; as well as an insulating layer disposed between the light control layer and the partition wall and covering the light control layer, wherein: the partition wall contacts each of the insulating layer and the lower display substrate; and Spaces respectively overlapping the pixel areas are defined by the partition walls, the insulating layer, and the lower display substrate.

15. The display panel according to claim 14, wherein: The reflecting portion exposes at least a portion of the partition wall portion; and The exposed portion of the partition wall portion contacts the lower display substrate.

16. The display panel according to claim 14, wherein: The lower display substrate comprises: a lower base substrate; a circuit element layer disposed on the lower base substrate; and A display element layer is arranged on the circuit element layer and includes the display element; and the partition wall contacts the display element layer.

17. The display panel according to claim 16, wherein: The display element layer further includes a cover layer disposed on the display element; and The partition wall is arranged on the cover layer.

18. A display panel comprising: an upper display substrate, the upper display substrate comprising a pixel area and a light shielding area adjacent to the pixel area; a lower display substrate, the lower display substrate including display elements respectively overlapping the pixel areas; as well as a partition wall disposed between the upper display substrate and the lower display substrate, the partition wall including a partition wall portion overlapping the light shielding region and a reflective portion covering the partition wall portion, in: A height between the upper display substrate and the lower display substrate is defined as a first length in a thickness direction of the upper display substrate; The height of the partition wall is defined as a second length in the thickness direction; and The second length is 0.6 to 0.95 times the first length.

19. The display panel according to claim 18, wherein: The reflective portion exposes at least a portion of the partition wall portion facing the lower display substrate.

Images