A method for eliminating current overshoot and a switching circuit

Abstract

The present invention provides a method and a switching circuit for eliminating current overshoot, belonging to the field of switching power supplies, including determining whether the system has entered a power-off state; if the system has entered a power-off state, activating a power-off protection device; when the power-off time reaches a preset time, and the preset time is greater than the bus voltage VM cycle time, an integrator performs reverse integration. The present invention provides a method for eliminating current overshoot, according to which the error signal V comp The signal rise is limited, and after power is restored, the current overshoot is also limited, which can greatly reduce the output current overshoot phenomenon.

Description

Technical Field

[0001] The present invention belongs to the field of switching power supplies, and more particularly, relates to a method for eliminating current overshoot and a switching circuit. Background Art

[0002] In the design and implementation of switching power supply circuits, the integration loop is a common circuit (such as Figure 1 、 Figure 2 ). refer to Figure 1 After the mains passes through the rectifier bridge, it outputs a DC signal VM (bus voltage) to provide energy to the switching power supply. The switching power supply consists of an error amplifier (EA), a driver, a switching network, and a feedback circuit. The feedback circuit samples the output voltage or current and other electrical parameters to obtain a feedback signal V fb , and then fed back to one input terminal of the error amplifier (such as the inverting input terminal), and the reference potential V ref Compare and amplify, and output an error signal V at the output end of EA comp When the feedback signal V fb Lower than V ref When the error signal V comp Increase; on the contrary, when the feedback signal V fb Greater than V ref When the error signal V comp Reduce. Error signal V comp The driver compares the signal with a sawtooth wave (or triangle wave) to obtain a PWM (Pulse-width-modulation) signal with a variable duty cycle. pwm . V pwm The power switch tube M1 in the driving switch network is turned on and off. The switching of M1 controls the energy storage device, such as the inductor L, to store and release energy, thereby controlling the output voltage or current to reach a preset value.

[0003] exist Figure 1 and Figure 2 In the switching integral loop power supply circuit, if the input mains power is off (the wall switch is turned off), the output voltage and current drop until they are reduced to zero, then the feedback electrical parameter V fb The signal will also gradually decrease, resulting in the error signal V comp Gradually increases until it is much higher than the stable V comp Value. Reference Figure 4 If the system is powered on again, the error signal is much larger than the V comp value, the duty cycle of the PWM signal generated by the driver is relatively large, resulting in the output current I LIt is also much larger than the current in steady state, which causes current overshoot and damages the reliability of the system. Summary of the Invention

[0004] The present invention aims to provide a method and a switching circuit for eliminating current overshoot, aiming to solve the technical problem that when the existing switching power supply system is powered on again after a power failure, current overshoot is easily caused, thereby damaging the reliability of the system.

[0005] To achieve the above object, the present invention adopts a technical solution of providing a method for eliminating current overshoot and a switching circuit, comprising:

[0006] Determine whether the system has entered the power-off state;

[0007] When the system enters the power-off state, the power-off protection device is activated;

[0008] When the power-off time reaches a preset time and the preset time is greater than the bus voltage VM cycle time, the integrator performs reverse integration.

[0009] Furthermore, determining whether the system enters a power-off state includes:

[0010] Get the power-off parameters and determine whether the system has entered the power-off state based on the change status of the power-off parameters.

[0011] Furthermore, obtaining the power-off parameter and determining whether the system enters the power-off state according to the change state of the power-off parameter includes:

[0012] Obtaining a bus voltage VM, where the bus voltage VM is lower than a power-off threshold voltage and the bus voltage VM continues to decrease; and determining that the system enters a power-off state.

[0013] Furthermore, obtaining the power-off parameter and determining whether the system enters the power-off state according to the change state of the power-off parameter includes:

[0014] The sampling resistor current or voltage is obtained. When the sampling resistor current or voltage is lower than a threshold and continues to decrease, it is determined that the system enters a power-off state.

[0015] Furthermore, the method further includes obtaining power-off parameters and determining whether to end the power-off state.

[0016] Furthermore, the obtaining of power-off parameters and determining whether to end the power-off state includes:

[0017] The bus voltage VM is obtained. If the bus voltage VM is higher than the power-on threshold, the system ends the power-off state and the integrator returns to the original state.

[0018] Furthermore, the obtaining of power-off parameters and determining whether to end the power-off state includes:

[0019] A sampling resistor parameter is obtained. If the sampling resistor parameter is higher than a power-on threshold, the system ends the power-off state and the integrator returns to an original state.

[0020] Furthermore, the sampling resistor parameters include the sampling resistor voltage or the sampling resistor current

[0021] Furthermore, the reverse integration time is between 0-.

[0022] Furthermore, the reverse integration time is.

[0023] Furthermore, the reverse integration time is greater than.

[0024] The present invention also provides a switching circuit, characterized in that it includes a power-off protection device, which controls the integrator according to the method described above.

[0025] Furthermore, the power-off protection device includes a power-off detection device and a power-off timer. The power-off detection device detects the bus voltage VM and controls the operation of the integrator according to the timing of the power-off timer.

[0026] Furthermore, the power-off protection device includes a power-off detection device and a power-off timer. The power-off detection device detects electrical parameters of the sampling resistor and controls the operation of the integrator according to the timing of the power-off timer.

[0027] Furthermore, the integrator includes an error amplifier EA and an integrating capacitor C connected in series with the error amplifier EA. comp .

[0028] Furthermore, the integrator is a digital integrator.

[0029] The beneficial effect of the method for eliminating current overshoot and the switch circuit provided by the present invention is that: compared with the prior art, the method for eliminating current overshoot provided by the present invention, according to the method, when the integrator reaches , the symmetrical reverse integration period, at this time the error signal V comp The signal is 0, and there is no overshoot after power is turned on again. In another case, as long as the integrator integrates in reverse, the error signal V comp The present invention provides a switch circuit that reduces or eliminates the current overshoot phenomenon when it is powered on again after a power-off process, causing less damage to the switch circuit and extending the service life of the switch circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0031] Figure 1 An integral loop circuit diagram provided by the prior art;

[0032] Figure 2 Another integrating loop circuit diagram provided in the prior art;

[0033] Figure 3 A schematic diagram of the relative relationship among the error signal, bus voltage, and output current after the loop system provided by the prior art is stabilized.

[0034] Figure 4 A schematic diagram of the relative relationship among the error signal, bus voltage, and output current when the loop system provided by the prior art is powered on again.

[0035] Figure 5 This is a block diagram of a method for eliminating current overshoot in Embodiment 1 of the present invention;

[0036] Figure 6 This is the symmetrical integral waveform diagram of the present invention;

[0037] Figure 7 This is a block diagram of a method for eliminating current overshoot by bus sampling in a second embodiment of the present invention;

[0038] Figure 8 This is a block diagram of a method for eliminating current overshoot by sampling with a sampling resistor in embodiment 3 of the present invention;

[0039] Figure 9 Schematic diagram of ending the power-off state in the fourth embodiment of the present invention;

[0040] Figure 10 This is a schematic diagram of a bus sampling circuit according to a fourth embodiment of the present invention;

[0041] Figure 11 Schematic diagram of a sampling resistor sampling circuit according to a fifth embodiment of the present invention. DETAILED DESCRIPTION

[0042] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0043] The prior art switching buck type LED constant current driving circuit includes an integrator, wherein the integrator is composed of an error amplifier EA and an integral capacitor C comp The integrator integrates the electrical signal of the sampling resistor and transmits it to the driver; the driver outputs the error signal V according to the integrator. comp The PWM signal V generated by comparing with the sawtooth wave or triangle wave pwm , V pwm Drive the power switch tube M1 to be turned on and off.

[0044] When M1 is turned on, current flows through the LED string, inductor L, M1 and resistor Rcs.

[0045] When M1 is turned off, the current flows through the LED string, the inductor L and the freewheeling diode D.

[0046] In the prior art, when the bus loses power, an error signal V comp If the power is turned on quickly at this time, the PWM signal will increase and the output current I L Increase beyond the steady-state current, resulting in overshoot.

[0047] In order to solve the above technical problems, the present application provides the following embodiments:

[0048] Example 1

[0049] like Figure 5 The present invention provides a method for eliminating current overshoot, comprising the following steps:

[0050] Determine whether the system has entered the power-off state;

[0051] When the system enters the power-off state, the power-off protection device is activated and the power-off timer starts recording the power-off time;

[0052] When the power-off time reaches a preset time, the integrator starts reverse integration, wherein the preset time is greater than the bus voltage VM cycle time.

[0053] The bus voltage drops due to power failure, which causes the sampling resistor voltage to drop, which in turn causes V ref and V fb The difference increases, and the integrator generates an error signal V comp will increase, causing the driver to generate a PWM signal exceeding the steady-state value, and the output current I L Increase beyond the steady-state current, resulting in overshoot.

[0054] Therefore, in this embodiment, the integrator is controlled to prevent the error signal V from being compBy setting a reasonable preset time, the integrator stops within a reasonable range to prevent V comp When it continues to increase, the integrator is reversed and integrated in the opposite direction on this basis, further reducing the error signal V comp , which reduces the current overshoot phenomenon when the bus is re-energized.

[0055] In order to ensure the normal operation of the integrator, the preset time in this embodiment needs to be greater than the cycle time of the bus voltage, that is, for a 50 Hz mains supply, greater than or equal to 10 ms.

[0056] like Figure 6 As shown in the waveform, when the bus voltage is lower than the power-off threshold voltage and continues to drop, it enters the power-off state and starts to record the power-off time. At this time, as the bus voltage begins to drop, the error signal V comp When the power-off time reaches the preset time, the integrator starts reverse integration to prevent the error signal V comp Continuous increase leads to overshoot phenomenon.

[0057] Example 1.1

[0058] This embodiment is further optimized based on the embodiment 1. Figure 5 The present invention provides a method for eliminating current overshoot, comprising the following steps:

[0059] Determine whether the system has entered the power-off state;

[0060] When the system enters the power-off state, the power-off protection device is activated and the power-off timer starts recording the power-off time;

[0061] When the power-off time reaches a preset time, the integrator starts reverse integration, wherein the preset time is greater than the bus voltage VM cycle time.

[0062] The bus voltage drops due to power failure, which causes the sampling resistor voltage to drop, which in turn causes V ref and V fb The difference increases, and the integrator generates an error signal V comp will increase, causing the driver to generate a PWM signal exceeding the steady-state value, and the output current I L Increase beyond the steady-state current, resulting in overshoot.

[0063] from Figure 6 It can be seen that at the time instant the integral error V comp Reaching the maximum value, at this moment reverse integration, the integral error V comp Will decrease, and the integral error V comp will be less than the peak value of the error. It can be seen that the integral error V at any moment from to 2comp Both can play a role in reducing current overshoot.

[0064] Especially at moment 2, the integral error V comp When it reaches zero, the integration stops and the system is powered on again. There will be no overshoot in the system.

[0065] When the reverse integral time exceeds time, that is, exceeds 2 moments, the integral error V comp They are still smaller than the error peak. Restarting the power at this time can also suppress the overshoot phenomenon.

[0066] It should be noted that the power-off threshold voltage can be set by the user according to actual conditions.

[0067] It should be noted that when the bus is powered off, the integrator in the present invention integrates upward, and the error signal V comp In the rising state, this is related to the positive and negative terminal connection method of the integrator, but both reflect the error signal V comp The change from the initial value does not deviate from the problem reflected in the essence of this application.

[0068] Example 2

[0069] like Figure 7 As shown, a method for eliminating current overshoot includes the following steps:

[0070] Get the bus voltage parameters. When the bus voltage is less than the power-off threshold voltage V PL , and the bus voltage continues to drop (such as Figure 6 At this time, it is determined that the system has entered the power-off state.

[0071] The power-off protection device is activated, and the power-off timer begins to record the power-off time;

[0072] When the power-off time reaches a preset time, the integrator performs reverse integration, wherein the preset time is greater than the bus voltage VM cycle time.

[0073] When the integrator reverse integration time reaches, that is, the reverse integration reaches time 2, the integrator stops integrating until the system is powered on next time. Similarly, the reverse integration time can be any time from 1 to 2 in embodiment 1, or can be greater than 2.

[0074] The bus voltage drops due to power failure, which causes the sampling resistor voltage to drop, which in turn causes V ref and V fb The difference increases, and the integrator generates an error signal V comp will increase, causing the driver to generate a PWM signal exceeding the steady-state value, and the output current I L Increase beyond the steady-state current, resulting in overshoot.

[0075] from Figure 6 It can be seen that at the time instant the integral error V comp Reaching the maximum value, at this moment reverse integration, the integral error V comp Will decrease, and the integral error V comp will be less than the peak value of the error. It can be seen that the integral error V at any moment from to 2 comp Both can play a role in reducing current overshoot.

[0076] Especially at moment 2, the integral error V comp When it reaches zero, the integration stops and the system is powered on again. There will be no overshoot in the system.

[0077] When the reverse integral time exceeds time, that is, exceeds 2 moments, the integral error V comp They are still smaller than the error peak. Restarting the power at this time can also suppress the overshoot phenomenon.

[0078] Based on the above-mentioned first embodiment, this embodiment further defines it. By acquiring the bus voltage, the operating condition of the bus is determined, and whether the system is in a power-off state is inferred. This method is more direct than other sampling methods and has a simpler circuit implementation.

[0079] Example 3

[0080] like Figure 8 As shown, a method for eliminating current overshoot includes the following steps:

[0081] The sampling resistor electrical parameters are obtained. When the sampling resistor electrical parameters are less than a threshold and continue to decrease, it is determined that the system has entered a power-off state. The sampling resistor electrical parameters include the sampling resistor current or voltage.

[0082] The power-off protection device is activated, and the power-off timer begins to record the power-off time;

[0083] When the power-off time reaches the preset time, the integrator reversely integrates to time 2, where the preset time is greater than the bus voltage VM cycle time.

[0084] The bus voltage drops due to power failure, which causes the sampling resistor voltage to drop, which in turn causes V ref and V fb The difference increases, and the integrator generates an error signal V comp will increase, causing the driver to generate a PWM signal exceeding the steady-state value, and the output current I L Increase beyond the steady-state current, resulting in overshoot.

[0085] Therefore, in this embodiment, by controlling the integration time of the integrator, the error signal is prevented from continuously increasing due to long-term integration. When the power-off duration is reached, the integrator starts reverse integration to time 2, at which time the error signal V comp When it is 0, there is no overshoot.

[0086] In order to ensure the normal operation of the integrator, the preset time in this embodiment needs to be greater than the cycle time of the bus voltage, that is, for a 50 Hz mains supply, greater than or equal to 10 ms.

[0087] This embodiment further defines the first embodiment above. In this embodiment, the electrical parameters of a sampling resistor are obtained to determine whether the system has entered a power-off state. The electrical parameters of the sampling resistor differ significantly between the power-on and power-off states, so a power-off determination can be achieved without requiring overly sophisticated detection methods.

[0088] Based on the above embodiments 1 to 3, the present invention further includes obtaining power-off parameters and determining whether to end the power-off state.

[0089] Example 4

[0090] Determine whether the system is powered off and enters a power-off state by using any one of the methods or a combination of the methods in the first to third embodiments.

[0091] One method of eliminating current overshoot includes:

[0092] Get bus voltage parameters. When the bus voltage is less than the power-off threshold voltage and the bus voltage continues to drop (such as Figure 6 At this time, it is determined that the system has entered the power-off state.

[0093] and / or

[0094] The sampling resistor electrical parameters are obtained. When the sampling resistor electrical parameters are less than a threshold and continue to decrease, it is determined that the system has entered a power-off state. The sampling resistor electrical parameters include the sampling resistor current or voltage.

[0095] The power-off protection device is activated, and the power-off timer begins to record the power-off time;

[0096] When the power-off time reaches a preset time, the integrator stops integrating, wherein the preset time is greater than the bus voltage VM cycle time.

[0097] After completing the above steps, the system enters the power-off state, at which time the integrator integrates in reverse.

[0098] like Figure 9As shown, power-off parameters are acquired in real time. When the electrical parameters are greater than a threshold, the system ends the power-off state and the integrator resumes integration. The electrical parameters include one or a combination of bus voltage, sampling resistor voltage, or current.

[0099] The bus sampling has the following advantages: judging whether the bus has entered the power-off state by the bus voltage state is more direct and obvious, and the circuit implementation is relatively simple.

[0100] The sampling resistor sampling has the following advantages: the electrical parameters of the sampling resistor vary greatly between the system power-on and system power-off states, and the power-off state can be judged without overly sophisticated detection means.

[0101] Based on the above embodiments one to four, the present application further provides a switching circuit for implementing the methods in the above embodiments.

[0102] Example 5

[0103] like Figure 10 As shown, the present invention provides a switching circuit with a power-off protection function, including a rectifier bridge for converting AC voltage into DC voltage, a diode D, an LED light string and a filter capacitor connected in parallel, an inductor L connected in series between the diode D and the LED light string, and a power tube M1 and a sampling resistor R connected in series between the diode D and the inductor L. CS , where the sampling resistor R CS grounding;

[0104] Including integrator, the driver stage is based on the error signal V output by the integrator comp Compare with the sawtooth wave to generate PWM signal V pwm , V pwm Drive the power switch tube M1 to be turned on and off.

[0105] When M1 is turned on, current flows through the LED string, inductor L, M1 and resistor R cs .

[0106] When M1 is turned off, the current flows through the LED string, the inductor L and the freewheeling diode D.

[0107] The system also includes a power-off protection device, which includes a power-off detection device and a power-off timer. In this embodiment, the power-off detection device samples the bus voltage. By acquiring the bus voltage, the operating condition of the bus is determined, and whether the system is in a power-off state is estimated. This method is more direct than other sampling methods and has a simpler circuit implementation.

[0108] Example 6

[0109] like Figure 11As shown, the present invention provides a switching circuit with a power-off protection function, including a rectifier bridge for converting AC voltage into DC voltage, a diode D, an LED light string and a filter capacitor connected in parallel, an inductor L connected in series between the diode D and the LED light string, and a power tube M1 and a sampling resistor R connected in series between the diode D and the inductor L. CS , where the sampling resistor R CS grounding;

[0110] Including integrator, the driver stage is based on the error signal V output by the integrator comp Compare with the sawtooth wave to generate PWM signal V pwm , V pwm Drive the power switch tube M1 to be turned on and off.

[0111] When M1 is turned on, current flows through the LED string, inductor L, M1 and resistor Rcs.

[0112] When M1 is turned off, the current flows through the LED string, the inductor L and the freewheeling diode D.

[0113] The system also includes a power-off protection device, which includes a power-off detection device and a power-off timer. In this embodiment, the power-off detection device samples data from a sampling resistor. The electrical parameters of the sampling resistor differ significantly between when the system is powered on and when it is powered off, thus enabling a power-off determination without requiring overly sophisticated detection methods. The sampling resistor electrical parameters include the current or voltage across the sampling resistor.

[0114] In this embodiment, the sampling resistor is set at the ground position. Without departing from the main purpose of the present application, the sampling resistor can be located at any feasible position in the circuit.

[0115] It should be noted that in the above embodiment, the integrator includes an error amplifier EA and an integrating capacitor C connected in series with the error amplifier EA. comp . Alternatively, the integrator is a digital integrator.

[0116] In the above embodiment, the power failure detection device has a built-in preset parameter V ref2 , used to compare with the sampled electrical parameters to determine the power-off status.

[0117] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for eliminating current overshoot, characterized in that: include: Determine whether the system has entered the power-off state; Determining whether the system enters a power-off state includes: Obtain power-off parameters and determine whether the system has entered the power-off state based on the change status of the power-off parameters; Obtaining power-off parameters and determining whether the system has entered a power-off state based on the power-off parameter change status includes: Acquire the sampling resistor current or voltage. When the sampling resistor current or voltage is lower than a threshold and continues to decrease, determine that the system enters a power-off state. When the system enters the power-off state, the power-off protection device is activated; The power-off time reaches the preset time T PL , and the preset time T PL When the period is greater than the bus voltage VM cycle time, the integrator performs reverse integration; the reverse integration time is equal to T PL ; Get the power-off parameters and determine whether to end the power-off state; The obtaining of power-off parameters and determining whether to end the power-off state includes: Obtain bus voltage VM, which is higher than power-on threshold V PU , the system ends the power-off state and the integrator returns to its original state; The obtaining of power-off parameters and determining whether to end the power-off state further includes: A sampling resistor parameter is obtained. If the sampling resistor parameter is higher than a power-on threshold, the system ends the power-off state and the integrator returns to an original state.

2. A method for eliminating current overshoot according to claim 1, characterized in that : Get the power-off parameters and determine whether the system has entered the power-off state according to the change status of the power-off parameters, including: Obtain the bus voltage VM, which is lower than the power-off threshold voltage V PL , and the bus voltage VM continues to decrease; it is determined that the system enters a power-off state.

3. A method for eliminating current overshoot according to claim 2, characterized in that : The sampling resistor parameters include the sampling resistor voltage or the sampling resistor current.

4. A switching circuit, characterized in that: The invention comprises a power-off protection device, wherein the power-off protection device controls the integrator according to the method according to any one of claims 1 to 3.

5. A switching circuit according to claim 4, characterized in that: The power-off protection device includes a power-off detection device and a power-off timer. The power-off detection device detects the bus voltage VM and controls the operation of the integrator according to the timing of the power-off timer.

6. A switching circuit according to claim 5, characterized in that: The power-off protection device includes a power-off detection device and a power-off timer. The power-off detection device detects electrical parameters of the sampling resistor and controls the operation of the integrator according to the timing of the power-off timer.

7. A switching circuit according to claim 5 or 6, characterized in that: The integrator includes an error amplifier EA and an integration capacitor C connected in series with the error amplifier EA. comp .

8. A switching circuit according to claim 7, characterized in that: The integrator is a digital integrator.

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