Semiconductor memory device

Abstract

Disclose a semiconductor memory device. The semiconductor memory device includes: gate electrodes arranged on a substrate and separated from each other in a first direction perpendicular to the upper surface of the substrate; an upper insulating layer arranged on the uppermost gate electrode; a channel structure penetrating the upper insulating layer and the gate electrodes in the first direction; and a string selection line cutting insulating layer that horizontally separates the upper insulating layer and the uppermost gate electrode. Each of the string selection line cutting insulating layers includes a protrusion that protrudes toward the uppermost gate electrode and is at the same level as the first gate electrode.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2019-0026325, filed with the Korean Intellectual Property Office on Mar. 7, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The inventive concept relates to a semiconductor memory device. More particularly, the inventive concept relates to a semiconductor memory device having increased integration. Background Art

[0003] Multifunctional information and / or communication devices require large-capacity and highly integrated memory devices. Accordingly, memory devices having high integration density and good electrical characteristics are desired. Summary of the Invention

[0004] The inventive concept provides a semiconductor memory device having increased integration and increased reliability, and a method of manufacturing the semiconductor memory device.

[0005] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments.

[0006] According to an exemplary embodiment of the inventive concept, a semiconductor memory device includes: a plurality of gate electrodes disposed on a substrate to be spaced apart from each other in a first direction perpendicular to an upper surface of the substrate; a plurality of insulating layers disposed between the plurality of gate electrodes; an upper insulating layer disposed on the uppermost gate electrode of the plurality of gate electrodes; a plurality of channel structures penetrating the upper insulating layer, the plurality of gate electrodes, and the plurality of insulating layers in the first direction, each of the plurality of channel structures including a plurality of layers and having a circular cross-section; and a plurality of string select line cutting insulating layers horizontally separating the upper insulating layer and the uppermost gate electrode. Each of the plurality of string select line cutting insulating layers includes a protrusion protruding toward the separated uppermost gate electrode and located at the same level as the separated first gate electrode.

[0007] According to an exemplary embodiment of the inventive concept, a semiconductor memory device includes: a plurality of gate electrodes arranged on a substrate to be separated from each other in a first direction perpendicular to an upper surface of the substrate; a plurality of insulating layers arranged between the plurality of gate electrodes; an upper insulating layer arranged on the uppermost gate electrode among the plurality of gate electrodes; a plurality of channel structures penetrating the upper insulating layer, the plurality of gate electrodes, and the plurality of insulating layers in the first direction, each of the plurality of channel structures including a plurality of layers and having a circular cross section; a pair of word line cutting portions separating the plurality of gate electrodes and the plurality of insulating layers in a second direction parallel to the upper surface of the substrate; and a plurality of string select line cutting insulating layers arranged between the pair of word line cutting portions and separating the upper insulating layer and the uppermost gate electrode in the second direction. Each of the plurality of string select line cutting insulating layers includes sidewalls separated from sidewalls of the separated upper insulating layer.

[0008] According to an exemplary embodiment of the inventive concept, a semiconductor memory device includes: a plurality of gate electrodes arranged on a substrate to be separated from each other in a first direction perpendicular to an upper surface of the substrate, each of the plurality of gate electrodes including a gate conductive layer and a first barrier layer covering the gate conductive layer, each of the plurality of gate electrodes including at least one ground select gate electrode arranged on the substrate, a plurality of word line gate electrodes arranged on the at least one ground select gate electrode, and at least one string select gate electrode arranged on the plurality of word line gate electrodes; a plurality of insulating layers arranged between the plurality of gate electrodes; an upper insulating layer arranged on the at least one string select gate electrode; a plurality of channel structures penetrating the upper insulating layer, the plurality of gate electrodes, and the plurality of insulating layers in the first direction, each of the plurality of channel structures including a plurality of layers and having a circular cross section; a pair of word line cutting insulating layers between which the plurality of gate electrodes and the plurality of insulating layers are disposed, the pair of word line cutting insulating layers being separated from each other in a second direction parallel to the upper surface of the substrate, and a plurality of string select line cutting insulating layers arranged between the pair of word line cutting insulating layers and separating the upper insulating layer and the at least one string select gate electrode in the second direction. The first barrier layer included in the at least one string select gate electrode is located between the upper insulating layer and each of the plurality of string select line cutting insulating layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments of the inventive concept will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a block diagram of a semiconductor memory device according to some embodiments;

[0011] Figure 2 is a schematic perspective view of a semiconductor memory device according to some embodiments;

[0012] Figure 3 is a circuit diagram for explaining the operation of a semiconductor memory device according to some embodiments;

[0013] Figure 4A is a cross-sectional view for explaining a semiconductor memory device according to some embodiments;

[0014] Figure 4B is Figure 4A an enlarged cross-sectional view of the region of;

[0015] Figure 5A is a cross-sectional view for explaining a semiconductor memory device according to some embodiments;

[0016] Figure 5B is Figure 5A an enlarged cross-sectional view of the region of;

[0017] Figure 6 、 Figure 7 and Figure 8 are cross-sectional views for explaining a semiconductor memory device according to other embodiments;

[0018] Figure 9 is a flowchart of a method for manufacturing a semiconductor memory device according to some embodiments; and

[0019] Figures 10 to 12 、 Figure 13A 、 Figure 13B 、 Figure 14A 、 Figure 15A 、 Figure 16 、 Figure 17A 、 Figure 18A and Figure 19 are cross-sectional views, Figure 14B 、 Figure 15B 、 Figure 17B and Figure 18B are plan views for explaining a method for manufacturing a semiconductor memory device according to other embodiments. Detailed Description

[0020] Embodiments will now be described more fully with reference to the accompanying drawings. In the drawings, like reference numerals may denote like elements, and repeated description of like elements will be omitted. In the following drawings, for convenience and clarity of description, the thickness or size of each layer is exaggerated and may thus be slightly different from the actual shape and ratio.

[0021] Figure 1 is a block diagram of a semiconductor memory device 10 according to some embodiments.

[0022] Referring to Figure 1, the semiconductor memory device 10 includes a memory cell array 50 and a peripheral circuit 60. According to some embodiments, the semiconductor memory device 10 may further include a data input / output (I / O) circuit or an I / O interface.

[0023] The memory cell array 50 is connected to a string selection line SSL, a word line WL, a ground selection line GSL, and a bit line BL. The peripheral circuit 60 includes a control logic unit 61, a row decoder 62, and a page buffer 63. According to some embodiments, the memory cell array 50 is connected to the row decoder 62 via the string selection line SSL, the word line WL, and the ground selection line GSL, connected to the page buffer 63 via the bit line BL, and connected to a common source line driver 64 via a common source line CSL. The row decoder 62 receives an address ADDR, and the control logic unit 61 receives a command signal CMD and a control signal CTRL.

[0024] Figure 2 is a conceptual diagram schematically showing the structure of Figure 1 the semiconductor memory device 10 according to some embodiments.

[0025] The semiconductor memory device 10 includes a memory cell array 50 and a peripheral circuit 60, and these components of the semiconductor memory device 10 can be formed via a semiconductor manufacturing process.

[0026] Referring to Figure 1 and Figure 2 , the semiconductor memory device 10 includes a first semiconductor device layer L1 and a second semiconductor device layer L2. According to some embodiments, the second semiconductor device layer L2 is disposed on the first semiconductor device layer L1 along a first direction (Z direction). According to some embodiments, Figure 1 the memory cell array 50 of

[0027] The first semiconductor device layer L1 may include a lower substrate. The first semiconductor device layer L1 may include semiconductor devices (such as transistors) formed on the lower substrate and wirings for driving the semiconductor devices. Thus, for example, circuits corresponding to Figure 1 the control logic unit 61, the row decoder 62, the page buffer 63, and the common source line driver 64 of

[0028] The second semiconductor device layer L2 may include a conductive layer and an upper substrate disposed on the conductive layer. According to some embodiments, the upper surface of the upper substrate and the upper surface of the lower substrate may be substantially perpendicular to the first direction (Z direction), but the inventive concept is not limited thereto. According to some embodiments, the upper substrate may include a plurality of layers. The second semiconductor device layer L2 may include a memory cell array 50 formed on the upper substrate. According to some embodiments, at least one conductive layer may be used to supply a common source voltage to the memory cell array 50.

[0029] According to some embodiments, a conductive pattern for connecting the memory cell array 50 to the peripheral circuit 60 included in the first semiconductor device layer L1 may be formed in the second semiconductor device layer L2. According to some embodiments, a plurality of word lines WL may extend in a second direction (X direction) perpendicular to the first direction (Z direction). According to some embodiments, a plurality of bit lines BL may extend in a third direction (Y direction) perpendicular to the first direction (Z direction). The first direction (Z direction), the second direction (X direction), and the third direction (Y direction) may be substantially perpendicular to each other. The term "vertical direction" used hereinafter may represent a direction substantially parallel to the first direction (Z direction), and the term "vertical level" may represent a height along the first direction (Z direction) from a reference surface (e.g., the upper surface of the upper substrate). The term "horizontal direction" used hereinafter may represent a direction perpendicular to the first direction (Z direction). For example, the horizontal direction may represent the third direction (Y direction), the second direction (X direction), or any direction between the third direction and the second direction.

[0030] Memory cells included in the memory cell array 50 may be accessed through the plurality of word lines WL and the plurality of bit lines BL. The plurality of word lines WL and the plurality of bit lines BL may be electrically connected to the peripheral circuit 60 formed in the first semiconductor device layer L1.

[0031] Therefore, the semiconductor memory device 10 may have a structure in which the memory cell array 50 and the peripheral circuit 60 are arranged in the first direction (Z direction), that is, a cell-on-peripheral circuit (COP) structure. According to some embodiments, circuits other than the memory cell array 50 may be arranged below the memory cell array 50, and thus the COP structure may reduce the horizontal area of the semiconductor memory device 10. Therefore, the integration degree of the semiconductor memory device 10 may be improved.

[0032] Although in Figure 2The semiconductor memory device 10 has a COP structure, but this is only an example, and the inventive concept is not limited thereto. For example, the technical spirit of the inventive concept is basically equally applicable to a memory device having such a structure in which a peripheral circuit region is horizontally separated from the cell region at the same level as the cell region.

[0033] Figure 3 is a schematic circuit diagram for explaining Figure 1 the circuit structures of memory blocks BLK1 to BLKz. Figure 3 The memory block BLK of Figure 1 can be one of the memory blocks BLK1 to BLKz of

[0034] Referring to Figure 3 , the memory block BLK can be a NAND flash memory having a vertical structure. The memory block BLK includes a plurality of NAND strings NS11 to NS33 (i.e., NAND strings NS11, NS12, NS13, NS21, NS22, NS23, NS31, NS32, and NS33), a ground selection line GSL, a plurality of string selection lines SSL1, SSL2, and SSL3 (i.e., a first string selection line SSL1, a second string selection line SSL2, and a third string selection line SSL3), a plurality of word lines WL1 to WL8 (i.e., a first word line WL1, a second word line WL2, a third word line WL3, a fourth word line WL4, a fifth word line WL5, a sixth word line WL6, a seventh word line WL7, and an eighth word line WL8), a plurality of bit lines BL1 to BL3 (i.e., a first bit line BL1, a second bit line BL2, and a third bit line BL3), and a common source line CSL. The number of NAND strings, the number of word lines, the number of bit lines, the number of ground selection lines, and the number of string selection lines may vary according to embodiments, and the inventive concept is not limited thereto.

[0035] According to some embodiments, the plurality of NAND strings NS11 to NS33 are connected between the plurality of bit lines BL1 to BL3 and the common source line CSL. Each of the NAND strings NS11, NS21, NS31, NS12, NS22, NS32, NS13, NS23, and NS33 includes a string selection transistor SST, a plurality of memory cells MC1 to MC8 (i.e., memory cells MC1, MC2, MC3, MC4, MC5, MC6, MC7, and MC8), and a ground selection transistor GST connected in series with each other.

[0036] Figure 4A is a cross-sectional view for explaining the semiconductor memory device 10 according to some embodiments, Figure 4B is Figure 4A an enlarged cross-sectional view of the region E1 of

[0037] Referring to Figure 4A, the semiconductor memory device 10 includes a first semiconductor device layer L1 including a peripheral circuit and a second semiconductor device layer L2 including a channel structure operating as a memory cell. The second semiconductor device layer L2 is disposed on the first semiconductor device layer L1.

[0038] The first semiconductor device layer L1 includes a lower substrate 101, peripheral transistors 111 and 112, peripheral circuit wirings electrically connected to the peripheral transistors 111 and 112, and a lower insulating layer 150 covering the peripheral transistors 111 and 112 and the peripheral circuit wirings. The peripheral transistors 111 and 112, the peripheral circuit wirings, and the lower insulating layer 150 are disposed on the lower substrate 101. According to some embodiments, the lower insulating layer 150 may include an insulating material. For example, the lower insulating layer 150 may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, etc.

[0039] According to some embodiments, the lower substrate 101 may include a semiconductor substrate including a semiconductor material (such as single-crystalline silicon or single-crystalline germanium). Trenches for defining active regions and passive regions and an isolation layer 120 filling the trenches may be formed in the lower substrate 101.

[0040] According to some embodiments, the peripheral transistors 111 and 112 may constitute Figure 1 the peripheral circuit 60. According to some embodiments, the peripheral transistors 111 and 112 may constitute Figure 1 the control logic unit 61, the row decoder 62, the page buffer 63, and the common source line driver 64.

[0041] The peripheral circuit wirings include a plurality of peripheral conductive patterns 140 sequentially stacked on the lower substrate 101. The peripheral circuit wirings further include a plurality of peripheral vias 130 that connect the peripheral transistors 111 and 112 to the plurality of peripheral conductive patterns 140 formed at different levels. According to some embodiments, the peripheral circuit wirings are shown to include three layers of peripheral conductive patterns 140 and the peripheral vias 130 connecting them to each other, but the inventive concept is not limited thereto. The peripheral circuit wirings may include two or at least four layers of peripheral conductive patterns and vias connecting them to each other.

[0042] The second semiconductor device layer L2 includes a common source line CSL, an upper substrate 201 disposed on the common source line CSL, insulating layers 230 and gate electrodes 240 alternately and repeatedly stacked on the upper substrate 201, and a first upper insulating layer 261 and a second upper insulating layer 263 covering them. The second semiconductor device layer L2 includes a channel structure 250 penetrating the insulating layers 230 and the gate electrodes 240, a word line cut insulating layer WLCI separating the plurality of gate electrodes 240 from each other, and a string select line cut insulating layer SSLCI separating the plurality of uppermost gate electrodes 240 (SE) from each other. According to some embodiments, the second semiconductor device layer L2 may further include wirings enabling the gate electrodes 240 and the channel structure 250 to operate as Figure 1 a memory cell array 50.

[0043] The common source line CSL is disposed on the first semiconductor device layer L1. According to some embodiments, the common source line CSL may be in a planar shape. According to some embodiments, the common source line CSL may include tungsten (W) or a W compound.

[0044] According to some embodiments, the upper substrate 201 may be a support layer supporting the insulating layers 230 and the gate electrodes 240. According to some embodiments, the upper substrate 201 may include, but is not limited to, a plurality of layers. For example, the upper substrate 201 may include a single layer. According to some embodiments, the upper substrate 201 includes a first upper substrate layer 201a disposed on the common source line CSL, a second upper substrate layer 201b disposed on the first upper substrate layer 201a, and a third upper substrate layer 201c between the first upper substrate layer 201a and the second upper substrate layer 201b. The first upper substrate layer 201a contacts the third upper substrate layer 201c. The third upper substrate layer 201c may contact the second upper substrate layer 201b. The third upper substrate layer 201c may include an opening exposing the upper surface of the first upper substrate layer 201a. The second upper substrate layer 201b may partially contact the first upper substrate layer 201a via the opening. Unless otherwise indicated in the context, the term "contact" used herein means direct connection (i.e., touching).

[0045] According to some embodiments, the first upper substrate layer 201a, the second upper substrate layer 201b, and the third upper substrate layer 201c may include polysilicon. According to some embodiments, the first upper substrate layer 201a, the second upper substrate layer 201b, and the third upper substrate layer 201c may include doped polysilicon layers. According to some embodiments, the first upper substrate layer 201a, the second upper substrate layer 201b, and the third upper substrate layer 201c may be doped at substantially the same concentration, but the inventive concept is not limited thereto.

[0046] The first upper base layer 201a, the second upper base layer 201b, and the third upper base layer 201c may include a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or an epitaxial thin film substrate obtained by selective epitaxial growth (SEG). The first upper base layer 201a, the second upper base layer 201b, and the third upper base layer 201c may include at least one of, for example, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), and mixtures thereof.

[0047] According to some embodiments, the gate electrode 240 may correspond to Figure 3 the gate of a transistor. For example, the bottommost gate electrode 240 (GE) may correspond to Figure 3 the gate of the ground selection transistor GST, the topmost gate electrode 240 (SE) may correspond to Figure 3 the gate of the string selection transistor SST, and the gate electrode 240 (WE) between the bottommost gate electrode 240 (GE) and the topmost gate electrode 240 (SE) may correspond to Figure 3 the gates of the plurality of memory cells MC1 to MC8. Referring to Figure 4A , eight gate electrodes 240 (WE) are shown as operating as the gates of memory cells, but the inventive concept is not limited thereto. For example, various numbers of gate electrodes 240 (such as 4, 16, 32, 64, or 128 gate electrodes 240) may operate as the gates of memory cells.

[0048] According to some embodiments, one or more dummy gate electrodes may be further disposed between the gate electrode 240 (GE) corresponding to Figure 3 the ground selection transistor GST and the gate electrode 240 (WE) corresponding to Figure 3 the memory cell MC1, and / or between the gate electrode 240 (SE) corresponding to Figure 3 the string selection transistor SST and the gate electrode 240 (WE) corresponding to Figure 3 the memory cell MC8. In this case, the inter-cell interference generated between adjacent gate electrodes 240 may be reduced.

[0049] According to some embodiments, the gate electrode 240 may include a conductive material. According to some embodiments, as Figure 4B shown, each gate electrode 240 may include multiple layers. According to some embodiments, the gate electrode 240 may include tungsten, tantalum, cobalt, nickel, tungsten silicide, tantalum silicide, cobalt silicide, or nickel silicide. According to some embodiments, the gate electrode 240 may include polysilicon.

[0050] According to some embodiments, the first bit line contact via 271, the second bit line contact via 275, the upper conductive pattern 273, and the bit line BL (to be described later to explain the gate electrode 240) may include at least one of the above materials.

[0051] According to some embodiments, the first upper insulating layer 261 and the second upper insulating layer 263 are disposed on the uppermost gate electrode 240 (SE). The first upper insulating layer 261 and the second upper insulating layer 263 may include an insulating material.

[0052] According to some embodiments, a plurality of channel structures 250 penetrate the first upper insulating layer 261, the gate electrode 240, and the insulating layer 230 in a direction opposite to the first direction (Z direction). The channel structures 250 may penetrate the second upper base layer 201b. The lower portion of the channel structures 250 may be covered by the first upper base layer 201a. The upper surface of the channel structures 250 may be coplanar with the upper surface of the first upper insulating layer 261 (i.e., at the same height), and the lower surface of the channel structures 250 may be lower than the upper surface of the first upper base layer 201a. Adjacent channel structures may be spaced apart from each other at a specific interval in the second direction and the third direction (X direction and Y direction). According to some embodiments, the channel structures 250 may be arranged adjacent to each other in a zigzag manner in the second direction.

[0053] According to some embodiments, each channel structure 250 may include a plurality of layers. For example, each channel structure 250 includes a gate insulating layer 251, a channel layer 253, and a buried insulating layer 255.

[0054] According to some embodiments, the gate insulating layer 251 may have a conformal thickness. According to some embodiments, the gate insulating layer 251 may form the bottom surface and the outer side surface of the channel structure 250. Therefore, according to some embodiments, the gate insulating layer 251 may insulate the channel layer 253 from the gate electrode 240.

[0055] According to some embodiments, the gate insulating layer 251 may include a plurality of layers having a conformal thickness. According to some embodiments, the gate insulating layer 251 may include a tunnel insulating layer, a charge storage layer, and a blocking insulating layer. The tunnel insulating layer may include silicon oxide, hafnium silicate, aluminum oxide, zirconium oxide, tantalum oxide, etc. The charge storage layer may be a region for storing electrons tunneling from the channel layer 253, and may include silicon nitride, boron nitride, silicon boron nitride, or doped polycrystalline silicon. The blocking insulating layer may include a single layer or a stack of silicon oxide, silicon nitride, hafnium silicate, aluminum oxide, zirconium oxide, tantalum oxide, etc. However, the material of the blocking insulating layer is not limited thereto, and the blocking insulating layer may include a dielectric material having a high dielectric constant value.

[0056] According to some embodiments, since a part of the gate insulating layer 251 is removed during the replacement process for the third upper base layer 201c, the gate insulating layer 251 may not be disposed at the same level as the third upper base layer 201c. For example, the third upper base layer 201c divides the gate insulating layer 251 into an upper gate insulating layer that serves as the uppermost gate electrode 240(SE), the gate electrode 240(WE), and the lowermost gate electrode 240(GE), and a lower gate insulating layer that covers the bottom end of the channel structure 250. Accordingly, the third upper base layer 201c and the channel layer 253 are connected to each other.

[0057] According to some embodiments, the channel layer 253 may fill a part of the internal space defined by the gate insulating layer 251. The channel layer 253 formed on the inner sidewall of the gate insulating layer 251 may have a specific thickness. According to some embodiments, an upper portion of the channel layer 253 may have a thickness greater than a thickness of a portion of the channel layer 253 that contacts the inner sidewall of the gate insulating layer 251.

[0058] According to some embodiments, the space defined by the channel layer 253 may be filled with a buried insulating layer 255. An upper surface of the buried insulating layer 255 may be covered by an upper portion of the channel layer 253. According to some embodiments, an upper surface of the channel layer 253 may serve as a pad for forming an electrical connection with the first bit line contact via hole 271. In some cases, a separate contact pad may be provided on the upper surface of the channel layer 253.

[0059] Referring to Figure 4A , the gate insulating layer 251 is shown covering the lower surface of the channel layer 253, but the inventive concept is not limited thereto. In an exemplary embodiment, the gate insulating layer 251 may expose the lower surface of the channel layer 253 and only constitute the sidewalls of each channel structure 250. In this case, the semiconductor pattern grown via SEG from the upper substrate and the lower surface of the channel layer may contact each other, and the channel layer may not be directly connected to the upper substrate.

[0060] According to some embodiments, the word line cut insulating layer WLCI penetrates the first upper insulating layer 261, the second upper insulating layer 263, the gate electrode 240, and the insulating layer 230 in a direction opposite to the first direction (Z direction). The word line cut insulating layer WLCI further penetrates a part of the second upper base layer 201b and the first upper base layer 201a. In this case, the end portion of the word line cut insulating layer WLCI is buried in the first upper base layer 201a. However, the inventive concept is not limited thereto. According to some embodiments, the word line cut insulating layer WLCI may insulate different gate electrodes 240 arranged at the same vertical level from each other. For example, a gate electrode 240 separated from other gate electrodes may be disposed between two adjacent word line cut insulating layers (i.e., a pair of word line cut insulating layers). According to some embodiments, the word line cut insulating layer WLCI may extend long in the second direction (X direction) to separate the gate electrodes 240 from each other in the second direction (X direction). The length of the word line cut insulating layer WLCI in the second direction (X direction) may be greater than the length of the gate electrode 240 in the second direction (X direction). Therefore, the word line cut insulating layer WLCI may completely separate the gate electrodes 240 from each other. Accordingly, the gate electrodes 240 horizontally separated from each other may operate as gates of different transistors (e.g., a ground selection transistor, a memory cell transistor, and / or a string selection transistor).

[0061] According to some embodiments, the word line cut insulating layer WLCI has a tapered shape in the first direction (Z direction). The tapered shape means a shape in which its horizontal width linearly or gradually decreases in a direction toward the upper substrate 201. According to some embodiments, the word line cut insulating layer WLCI includes a portion having a width (e.g., a width in the third direction (Y direction)) that decreases in a direction opposite to the first direction (Z direction). The word line cut insulating layer WLCI further includes a portion protruding at the same horizontal level as the gate electrode 240 in a horizontal direction (e.g., the third direction (Y direction)). Accordingly, the portion of the word line cut insulating layer WLCI at the same level as the gate electrode 240 has a width greater than the width of the portion of the word line cut insulating layer WLCI at the same level as the insulating layer 230 adjacent to the gate electrode 240. The above-described structure of the word line cut insulating layer WLCI may be formed by recessing the gate electrode material during a node isolation process P180 of Figure 9 .

[0062] According to some embodiments, the word line cut insulating layer WLCI may include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. According to some embodiments, even when the word line cut insulating layer WLCI has the same composition as one of the insulating layer 230, the first upper insulating layer 261, and the second upper insulating layer 263, Figure 4BThe first barrier 241 is also located between the word line cutting insulation layer WLCI and the insulation layer 230, between the word line cutting insulation layer WLCI and the first upper insulation layer 261, and between the word line cutting insulation layer WLCI and the second upper insulation layer 263, so the word line cutting insulation layer WLCI can be distinguished from the insulation layer 230, the first upper insulation layer 261, and the second upper insulation layer 263. The first barrier 241 can be referred to as a first barrier layer.

[0063] Since the space filled with the word line cutting insulating layer WLCI will be separated from the plurality of gate electrodes connected to the adjacent word lines, the space will be referred to as a word line cutting portion. Figure 18A The second word line cutting trench WCT2 is substantially the same.

[0064] Will refer to Figure 4A and Figure 4B The structure and composition features of the string selection line cutting insulating layer SSLCI are described in detail. The string selection line cutting insulating layer SSLCI may extend along the first direction (Z direction). According to some embodiments, the string selection line cutting insulating layer SSLCI is located at the same level as the first upper insulating layer 261, the second upper insulating layer 263, and the uppermost gate electrode 240 (SE). According to some embodiments, the string selection line cutting insulating layer SSLCI penetrates along the first direction (Z direction) as Figure 3 The string selection line cutting insulating layer SSLCI may insulate a plurality of uppermost gate electrodes 240 (SE) that are horizontally separated from each other.

[0065] According to some embodiments, the string selection line cutting insulating layer SSLCI may extend long in the second direction (X direction) so as to separate the plurality of uppermost gate electrodes 240 (SE) from each other in the third direction (Y direction). The length of the string selection line cutting insulating layer SSLCI in the second direction (X direction) may be greater than the length of the uppermost gate electrode 240 (SE) in the second direction (X direction). According to some embodiments, the string selection line cutting insulating layer SSLCI may completely separate the plurality of uppermost gate electrodes 240 (SE) from each other. Therefore, the plurality of uppermost gate electrodes 240 (SE) disposed between two adjacent word line cutting insulating layers WLCI and horizontally separated from each other may be operated as gates of different string selection transistors. For example, as Figure 3 As shown in FIG. 1 , each block includes three string selection lines SSL1, SSL2, and SSL3 that can be independently controlled, and Figure 4A , the uppermost gate electrode 240 (SE) is separated by two string selection line cutting insulating layers to form three separated uppermost gate electrodes serving as three string selection lines SSL1 , SSL2 , and SSL3 .

[0066] According to some embodiments, a portion of the string select line cut insulating layer (SSLCI) that is at the same level as the first upper insulating layer 261 and the second upper insulating layer 263 has a tapered shape in a first direction (Z direction). According to some embodiments, the string select line cut insulating layer (SSLCI) has a discontinuously changing width at the junction between the first upper insulating layer 261 and the topmost gate electrode 240 (SE). According to some embodiments, the width of the string select line cut insulating layer (SSLCI) includes a protrusion R that protrudes in a horizontal direction (e.g., a third direction (Y direction)) from the center of the string select line cut insulating layer (SSLCI) at a level that is the same as the level of the topmost gate electrode 240 (SE). According to some embodiments, the string select line cut insulating layer (SSLCI) has a maximum width at a level that is the same as the level of the topmost gate electrode 240 (SE), but the inventive concept is not limited thereto. In an exemplary embodiment, the horizontal width (e.g., the width in the third direction (Y direction)) of the string select line cut insulating layer (SSLCI) may be maximum at the upper surface of the second upper insulating layer 263.

[0067] Each of the topmost gate electrodes 240 (SE) includes a first blocking portion 241, a second blocking portion 242, and a gate conductive layer 243. The second blocking portion 242 may be referred to as a second blocking layer. According to some embodiments, the first blocking portion 241, the second blocking portion 242, and the gate conductive layer 243 may include different materials from each other. According to some embodiments, the first blocking portion 241 and the second blocking portion 242 may have a consistent thickness. According to some embodiments, the first blocking portion 241 may have a thickness of but not limited to about 2 nm. According to some embodiments, the second blocking portion 242 may have a thickness of but not limited to about 2 nm. According to some embodiments, the first blocking portion 241 may include but not limited to one of a metal oxide (e.g., aluminum oxide), a metal nitride, and a metal oxynitride. According to some embodiments, the second blocking portion 242 may include but not limited to titanium nitride. According to some embodiments, the gate conductive layer 243 may include but not limited to tungsten.

[0068] According to some embodiments, a side surface of the protrusion R contacts the second blocking portion 242 and the gate conductive layer 243. According to some embodiments, the protrusion R has a thickness in the first direction (Z direction) that is substantially the same as the sum of the respective thicknesses of the second blocking portion 242 and the gate conductive layer 243 in the first direction (Z direction), but the inventive concept is not limited thereto. Accordingly, the thickness of the topmost gate electrode 240 (SE) in the first direction (Z direction) is greater than the thickness of the protrusion R in the first direction (Z direction).

[0069] According to some embodiments, the first blocking part 241 may be located between the string selection line cutting insulating layer SSLCI and the second upper insulating layer 263. According to some embodiments, the first blocking part 241 is disposed between the string selection line cutting insulating layer SSLCI and the first upper insulating layer 261. Accordingly, the string selection line cutting insulating layer SSLCI is separated from the first upper insulating layer 261 and the second upper insulating layer 263. According to some embodiments, the upper surface and the lower surface of the protrusion R contact the first blocking part 241.

[0070] According to some embodiments, the first blocking part 241 covers the upper surface and the lower surface of the protrusion R. According to some embodiments, the first blocking part 241 covers the portion of the string selection line cutting insulating layer SSLCI that is at the same level as the first upper insulating layer 261 and the second upper insulating layer 263. According to some embodiments, the first blocking part 241 covers the first upper insulating layer 261 and the second upper insulating layer 263 adjacent to the string selection line cutting insulating layer SSLCI.

[0071] According to some embodiments, the string selection line cutting insulating layer SSLCI may include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. According to some embodiments, even when the string selection line cutting insulating layer SSLCI has the same composition as one of the first upper insulating layer 261 and the second upper insulating layer 263, the first blocking part 241 is located between the string selection line cutting insulating layer SSLCI and the first upper insulating layer 261 and the second upper insulating layer 263. Accordingly, the string selection line cutting insulating layer SSLCI can be distinguished from the insulating layer 230, the first upper insulating layer 261, and the second upper insulating layer 263 by the first blocking part 241. The sidewall of the string selection line cutting insulating layer SSLCI is separated from the sidewalls of the first upper insulating layer 261 and the second upper insulating layer 263 by the first blocking part 241. In an exemplary embodiment, the first blocking part 241 may contact the sidewall of the string selection line cutting insulating layer SSLCI and the sidewalls of the first upper insulating layer 261 and the second upper insulating layer 263.

[0072] Referring to Figure 4A , two string selection line cutting insulating layers SSLCI are shown as being arranged between adjacent word line cutting insulating layers WLCI, but the present disclosure is not limited thereto. For example, three or more string selection line cutting insulating layers SSLCI may be arranged between adjacent word line cutting insulating layers WLCI.

[0073] The third upper insulating layer 265 is disposed on the second upper insulating layer 263. The third upper insulating layer 265 may include an insulating material. According to some embodiments, the first bit line contact via 271 and the second bit line contact via 275 may extend in a first direction (Z direction) at a level the same as at least a part of the third upper insulating layer 265. According to some embodiments, the combined structure of the first bit line contact via 271, the second bit line contact via 275, and the upper conductive pattern 273 penetrates the third upper insulating layer 265, and the first bit line contact via 271 further penetrates the second upper insulating layer 263. According to some embodiments, the first bit line contact via 271 may contact the channel layer 253. According to some embodiments, the upper conductive pattern 273 is disposed between the first bit line contact via 271 and the second bit line contact via 275. According to some embodiments, the upper conductive pattern 273 may extend in a horizontal direction (e.g., a second direction (X direction) and / or a third direction (Y direction)). According to some embodiments, the upper conductive pattern 273 contacts the first bit line contact via 271 and the second bit line contact via 275. According to some embodiments, the bit line BL contacts the second bit line contact via 275.

[0074] According to some embodiments, the channel structure 250 is connected to the bit line BL via the first bit line contact via 271, the upper conductive pattern 273, and the second bit line contact via 275.

[0075] Figure 5A is a schematic cross-sectional view for explaining a semiconductor memory device 11 according to still other embodiments. Figure 5B is Figure 5A an enlarged cross-sectional view of region E2 of

[0076] For ease of explanation, the following will not repeat Figure 5A and Figure 5B the descriptions that are the same as or similar to those given above with reference to Figure 4A and Figure 4B and will now focus on and describe the differences between them.

[0077] Referring to Figure 5A , the semiconductor memory device 11 includes a plurality of gate electrodes 240. The gate electrodes 240 may correspond to Figure 3 the gates of the transistors of Figure 3 . Specifically, the lowermost gate electrode 240 (GE) may correspond to Figure 3 the gate of the ground selection transistor GST of

[0078] The gate electrode 240(WE) disposed on each bottommost gate electrode 240(GE) may correspond to Figure 3 the gates of a plurality of memory cells MC1 to MC8. Referring to Figure 5A , eight gate electrodes 240(WE) are shown to operate as the gates of memory cells MC1 to MC8, but the inventive concept is not limited thereto. For example, various numbers of gate electrodes 240 (such as 4, 16, 32, 64, or 128 gate electrodes 240) may operate as the gates of memory cells.

[0079] A plurality (e.g., two) of dummy gate electrodes 240(DE) may be disposed between the gate electrode 240(WE) corresponding to Figure 3 the eight memory cells MC1 to MC8 and the gate electrode 240(SE) corresponding to Figure 3 the string selection transistor SST.

[0080] However, Figure 5A FIG. shows an example of the structure of the gate electrode 240 and does not limit the technical spirit of the inventive concept. In this example, a plurality of dummy gate electrodes 240(DE) and the gate electrode 240(SE) corresponding to Figure 3 the string selection transistor SST are given. For example, one or more dummy gate electrodes may be further provided between the bottommost gate electrode 240(GE) and the gate electrode 240(WE), or three or more gate electrodes 240(SE) may correspond to Figure 3 the string selection transistor SST, or the number of dummy gate electrodes 240(DE) may be one or at least three.

[0081] The semiconductor memory device 11 includes a string selection line cutting insulating layer SSLCI1. Now, the structure of the string selection line cutting insulating layer SSLCI1 will be described in detail with reference to Figure 5B FIG.

[0082] The string selection line cutting insulating layer SSLCI1 may extend in a first direction (Z direction). According to some embodiments, the string selection line cutting insulating layer SSLCI1 is at the same level as the first upper insulating layer 261 and the second upper insulating layer 263, and the gate electrode 240(SE) corresponding to Figure 3 the string selection transistor SST, and the dummy gate electrode 240(DE).

[0083] According to some embodiments, the string selection line cutting insulating layer SSLCI1 penetrates in a direction opposite to the first direction (Z direction) through the Figure 3The gate electrode 240(SE) corresponding to the gate electrode of the string selection transistor SST (i.e., the uppermost gate electrode 240(SE) and the second uppermost gate electrode 240(SE) directly below the uppermost gate electrode 240(SE)). The string selection line cut insulating layer SSLCI1 further penetrates the dummy gate electrode 240(DE) in a direction opposite to the first direction (Z direction).

[0084] According to some embodiments, the string selection line cut insulating layer SSLCI1 can insulate the horizontally separated uppermost gate electrode 240(SE) and the horizontally separated second uppermost gate electrode 240(SE) from each other. According to some embodiments, the string selection line cut insulating layer SSLCI1 can extend long in the second direction (X direction), so as to separate the gate electrodes 240 from each other in the third direction (Y direction). The length of the string selection line cut insulating layer SSLCI1 in the second direction (X direction) can be equal to or greater than the length of the gate electrodes 240 in the second direction (X direction). Therefore, the string selection line cut insulating layer SSLCI1 can completely separate the plurality of uppermost gate electrodes 240(SE) from each other. Therefore, the plurality of uppermost gate electrodes 240(SE) disposed between two adjacent word line cut insulating layers WLCI and horizontally separated from each other can operate as the gates of different string selection transistors. According to some embodiments, the string selection line cut insulating layer SSLCI1 can insulate the horizontally separated dummy gate electrodes 240(DE) from each other.

[0085] According to some embodiments, the portion of the string selection line cut insulating layer SSLCI1 that is at the same level as the first upper insulating layer 261 and the second upper insulating layer 263 has a tapered shape in the first direction (Z direction). The portion of the string selection line cut insulating layer SSLCI1 that is at the same level as the insulating layer 230 has a tapered shape in the first direction (Z direction).

[0086] According to some embodiments, the string select line cut insulating layer SSLCI1 has a discontinuously changing width (e.g., width in the third direction (Y direction)) at the junction between the first upper insulating layer 261 and the uppermost gate electrode 240 (SE). According to some embodiments, the string select line cut insulating layer SSLCI1 includes: a first protrusion R1 protruding horizontally (e.g., in the third direction (Y direction)) from the center of the string select line cut insulating layer SSLCI1 at the same level as the uppermost gate electrode 240 (SE). According to some embodiments, the first protrusion R1 protrudes from opposite sidewalls of each of the string select line cut insulating layers SSLCI1. According to some embodiments, the string select line cut insulating layer SSLCI1 has a maximum width at the same level as the uppermost gate electrode 240 (SE), but the inventive concept is not limited thereto. According to some embodiments, the side surface of the first protrusion R1 contacts the second blocking part 242 and the gate conductive layer 243. The upper and lower surfaces of the first protrusion R1 contact the first blocking part 241.

[0087] According to some embodiments, the string select line cut insulating layer SSLCI1 has a discontinuously changing width (e.g., width in the third direction (Y direction)) at the junction between the insulating layer 230 and some of the gate electrodes (e.g., the second uppermost gate electrode 240 (SE) and the dummy gate electrode 240 (DE)). According to some embodiments, the string select line cut insulating layer SSLCI1 further includes: a second protrusion R2, a third protrusion R3, and a fourth protrusion R4 protruding horizontally (e.g., in the third direction (Y direction)) from the center of the string select line cut insulating layer SSLCI1 at the same level as the second uppermost gate electrode 240 (SE) and the dummy gate electrode 240 (DE). The side surfaces of the second protrusion R2, the third protrusion R3, and the fourth protrusion R4 contact the second blocking part 242 and the gate conductive layer 243, respectively. The upper and lower surfaces of the second protrusion R2, the third protrusion R3, and the fourth protrusion R4 contact the first blocking part 241.

[0088] The second protrusion R2 is at the same level as the second uppermost gate electrode 240 (SE). The third protrusion R3 is at the same level as the dummy gate electrode 240 (DE) that is farther from the upper substrate 201 among the dummy gate electrodes 240 (DE). The fourth protrusion R4 is at the same level as the dummy gate electrode 240 (DE) that is closer to the upper substrate 201 among the dummy gate electrodes 240 (DE).

[0089] The first protrusion R1 protrudes farther from the center of the string selection line cut insulating layer SSLCI1 than the second protrusion R2. The second protrusion R2 protrudes farther from the center of the string selection line cut insulating layer SSLCI1 than the third protrusion R3. The third protrusion R3 protrudes farther from the center of the string selection line cut insulating layer SSLCI1 than the fourth protrusion R4.

[0090] According to some embodiments, the string selection line cut insulating layer SSLCI1 penetrates the entire portion of the dummy gate electrode 240 (DE). According to some embodiments, the string selection line cut insulating layer SSLCI1 may extend to a level lower than the level of the lower surface of the dummy gate electrode 240 (DE). For example, the lower surface of the string selection line cut insulating layer SSLCI1 is disposed closer to the upper substrate 201 than the lower surface of the dummy gate electrode 240 (DE). In this case, the string selection line cut insulating layer SSLCI1 partially penetrates the upper portion of the insulating layer 230 disposed below the dummy gate electrode 240 (DE). The lower end of the string selection line cut insulating layer SSLCI1 is buried in the upper portion of the insulating layer 230 disposed below the dummy gate electrode 240 (DE). The string selection line cut insulating layer SSLCI1 has a minimum width on the lower surface at its bottom end.

[0091] Figure 6 , Figure 7 and Figure 8 are cross-sectional views respectively for explaining semiconductor memory devices 12, 13, and 14 according to other embodiments.

[0092] For ease of explanation, the following will not repeat Figures 6 to 8 the descriptions that are the same or similar to those given above with reference to Figures 4A to 5B and will now focus on the differences between them and describe the differences between them.

[0093] Referring to Figure 6 , the string selection line cut insulating layer SSLCI2 included in the semiconductor memory device 12 may have a shape different from the shape of the string selection line cut insulating layer SSLCI1 included in Figure 5A the semiconductor memory device 11.

[0094] For example, the lower surface of the string select line cut insulating layer SSLCI2 is coplanar with the lower surface of the dummy gate electrode 240(DE) closer to the upper substrate 201 among the dummy gate electrodes 240(DE) (i.e., at the same height as the lower surface of the dummy gate electrode 240(DE) closer to the upper substrate 201 among the dummy gate electrodes 240(DE)). The horizontal width of the upper surface of the string select line cut insulating layer SSLCI2 (e.g., the width in the third direction (Y direction)) is smaller than the horizontal width of the lower surface of the string select line cut insulating layer SSLCI2 (e.g., the width in the third direction (Y direction)).

[0095] Referring Figure 7 , the string select line cut insulating layer SSLCI3 included in the semiconductor memory device 13 may have a shape different from the shape of the string select line cut insulating layer SSLCI1 included in the Figure 5A semiconductor memory device 11.

[0096] According to some embodiments, the string select line cut insulating layer SSLCI3 may penetrate only some of the dummy gate electrodes 240(DE). For example, the string select line cut insulating layer SSLCI3 penetrates only the upper dummy gate electrode among the two dummy gate electrodes 240(DE). In this case, the lower surface of the string select line cut insulating layer SSLCI3 is coplanar with the lower surface of the upper dummy gate electrode farther from the upper substrate 201 among the dummy gate electrodes 240(DE) (i.e., at the same height as the lower surface of the upper dummy gate electrode farther from the upper substrate 201 among the dummy gate electrodes 240(DE)). According to some embodiments, the horizontal width of the upper surface of the string select line cut insulating layer SSLCI3 (e.g., the width in the third direction (Y direction)) is smaller than the horizontal width of the lower surface of the string select line cut insulating layer SSLCI3 (e.g., the width in the third direction (Y direction)).

[0097] Referring Figure 8 , the string select line cut insulating layer SSLCI4 included in the semiconductor memory device 14 may have a shape different from the shape of the string select line cut insulating layer SSLCI1 included in the Figure 5A semiconductor memory device 11.

[0098] For example, the string select line cut insulating layer SSLCI4 may penetrate only the one Figure 3The string selection transistor SST corresponds to the topmost gate electrode 240 (SE) and the second topmost gate electrode 240 (SE). In this case, the string selection line cutting insulating layer SSLCI4 only penetrates the topmost gate electrode 240 (SE) and the second topmost gate electrode 240 (SE). The horizontal width of the upper surface of the string selection line cutting insulating layer SSLCI4 (for example, the width in the third direction (Y direction)) is smaller than the horizontal width of the lower surface of the string selection line cutting insulating layer SSLCI4 (for example, the width in the third direction (Y direction)).

[0099] Figure 9 is a flow chart of a method of manufacturing a semiconductor memory device according to some embodiments.

[0100] Figures 10 to 13A , Figure 14A , Figure 15A , Figure 16 , Figure 17A , Figure 18A and Figure 19 is a cross-sectional view for explaining a method of manufacturing a semiconductor memory device according to some embodiments. Figure 13B is along Figure 13A A cross-sectional view taken along line A-A', Figure 14B is along Figure 14A A cross-sectional view taken along line BB' of Figure 15B is along Figure 15A A cross-sectional view taken along line C-C', Figure 17B is along Figure 17A A cross-sectional view taken along the line D-D', Figure 18B is along Figure 18A A cross-sectional view taken along line EE'.

[0101] The method of manufacturing a semiconductor memory device described below is to manufacture Figure 4A and Figure 4B An example of a method of a semiconductor memory device 10 is provided, and does not limit the technical spirit of the inventive concept. A person skilled in the art of semiconductor technology may use the same method as will be referred to below. Figures 9 to 19 The method described is basically the same as the method to make Figures 5A to 8 Semiconductor memory devices 11, 12, 13 and 14.

[0102] Reference Figure 9 and Figure 10 In P110 , a first semiconductor device layer L1 , a first upper substrate layer 201 a , a second upper substrate layer 201 b , a stacked structure SS, and a first upper insulating layer 261 may be formed.

[0103] The provision of the first semiconductor device layer L1 may include a process of forming an isolation layer 120 on the lower substrate 101, a process of forming a p-well region and an n-well region in the lower substrate 101 in this stated order (or in the reverse order) via a first ion implantation process using a photoresist pattern of the lower substrate 101, a process of forming the peripheral transistors 111 and 112, and a process of patterning a conductive material and disposing an insulating material to form the peripheral circuit wiring.

[0104] The common source line CSL and the first upper base layer 201a may be formed on the lower insulating layer 150. The common source line CSL and the first upper base layer 201a may be formed via chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), etc.

[0105] After the upper substrate sacrificial layer 202 is disposed on the first upper base layer 201a and a part of the upper substrate sacrificial layer 202 is patterned and removed, the second upper base layer 201b may be conformally formed on the partially removed upper substrate sacrificial layer 202. The second upper base layer 201b may include doped polysilicon. Thus, the first upper base layer 201a and the second upper base layer 201b are in contact with each other through the removed part of the upper substrate sacrificial layer 202. According to some embodiments, the first upper base layer 201a and the second upper base layer 201b may include doped polysilicon.

[0106] According to some embodiments, the upper substrate sacrificial layer 202 may include an insulating material. According to some embodiments, the upper substrate sacrificial layer 202 may include one of silicon oxide, silicon nitride, and silicon oxynitride. According to some embodiments, the upper substrate sacrificial layer 202 may have a high etching selectivity with respect to the insulating layer 230.

[0107] Then, the sacrificial layer 220 and the insulating layer 230 are alternately stacked on the second upper base layer 201b, thereby forming a stacked structure SS. According to some embodiments, the insulating layer 230 and the sacrificial layer 220 may include different materials from each other. According to some embodiments, the insulating layer 230 may have a high etching selectivity with respect to the sacrificial layer 220. For example, when the sacrificial layer 220 includes silicon oxide, the insulating layer 230 may include silicon nitride. As another example, when the sacrificial layer 220 includes silicon nitride, the insulating layer 230 may include silicon oxide. As another example, when the sacrificial layer 220 includes undoped polysilicon, the insulating layer 230 may include silicon nitride or silicon oxide.

[0108] The first upper insulating layer 261 may be formed on the stacked structure SS. The first upper insulating layer 261 may include an insulating material.

[0109] Refer to Figure 9 and Figure 11, in P120, a channel hole CH can be formed. After the photoresist material layer is disposed on the stacked structure SS, the channel hole CH can be formed by sequentially performing exposure, development, and etching to penetrate the upper portions of the first upper insulating layer 261, the stacked structure SS, the second upper base layer 201b, the upper base sacrificial layer 202, and the first upper base layer 201a.

[0110] Referring to Figure 9 and Figure 12 , in P130, a channel structure 250 can be formed. After the gate insulating material layer, the channel material layer, and the buried insulating material layer are sequentially disposed on the stacked structure SS in which the Figure 11 formed channel hole CH is located, the material layers filling the channel hole CH can be separated from each other by performing a planarization process until the upper surface of the first upper insulating layer 261 is exposed. In one exemplary embodiment, the planarization process may include a re-etching process or a chemical mechanical polishing (CMP) process. Then, the upper portion of the buried insulating material layer within the channel hole CH is further removed to form a recessed region, and then a material the same as that of the channel material layer can be deposited in the recessed region to cover the recessed upper portion of the buried insulating layer 255. In one exemplary embodiment, the channel material formed in the recessed region can be used as a pad to be contacted by the first bit line contact via 271 that will be Figure 4A contacted.

[0111] Referring to Figure 9 , Figure 13A and Figure 13B , in P140, a first string selection line cutting trench SCT1 can be formed. The formation of the first string selection line cutting trench SCT1 may include forming a second upper insulating layer 263 on the first upper insulating layer 261, and then etching the first upper insulating layer 261, the second upper insulating layer 263, and the uppermost sacrificial layer 220 via dry etching or wet etching. The first string selection line cutting trench SCT1 exposes the upper surface of the uppermost insulating layer 230 by penetrating the first upper insulating layer 261, the second upper insulating layer 263, and the uppermost sacrificial layer 220. In some cases, the first string selection line cutting trench SCT1 may partially penetrate the upper portion of the uppermost insulating layer 230 via over-etching (i.e., over-etch).

[0112] The first string selection line cutting trench SCT1 may have a tapered shape in the first direction (Z direction). The length of the first string selection line cutting trench SCT1 in the second direction (X direction) may be equal to or greater than the length of the uppermost sacrificial layer 220 in the second direction (X direction). Thus, the first string selection line cutting trench SCT1 can horizontally separate the uppermost sacrificial layer 220.

[0113] Referring to Figure 9 and Figures 14A to 15B, in P150, a first word line cutting trench WCT1 can be formed. The formation of the first word line cutting trench WCT1 can include: forming a hard mask layer HDM that fills a first string selection line cutting trench SCT1, and then etching the stacked structure by using the hard mask layer HDM.

[0114] More specifically, referring to Figure 14A and Figure 14B , the hard mask layer HDM is formed on the first upper insulating layer 261 and the second upper insulating layer 263 to cover the first upper insulating layer 261 and the second upper insulating layer 263. The hard mask layer HDM fills Figure 13A the first string selection line cutting trench SCT1.

[0115] Then, referring to Figure 15A and Figure 15B , after patterning the hard mask layer HDM, the patterned hard mask layer HDM is used as an etching mask to etch the stacked structure SS, the first upper base layer 201a, the second upper base layer 201b, and the upper base sacrificial layer 202, thereby forming the first word line cutting trench WCT1.

[0116] After forming the first word line cutting trench WCT1, the patterned hard mask layer HDM can be removed. According to some embodiments, the first word line cutting trench WCT1 can have a tapered shape in the first direction (Z direction). According to some embodiments, the length of the first word line cutting trench WCT1 in the second direction (X direction) can be greater than the length of each sacrificial layer 220 in the second direction (X direction). Therefore, the first word line cutting trench WCT1 can horizontally separate a plurality of sacrificial layers 220 from each other.

[0117] In the prior art, before forming the word line cutting trench, the string selection line cutting trench is filled with an insulating material. However, in this case, the sacrificial layers arranged between the string selection line cutting trenches filled with the insulating material are not replaced by the gate insulating material layer. In addition, even when the gate electrodes for the string selection lines are formed and then separated from each other, it is difficult to etch tungsten or the like, which is often used as the gate electrode material, via dry etching.

[0118] According to some embodiments, after forming the first string selection line cutting trench SCT1, the string selection line cutting trench SCT1 undergoes a subsequent process without being filled with an insulating material, so that the topmost sacrificial layer 220 between adjacent first string selection line cutting trenches SCT1 can be replaced by a gate electrode material layer.

[0119] Referring to Figure 9 and Figure 16 , in P160, a third upper base layer 201c can be formed. The formation of the third upper base layer 201c can include: removing Figure 15AThe upper base sacrificial layer 202, and a third upper base layer 201c is formed in the space formed by removing the upper base sacrificial layer 202.

[0120] After forming a word line cut pad material layer in the first word line cut trench WLC1, the lower portion of the word line cut pad material layer is removed via an etch back process to form a word line cut pad PL. The word line cut pad PL can be a material having a high etch selectivity with respect to Figure 15A the upper base sacrificial layer 202. The sacrificial layer 220 is covered by the word line cut pad PL, but Figure 15A the upper base sacrificial layer 202 is exposed. The word line cut pad PL can be a layer for protecting the sacrificial layer 220 in the process of removing Figure 15A the upper base sacrificial layer 202. In one exemplary embodiment, for example, a wet etch process can be used to remove the upper base sacrificial layer 202 through WCT1. In this case, the upper base sacrificial layer 202 can have a high etch selectivity with respect to the word line cut pad PL, the second upper base layer 201b, and the first upper base layer 201a.

[0121] The third upper base layer 201c can be formed in the space formed by selectively removing Figure 15A the upper base sacrificial layer 202. As described above, the third upper base layer 201c can include polysilicon doped using a method substantially the same as that of the first upper base layer 201a and the second upper base layer 201b. At this time, the gate insulating layer 251 at the same level as Figure 15A the upper base sacrificial layer 202 can be removed together with Figure 15A the upper base sacrificial layer 202. Therefore, the newly formed third upper base layer 201c contacts the channel layer 253. Thus, a charge transfer path can be formed to enable the channel structure 250 to operate as a memory cell.

[0122] In addition, since the first upper base layer 201a and the second upper base layer 201b are in partial contact with each other, collapse of the first upper base layer 201a, the second upper base layer 201b, and the stacked structure SS disposed on the first upper base layer 201a and the second upper base layer 201b can be prevented. After forming the third upper base layer 201c, the word line cut pad PL can be removed.

[0123] Referring to Figure 9 、 Figure 17A and Figure 17B , in P170, after removing the word line cut pad PL from the resulting structure in Figure 16 , a gate electrode material layer EML can be formed on the resulting structure in Figure 16 .

[0124] The gate electrode material layer EML can include respectively withFigure 4B the first blocking portion 241 and the second blocking portion 242, and Figure 4B the first blocking material layer, the second blocking material layer, and the gate conductive material layer corresponding to the gate conductive layer 243 of

[0125] Referring to Figure 9 , Figure 18A and Figure 18B , in P180, a node separation process may be performed.

[0126] The node separation process may be a process of removing the exposed gate electrode material layer EML of Figure 17A by wet etching. Since the first blocking material layer corresponding to the first blocking portion 241 of Figure 4B is an oxide layer, the first blocking material layer may be retained. Therefore, as shown in Figure 4B , the first blocking portion 241 is disposed between the first upper insulating layer 261 and the second upper insulating layer 263 and the string selection line cut insulating layer SSLCI. However, since the second blocking material layer corresponding to the second blocking portion 242 of Figure 4B and the gate conductive material layer corresponding to the gate conductive layer 243 of Figure 4B have the characteristics of a metal layer, the second blocking material layer and the gate conductive material layer may be removed by the node separation process. Therefore, Figure 15A each of the first string selection line cut trench SCT1 and the first word line cut trench WCT1 of Figure 18A extends in the lateral direction, and thus the second string selection line cut trench SCT2 and the second word line cut trench WCT2 of

[0127] Then, referring to Figure 9 and Figure 19 , in P190, a selection line cut insulating material may be formed.

[0128] The selection line cut insulating material may fill Figure 18A the second string selection line cut trench SCT2 and the second word line cut trench WCT2 of

[0129] According to some embodiments, after forming the third upper insulating layer 265, a first bit line contact via 271 that penetrates the second upper insulating layer 263 and the third upper insulating layer 265 and contacts the channel layer 253 of the channel structure 250 may be further formed.

[0130] Then, referring to Figure 4A, an upper conductive pattern 273, a second bit line contact via 275, and a bit line BL can be further formed. Accordingly, a semiconductor memory device 10 can be provided.

[0131] Although the inventive concept has been specifically shown and described with reference to exemplary embodiments of the present invention, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the inventive concept. Accordingly, the above embodiments should be considered in a descriptive sense only and not for purposes of limitation.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: A plurality of gate electrodes arranged on a substrate and separated from each other in a first direction perpendicular to the upper surface of the substrate; A plurality of insulating layers arranged between the plurality of gate electrodes; An upper insulating layer arranged on the uppermost gate electrode among the plurality of gate electrodes; A plurality of channel structures penetrating the upper insulating layer, the plurality of gate electrodes, and the plurality of insulating layers in the first direction, each of the plurality of channel structures including a plurality of layers; A pair of word line cutting portions separating each of the plurality of gate electrodes and each of the plurality of insulating layers in a second direction parallel to the upper surface of the substrate; A plurality of string selection line cutting insulating layers arranged between the pair of word line cutting portions and separating both the upper insulating layer and the uppermost gate electrode in the second direction, such that the uppermost gate electrode is the separated uppermost gate electrode and the upper insulating layer is the separated upper insulating layer; And A first barrier layer located between the upper insulating layer and each of the plurality of string selection line cutting insulating layers, Wherein each of the plurality of string selection line cutting insulating layers includes a first protrusion protruding toward the separated uppermost gate electrode and located at the same level as the separated uppermost gate electrode, and Wherein the upper surface and the lower surface of the first protrusion are in contact with the first barrier layer.

2. The semiconductor memory device according to claim 1, Among them, Each of the plurality of string selection line cutting insulating layers is separated from the upper insulating layer.

3. The semiconductor memory device according to claim 1, Among them, A portion of each of the plurality of string selection line cutting insulating layers that is at the same level as the upper insulating layer has a width that decreases in a direction toward the substrate.

4. The semiconductor memory device according to claim 1, Among them, Each of the plurality of string selection line cutting insulating layers includes an upper surface having a first width and a lower surface having a second width that is greater than the first width of the upper surface.

5. The semiconductor memory device according to claim 4, Among them, The second width of the lower surface is the maximum width of each of the plurality of string selection line cutting insulating layers.

6. The semiconductor memory device according to claim 1, Among them, The first protrusion protrudes from opposite sidewalls of each of the plurality of string selection line cutting insulating layers.

7. The semiconductor memory device according to claim 1, Among them, The thickness of the first protrusion in the first direction is less than the thickness of the uppermost gate electrode in the first direction.

8. The semiconductor memory device according to claim 1, Among them, Each of the plurality of string selection line cutting insulating layers extends in a second direction parallel to the upper surface of the substrate, Wherein the plurality of channel structures include: A first group of first channel structures arranged adjacent to each other in a zigzag manner in the second direction; and A second group of second channel structures arranged adjacent to each other in a zigzag manner in the second direction, and Wherein each of the plurality of string selection line cutting insulating layers is provided between the first group of first channel structures and the second group of second channel structures.

9. A semiconductor memory device, the semiconductor memory device comprising: A plurality of gate electrodes arranged on a substrate and separated from each other in a first direction perpendicular to the upper surface of the substrate; A plurality of insulating layers arranged between the plurality of gate electrodes; An upper insulating layer arranged on a first gate electrode, the first gate electrode being the uppermost gate electrode among the plurality of gate electrodes; A plurality of channel structures penetrating the upper insulating layer, the plurality of gate electrodes, and the plurality of insulating layers in the first direction, each of the plurality of channel structures including a plurality of layers; A pair of word line cutting portions separating each of the plurality of gate electrodes and each of the plurality of insulating layers in a second direction parallel to the upper surface of the substrate; A plurality of string selection line cutting insulating layers arranged between the pair of word line cutting portions and separating the upper insulating layer in the second direction to form separated upper insulating layers, and separating the first gate electrode in the second direction to form a separated first gate electrode; And A first barrier layer located between the upper insulating layer and each of the plurality of string selection line cutting insulating layers, wherein each of the plurality of string selection line cutting insulating layers includes sidewalls separated from sidewalls of the separated upper insulating layer, wherein each of the plurality of string selection line cutting insulating layers includes a first protrusion protruding toward the first gate electrode and at the same level as the first gate electrode, and wherein upper and lower surfaces of the first protrusion contact the first barrier layer.

10. The semiconductor memory device according to claim 9, Among them, the plurality of string selection line cutting insulating layers further separating a second gate electrode arranged below the first gate electrode among the plurality of gate electrodes, and each of the plurality of string selection line cutting insulating layers further includes: A second protrusion protruding toward the second gate electrode and at the same level as the second gate electrode.

11. The semiconductor memory device according to claim 10, Among them, The first protrusion protrudes further than the second protrusion.

12. The semiconductor memory device according to claim 10, Among them, Each of the plurality of string selection line cutting insulating layers has a maximum width at the same level as the first protrusion.

13. The semiconductor memory device according to claim 10, Among them, The width of the upper surface of each of the plurality of string selection line cutting insulating layers is smaller than the width of each of the plurality of string selection line cutting insulating layers at the same level as the second gate electrode.

14. The semiconductor memory device according to claim 10, Among them, Each of the first gate electrode and the second gate electrode includes a first barrier layer, a second barrier layer, and a gate conductive layer, and upper and lower surfaces of the second protrusion contact the first barrier layer.

15. The semiconductor memory device according to claim 14, Among them, Side surfaces of the first protrusion and side surfaces of the second protrusion contact the second barrier layer and the gate conductive layer.

16. The semiconductor memory device according to claim 10, Among them, The number of the plurality of string selection line cutting insulating layers is two or more.

17. A semiconductor memory device, the semiconductor memory device comprising: A plurality of gate electrodes are arranged on a substrate to be separated from each other in a first direction perpendicular to the upper surface of the substrate. Each of the plurality of gate electrodes includes a gate conductive layer and a first barrier layer covering the gate conductive layer. The plurality of gate electrodes include: At least one ground selection gate electrode arranged on the substrate, A plurality of word line gate electrodes arranged on the at least one ground selection gate electrode, and At least one string selection gate electrode arranged on the plurality of word line gate electrodes; A plurality of insulating layers arranged between the plurality of gate electrodes; An upper insulating layer arranged on the at least one string selection gate electrode; A plurality of channel structures penetrate the upper insulating layer, the plurality of gate electrodes, and the plurality of insulating layers in the first direction. Each of the plurality of channel structures includes a plurality of layers; A pair of word line cut insulating layers, wherein the plurality of gate electrodes and the plurality of insulating layers are disposed between the pair of word line cut insulating layers to be separated from each other in a second direction parallel to the upper surface of the substrate, and A plurality of string selection line cut insulating layers are arranged between the pair of word line cut insulating layers and separate each of the upper insulating layer and the at least one string selection gate electrode in the second direction, Wherein, the first barrier layer included in the at least one string selection gate electrode is located between the upper insulating layer and each of the plurality of string selection line cut insulating layers, and Wherein, each of the plurality of string selection line cut insulating layers includes a first protrusion that protrudes toward the uppermost separated gate electrode and is at the same level as the uppermost separated gate electrode. And wherein, the upper surface and the lower surface of the first protrusion are in contact with the first barrier layer.

18. The semiconductor memory device according to claim 17, Among them, The first barrier layer includes a metal oxide.

19. The semiconductor memory device according to claim 17, Among them, The first barrier layer included in the at least one string selection gate electrode is also located between the uppermost insulating layer of the plurality of insulating layers and each of the plurality of string selection line cut insulating layers.

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