Silicon carbide bipolar transistor device with surge resistance and manufacturing method thereof

Abstract

The present invention relates to a silicon carbide bipolar transistor device with surge resistance and a manufacturing method thereof. The bipolar transistor device comprises a first-conductivity-type heavily doped silicon carbide substrate, a first-conductivity-type silicon carbide epitaxial region, stepped trenches, a second-conductivity-type body region, a Schottky metal layer, and an ohmic metal layer. Multiple stepped trenches are formed on the upper surface of the first-conductivity-type silicon carbide epitaxial region, and the width of the stepped trenches increases stepwise from bottom to top. A Schottky metal layer is provided on the upper surface of the first-conductivity-type silicon carbide epitaxial region and within the stepped trenches. The second-conductivity-type body region is stepped and surrounds the bottom surface of each trench level and the sidewalls of the trenches from the second to the last level. The present invention improves forward surge current resistance and has lower device forward conduction voltage, higher device withstand voltage, lower leakage current, better surge current resistance, and lower manufacturing cost.

Description

Technical Field

[0001] The present invention belongs to the technical field of silicon carbide Schottky bipolar transistors made of third-generation wide-bandgap semiconductor materials, and in particular relates to a silicon carbide bipolar transistor device with surge resistance capability and a manufacturing method thereof. Background Art

[0002] Silicon carbide (SiC) Schottky diodes (SBDs), a third-generation wide-bandgap semiconductor material, have gradually replaced silicon-based PiN diodes in high-voltage, high-current applications above 600V due to their high withstand voltage, low forward voltage drop, and fast reverse recovery time. However, SiC Schottky diodes also present challenges, such as tunneling and nano-pit defects on the SiC surface, which can lead to significant leakage current and surge current immunity. While the JBS (Junction Barrier Schottky) structure can reduce leakage current under reverse bias, it cannot effectively address surge current immunity. Surge currents typically occur when a power circuit is momentarily turned on or when the power supply is subjected to sudden external disturbances, such as lightning strikes. The surge currents encountered by devices can be several to dozens of times greater than the normal operating current. Summary of the Invention

[0003] One of the purposes of the present invention is to overcome the deficiencies in the prior art and provide a silicon carbide bipolar transistor device with surge protection capability that can reduce forward conduction voltage, increase breakdown voltage and reduce switching losses.

[0004] Another object of the present invention is to provide a method for manufacturing a silicon carbide bipolar transistor device with surge resistance.

[0005] According to the technical solution provided by the present invention, the silicon carbide bipolar transistor device with surge resistance includes a first conductivity type heavily doped silicon carbide substrate, a first conductivity type silicon carbide epitaxial region, a stepped trench, a second conductivity type body region, a Schottky metal layer and an ohmic metal layer;

[0006] This device includes a stepped trench Schottky metal layer region, which is located in the central region of the device. The stepped trench Schottky metal layer region includes a semiconductor substrate, which includes a first conductive type heavily doped silicon carbide substrate and a first conductive type silicon carbide epitaxial region located on the upper surface of the first conductive type heavily doped substrate. An ohmic metal layer with low contact resistance is provided on the lower surface of the first conductive type heavily doped substrate, and the ohmic metal layer serves as the cathode of the device. A plurality of stepped trenches are opened on the upper surface of the first conductive type silicon carbide epitaxial region, and the stepped trenches are formed by combining at least three levels of trenches, and the width of the stepped trenches increases step by step from bottom to top.

[0007] A Schottky metal layer is provided on the upper surface of the first conductive type silicon carbide epitaxial region and the inside of the stepped trench, and the Schottky metal layer serves as the anode of the device; the second conductive type body region is stepped, and the second conductive type body region surrounds the bottom surface of each level of the trench and the side walls of the second to last level of the trench from top to bottom.

[0008] Preferably, the depth of each step of the stepped groove is 0.3-1 μm.

[0009] Preferably, the thickness of the Schottky metal layer fixed to the upper surface of the first conductivity type silicon carbide epitaxial region is 100-1000 Å.

[0010] Preferably, the first conductive type heavily doped silicon carbide substrate and the first conductive type silicon carbide epitaxial body region are N-type conductive, and the second conductive type body region is P-type conductive.

[0011] Preferably, the Schottky metal layer is made of Ti or Ni.

[0012] Preferably, the ohmic metal layer is made of Ti / Ni / Ag alloy or Ti / Ni / Al alloy.

[0013] A method for manufacturing a silicon carbide bipolar transistor device with surge protection capability comprises the following steps:

[0014] Step 1. Providing a heavily doped silicon carbide substrate of a first conductivity type, growing a first conductivity type silicon carbide epitaxial region on an upper surface of the heavily doped silicon carbide substrate of the first conductivity type, wherein the upper surface of the first conductivity type silicon carbide epitaxial region is a first primary surface, and the lower surface of the heavily doped silicon carbide substrate of the first conductivity type is a second primary surface;

[0015] Step 2. Through the masking of the patterned photomask designed for the device, the first main surface of the first conductivity type silicon carbide epitaxial region is etched using reactive ion etching to form a plurality of first-level trenches;

[0016] Step 3. Using the device's designed single-pass patterned mask and the hard mask formed by etching the oxide layer from the first-stage trench sidewalls, a second reactive ion etch is performed on the bottom surface of each first-stage trench to form a second-stage trench. The width of the second etch is controlled to be smaller than the width of the first etch.

[0017] Step 4. Using the device's designed single-pass patterned mask and a hard mask formed from the oxide layer etched from the previous trench sidewalls, the bottom surface of the previous trench is etched at least once using reactive ion etching to form a trench. The width of each etch is controlled to be smaller than the width of the previous etch. Each level of trenches is combined to form a stepped trench. After the final trench etch, the oxide layer on the upper surface of the first conductivity type silicon carbide epitaxial region and within the trench is removed.

[0018] Step 5. Using a single-pass mask patterned after the device design, a second-conductivity-type material is implanted into the first-conductivity-type silicon carbide epitaxial body region corresponding to the bottom surface of each trench level and the sidewalls of the second to final trench levels using a high-temperature, high-energy ion device to form a second-conductivity-type body region surrounding the trenches.

[0019] Step 6. After the implantation is complete, use wet etching or hot HF to remove the surface oxide layer, and then use hot nitrogen to remove any remaining impurities on the surface.

[0020] Step 7. Coating a Schottky metal layer inside the stepped trench and on the upper surface of the first conductivity type silicon carbide epitaxial region, with the Schottky metal layer serving as the anode of the device;

[0021] Step 8. Plate a low-resistance ohmic metal layer on the second main surface of the first conductive type heavily doped silicon carbide substrate, with the ohmic metal layer serving as the cathode of the device.

[0022] Preferably, in step five, the angle of ion implantation is 0°.

[0023] The beneficial effects of the present invention are:

[0024] 1. The device of the present invention optimizes the single-pass mask design and simplifies the manufacturing process. A plurality of multi-layer stepped trench structures are etched on the upper surface of the first conductive type silicon carbide epitaxial region. By filling the stepped trenches with a Schottky metal layer, the contact area between the Schottky metal layer and the first conductive type silicon carbide epitaxial region is increased, reducing the resistance of the J1 interface and thereby lowering the forward conduction voltage of the device. The JBS device structure formed by the second conductive type body region is adjusted and designed with multi-dimensional variables such as the number of steps in the second conductive type body region, the depth and thickness of each step, etc., to optimize the distributed surface electric field. When the device is reverse biased, the peak distribution of the surface electric field of the first conductive type silicon carbide epitaxial region is reduced, thereby reducing the leakage current under reverse bias. When the second conductive type body region encounters a large forward surge current, it can provide minority carriers to reduce the resistance of the J2 interface, increase the forward current, and improve the ability to resist forward surge current.

[0025] 2. Compared with the traditional silicon carbide bipolar device structure, the device of the present invention has a lower device forward conduction voltage;

[0026] 3. Compared with the traditional silicon carbide bipolar device structure, the device of the present invention has a higher device withstand voltage;

[0027] 4. Compared with the traditional silicon carbide bipolar device structure, the device of the present invention has lower leakage current;

[0028] 5. Compared with the traditional silicon carbide bipolar device structure, the device of the present invention has better anti-surge current capability;

[0029] 6. Compared with the traditional silicon carbide bipolar device structure, the device of the present invention has optimized process steps and lower production cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 Schematic diagram of the cross-sectional structure of a first conductivity type silicon carbide heavily doped substrate and a first conductivity type silicon carbide epitaxial layer in an embodiment of the present invention.

[0031] Figure 2 Schematic diagram of the cross-sectional structure of a first layer of trenches formed by etching in a first conductivity type body region in an embodiment of the present invention.

[0032] Figure 3 Schematic diagram of the cross-sectional structure of the second layer trench formed by etching in the first conductive type body region in an embodiment of the present invention.

[0033] Figure 4 Schematic diagram of the cross-sectional structure of the third-layer trench formed by etching in the first conductive type body region in an embodiment of the present invention.

[0034] Figure 5 This is a schematic cross-sectional structural diagram of forming a second conductivity type body region by implanting second conductivity type material ions into the second layer trench and the third layer trench in an embodiment of the present invention.

[0035] Figure 6 Schematic diagram of the cross-sectional structure of the Schottky metal layer formed in an embodiment of the present invention

[0036] Figure 7 Schematic diagram of the cross-sectional structure of the back ohmic metal layer formed in an embodiment of the present invention.

[0037] FIG8 is a schematic diagram of the cross-sectional structure of a silicon carbide Schottky diode in the prior art.

[0038] FIG9 is a schematic diagram of the cross-sectional structure of a trench silicon carbide bipolar tube in the prior art. DETAILED DESCRIPTION

[0039] The present invention will be further described below with reference to specific embodiments.

[0040] A silicon carbide bipolar transistor device with surge protection capability includes a first-conductivity-type heavily doped silicon carbide substrate 1, a first-conductivity-type silicon carbide epitaxial region 2, a stepped trench 3, a second-conductivity-type body region 4, a Schottky metal layer 5, and an ohmic metal layer 6. The first-conductivity-type heavily doped silicon carbide substrate 1 is N+ type, the first-conductivity-type silicon carbide epitaxial region 2 is N- type, and the second-conductivity-type body region 4 is P+ type.

[0041] This device includes a stepped trench Schottky metal layer region, which is located in the central region of the device. The stepped trench Schottky metal layer region includes a semiconductor substrate, which includes a first conductive type heavily doped silicon carbide substrate 1 and a first conductive type silicon carbide epitaxial region 2 located on the upper surface of the first conductive type heavily doped substrate 1. An ohmic metal layer 6 with low contact resistance is provided on the lower surface of the first conductive type heavily doped substrate 1, and the ohmic metal layer 6 serves as the cathode of the device; a plurality of stepped trenches 3 are opened on the upper surface of the first conductive type silicon carbide epitaxial region 2, and the stepped trenches 3 are formed by a combination of at least three levels of trenches, and the width of the stepped trenches 3 increases step by step from bottom to top;

[0042] A Schottky metal layer 5 is provided on the upper surface of the first conductive type silicon carbide epitaxial region 2 and the inside of the stepped trench 3, and the Schottky metal layer 5 serves as the anode of the device; the second conductive type body region 4 is stepped, and the second conductive type body region 4 surrounds the bottom surface of each level of the trench and the side walls of the second to last level of the trench from top to bottom.

[0043] The depth of each step of the stepped trench 3 is 0.3–1 μm. The Schottky metal layer 5, affixed to the upper surface of the first-conductivity-type silicon carbide epitaxial region 2, has a thickness of 100–1000 Å. The Schottky metal layer 5 is made of Ti or Ni. The ohmic metal layer 6 is made of a Ti / Ni / Ag alloy or a Ti / Ni / Al alloy.

[0044] In an embodiment of the present invention, the first-level, second-level and third-level trench process steps in the stepped groove 3 cannot use the etching and diffusion process manufacturing methods of conventional silicon-based material processes due to the characteristics of the third-generation wide bandgap semiconductor silicon carbide material, so reactive ion etching (RIE) is used instead to perform multiple multi-layer trench etching on the first conductive type silicon carbide epitaxial region 2; the etching process of the stepped grooves 3, 4, and 5 only needs to use a single mask 7, and the hard mask formed by the oxide layer 8 in the etching process is used as a graphic design baffle, which can simplify the process and save production costs; the stepped groove 3 can increase the contact area between the Schottky metal layer 5 and the first conductive type silicon carbide epitaxial region 2, further reducing the J1 interface resistance and forward conduction voltage. The second conductive type body region 4 is formed by ion implanting boron or aluminum or other P+ materials at a 0-degree angle into the bottom surface of each level of trench and the sidewalls of the second to last level of trenches using a high-temperature, high-energy ion implantation device. During device design, the number of layers, height, and width of the second conductive type body region 4 can be controlled in multiple dimensions and multiple variables, and the number of control steps, as well as the height and width of each step, can be adjusted to better meet the design requirements of device voltage and leakage current parameters to optimize and reduce the surface electric field strength and leakage current. At the same time, the second conductive type body region 4 can also release minority carrier current when the forward voltage encounters a large current, thereby reducing the resistance of the J2 interface and enhancing the silicon carbide bipolar transistor's ability to resist forward surge currents.

[0045] The method for manufacturing the aforementioned silicon carbide bipolar transistor device with surge protection capability comprises the following steps:

[0046] Step 1. Providing a heavily doped silicon carbide substrate 1 of a first conductivity type, and growing a first conductivity type silicon carbide epitaxial region 2 on the upper surface of the heavily doped silicon carbide substrate 1, wherein the upper surface of the first conductivity type silicon carbide epitaxial region 2 is a first primary surface, and the lower surface of the heavily doped silicon carbide substrate 1 is a second primary surface;

[0047] Step 2. By blocking the patterned photomask of the device design, the first main surface of the first conductivity type silicon carbide epitaxial region 2 is etched using reactive ion etching to form a plurality of first-level trenches;

[0048] Step 3. Using the device's designed single-pass patterned mask and the hard mask formed by etching the oxide layer from the first-stage trench sidewalls, a second reactive ion etch is performed on the bottom surface of each first-stage trench to form a second-stage trench. The width of the second etch is controlled to be smaller than the width of the first etch.

[0049] Step 4. Using a patterned single-pass mask designed for the device and a hard mask formed by etching the oxide layer from the sidewalls of the second-stage trench, the bottom surface of the second-stage trench is etched using reactive ion etching to form a third-stage trench. The width of the third etch is controlled to be smaller than that of the second etch. The first, second, and third stages are combined to form a stepped trench 3. After the third-stage trench is etched, the oxide layer on the upper surface of the first-conductivity-type silicon carbide epitaxial region 2 and within the trench is removed.

[0050] Step 5. Through the device design pattern and single-pass mask, a second conductivity type material is implanted into the first conductivity type silicon carbide epitaxial region 2 corresponding to the bottom surfaces of the first, second, and third-level trenches and the sidewalls of the second and third-level trenches using a high-temperature, high-energy ion device to form a second conductivity type body region 4 surrounding the trenches. The ion implantation angle is 0°.

[0051] Step 6. After the implantation is complete, use wet etching or hot HF to remove the surface oxide layer, and then use hot nitrogen to remove any remaining impurities on the surface.

[0052] Step 7. A Schottky metal layer 5 is plated inside the stepped trench 3 and on the upper surface of the first conductivity type silicon carbide epitaxial region 2. The Schottky metal layer 5 serves as the anode of the device.

[0053] Step 8. A low-resistance ohmic metal layer 6 is plated on the second main surface of the first conductivity type heavily doped silicon carbide substrate 1 . The ohmic metal layer 6 serves as the cathode of the device.

[0054] Compared with the traditional planar silicon carbide Schottky two-stage tube structure (such as Figure 8 Compared to the silicon carbide bipolar transistor design with surge immunity of the present invention, the device structure with stepped trenches 3 increases the contact area between the Schottky metal layer 5 and the first conductivity type silicon carbide epitaxial region 2, thereby reducing the J1 interface resistance and lowering the forward conduction voltage of the device;

[0055] Compared with the original trench silicon carbide two-stage tube structure (such as Figure 9 Compared with the embodiment shown in the figure, the present invention utilizes the second conductive type body region 4 located outside the second and third level trenches to form a JBS structure, and forms a multi-level PN junction interface between the second conductive type body region 4 and the first conductive type silicon carbide epitaxial region 2. The number of steps, depth and width of the second conductive type body region 4 can be optimized and adjusted in three dimensions with multiple variables according to the electrical parameter characteristics of the device. When subjected to reverse bias withstand voltage, the surface electric field intensity can be better dispersed, so that the electric field distribution of the peak electric field on the surface of the device becomes smoother and more uniform. The peak point of the device is not easily broken down during withstand voltage, thereby effectively improving the breakdown voltage of the device.

[0056] When the device of the present invention is operated at a reverse bias voltage, compared with the original trench silicon carbide Schottky bipolar transistor device, the device of the present invention can reduce the leakage current of the device under the reverse bias voltage by optimizing the number of steps, depth and width of the second conductive type body region 4, thereby reducing the switching loss of the device.

[0057] Compared with the existing trench silicon carbide Schottky bipolar transistor device, the device structure of the present invention optimizes the structural design of the second conductivity type body region 4 and designs the second conductivity type body region 4 into a stepped structure. This allows the device of the present invention to release minority carriers when the forward voltage encounters a surge current, reducing the J2 interface resistance and further enhancing the ability to resist forward surge current.

[0058] During the manufacturing process of the present invention, only a single photomask 7 and a hard mask formed by the etched oxide layer 8 are required, which can simplify the process of forming the multi-level stepped trenches 3 and reduce the manufacturing cost.

Claims

1. A silicon carbide bipolar transistor device with surge resistance, comprising a first conductive type heavily doped silicon carbide substrate (1), a first conductive type silicon carbide epitaxial region (2), a stepped trench (3), a second conductive type body region (4), a Schottky metal layer (5) and an ohmic metal layer (6); Its characteristics are: The device comprises a stepped trench Schottky metal layer region, the stepped trench Schottky metal layer region is located in the central region of the device, the stepped trench Schottky metal layer region comprises a semiconductor substrate, the semiconductor substrate comprises a first conductive type heavily doped silicon carbide substrate (1) and a first conductive type silicon carbide epitaxial region (2) located on the upper surface of the first conductive type heavily doped substrate (1), an ohmic metal layer (6) with low contact resistance is provided on the lower surface of the first conductive type heavily doped substrate (1), and the ohmic metal layer (6) serves as the cathode of the device; a plurality of stepped trenches (3) are provided on the upper surface of the first conductive type silicon carbide epitaxial region (2), the stepped trenches (3) are formed by combining at least three levels of trenches, and the width of the stepped trenches (3) increases step by step in a direction from bottom to top; A Schottky metal layer (5) is provided on the upper surface of the first conductive type silicon carbide epitaxial region (2) and inside the stepped trench (3), and the Schottky metal layer (5) serves as the anode of the device; the second conductive type body region (4) is stepped, and the second conductive type body region (4) surrounds the bottom surface of each level of trench and the sidewalls of the second to last level trenches from top to bottom.

2. The silicon carbide bipolar transistor device with surge protection capability according to claim 1, wherein: The depth of each step of the stepped groove (3) is 0.3-1 μm.

3. The silicon carbide bipolar transistor device with surge protection capability according to claim 1, wherein: The thickness of the Schottky metal layer (5) fixed to the upper surface of the first conductive type silicon carbide epitaxial region (2) is 100-1000 Å.

4. The silicon carbide bipolar transistor device with surge protection capability according to claim 1, wherein: The first conductive type heavily doped silicon carbide substrate (1) and the first conductive type silicon carbide epitaxial region (2) are N-type conductive, and the second conductive type body region (4) is P-type conductive.

5. The silicon carbide bipolar transistor device with surge protection capability according to claim 1, wherein: The material of the Schottky metal layer (5) is Ti or Ni.

6. The silicon carbide bipolar transistor device with surge protection capability according to claim 1, wherein: The material of the ohmic metal layer (6) is Ti / Ni / Ag alloy or Ti / Ni / Al alloy.

7. A method for manufacturing a silicon carbide bipolar transistor device with surge protection capability comprises the following steps: Step 1. Providing a first conductive type heavily doped silicon carbide substrate (1), growing a first conductive type silicon carbide epitaxial region (2) on the upper surface of the first conductive type heavily doped silicon carbide substrate (1), wherein the upper surface of the first conductive type silicon carbide epitaxial region (2) is a first main surface, and the lower surface of the first conductive type heavily doped silicon carbide substrate (1) is a second main surface; Step 2. Through the shielding of the patterned photomask designed for the device, the first main surface located in the first conductive type silicon carbide epitaxial region (2) is etched for the first time using reactive ion etching to form a plurality of first-level trenches; Step 3. Through the hard mask formed by the graphic single-pass mask (7) of the device design and the oxide layer (8) after the first-level groove sidewall etching, a second etching is performed on the bottom surface of each first-level groove using reactive ion etching to form a second-level groove, and the width of the second etching is controlled to be smaller than the width of the first etching; Step 4. Through the hard mask formed by the graphic single-pass mask (7) of the device design and the oxide layer (8) after the sidewall of the previous groove is etched, the bottom surface of the previous groove is etched at least once using reactive ion etching to form a groove, and the width of each etching is controlled to be smaller than the width of the previous etching. Each level of grooves is combined to form a stepped groove (3). After the last trench etching is completed, the upper surface layer of the first conductive type silicon carbide epitaxial region (2) and the oxide layer inside the groove are removed; Step 5. Through the masking of the device design pattern single-pass photomask, a second conductive type material is implanted into the first conductive type silicon carbide epitaxial region (2) corresponding to the bottom surface of each level of trench and the sidewalls of the second to the last level of trenches using a high-temperature high-energy ion device to form a second conductive type body region (4) surrounding the trenches; Step 6. After the implantation is complete, use wet etching or hot HF to remove the surface oxide layer, and then use hot nitrogen to remove any remaining impurities on the surface. Step 7. A Schottky metal layer (5) is plated inside the stepped trench (3) and on the upper surface of the first conductive type silicon carbide epitaxial region (2), and the Schottky metal layer (5) serves as the anode of the device; Step 8. Plate a low-resistance ohmic metal layer (6) on the second main surface of the first conductive type heavily doped silicon carbide substrate (1), and the ohmic metal layer (6) serves as the cathode of the device.

8. The method for manufacturing a silicon carbide bipolar transistor device with surge protection capability according to claim 7, wherein: In step five, the ion implantation angle is 0°.

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