Display device and method of manufacturing the same

Abstract

The present invention discloses a display device and a manufacturing method thereof. The display device may include: a substrate; an organic light-emitting layer overlapping the substrate and including an opening; and a perforated insulating layer located between the substrate and the organic light-emitting layer. The perforated insulating layer may include a first through hole, a first groove, and a first undercut. The position of the opening may overlap with the position of the first groove. In a plan view of the display device, the first groove may surround the first through hole. In a plan view of the display device, the first undercut may surround the first groove.

Description

[0001] The technical field relates to a display device and a method for manufacturing the same. Background Art

[0002] A display device (such as a liquid crystal display device or an organic light emitting diode display device) may include various electrical / electronic components and / or optical components. The electrical / electronic components and / or optical components may control light transmission and / or light emission so that the display device may display an image.

[0003] If contaminants (e.g., moisture and / or oxygen) are introduced into the display device, the durability and / or performance of some of the electrical / electronic components and / or optical components may be degraded. For example, in an organic light emitting diode display device, the luminous efficiency of the organic light emitting layer may be reduced. As a result, the image display quality of the display device may be undesirable. Summary of the invention

[0004] Some example embodiments may relate to a display device capable of preventing the inflow of potential contaminants such as moisture and / or oxygen.

[0005] Some example embodiments may relate to a method of manufacturing a display device.

[0006] According to an example embodiment, a display device may include: a substrate including a display area and a non-display area located within the display area, a plurality of insulating layers disposed on the substrate, an organic light-emitting layer disposed on the insulating layer, and an undercut groove disposed in the non-display area and including a groove formed by removing at least one of the insulating layers and an undercut formed in a sidewall of the groove.

[0007] In example embodiments, the display device may further include: a buffer layer formed on the substrate, a first insulating layer formed on the buffer layer, a second insulating layer formed on the first insulating layer to cover a gate electrode formed on the first insulating layer, a third insulating layer formed on the second insulating layer to cover a capacitor electrode formed on the second insulating layer, and a fourth insulating layer formed on the third insulating layer to cover a source electrode and a drain electrode formed on the third insulating layer.

[0008] In example embodiments, the undercut groove may include: a groove formed by removing the buffer layer, the first insulating layer, the second insulating layer, and the third insulating layer, a first undercut formed in a first sidewall of the groove, and a second undercut formed in a second sidewall of the groove facing the first sidewall.

[0009] In example embodiments, a first undercut may be formed between the first insulating layer and the second insulating layer in the first sidewall. Additionally, a second undercut may be formed between the first insulating layer and the second insulating layer in the second sidewall.

[0010] In example embodiments, a first undercut may be formed between the second insulating layer and the third insulating layer in a first sidewall of the groove. Additionally, a second undercut may be formed between the second insulating layer and the third insulating layer in a second sidewall of the groove.

[0011] In example embodiments, the undercut groove may include: a groove formed by removing the second insulating layer and the third insulating layer, a first undercut formed between a bottom surface of the groove and a first sidewall, and a second undercut formed between the bottom surface of the groove and a second sidewall facing the first sidewall.

[0012] In example embodiments, a first undercut may be formed between the first insulating layer on the bottom surface and the second insulating layer on the first sidewall. In addition, a second undercut may be formed between the first insulating layer on the bottom surface and the second insulating layer on the second sidewall.

[0013] In example embodiments, the undercut groove may further include a third undercut formed between the second insulation layer and the third insulation layer in the first sidewall and a fourth undercut formed between the second insulation layer and the third insulation layer in the second sidewall.

[0014] In example embodiments, the undercut groove may include: a groove formed by removing the third insulating layer, a first undercut formed under the second insulating layer adjacent to a first sidewall of the groove, and a second undercut formed under the second insulating layer adjacent to a second sidewall of the groove facing the first sidewall.

[0015] In an example embodiment, the undercut groove may include: a groove formed by removing a buffer layer, a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer, a first undercut formed between the third insulating layer and the fourth insulating layer in a first side wall of the groove, and a second undercut formed between the third insulating layer and the fourth insulating layer in a second side wall of the groove facing the first side wall.

[0016] In example embodiments, the display device may further include a fifth insulating layer formed between the third insulating layer and the fourth insulating layer. In addition, the undercut groove may include: a groove formed by removing the buffer layer, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer, a first undercut formed between the first insulating layer and the fourth insulating layer in a first sidewall of the groove, and a second undercut formed between the first insulating layer and the fourth insulating layer in a second sidewall of the groove facing the first sidewall.

[0017] According to an example embodiment, a method for manufacturing a display device may include: forming a plurality of insulating layers on a substrate including a display area and a non-display area located within the display area, forming an undercut groove including a groove formed by removing at least one of the insulating layers formed in the non-display area and an undercut formed in a sidewall of the groove, and forming an organic light-emitting layer on the substrate having the undercut groove formed therein.

[0018] In example embodiments, forming the insulating layer may include forming a buffer layer on a substrate, forming a first insulating layer on the buffer layer, forming a second insulating layer on the first insulating layer to cover a gate electrode formed by a first conductive layer on the first insulating layer, forming a third insulating layer on the second insulating layer to cover a capacitor electrode formed by a second conductive layer on the second insulating layer, and forming a fourth insulating layer on the third insulating layer to cover a source electrode and a drain electrode formed by a third conductive layer on the third insulating layer.

[0019] In an example embodiment, forming the undercut groove may include: forming a first undercut electrode and a second undercut electrode spaced apart from the first undercut electrode in a non-display area by using a first conductive layer, forming the groove by removing a buffer layer, a first insulating layer, a second insulating layer, and a third insulating layer to expose the first undercut electrode and the second undercut electrode, and removing the first undercut electrode and the second undercut electrode to form a first undercut in a first sidewall of the groove in which the first undercut electrode is removed and forming a second undercut in a second sidewall of the groove in which the second undercut electrode is removed.

[0020] In an example embodiment, forming the undercut groove may include: forming a first undercut electrode and a second undercut electrode spaced apart from the first undercut electrode in a non-display area by using a second conductive layer, forming the groove by removing a buffer layer, a first insulating layer, a second insulating layer, and a third insulating layer to expose the first undercut electrode and the second undercut electrode, and removing the first undercut electrode and the second undercut electrode to form a first undercut in a first sidewall of the groove in which the first undercut electrode is removed and forming a second undercut in a second sidewall of the groove in which the second undercut electrode is removed.

[0021] In an example embodiment, forming the undercut groove may include: forming an undercut electrode in the non-display area by using a first conductive layer, forming the groove by removing a second insulating layer and a third insulating layer to expose a portion of a top surface of the undercut electrode, and removing the undercut electrode to form a first undercut in a first sidewall of the groove in which a first end of the undercut electrode is removed and forming a second undercut in a second sidewall of the groove in which a second end of the undercut electrode is removed.

[0022] In example embodiments, the method may further include removing the buffer layer and the first insulating layer exposed by the groove.

[0023] In an example embodiment, forming the undercut groove may include: forming a first undercut electrode in a non-display area by using a first conductive layer, forming a second undercut electrode overlapping a first end of the first undercut electrode and a third undercut electrode overlapping a second end of the first undercut electrode by using a second conductive layer, forming the groove by removing a second insulating layer and a third insulating layer to expose the first undercut electrode, the second undercut electrode, and the third undercut electrode; and removing the first undercut electrode, the second undercut electrode, and the third undercut electrode to form a first undercut between a bottom surface and a first side wall of the groove in which the first end of the first undercut electrode is removed, to form a second undercut between the bottom surface and the second side wall of the groove in which the second end of the first undercut electrode is removed, to form a third undercut in the first side wall in which the second undercut electrode is removed, and to form a fourth undercut in the second side wall in which the third undercut electrode is removed.

[0024] In an example embodiment, forming the undercut groove may include: forming a first undercut electrode and a second undercut electrode spaced apart from the first undercut electrode in a non-display area by using a first conductive layer, forming a third undercut electrode including a first end overlapping the first undercut electrode and a second end overlapping the second undercut electrode by using a second conductive layer, forming the groove by removing the second insulating layer and the third insulating layer to expose the first undercut electrode, the second undercut electrode, and the third undercut electrode, and removing the first undercut electrode, the second undercut electrode, and the third undercut electrode to form a first undercut under the second insulating layer adjacent to a first sidewall of the groove in which the first undercut electrode is removed, and to form a second undercut under the second insulating layer adjacent to a second sidewall of the groove in which the second undercut electrode is removed.

[0025] In an example embodiment, forming an undercut groove may include: forming a groove pattern in a non-display area by removing a buffer layer, a first insulating layer, a second insulating layer, and a third insulating layer, forming an undercut electrode including a bottom formed on a bottom surface of the groove pattern, a first side formed on a first sidewall of the groove pattern, a second side formed on a second sidewall of the groove pattern, a first end formed on a top of the third insulating layer connected to the first sidewall, and a second end formed on a top of the third insulating layer connected to the second sidewall by using a third conductive layer, forming the groove by removing a fourth insulating layer to expose the first side, the second side, and the bottom of the undercut electrode, and removing the undercut electrode to form a first undercut in the first sidewall of the groove in which the first end of the undercut electrode is removed and to form a second undercut in the second sidewall of the groove in which the second end of the undercut electrode is removed.

[0026] In an example embodiment, forming the undercut groove may include: forming a first undercut electrode and a second undercut electrode spaced apart from the first undercut electrode in a non-display area by using a first conductive layer, forming a groove pattern by removing a buffer layer, a first insulating layer, a second insulating layer, and a third insulating layer to expose the first undercut electrode and the second undercut electrode, forming a third undercut electrode including a first end in contact with the first undercut electrode, a first side in contact with a first sidewall of the groove pattern, a bottom in contact with a substrate, a second side in contact with a second sidewall of the groove pattern, and a second end in contact with the second undercut electrode by using a fourth conductive layer; forming a groove configured to expose the bottom, the first side, and the second side of the third undercut electrode by removing at least one of the insulating layers formed on the third undercut electrode; and removing the third undercut electrode and the first and second undercut electrodes in contact with the third undercut electrode to form a first undercut in the first sidewall of the groove in which the first ends of the first and third undercut electrodes are removed, and to form a second undercut in the second sidewall of the groove in which the second ends of the second and third undercut electrodes are removed.

[0027] Embodiments may relate to a display device. The display device may include: a substrate; an organic light-emitting layer overlapping the substrate and including an opening; and a perforated insulating layer located between the substrate and the organic light-emitting layer. The perforated insulating layer may include a first through hole, a first groove, and a first undercut. In a plan view of the display device, the first groove may surround the first through hole. The position of the opening may overlap the position of the first groove. In a plan view of the display device, the first undercut may surround the first groove. For example, the perforated insulating layer may be composed of Figure 3 Layer 160, Figure 8 Layer 180, Fig.12 Layer 160, Fig.17 Layer 160, Fig.21 Layer 160, Fig.25 Layer 210 and / or Fig.29 Layer 160 is shown in FIG.

[0028] The display device may include the following elements: a buffer layer formed on a substrate, an intermediate insulating layer between the buffer layer and the porous insulating layer, and a gate electrode between the intermediate insulating layer and the porous insulating layer. These features may be, for example, Figure 3 and / or Figure 8 Shown in.

[0029] The perforated insulating layer may include a second undercut, wherein the second undercut may surround the first through hole in a plan view of the display device, and wherein the first groove may surround the second undercut in a plan view of the display device. These features may be, for example, Figure 1 , Figure 2 , Figure 3 , Figure 8 , Fig.12 , Fig.17 , Fig.21 , Fig.25 and / or Fig.29 Shown in.

[0030] The display device may include the following elements: a transistor including a gate electrode; an intermediate insulating layer located between a substrate and a porous insulating layer, wherein the gate electrode may be located between the intermediate insulating layer and the porous insulating layer, and wherein a wall of the first undercut is in direct contact with the intermediate insulating layer. These features may be, for example, Figure 3 Shown in.

[0031] The display device may include the following elements: a transistor including a source electrode; an intermediate insulating layer located between a substrate and a perforated insulating layer, wherein the source electrode may be located between the perforated insulating layer and the organic light emitting layer, and wherein a wall of the first undercut is in direct contact with the intermediate insulating layer. These features may be, for example, Figure 8 Shown in.

[0032] The display device may include the following elements: an overlapping insulating layer overlapping the perforated insulating layer, located between the perforated insulating layer and the organic light emitting layer, and including a second groove, wherein the second groove may be directly connected to the first groove. These features may be, for example, Fig.12 Shown in.

[0033] The display device may include the following elements: A transistor including a source electrode, wherein the source electrode may be located between an overlying insulating layer and an organic light emitting layer. These features may be present in, for example, Fig.12 Shown in.

[0034] The display device may include the following elements: an overlapping insulating layer overlapping the apertured insulating layer and located between the apertured insulating layer and the organic light emitting layer, wherein the apertured insulating layer may include a second undercut. In a plan view of the display device, the second undercut may surround the first through hole. In a plan view of the display device, the first groove may surround the second undercut. The overlapping insulating layer may include a second groove, a third undercut, and a fourth undercut. The position of the second groove may overlap the position of the first groove. The fourth undercut may be closer to the first through hole than the second groove. The second groove may be closer to the first through hole than the third undercut. These features may be, for example, Figure 1 , Figure 2 and Fig.17 Shown in.

[0035] The display device may include the following elements: A transistor including a source electrode, wherein the source electrode may be located between an overlying insulating layer and an organic light emitting layer. These features may be present in, for example, Fig.17 Shown in.

[0036] The display device may include the following elements: a transistor including a source electrode; and a storage capacitor including a first capacitor electrode, wherein the porous insulating layer may be located between at least one of the source electrode and the first capacitor electrode and the organic light emitting layer. These features may be used, for example, Fig.25 Shown in.

[0037] The display device may include the following elements: an overlapping insulating layer located between the apertured insulating layer and the organic light emitting layer, overlapping the apertured insulating layer, partially located inside the first groove, and including an additional undercut, wherein the additional undercut may be at least partially located inside the first groove. These features may be, for example, Fig.29 Shown in.

[0038] Embodiments may relate to a method for manufacturing a display device. The method may include the following steps: forming a perforated insulating layer, wherein the perforated insulating layer may overlap with a substrate and include a first through hole, a first groove, and a first undercut, wherein in a plan view of the display device, the first groove may surround the first through hole, and wherein in a plan view of the display device, the first undercut may surround the first groove; and forming an organic light-emitting layer including an opening. The perforated insulating layer may be located between the substrate and the organic light-emitting layer. The location of the opening may overlap with the location of the first groove. For example, the perforated insulating layer may be composed of Figure 3 Layer 160, Figure 8 Layer 180, Fig.12 Layer 160, Fig.17 Layer 160, Fig.21 Layer 160, Fig.25 Layer 210 and / or Fig.29 Layer 160 in is represented.

[0039] The method may include the following steps: forming a storage capacitor, wherein the storage capacitor may include a first capacitor electrode and a second capacitor electrode, and wherein the first capacitor electrode may be located between the substrate and the second capacitor electrode; forming a transistor, wherein the transistor may include a gate electrode; forming a first conductive member, wherein a material of the first conductive member may be the same as a material of at least one of the first capacitor electrode and a material of the gate electrode; forming (and shaping) a first undercut using the first conductive member; and removing the first conductive member. These features may be, for example, Figures 3 to 7 Shown in.

[0040] The method may include the following steps: forming a buffer layer, wherein the buffer layer may be located between the substrate and the porous insulating layer, and may include a buffer layer groove, wherein the position of the buffer layer groove may overlap the position of the first groove; forming an organic member inside the buffer layer groove, wherein the material of the organic member may be the same as the material of the organic light emitting layer. These features may be, for example, Figure 3 and / or Figure 8 Shown in.

[0041] The method may include the following steps: forming a storage capacitor, wherein the storage capacitor may include a first capacitor electrode and a second capacitor electrode, and wherein the first capacitor electrode may be located between the substrate and the second capacitor electrode; forming a first conductive member, wherein the material of the first conductive member may be the same as the material of the second capacitor electrode; forming a first undercut using the first conductive member; and removing the first conductive member. These features may be present, for example, in Figures 8 to 11 Shown in.

[0042] The method may include the following steps: forming a storage capacitor, wherein the storage capacitor may include a first capacitor electrode and a second capacitor electrode, and wherein the first capacitor electrode may be located between the substrate and the second capacitor electrode; forming a transistor, wherein the transistor may include a gate electrode; forming a first conductive member, wherein a material of the first conductive member may be the same as a material of the first capacitor electrode and a material of the gate electrode; forming both a first undercut and a second undercut using the first conductive member, wherein the apertured insulating layer may include a second undercut, and wherein the first undercut may be closer to the first capacitor electrode than the second undercut; and removing the first conductive member. These features may be, for example, Figures 12 to 16 and / or Figures 17 to 20 Shown in.

[0043] The method may include the following steps: forming an organic member inside the first groove, wherein the material of the organic member may be the same as the material of the organic light emitting layer. These features may be, for example, Fig.12 and / or Fig.17 Shown in.

[0044] The method may include the following steps: forming an overlapping insulating layer, wherein the overlapping insulating layer may overlap the apertured insulating layer, may be located between the apertured insulating layer and the organic light emitting layer, and may include a third undercut; forming a second conductive member, wherein a material of the second conductive member may be the same as a material of the second capacitor electrode; forming the third undercut using the second conductive member; and removing the second conductive member. These features may be, for example, Figures 17 to 20 Shown in.

[0045] The method may include the following steps: forming an included insulating member inside the first groove, wherein the material of the included insulating member may be the same as the material of the perforated insulating layer, wherein the included insulating member may include an included undercut, and wherein the included undercut may be opposite to the first undercut; forming a storage capacitor, wherein the storage capacitor may include a first capacitor electrode and a second capacitor electrode, wherein the second capacitor electrode may be spaced apart from the first capacitor electrode; forming a transistor, wherein the transistor may include a gate electrode; forming a first conductive member, wherein the material of the first conductive member may be the same as at least one of the material of the first capacitor electrode and the material of the gate electrode; forming both the first undercut and the included undercut using the first conductive member; removing the first conductive member; forming a second conductive member, wherein the material of the second conductive member may be the same as the material of the second capacitor electrode, wherein a first portion of the second conductive member may be located inside the recess of the included insulating member, wherein a second portion of the second conductive member may be located outside the recess of the included insulating member and may overlap with the first conductive member; and removing the first portion of the second conductive member and the second portion of the second conductive member. These features may be, for example, Figure 21 to Figure 24 Shown in.

[0046] The method may include the following steps: forming a transistor, wherein the transistor may include a source electrode; forming a first conductive member, wherein the material of the first conductive member may be the same as the material of the source electrode; forming a first undercut using the first conductive member; and removing the first conductive member. These features may be present, for example, in Figure 25 to Figure 28 Shown in.

[0047] The method may include the following steps: forming a storage capacitor, wherein the storage capacitor may include a first capacitor electrode and a second capacitor electrode; forming a transistor, wherein the transistor may include a source electrode and a gate electrode; forming a connection electrode, wherein the source electrode may be electrically connected to the second capacitor electrode through the connection electrode; forming an overlapping insulating layer, wherein the overlapping insulating layer may overlap with the perforated insulating layer, may be located between the perforated insulating layer and the organic light-emitting layer, and may include an additional undercut and an additional groove, wherein the location of the additional groove may overlap with the location of the first groove; forming a first conductive member, wherein the material of the first conductive member may be the same as at least one of the material of the first capacitor electrode and the material of the gate electrode; forming a second conductive member, wherein the material of the second conductive member may be the same as the material of the connection electrode, and wherein the second conductive member may partially overlap with the first conductive member; forming a first undercut using the first conductive member; removing the first conductive member; forming an additional undercut using the second conductive member; and removing the second conductive member. These features may be, for example, Figure 29 to Figure 32 Shown in.

[0048] According to an embodiment, one or more undercuts of the insulating layer can effectively separate the organic material portion (e.g., a portion of the organic light emitting material layer). Advantageously, the display device according to the example embodiment can prevent potential contaminants such as moisture (e.g., in the external air) from being transmitted through the organic material layer into the display area. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 is a schematic plan view illustrating a display device according to example embodiments.

[0050] Figure 2 According to an example embodiment Figure 1 An enlarged view of portion A is shown in FIG.

[0051] Figure 3 It is along Figure 2 A cross-sectional view (or sectional view) taken along line II′ shown in FIG. 1 is used to describe a display device according to example embodiments.

[0052] Figure 4 , Figure 5 , Figure 6 and Figure 7 is a diagram showing the process of manufacturing an Figure 3 A cross-sectional view (or sectional view) of a structure formed in a method of displaying a device.

[0053] Figure 8 is a cross-sectional view for describing a display device according to example embodiments.

[0054] Fig. 9 , Fig.10 and Fig.11 It is shown in the manufacturing Figure 8 A cross-sectional view of a structure formed in a method of displaying a device.

[0055] Fig.12 is a cross-sectional view for describing a display device according to example embodiments.

[0056] Fig.13 , Fig.14 and Fig.15 It is shown in the manufacturing Fig.12 A cross-sectional view of a structure formed in a method of displaying a device.

[0057] Fig.16 is a cross-sectional view illustrating a structure formed in a method of manufacturing a display device according to example embodiments.

[0058] Fig.17 is a cross-sectional view for describing a display device according to example embodiments.

[0059] Fig.18 , Fig.19and Fig. 20 is a diagram showing the process of manufacturing an Fig.17 A cross-sectional view of a structure formed in a method of displaying a device.

[0060] Fig.21 is a cross-sectional view for describing a display device according to example embodiments.

[0061] Fig. 22 , Fig.23 and Fig.24 is a diagram showing the process of manufacturing an Fig.21 A cross-sectional view of a structure formed in a method of displaying a device.

[0062] Fig.25 is a cross-sectional view for describing a display device according to example embodiments.

[0063] Fig.26 , Fig. 27 and Fig.28 is a diagram showing the process of manufacturing an Fig.25 A cross-sectional view of a structure formed in a method of displaying a device.

[0064] Fig.29 is a cross-sectional view for describing a display device according to example embodiments.

[0065] Fig.30 , Fig.31 and Fig.32 is a diagram showing the process of manufacturing an Fig.29 A cross-sectional view of a structure formed in a method of displaying a device. DETAILED DESCRIPTION

[0066] Although the terms "first", "second", etc. can be used to describe various elements, these elements should not be limited by these terms. These terms can be used to distinguish one element from another element. The first element can be called the second element without departing from the teaching of one or more embodiments. Describing an element as a "first" element may not require or imply the existence of a second element or other elements. The terms "first", "second", etc. can be used to distinguish different element categories or element groups. For simplicity, the terms "first", "second", etc. can respectively represent "first type (or first group)", "second type (or second group)", etc.

[0067] Depending on the context, the term "removal" may mean "partial removal" or "complete removal". The term "groove" may mean "opening". The term "undercut" may mean "a (empty) recess having walls and a top". The term "electrode" may mean "a conductive member". The term "undercut electrode" may mean "a conductive member for forming an undercut". The term "removing the undercut electrode" may mean "using and removing the conductive member". The term "forming the undercut" may mean "forming and shaping the undercut". The term "external element" may mean a "functional element" for performing a function different from displaying an image. The term "connection" may mean "electrical connection". The term "insulation" may mean "electrical insulation". The term "contact" may mean "direct contact". The term "positioned together with..." may mean "surrounded by...". The term "pattern" may mean "member". The term "bottom surface of the groove" may mean "the surface of the insulating layer located below the groove". A column / multiple items may mean at least one of the items.

[0068] Figure 1 is a schematic plan view showing a display device according to an example embodiment, and Figure 2 According to an example embodiment Figure 1 An enlarged view of portion A is shown in FIG.

[0069] refer to Figure 1 and Figure 2 The display device 1000 includes a first substrate 100 ( Figure 3 ) and a second substrate 400 (shown in Figure 3 ).

[0070] The first substrate 100 and the second substrate 400 may include an insulating substrate including at least one of glass, quartz, plastic, etc. In one embodiment, the first substrate 100 and the second substrate 400 may include an insulating substrate formed of a rigid material such as glass or quartz.

[0071] The display device 1000 includes a display area DA, a light blocking area BMA, and a non-display area NDA.

[0072] The display area DA is a region configured to display an image, and the pixels P may be arranged in the display area DA.

[0073] The pixel P may be connected to the gate line GL, the data line DL, the first power signal ELVDD line, and the second power signal ELVSS line, and may include a storage capacitor and a plurality of transistors.

[0074] For example, the pixel P includes a first transistor TR1, a second transistor TR2, a storage capacitor CST, and an organic light emitting diode OLED.

[0075] The first transistor TR1 includes a gate electrode connected to the gate line GL, a source electrode connected to the data line DL, and a drain electrode connected to the first node N1. The second transistor TR2 includes a gate electrode connected to the first node N1, a source electrode connected to the first power signal ELVDD line, and a drain electrode connected to the organic light emitting diode OLED. The storage capacitor CST includes a first capacitor electrode connected to the first node N1 and a second capacitor electrode connected to the first power signal ELVDD line. The organic light emitting diode OLED includes an anode connected to the second transistor TR2 and a cathode connected to the second power signal ELVSS line.

[0076] When the first transistor TR1 is turned on by the gate signal transmitted from the gate line GL, the first transistor TR1 transmits the data signal transmitted from the data line DL to the first node N1. The second transistor TR2 supplies a driving current to the organic light emitting diode OLED based on a voltage difference between the first power signal ELVDD stored in the storage capacitor CST and the data signal applied to the first node N1. The organic light emitting diode OLED emits light based on the driving current.

[0077] The light blocking area BMA is an area configured to surround the edge of the display area DA, and is an area in which light is blocked. Various driving circuits for driving the pixels P may be provided in the light blocking area BMA.

[0078] The non-display area NDA is an area located within the display area DA, and the pixels P are not arranged in the non-display area NDA. The non-display area NDA may include an area in which a hole is formed by cutting the display device 1000 to dispose external elements having various functions such as a camera and a sensor.

[0079] refer to Figure 2 , the non-display area NDA may have at least one of various shapes such as, for example, a circular shape, a rectangular shape, or a polygonal shape.

[0080] The non-display area NDA may include a hole area HA, a sealing area SLA, a groove area GA, and a signal line area LA.

[0081] The hole area HA may include a hole (referred to as a first through hole in the claims), and an external element may be inserted into the hole.

[0082] The sealing area SLA may include a sealant configured to seal the first substrate 100 and the second substrate 400 of the display device 1000 .

[0083] The groove area GA is configured to block potential contaminants such as moisture in the air from being introduced into the display area DA.

[0084] The undercut groove UG1 (in the Figure 3 ) may be disposed in the groove area GA.

[0085] The undercut groove UG1 may include a groove GR formed by removing the insulating layer (in Figure 3 ), at least one first undercut UC1 formed in the first side wall of the groove GR (in Figure 3 ) and at least one second undercut UC2 formed in the second side wall of the groove GR facing the first side wall (in Figure 3 ).

[0086] The groove GR may be formed along the shape of the non-display area NDA. For example, the groove GR may have a shape similar to that of Figure 2 The non-display area NDA shown in FIG. 1 corresponds to a circular shape. In a plan view of the display device 1000, the first undercut UC1 may surround the groove GR, and the groove GR may surround the sealant 300 (in FIG. Figure 3 ), and each of the sealant 300 and the second undercut UC2 may surround the hole and the hole area HA.

[0087] A plurality of signal lines connected to external elements disposed in the non-display area NDA to transmit driving signals may be arranged in the signal line area LA. The signal lines may have segments formed along the shape of the non-display area NDA. For example, each of the signal lines may include a segment having a circular shape corresponding to the non-display area NDA.

[0088] According to an embodiment, the undercut groove UG1 formed in the groove area GA may prevent potential pollutants in the air from being introduced into the display area DA through a section of the hole area HA.

[0089] Figure 3 It is along Figure 2 1 is a cross-sectional view taken along line II′ shown in FIG. 1 for describing a display device according to an example embodiment.

[0090] refer to Figure 2 and Figure 3 The display device 1000 includes a first substrate 100 and a second substrate 400, and includes a display area DA (where pixels P are arranged) and a non-display area NDA (located within the display area DA). The non-display area NDA includes a signal line area LA, a groove area GA, a sealing area SLA, and a hole area HA.

[0091] The first substrate 100 includes a base substrate 110. The base substrate 110 may be an insulating substrate including glass, quartz, plastic, etc. In one embodiment, the base substrate 110 may be a rigid insulating substrate formed of glass or quartz.

[0092] The buffer layer 120 may be disposed on the base substrate 110 .

[0093] The buffer layer 120 may block potential contaminants such as oxygen or moisture from penetrating the base substrate 110. In addition, the buffer layer 120 may provide a flat surface on the base substrate 110. The buffer layer 120 may be an inorganic insulating layer including silicon nitride, silicon oxide, silicon oxynitride, etc. In embodiments, the buffer layer 120 may be optional.

[0094] The semiconductor layer AC may be disposed on the buffer layer 120. The semiconductor layer AC may be formed of amorphous silicon, polycrystalline silicon, an oxide semiconductor, or the like.

[0095] The semiconductor layer AC may include a source region, a channel region, and a drain region.

[0096] The first insulating layer 140 may be disposed on the semiconductor layer AC.

[0097] The first insulating layer 140 may be disposed on the buffer layer 120 to cover the semiconductor layer AC. The first insulating layer 140 may be an inorganic insulating layer including silicon nitride, silicon oxide, silicon oxynitride, or the like.

[0098] The first conductive patterns GE, E1, and L1 may be disposed on the first insulating layer 140. The first conductive patterns GE, E1, and L1 may include the gate electrode GE of the transistor TR and the first capacitor electrode E1 of the storage capacitor CST disposed in the display area DA, and may include the first signal line L1 in the signal line area LA.

[0099] The second insulating layer 160 may be disposed on the first conductive patterns GE, E1, and L1. The second insulating layer 160 may be disposed on the first insulating layer 140 to cover the first conductive patterns GE, E1, and L1. The second insulating layer 160 may be an inorganic insulating layer including silicon nitride, silicon oxide, silicon oxynitride, or the like.

[0100] The second conductive pattern E2 may be disposed on the second insulating layer 160 .

[0101] The second conductive pattern E2 may include a second capacitor electrode E2 of a storage capacitor CST disposed in the display area DA.

[0102] The third insulating layer 180 may be disposed on the second conductive pattern E2. The third insulating layer 180 may be disposed on the second insulating layer 160 to cover the second conductive pattern E2. The third insulating layer 180 may be an inorganic insulating layer including silicon nitride, silicon oxide, silicon oxynitride, etc., or may be an organic insulating layer including acrylic resin, epoxy resin, polyimide resin, polyester resin, etc.

[0103] The third conductive patterns SE, DE, and L2 may be disposed on the third insulating layer 180 .

[0104] The third conductive pattern SE, DE, and L2 may include the source electrode SE and the drain electrode DE of the transistor TR disposed in the display area DA, and may include the second signal line L2 disposed in the signal line area LA.

[0105] The source electrode SE and the drain electrode DE may be connected to the source region and the drain region of the semiconductor layer AC, respectively, through contact holes formed through the first insulating layer 140 , the second insulating layer 160 , and the third insulating layer 180 .

[0106] The fourth insulating layer 210 may be disposed on the third conductive patterns SE, DE, and L2. The fourth insulating layer 210 may be disposed on the third insulating layer 180 to cover the third conductive patterns SE, DE, and L2. The fourth insulating layer 210 may provide a flat surface on the third conductive patterns SE, DE, and L2. The fourth insulating layer 210 may be an organic insulating layer including acrylic resin, epoxy resin, polyimide resin, polyester resin, or the like, or may be an inorganic insulating layer including silicon nitride, silicon oxide, silicon oxynitride, or the like.

[0107] The pixel electrode 220 may be disposed on the fourth insulating layer 210. The pixel electrode 220 may be formed for each pixel P. The pixel electrode 220 may be connected to the transistor TR through a contact hole formed in the fourth insulating layer 210. The pixel electrode 220 may include metal, transparent conductive oxide, or the like.

[0108] The fifth insulating layer 230 may be disposed on the pixel electrode 220. The fifth insulating layer 230 may be disposed on the fourth insulating layer 210 to cover the edge of the pixel electrode 220. The fifth insulating layer 230 may include an opening configured to expose a portion of the pixel electrode 220. The opening may define a light emitting region of the pixel P. The fifth insulating layer 230 may include an organic insulating material such as an acrylic resin, an epoxy resin, a polyimide resin, or a polyester resin.

[0109] The organic light emitting layer 240 may be disposed substantially over the entire area of ​​the base substrate 110 on which the pixel electrode 220 is disposed. The organic light emitting layer 240 may be provided with a hole injection layer (HIL) and / or a hole transport layer (HTL) having excellent hole transport properties and configured to suppress the movement of electrons that are not recombined with holes in the organic light emitting layer 240 to increase the chance of recombination between holes and electrons.

[0110] The common electrode layer 250 may be disposed over the entire area of ​​the base substrate 110 on which the organic light emitting layer 240 is disposed. The common electrode layer 250 may overlap the pixel electrode 220. The common electrode layer 250 may include a metal, a transparent conductive oxide, etc. The organic light emitting diode OLED may be defined in an area where the pixel electrode 220, the organic light emitting layer 240, and the common electrode layer 250 overlap each other.

[0111] The undercut groove UG1 is provided in the groove area GA on the base substrate 110 .

[0112] In one embodiment, the undercut groove UG1 includes a groove GR formed by partially removing the buffer layer 120, the first insulating layer 140, the second insulating layer 160, and the third insulating layer 180. The undercut groove UG1 includes a first undercut UC1 formed between the first insulating layer 140 and the second insulating layer 160 in a first sidewall of the groove GR, and a second undercut UC2 formed between the first insulating layer 140 and the second insulating layer 160 in a second sidewall of the groove GR.

[0113] The sealant 300 for coupling the second substrate 400 to the first substrate 100 is disposed in the sealing area SLA on the base substrate 110 .

[0114] According to an embodiment, even when potential contaminants such as moisture and oxygen contained in the external air are introduced through a portion of the organic light emitting layer 240 exposed at the hole area HA, the potential contaminants are physically blocked / stopped by the undercut groove UG1 formed in the groove area GA, so that the potential contaminants can be prevented from being introduced into the display area DA. The undercuts UC1 and UC2 can effectively separate the organic material portion of the organic light emitting layer 240; therefore, the undercut groove UG1 can effectively prevent the potential contaminants from reaching the display area DA through the organic light emitting layer 240.

[0115] Figures 4 to 7 It is used to describe manufacturing Figure 3 A cross-sectional view of a method of displaying a device.

[0116] refer to Figure 4, the buffer layer 120 may be formed on the base substrate 110 . The semiconductor layer AC is formed on the buffer layer 120 .

[0117] The first insulating layer 140 is formed on the base substrate 110 on which the semiconductor layer AC is formed.

[0118] A first conductive layer is formed on the first insulating layer 140, and first conductive patterns GE, E1, M11, and M12 are formed by patterning the first conductive layer. The first conductive patterns GE, E1, M11, and M12 include a gate electrode GE of the transistor TR and a first capacitor electrode E1 of the storage capacitor CST formed in the display area DA, and include first and second undercut electrodes M11 and M12 formed in the groove area GA of the non-display area NDA.

[0119] The first undercut electrode M11 and the second undercut electrode M12 are spaced apart from each other, and a spacing distance between the first undercut electrode M11 and the second undercut electrode M12 may correspond to a width of a groove GR to be formed in a subsequent process.

[0120] The second insulating layer 160 is formed on the base substrate 110 on which the first conductive patterns GE, E1, M11, and M12 are formed.

[0121] refer to Figure 5 A second conductive layer is formed on the base substrate 110 on which the second insulating layer 160 is formed, and a second conductive pattern E2 is formed by patterning the second conductive layer. The second conductive pattern E2 may include a second capacitor electrode E2 of the storage capacitor CST formed in the display area DA.

[0122] After the second conductive pattern E2 is formed, impurities are doped into the semiconductor layer AC by using the gate electrode GE as a mask. Therefore, the semiconductor layer AC may be divided into a source region, a channel region, and a drain region.

[0123] The third insulating layer 180 is formed on the base substrate 110 on which the second conductive pattern E2 is formed. A plurality of contact holes are formed by etching the first insulating layer 140, the second insulating layer 160, and the third insulating layer 180 simultaneously.

[0124] The third conductive layer is formed on the base substrate 110 having the contact holes formed thereon, and third conductive patterns SE and DE are formed by patterning the third conductive layer.

[0125] The third conductive patterns SE and DE may include a source electrode SE and a drain electrode DE of the transistor TR formed in the display area DA. The source electrode SE may be connected to the source region of the semiconductor layer AC through a contact hole, and the drain electrode DE may be connected to the drain region of the semiconductor layer AC through a contact hole. In addition, the transistor TR may be connected to the second capacitor electrode E2 of the storage capacitor CST through a contact hole.

[0126] The fourth insulating layer 210 is formed on the base substrate 110 on which the third conductive patterns SE and DE are formed. A contact hole configured to expose the drain electrode DE of the transistor TR is formed by patterning the fourth insulating layer 210.

[0127] The pixel electrode 220 is formed by depositing a conductive material such as metal or transparent conductive oxide on the fourth insulating layer 210 having the contact hole and patterning the deposited conductive material.

[0128] The fifth insulating layer 230 is formed on the base substrate 110 on which the pixel electrode 220 is formed, and an opening configured to expose the pixel electrode 220 is formed by patterning the fifth insulating layer 230. The opening may define a light emitting region of the pixel P.

[0129] refer to Figure 6 , after the fifth insulating layer 230 is formed in the display area DA, the groove GR is formed in the groove area GA through an etching process.

[0130] The groove GR is formed by removing the buffer layer 120 , the first insulating layer 140 , the second insulating layer 160 , and the third insulating layer 180 between the first undercut electrode M11 and the second undercut electrode M12 .

[0131] The groove GR is configured to expose an end portion of the first undercut electrode M11 and an end portion of the second undercut electrode M12 .

[0132] The groove GR may include an upper region where the second insulating layer 160 and the third insulating layer 180 are removed with respect to the first undercut electrode M11 and the second undercut electrode M12, and a lower region where the buffer layer 120 and the first insulating layer 140 are removed. The upper region of the groove GR may have a first width W1, and the lower region of the groove GR may have a second width W2 less than the first width W1.

[0133] refer to Figure 7 Through the dry etching process, the entire first undercut electrode M11 and the second undercut electrode M12 may be removed through the ends of the first undercut electrode M11 and the second undercut electrode M12 exposed by the groove GR.

[0134] A first undercut UC1 (shaped and formed by using and removing the first undercut electrode M11) may be formed in the first sidewall of the groove GR, and a second undercut UC2 (shaped and formed by using and removing the second undercut electrode M12) may be formed in the second sidewall of the groove GR.

[0135] An undercut groove UG1 may be formed in the groove area GA.

[0136] The undercut groove UG1 may include a groove GR having a depth corresponding to the thickness of the buffer layer 120, the first insulating layer 140, the second insulating layer 160 and the third insulating layer 180, a first undercut UC1 formed between the first insulating layer 140 and the second insulating layer 160 in a first sidewall of the groove GR, and a second undercut UC2 formed between the first insulating layer 140 and the second insulating layer 160 in a second sidewall of the groove GR.

[0137] After the undercut groove UG1 is formed, the organic light emitting layer 240 and the common electrode layer 250 may be sequentially formed over the entire area of ​​the base substrate 110 .

[0138] The organic light emitting layer 240 and the common electrode layer 250 may be formed along the sidewall of the groove GR in the groove area GA, may be effectively disconnected by the undercuts UC1 and UC2, and may be formed on the bottom surface of the groove GR. Therefore, potential pollutants such as moisture and oxygen from the external air may be prevented from being introduced into the display area DA along the organic light emitting layer 240 formed of an organic material.

[0139] Hereinafter, the same elements as those described above may be denoted by the same reference numerals, and the related description may not be repeated.

[0140] Figure 8 is a cross-sectional view for describing a display device according to example embodiments.

[0141] refer to Figure 8 According to one embodiment, the display device may include a transistor TR, a storage capacitor CST, a pixel electrode 220, an organic light emitting layer 240, and a common electrode layer 250 disposed in the display area DA, and may include an undercut groove UG2 disposed in the groove area GA of the non-display area NDA.

[0142] The undercut groove UG2 includes a groove GR formed by removing the buffer layer 120, the first insulating layer 140, the second insulating layer 160, and the third insulating layer 180. The undercut groove UG2 includes a first undercut UC1 formed between the second insulating layer 160 and the third insulating layer 180 in a first sidewall of the groove GR, and a second undercut UC2 formed between the second insulating layer 160 and the third insulating layer 180 in a second sidewall of the groove GR.

[0143] Figures 9 to 11 It is used to describe manufacturing Figure 8 A cross-sectional view of a method of displaying a device.

[0144] refer to Fig. 9 , the buffer layer 120 may be formed on the base substrate 110 . The semiconductor layer AC is formed on the buffer layer 120 .

[0145] The first insulating layer 140 is formed on the base substrate 110 on which the semiconductor layer AC is formed.

[0146] A first conductive layer is formed on the first insulating layer 140, and first conductive patterns GE and E1 are formed by patterning the first conductive layer. The first conductive patterns GE and E1 include a gate electrode GE of the transistor TR formed in the display area DA and a first capacitor electrode E1 of the storage capacitor CST.

[0147] The second insulating layer 160 is formed on the base substrate 110 on which the first conductive patterns GE and E1 are formed.

[0148] The second conductive layer is formed on the base substrate 110 on which the second insulating layer 160 is formed, and the second conductive patterns E2 , M21 , and M22 are formed by patterning the second conductive layer.

[0149] The second conductive patterns E2 , M21 , and M22 may include the second capacitor electrode E2 of the storage capacitor CST formed in the display area DA, and may include the first and second undercut electrodes M21 and M22 formed in the groove area GA which is the non-display area NDA.

[0150] The first undercut electrode M21 and the second undercut electrode M22 may be spaced apart from each other.

[0151] After the second conductive patterns E2, M21, and M22 are formed, impurities are doped into the semiconductor layer AC by using the gate electrode GE as a mask. Therefore, the semiconductor layer AC may be divided into a source region, a channel region, and a drain region.

[0152] refer to Fig.10 The third insulating layer 180 is formed on the base substrate 110 on which the second conductive patterns E2, M21, and M22 are formed. The contact hole is formed by etching the first insulating layer 140, the second insulating layer 160, and the third insulating layer 180 simultaneously.

[0153] The third conductive layer is formed on the base substrate 110 having the contact holes formed thereon, and third conductive patterns SE and DE are formed by patterning the third conductive layer.

[0154] The third conductive patterns SE and DE may include a source electrode SE and a drain electrode DE of the transistor TR formed in the display area DA. The source electrode SE may be connected to the source region of the semiconductor layer AC through a contact hole, and the drain electrode DE may be connected to the drain region of the semiconductor layer AC through a contact hole. In addition, the transistor TR may be connected to the second capacitor electrode E2 of the storage capacitor CST through a contact hole.

[0155] The fourth insulating layer 210 is formed on the base substrate 110 on which the third conductive patterns SE and DE are formed. A contact hole configured to expose the drain electrode DE of the transistor TR is formed by patterning the fourth insulating layer 210.

[0156] The pixel electrode 220 is formed by depositing a conductive material such as metal or transparent conductive oxide on the fourth insulating layer 210 having the contact hole and patterning the deposited conductive material.

[0157] The fifth insulating layer 230 is formed on the base substrate 110 on which the pixel electrode 220 is formed, and an opening configured to expose the pixel electrode 220 is formed by patterning the fifth insulating layer 230. The opening may define a light emitting region of the pixel P.

[0158] refer to Fig.11 , after the fifth insulating layer 230 is formed in the display area DA, the groove GR is formed in the groove area GA through an etching process.

[0159] The groove GR is formed by removing the buffer layer 120 , the first insulating layer 140 , the second insulating layer 160 , and the third insulating layer 180 between the first undercut electrode M21 and the second undercut electrode M22 .

[0160] The groove GR is configured to expose ends of the first undercut electrode M21 and ends of the second undercut electrode M22 .

[0161] The groove GR may include an upper region where the third insulating layer 180 is removed with respect to the first and second undercut electrodes M21 and M22 and a lower region where the buffer layer 120, the first insulating layer 140, and the second insulating layer 160 are removed. The upper region of the groove GR may have a first width W1, and the lower region of the groove GR may have a second width W2 less than the first width W1.

[0162] refer to Figure 8 Through the dry etching process, the entire first undercut electrode M21 and the second undercut electrode M22 may be removed through the end portions of the first undercut electrode M21 and the second undercut electrode M22 exposed by the groove GR.

[0163] A first undercut UC1 formed by removing the first undercut electrode M21 may be formed in the first sidewall of the groove GR, and a second undercut UC2 formed by removing the second undercut electrode M22 may be formed in the second sidewall of the groove GR.

[0164] An undercut groove UG2 may be formed in the groove area GA.

[0165] The undercut groove UG2 may include a groove GR having a depth corresponding to the thickness of the buffer layer 120, the first insulating layer 140, the second insulating layer 160 and the third insulating layer 180, a first undercut UC1 formed between the second insulating layer 160 and the third insulating layer 180 in a first side wall of the groove GR, and a second undercut UC2 formed between the second insulating layer 160 and the third insulating layer 180 in a second side wall of the groove GR.

[0166] After the undercut groove UG2 is formed, the organic light emitting layer 240 and the common electrode layer 250 may be sequentially formed over the entire area of ​​the base substrate 110 .

[0167] The organic light emitting layer 240 and the common electrode layer 250 may be formed along the sidewall of the groove GR in the groove area GA, may be effectively disconnected by the undercuts UC1 and UC2, and may be formed on the bottom surface of the groove GR. Therefore, potential pollutants such as moisture and oxygen from the external air may be prevented from being introduced into the display area DA along the organic light emitting layer 240 formed of an organic material.

[0168] Fig.12 is a cross-sectional view for describing a display device according to example embodiments.

[0169] refer to Fig.12 According to one embodiment, a display device may include a transistor TR, a storage capacitor CST, a pixel electrode 220, an organic light emitting layer 240, and a common electrode layer 250 disposed in a display area DA, and may include an undercut groove UG3 disposed in a groove area GA of a non-display area NDA.

[0170] The undercut groove UG3 includes a first undercut UC1 formed in a first sidewall adjacent to the bottom surface of the groove GR and a second undercut UC2 formed in a second sidewall adjacent to the bottom surface of the groove GR.

[0171] The bottom surface of the groove GR may be the top surface of the first insulating layer 140. A first undercut UC1 may be formed between the first insulating layer 140 and the second insulating layer 160 in a first sidewall adjacent to the bottom surface of the groove GR, and a second undercut UC2 may be formed between the first insulating layer 140 and the second insulating layer 160 in a second sidewall adjacent to the bottom surface of the groove GR.

[0172] Figures 13 to 15 It is used to describe manufacturing Fig.12 A cross-sectional view of a method of displaying a device.

[0173] refer to Fig.13 , the buffer layer 120 may be formed on the base substrate 110 . The semiconductor layer AC is formed on the buffer layer 120 .

[0174] The first insulating layer 140 is formed on the base substrate 110 on which the semiconductor layer AC is formed.

[0175] A first conductive layer is formed on the first insulating layer 140, and first conductive patterns GE, E1, and M13 are formed by patterning the first conductive layer. The first conductive patterns GE, E1, and M13 may include a gate electrode GE of the transistor TR and a first capacitor electrode E1 of the storage capacitor CST formed in the display area DA, and may include an undercut electrode M13 formed in the groove area GA which is the non-display area NDA.

[0176] The undercut electrode M13 may have a width MW corresponding to a width of a groove GR to be formed in a subsequent process.

[0177] The second insulating layer 160 is formed on the base substrate 110 on which the first conductive patterns GE, E1, and M13 are formed.

[0178] refer to Fig.14 A second conductive layer is formed on the base substrate 110 on which the second insulating layer 160 is formed, and a second conductive pattern E2 is formed by patterning the second conductive layer. The second conductive pattern E2 may include a second capacitor electrode E2 of the storage capacitor CST formed in the display area DA.

[0179] After the second conductive pattern E2 is formed, impurities are doped into the semiconductor layer AC by using the gate electrode GE as a mask. Therefore, the semiconductor layer AC may be divided into a source region, a channel region, and a drain region.

[0180] The third insulating layer 180 is formed on the base substrate 110 on which the second conductive pattern E2 is formed. The contact hole is formed by etching the first insulating layer 140, the second insulating layer 160, and the third insulating layer 180 simultaneously.

[0181] The third conductive layer is formed on the base substrate 110 having the contact holes formed thereon, and third conductive patterns SE and DE are formed by patterning the third conductive layer.

[0182] The third conductive patterns SE and DE may include a source electrode SE and a drain electrode DE of the transistor TR formed in the display area DA. The source electrode SE may be connected to the source region of the semiconductor layer AC through a contact hole, and the drain electrode DE may be connected to the drain region of the semiconductor layer AC through a contact hole. In addition, the transistor TR may be connected to the second capacitor electrode E2 of the storage capacitor CST through a contact hole.

[0183] The fourth insulating layer 210 is formed on the base substrate 110 on which the third conductive patterns SE and DE are formed. A contact hole configured to expose the drain electrode DE of the transistor TR is formed by patterning the fourth insulating layer 210.

[0184] The pixel electrode 220 is formed by depositing a conductive material such as metal or transparent conductive oxide on the fourth insulating layer 210 having the contact hole and patterning the deposited conductive material.

[0185] The fifth insulating layer 230 is formed on the base substrate 110 on which the pixel electrode 220 is formed, and an opening configured to expose the pixel electrode 220 is formed by patterning the fifth insulating layer 230. The opening may define a light emitting region of the pixel P.

[0186] refer to Fig.15 , after the fifth insulating layer 230 is formed in the display area DA, the groove GR is formed in the groove area GA through an etching process.

[0187] The groove GR may be formed by removing the second insulating layer 160 and the third insulating layer 180 located on an upper portion with respect to the undercut electrode M13 .

[0188] The groove GR is configured to expose the top surface of the undercut electrode M13 without exposing the first end portion EP1 and the second end portion EP2 of the undercut electrode M13 .

[0189] refer to Fig.12 , through the dry etching process, the entire undercut electrode M13 may be removed through the top surface of the undercut electrode M13 exposed by the groove GR.

[0190] A first undercut UC1 formed by removing the first end EP1 of the undercut electrode M13 may be formed in the first sidewall of the groove GR, and a second undercut UC2 formed by removing the second end EP2 of the undercut electrode M13 may be formed in the second sidewall of the groove GR.

[0191] An undercut groove UG3 may be formed in the groove area GA.

[0192] The undercut groove UG3 may include a groove GR having a depth corresponding to the thickness of the undercut electrode M13, the second insulating layer 160, and the third insulating layer 180, a first undercut UC1 formed between the first insulating layer 140 and the second insulating layer 160 in a first sidewall adjacent to the bottom surface of the groove GR, and a second undercut UC2 formed between the first insulating layer 140 and the second insulating layer 160 in a second sidewall adjacent to the bottom surface of the groove GR. The bottom surface of the groove GR may be a top surface of the first insulating layer 140.

[0193] After the undercut groove UG3 is formed, the organic light emitting layer 240 and the common electrode layer 250 may be sequentially formed over the entire area of ​​the base substrate 110 .

[0194] The organic light emitting layer 240 and the common electrode layer 250 may be formed along the sidewall of the groove GR in the groove area GA, may be effectively disconnected by the undercuts UC1 and UC2, and may be formed on the bottom surface of the groove GR. Therefore, potential pollutants such as moisture and oxygen from the external air may be prevented from being introduced into the display area DA along the organic light emitting layer 240 formed of an organic material.

[0195] Fig.16 is a cross-sectional view for describing a method of manufacturing a display device according to example embodiments.

[0196] refer to Fig.16 , the display device according to one embodiment may include an undercut groove UG4 disposed in the groove area GA.

[0197] The method of manufacturing a display device including an undercut groove UG4 may include: Figures 12 to 15 The steps of the method of manufacturing the display device of the previous embodiment are described.

[0198] refer to Figures 12 to 15 , after the fifth insulating layer 230 is formed in the display area DA, the groove GR is formed in the groove area GA through an etching process.

[0199] The groove GR may be formed by removing the second insulating layer 160 and the third insulating layer 180 located on an upper portion with respect to the undercut electrode M13 .

[0200] Next, through the first dry etching process, the entire undercut electrode M13 may be removed through the top surface of the undercut electrode M13 exposed by the groove GR.

[0201] refer to Fig.16, a first undercut UC1 formed by removing the first end EP1 of the undercut electrode M13 may be formed in the first sidewall of the groove GR, and a second undercut UC2 formed by removing the second end EP2 of the undercut electrode M13 may be formed in the second sidewall of the groove GR.

[0202] Next, the buffer layer 120 and the first insulating layer 140 exposed by the removed undercut electrode M13 are etched by a second dry etching process. As the buffer layer 120 and the first insulating layer 140 are removed, the groove GR may become deeper corresponding to the thickness t of the buffer layer 120 and the first insulating layer 140.

[0203] According to this embodiment, the groove GR may include an upper region having a first depth d1 corresponding to the thickness of the second insulating layer 160 and the third insulating layer 180, and a lower region having a second depth d2 corresponding to the thickness of the buffer layer 120 and the first insulating layer 140 below the first undercut UC1 and the second undercut UC2.

[0204] After the undercut groove UG4 is formed, the organic light emitting layer 240 and the common electrode layer 250 may be sequentially formed over the entire area of ​​the base substrate 110 .

[0205] The organic light emitting layer 240 and the common electrode layer 250 may be formed along the sidewall of the groove GR in the groove area GA, may be effectively disconnected by the undercuts UC1 and UC2, and may be formed on the bottom surface of the groove GR. Therefore, potential pollutants such as moisture and oxygen from the external air may be prevented from being introduced into the display area DA along the organic light emitting layer 240 formed of an organic material.

[0206] Fig.17 is a cross-sectional view for describing a display device according to example embodiments.

[0207] refer to Fig.17 According to one embodiment, a display device may include a transistor TR, a storage capacitor CST, a pixel electrode 220, an organic light emitting layer 240, and a common electrode layer 250 disposed in a display area DA, and may include an undercut groove UG5 disposed in a groove area GA of a non-display area NDA.

[0208] The undercut groove UG5 includes a groove GR formed by removing the second insulating layer 160 and the third insulating layer 180. The undercut groove UG5 includes a first undercut UC1, a second undercut UC2, a third undercut UC3, and a fourth undercut UC4 formed in a sidewall of the groove GR.

[0209] A first undercut UC1 is formed between the first insulating layer 140 and the second insulating layer 160 in the first side wall of the groove GR, a second undercut UC2 is formed between the first insulating layer 140 and the second insulating layer 160 in the second side wall of the groove GR, a third undercut UC3 is formed between the second insulating layer 160 and the third insulating layer 180 in the first side wall of the groove GR, and a fourth undercut UC4 is formed between the second insulating layer 160 and the third insulating layer 180 in the second side wall of the groove GR.

[0210] The undercut groove UG5 may include the groove GR, first and third undercuts UC1 and UC3 formed in a first sidewall of the groove GR, and second and fourth undercuts UC2 and UC4 formed in a second sidewall of the groove GR.

[0211] Figures 18 to 20 It is used to describe manufacturing Fig.17 A cross-sectional view of a method of displaying a device.

[0212] refer to Fig.18 , the buffer layer 120 may be formed on the base substrate 110 . The semiconductor layer AC is formed on the buffer layer 120 .

[0213] The first insulating layer 140 is formed on the base substrate 110 on which the semiconductor layer AC is formed.

[0214] A first conductive layer is formed on the first insulating layer 140, and first conductive patterns GE, E1, and M13 are formed by patterning the first conductive layer. The first conductive patterns GE, E1, and M13 may include a gate electrode GE of the transistor TR and a first capacitor electrode E1 of the storage capacitor CST formed in the display area DA, and may include an undercut electrode M13 formed in the groove area GA which is the non-display area NDA. The undercut electrode M13 may have a width MW corresponding to a width of a groove GR to be formed in a subsequent process.

[0215] The second insulating layer 160 is formed on the base substrate 110 on which the first conductive patterns GE, E1, and M13 are formed.

[0216] The second conductive layer is formed on the second insulating layer 160, and the second conductive patterns E2, M21, and M22 are formed by patterning the second conductive layer. The second conductive patterns E2, M21, and M22 may include a second capacitor electrode E2 of the storage capacitor CST formed in the display area DA, and may include a first undercut electrode M21 formed in the groove area GA which is the non-display area NDA and a second undercut electrode M22 spaced apart from the first undercut electrode M21. The first undercut electrode M21 may overlap with the first end portion EP1 of the undercut electrode M13, and the second undercut electrode M22 may overlap with the second end portion EP2 of the undercut electrode M13.

[0217] refer to Fig.19 After the second conductive patterns E2, M21, and M22 are formed, impurities are doped into the semiconductor layer AC by using the gate electrode GE as a mask. Therefore, the semiconductor layer AC may be divided into a source region, a channel region, and a drain region.

[0218] The third insulating layer 180 is formed on the base substrate 110 on which the second conductive patterns E2, M21, and M22 are formed. The contact holes are formed by etching the first insulating layer 140, the second insulating layer 160, and the third insulating layer 180 simultaneously.

[0219] The third conductive layer is formed on the base substrate 110 having the contact holes formed thereon, and third conductive patterns SE and DE are formed by patterning the third conductive layer.

[0220] The third conductive patterns SE and DE may include a source electrode SE and a drain electrode DE of the transistor TR formed in the display area DA. The source electrode SE may be connected to the source region of the semiconductor layer AC through a contact hole, and the drain electrode DE may be connected to the drain region of the semiconductor layer AC through a contact hole. In addition, the transistor TR may be connected to the second capacitor electrode E2 of the storage capacitor CST through a contact hole.

[0221] The fourth insulating layer 210 is formed on the base substrate 110 on which the third conductive patterns SE and DE are formed. A contact hole configured to expose the drain electrode DE of the transistor TR is formed by patterning the fourth insulating layer 210.

[0222] The pixel electrode 220 is formed by depositing a conductive material such as metal or transparent conductive oxide on the fourth insulating layer 210 having the contact hole and patterning the deposited conductive material.

[0223] The fifth insulating layer 230 is formed on the base substrate 110 on which the pixel electrode 220 is formed, and an opening configured to expose the pixel electrode 220 is formed by patterning the fifth insulating layer 230. The opening may define a light emitting region of the pixel P.

[0224] refer to Fig. 20 , after the fifth insulating layer 230 is formed in the display area DA, the groove GR is formed in the groove area GA through an etching process.

[0225] The groove GR may be formed by removing the second insulating layer 160 located on the lower portion and the third insulating layer 180 located on the upper portion with respect to the first undercut electrode M21 and the second undercut electrode M22 .

[0226] Meanwhile, the second insulating layer 160 located on the first end portion EP1 of the undercut electrode M13 and the second insulating layer 160 located on the second end portion EP2 of the undercut electrode M13 are not etched.

[0227] The groove GR is configured to expose a portion of the top surface of the undercut electrode M13 , and is configured to expose ends of the first undercut electrode M21 and the second undercut electrode M22 .

[0228] refer to Fig.17 and Fig. 20 , through the dry etching process, the entire undercut electrode M13 can be removed through the top surface of the undercut electrode M13 exposed by the groove GR. In addition, through the dry etching process, the entire first undercut electrode M21 and the second undercut electrode M22 can be removed through the end portions of the first undercut electrode M21 and the second undercut electrode M22 exposed by the groove GR.

[0229] A first undercut UC1 formed by removing the first end EP1 of the undercut electrode M13 and a third undercut UC3 formed by removing the first undercut electrode M21 may be formed in the first sidewall of the groove GR. In addition, a second undercut UC2 formed by removing the second end EP2 of the undercut electrode M13 and a fourth undercut UC4 formed by removing the second undercut electrode M22 may be formed in the second sidewall of the groove GR.

[0230] An undercut groove UG5 may be formed in the groove area GA.

[0231] The undercut groove UG5 may include a groove GR having a depth corresponding to the thickness of the undercut electrode M13, the second insulating layer 160 and the third insulating layer 180, may include a first undercut UC1 formed between the second insulating layer 160 and the first insulating layer 140 protruding from the first side wall of the groove GR, and a third undercut UC3 formed between the second insulating layer 160 and the third insulating layer 180 protruding from the first side wall of the groove GR, and may include a second undercut UC2 formed between the second insulating layer 160 and the first insulating layer 140 protruding from the second side wall of the groove GR, and a fourth undercut UC4 formed between the second insulating layer 160 and the third insulating layer 180 protruding from the second side wall of the groove GR.

[0232] After the undercut groove UG5 is formed, the organic light emitting layer 240 and the common electrode layer 250 may be sequentially formed over the entire area of ​​the base substrate 110 .

[0233] The organic light emitting layer 240 and the common electrode layer 250 may be formed along the sidewall of the groove GR in the groove area GA, may be effectively disconnected by the undercuts UC1, UC2, UC3, and UC4, and may be formed on the bottom surface of the groove GR. Therefore, potential pollutants such as moisture and oxygen from the external air may be prevented from being introduced into the display area DA along the organic light emitting layer 240 formed of an organic material.

[0234] Fig.21 is a cross-sectional view for describing a display device according to example embodiments.

[0235] refer to Fig.21 According to one embodiment, a display device may include a transistor TR, a storage capacitor CST, a pixel electrode 220, an organic light emitting layer 240, and a common electrode layer 250 disposed in a display area DA, and may include an undercut groove UG6 disposed in a groove area GA of a non-display area NDA.

[0236] The undercut groove UG6 includes a groove GR formed by removing the second insulating layer 160 and the third insulating layer 180. In addition, the undercut groove UG6 may include a first undercut UC1 located at a bottom surface adjacent to the first sidewall of the groove GR and a second undercut UC2 located at a bottom surface adjacent to the second sidewall of the groove GR. The undercut groove UG6 may include an included insulating member located between the undercuts UC1 and UC2. The included insulating member may be part of the second insulating layer 160, that is, the material of the included insulating member may be the same as that of the second insulating layer 160. The included insulating member may include two undercuts respectively opposite to the undercuts UC1 and UC2.

[0237] Figure 22 to Figure 24 It is used to describe manufacturing Fig.21 A cross-sectional view of a method of displaying a device.

[0238] refer to Fig. 22 , the buffer layer 120 may be formed on the base substrate 110 . The semiconductor layer AC is formed on the buffer layer 120 .

[0239] The first insulating layer 140 is formed on the base substrate 110 on which the semiconductor layer AC is formed.

[0240] A first conductive layer is formed on the first insulating layer 140, and first conductive patterns GE, E1, M11, and M12 are formed by patterning the first conductive layer. The first conductive patterns GE, E1, M11, and M12 may include a gate electrode GE of the transistor TR and a first capacitor electrode E1 of the storage capacitor CST formed in the display area DA, and may include a first undercut electrode M11 formed in the groove area GA which is the non-display area NDA and a second undercut electrode M12 spaced apart from the first undercut electrode M11. The first undercut electrode M11 and the second undercut electrode M12 may correspond to first undercuts UC1 and second undercuts UC2 to be formed in a bottom surface adjacent to a sidewall of the groove GR in a subsequent process, respectively.

[0241] The second insulating layer 160 is formed on the base substrate 110 on which the first conductive patterns GE, E1, M11, and M12 are formed.

[0242] The second conductive layer is formed on the second insulating layer 160, and the second conductive patterns E2 and M23 are formed by patterning the second conductive layer. The second conductive patterns E2 and M23 may include the second capacitor electrode E2 of the storage capacitor CST formed in the display area DA, and may include the third undercut electrode M23 formed in the groove area GA which is the non-display area NDA. The third undercut electrode M23 may be disposed in the interval area between the first undercut electrode M11 and the second undercut electrode M12, the first end EP1 of the third undercut electrode M23 may partially overlap with the first undercut electrode M11, and the second end EP2 of the third undercut electrode M23 may partially overlap with the second undercut electrode M12.

[0243] refer to Fig.23 After the second conductive patterns E2 and M23 are formed, impurities are doped into the semiconductor layer AC by using the gate electrode GE as a mask. Therefore, the semiconductor layer AC may be divided into a source region, a channel region, and a drain region.

[0244] The third insulating layer 180 is formed on the base substrate 110 on which the second conductive patterns E2 and M23 are formed. The contact holes are formed by etching the first insulating layer 140, the second insulating layer 160, and the third insulating layer 180 simultaneously.

[0245] The third conductive layer is formed on the base substrate 110 having the contact holes formed thereon, and third conductive patterns SE and DE are formed by patterning the third conductive layer.

[0246] The third conductive patterns SE and DE may include a source electrode SE and a drain electrode DE of the transistor TR formed in the display area DA. The source electrode SE may be connected to the source region of the semiconductor layer AC through a contact hole, and the drain electrode DE may be connected to the drain region of the semiconductor layer AC through a contact hole. In addition, the transistor TR may be connected to the second capacitor electrode E2 of the storage capacitor CST through a contact hole.

[0247] The fourth insulating layer 210 is formed on the base substrate 110 on which the third conductive patterns SE and DE are formed. A contact hole configured to expose the drain electrode DE of the transistor TR is formed by patterning the fourth insulating layer 210.

[0248] The pixel electrode 220 is formed by depositing a conductive material such as metal or transparent conductive oxide on the fourth insulating layer 210 having the contact hole and patterning the deposited conductive material.

[0249] The fifth insulating layer 230 is formed on the base substrate 110 on which the pixel electrode 220 is formed, and an opening configured to expose the pixel electrode 220 is formed by patterning the fifth insulating layer 230. The opening may define a light emitting region of the pixel P.

[0250] refer to Fig.24 , after the fifth insulating layer 230 is formed in the display area DA, the groove GR is formed in the groove area GA through an etching process.

[0251] The groove GR may be formed by removing the third insulating layer 180 on the upper portion of the third undercut electrode M23 and the second insulating layer 160 on the upper portions of the first and second undercut electrodes M11 and M12 and exposed by the third undercut electrode M23 .

[0252] The groove GR is configured to expose the top surface and side surface of the third undercut electrode M23. In addition, the groove GR is configured to expose the top surface of the first undercut electrode M11 that does not overlap with the first end EP1 of the third undercut electrode M23 and the top surface of the second undercut electrode M12 that does not overlap with the second end EP2 of the third undercut electrode M23.

[0253] refer to Fig.21 and Fig.24 , through the dry etching process, the entire third undercut electrode M23 can be removed through the top surface and side surface of the third undercut electrode M23 exposed by the groove GR. In addition, the entire first undercut electrode M11 and the second undercut electrode M12 can be removed through the top surfaces of the first undercut electrode M11 and the second undercut electrode M12 exposed by the groove GR.

[0254] The bottom surface of the groove GR may be formed as the top surface of the second insulating layer 160. A first undercut UC1 may be formed in the bottom surface adjacent to the first sidewall of the groove GR between the first insulating layer 140 and the second insulating layer 160, and a second undercut UC2 may be formed in the bottom surface adjacent to the second sidewall of the groove GR between the first insulating layer 140 and the second insulating layer 160.

[0255] An undercut groove UG6 may be formed in the groove area GA.

[0256] The undercut groove UG6 may include a groove GR having a depth corresponding to the thickness of the third insulating layer 180 , a first undercut UC1 formed in a bottom surface adjacent to a first sidewall of the groove GR, and a second undercut UC2 formed in a bottom surface adjacent to a second sidewall of the groove GR.

[0257] After the undercut groove UG6 is formed, the organic light emitting layer 240 and the common electrode layer 250 may be sequentially formed over the entire area of ​​the base substrate 110 .

[0258] The organic light emitting layer 240 and the common electrode layer 250 may be formed along the sidewall of the groove GR in the groove area GA, may be effectively disconnected by the undercuts UC1 and UC2, and may be formed on the bottom surface of the groove GR. Therefore, potential pollutants such as moisture and oxygen from the external air may be prevented from being introduced into the display area DA along the organic light emitting layer 240 formed of an organic material.

[0259] Fig.25 is a cross-sectional view for describing a display device according to example embodiments.

[0260] refer to Fig.25 According to one embodiment, a display device may include a transistor TR, a storage capacitor CST, a pixel electrode 220, an organic light emitting layer 240, and a common electrode layer 250 disposed in a display area DA, and may include an undercut groove UG7 disposed in a groove area GA of a non-display area NDA.

[0261] The undercut groove UG7 includes a groove GR formed by removing the buffer layer 120, the first insulating layer 140, the second insulating layer 160, the third insulating layer 180, and the fourth insulating layer 210. In addition, the undercut groove UG7 includes a first undercut UC1 formed between the third insulating layer 180 and the fourth insulating layer 210 in a first sidewall of the groove GR, and a second undercut UC2 formed between the third insulating layer 180 and the fourth insulating layer 210 in a second sidewall of the groove GR.

[0262] Figure 26 to Figure 28 It is used to describe manufacturing Fig.25 A cross-sectional view of a method of displaying a device.

[0263] refer to Fig.26 , the buffer layer 120 may be formed on the base substrate 110 . The semiconductor layer AC is formed on the buffer layer 120 .

[0264] The first insulating layer 140 is formed on the base substrate 110 on which the semiconductor layer AC is formed.

[0265] A first conductive layer is formed on the first insulating layer 140, and first conductive patterns GE and E1 are formed by patterning the first conductive layer. The first conductive patterns GE and E1 may include a gate electrode GE of the transistor TR formed in the display area DA and a first capacitor electrode E1 of the storage capacitor CST.

[0266] The second insulating layer 160 is formed on the base substrate 110 on which the first conductive patterns GE and E1 are formed. The second conductive layer is formed on the second insulating layer 160, and the second conductive pattern E2 is formed by patterning the second conductive layer. The second conductive pattern E2 may include a second capacitor electrode E2 of the storage capacitor CST formed in the display area DA.

[0267] The third insulating layer 180 is formed on the base substrate 110 on which the second conductive pattern E2 is formed. A plurality of contact holes are formed in the display area DA by simultaneously etching the first insulating layer 140, the second insulating layer 160, and the third insulating layer 180, and the first groove pattern GP1 is formed in the groove area GA which is the non-display area NDA by simultaneously etching the buffer layer 120 and the first insulating layer 140, the second insulating layer 160, and the third insulating layer 180. The contact holes in the display area DA may be formed by removing the first insulating layer 140, the second insulating layer 160, and the third insulating layer 180 to expose the semiconductor layer AC and the second capacitor electrode E2. The first groove pattern GP1 in the groove area GA may be formed by removing the buffer layer 120, the first insulating layer 140, the second insulating layer 160, and the third insulating layer 180 to expose the base substrate 110.

[0268] The third conductive layer is formed on the base substrate 110 on which the contact hole and the first groove pattern GP1 are formed, and the third conductive patterns SE, DE, and M31 are formed by patterning the third conductive layer.

[0269] The third conductive patterns SE, DE, and M31 may include the source electrode SE and the drain electrode DE of the transistor TR formed in the display area DA, and may include an undercut electrode M31 located in the groove area GA.

[0270] The source electrode SE may be connected to the source region of the semiconductor layer AC through the contact hole, and the drain electrode DE may be connected to the drain region of the semiconductor layer AC through the contact hole. In addition, the transistor TR may be connected to the second capacitor electrode E2 of the storage capacitor CST through the contact hole.

[0271] The bottom cut electrode M31 may include a bottom MB formed on the bottom surface of the first groove pattern GP1, a first side MS1 formed on the first side wall of the first groove pattern GP1, a second side MS2 formed on the second side wall of the first groove pattern GP1, a first end ME1 formed on the top of the third insulating layer 180 connected to the first side wall, and a second end ME2 formed on the top of the third insulating layer 180 connected to the second side wall.

[0272] refer to Fig. 27 The fourth insulating layer 210 is formed on the base substrate 110 on which the third conductive patterns SE, DE and M31 are formed. A contact hole configured to expose the drain electrode DE of the transistor TR is formed by patterning the fourth insulating layer 210.

[0273] The pixel electrode 220 is formed by depositing a conductive material such as metal or transparent conductive oxide on the fourth insulating layer 210 having the contact hole and patterning the deposited conductive material.

[0274] The fifth insulating layer 230 is formed on the base substrate 110 on which the pixel electrode 220 is formed, and an opening configured to expose the pixel electrode 220 is formed by patterning the fifth insulating layer 230. The opening may define a light emitting region of the pixel P.

[0275] refer to Fig.28 The second groove pattern GP2 configured to expose the bottom MB, the first side MS1, and the second side MS2 of the undercut electrode M31 is formed by patterning the fourth insulating layer 210 formed in the groove area GA of the non-display area NDA.

[0276] refer to Fig.25 and Fig.28 Through the dry etching process, the entire undercut electrode M31 may be removed through the bottom MB, the first side MS1, and the second side MS2 of the undercut electrode M31 exposed by the second groove pattern GP2 in the groove area GA.

[0277] Therefore, in the groove area GA, a groove GR corresponding to the second groove pattern GP2 can be formed, a first undercut UC1 can be formed between the third insulating layer 180 and the fourth insulating layer 210 in the first side wall of the groove GR through the first end portion ME1 of the undercut electrode M31, and a second undercut UC2 can be formed between the third insulating layer 180 and the fourth insulating layer 210 in the second side wall of the groove GR through the second end portion ME2 of the undercut electrode M31.

[0278] An undercut groove UG7 may be formed in the groove area GA.

[0279] The undercut groove UG7 may include a groove GR having a depth corresponding to the thickness of the buffer layer 120, the first insulating layer 140, the second insulating layer 160, the third insulating layer 180 and the fourth insulating layer 210, a first undercut UC1 formed between the third insulating layer 180 and the fourth insulating layer 210 in the first side wall of the groove GR, and a second undercut UC2 formed between the third insulating layer 180 and the fourth insulating layer 210 in the second side wall of the groove GR.

[0280] After the undercut groove UG7 is formed, the organic light emitting layer 240 and the common electrode layer 250 may be sequentially formed over the entire area of ​​the base substrate 110 .

[0281] The organic light emitting layer 240 and the common electrode layer 250 may be formed along the sidewall of the groove GR in the groove area GA, may be effectively disconnected by the undercuts UC1 and UC2, and may be formed on the bottom surface of the groove GR. Therefore, potential pollutants such as moisture and oxygen from the external air may be prevented from being introduced into the display area DA along the organic light emitting layer 240 formed of an organic material.

[0282] Fig.29 is a cross-sectional view for describing a display device according to example embodiments.

[0283] refer to Fig.29 According to one embodiment, a display device may include a transistor TR, a storage capacitor CST, a pixel electrode 220, an organic light emitting layer 240, and a common electrode layer 250 disposed in a display area DA, and may include an undercut groove UG8 disposed in a groove area GA of a non-display area NDA.

[0284] The undercut groove UG8 includes a groove GR formed by removing the buffer layer 120, the first insulating layer 140, the second insulating layer 160, the third insulating layer 180, the fourth insulating layer 190, and the fifth insulating layer 210. In addition, the undercut groove UG8 includes a first undercut UC1 formed between the first insulating layer 140 and the fourth insulating layer 190 in the first side wall of the groove GR, and a second undercut UC2 formed between the first insulating layer 140 and the fourth insulating layer 190 in the second side wall of the groove GR. The fourth insulating layer 190 may be an inorganic insulating layer including silicon nitride, silicon oxide, or silicon oxynitride, or may be an organic insulating layer including acrylic resin, epoxy resin, polyimide resin, or polyester resin. The second insulating layer 160 may include a first lower undercut and a second lower undercut. The fourth insulating layer 190 may include a first upper undercut and a second upper undercut. The first undercut UC1 may include a first lower undercut and a first upper undercut. The second undercut UC2 may include a second lower undercut and a second upper undercut.

[0285] According to the present embodiment, a thickness ut of each of the first undercut UC1 and the second undercut UC2 of the undercut groove UG8 may be thicker than a thickness of each of the undercuts included in the undercut groove of the previous embodiment.

[0286] Figure 30 to Figure 32 It is used to describe manufacturing Fig.29 A cross-sectional view of a method of displaying a device.

[0287] refer to Fig.30 , the buffer layer 120 may be formed on the base substrate 110 . The semiconductor layer AC is formed on the buffer layer 120 .

[0288] The first insulating layer 140 is formed on the base substrate 110 on which the semiconductor layer AC is formed.

[0289] A first conductive layer is formed on the first insulating layer 140, and first conductive patterns GE, E1, M11, and M12 are formed by patterning the first conductive layer. The first conductive patterns GE, E1, M11, and M12 may include a gate electrode GE of the transistor TR and a first capacitor electrode E1 of the storage capacitor CST formed in the display area DA, and may include a first undercut electrode M11 formed in the recess area GA which is the non-display area NDA and a second undercut electrode M12 spaced apart from the first undercut electrode M11.

[0290] The second insulating layer 160 is formed on the base substrate 110 on which the first conductive patterns GE, E1, M11, and M12 are formed. The second conductive layer is formed on the second insulating layer 160, and the second conductive pattern E2 is formed by patterning the second conductive layer. The second conductive pattern E2 may include a second capacitor electrode E2 of the storage capacitor CST formed in the display area DA.

[0291] The third insulating layer 180 is formed on the base substrate 110 on which the second conductive pattern E2 is formed. A contact hole is formed in the display area DA by etching the third insulating layer 180, and a first groove pattern GP1 is formed in the groove area GA which is the non-display area NDA by simultaneously etching the buffer layer 120 and the first insulating layer 140, the second insulating layer 160, and the third insulating layer 180.

[0292] The contact hole in the display area DA may be formed by removing the third insulating layer 180 to expose the second capacitor electrode E2. The first groove pattern GP1 in the groove area GA may be formed by removing the buffer layer 120, the first insulating layer 140, the second insulating layer 160, and the third insulating layer 180 with respect to the first undercut electrode M11 and the second undercut electrode M12 to expose the base substrate 110, the top surface and the cross section of the first undercut electrode M11, and the top surface and the cross section of the second undercut electrode M12.

[0293] refer to Fig.31 , a third conductive layer is formed on the base substrate 110 having the contact hole and the first groove pattern GP1 formed thereon, and third conductive patterns CE and M41 are formed by patterning the third conductive layer.

[0294] The third conductive patterns CE and M41 may include the connection electrode CE formed in the display area DA and the third undercut electrode M41 in the groove area GA.

[0295] The connection electrode CE may be connected to the second capacitor electrode E2 through a contact hole. The third undercut electrode M41 is disposed in a spacing region between the first undercut electrode M11 and the second undercut electrode M12. The first end ME1 of the third undercut electrode M41 may overlap with the first undercut electrode M11 while directly contacting the first undercut electrode M11 from the top of the first undercut electrode M11, and the second end ME2 of the third undercut electrode M41 may overlap with the second undercut electrode M12 while directly contacting the second undercut electrode M12 from the top of the second undercut electrode M12.

[0296] The third undercut electrode M41 may contact the top surface and the cross section of the first undercut electrode M11 exposed by the first groove pattern GP1 , the bottom substrate 110 , and the top surface and the cross section of the second undercut electrode M12 .

[0297] The fourth insulating layer 190 is formed on the base substrate 110 on which the third conductive patterns CE and M41 are formed. A plurality of contact holes are formed by simultaneously etching the first insulating layer 140, the second insulating layer 160, the third insulating layer 180, and the fourth insulating layer 190 in the display area DA. The contact holes in the display area DA may be formed by removing the first insulating layer 140, the second insulating layer 160, the third insulating layer 180, and the fourth insulating layer 190 to expose the semiconductor layer AC and the connection electrode CE.

[0298] The fourth conductive layer is formed on the base substrate 110 having the contact holes formed thereon, and fourth conductive patterns SE and DE are formed by patterning the fourth conductive layer.

[0299] The fourth conductive patterns SE and DE may include a source electrode SE and a drain electrode DE of the transistor TR formed in the display area DA.

[0300] The source electrode SE may be connected to the source region of the semiconductor layer AC through the contact hole, and the drain electrode DE may be connected to the drain region of the semiconductor layer AC through the contact hole. In addition, the transistor TR may be connected to the second capacitor electrode E2 and the connection electrode CE of the storage capacitor CST through the contact hole.

[0301] The fifth insulating layer 210 is formed on the base substrate 110 on which the fourth conductive patterns SE and DE are formed. A contact hole configured to expose the drain electrode DE of the transistor TR is formed by patterning the fifth insulating layer 210.

[0302] The pixel electrode 220 is formed by depositing a conductive material such as metal or transparent conductive oxide on the fifth insulating layer 210 having the contact hole and patterning the deposited conductive material.

[0303] The sixth insulating layer 230 is formed on the base substrate 110 on which the pixel electrode 220 is formed, and an opening configured to expose the pixel electrode 220 is formed by patterning the sixth insulating layer 230. The opening may define a light emitting region of the pixel P.

[0304] refer to Fig.29 and Fig.32 The second groove pattern GP2 configured to expose the bottom MB, the first side MS1, and the second side MS2 of the third undercut electrode M41 is formed by patterning the fourth insulating layer 190 and the fifth insulating layer 210 formed in the groove area GA of the non-display area NDA.

[0305] Through the dry etching process, the entire third undercut electrode M41 may be removed through the bottom MB, the first side MS1, and the second side MS2 of the third undercut electrode M41 exposed by the second groove pattern GP2 in the groove area GA.

[0306] Therefore, in the groove area GA, a groove GR corresponding to the second groove pattern GP2 can be formed, a first undercut UC1 having a thickness ut corresponding to the thickness of the first end portion ME1 of the first undercut electrode M11 and the third undercut electrode M41 can be formed in the first side wall of the groove GR by the first undercut electrode M11 and the first end portion ME1 of the third undercut electrode M41 overlapping with the first undercut electrode M11, and a second undercut UC2 having a thickness ut corresponding to the thickness of the second end portion ME2 of the second undercut electrode M12 and the third undercut electrode M41 can be formed in the second side wall of the groove GR by the second undercut electrode M12 and the second end portion ME2 of the third undercut electrode M41 overlapping with the second undercut electrode M12.

[0307] An undercut groove UG8 may be formed in the groove area GA.

[0308] The undercut groove UG8 may include a groove GR having a depth corresponding to the thickness of the buffer layer 120, the first insulating layer 140, the second insulating layer 160, the third insulating layer 180, the fourth insulating layer 190 and the fifth insulating layer 210, a first undercut UC1 formed between the first insulating layer 140 and the fourth insulating layer 190 in the first side wall of the groove GR, and a second undercut UC2 formed between the first insulating layer 140 and the fourth insulating layer 190 in the second side wall of the groove GR.

[0309] After the undercut groove UG8 is formed, the organic light emitting layer 240 and the common electrode layer 250 may be sequentially formed over the entire area of ​​the base substrate 110 .

[0310] The organic light emitting layer 240 and the common electrode layer 250 may be formed along the sidewall of the groove GR in the groove area GA, may be effectively disconnected by the undercuts UC1 and UC2, and may be formed on the bottom surface of the groove GR. Therefore, potential pollutants such as moisture and oxygen from the external air may be prevented from being introduced into the display area DA along the organic light emitting layer 240 formed of an organic material.

[0311] According to an embodiment, the undercut of the insulating layer can effectively separate the organic material portion (e.g., portion of the organic light-emitting material layer); the undercut groove having the undercut can effectively prevent potential contaminants such as moisture (e.g., contained in the external air) from being transmitted through the organic material layer into the display area.

[0312] In the undercut groove pattern, the groove can be formed by etching the undercut electrode and the insulating layer overlapping the undercut electrode, and the undercut can be formed in the sidewall of the groove by etching the undercut electrode exposed by the groove. Therefore, the depth of the groove can be optimized by setting the thickness of the insulating layer, and the size of the undercut can be optimized by setting the thickness of the undercut electrode.

[0313] One or more embodiments may be applied to display devices. For example, one or more embodiments may be applied to display devices included in computers, laptop computers, cellular phones, smart phones, smart tablets, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, etc.

[0314] The foregoing is illustrative of example embodiments and is not intended to be limiting. Although some example embodiments have been described, many modifications are possible. All such modifications are within the scope defined by the claims.

Claims

1. A display device, comprising: substrate; a transistor including a gate electrode located on the substrate; an organic light emitting layer overlapping the substrate and comprising an opening; as well as A perforated insulating layer located between the gate electrode and the organic light-emitting layer, wherein the perforated insulating layer includes a first through hole, a first groove and a first undercut, wherein a position of the opening overlaps with a position of the first groove, wherein in a plan view of the display device, the first groove surrounds the first through hole, and wherein in the plan view of the display device, the first undercut surrounds the first groove.

2. The display device according to claim 1, further comprising: a buffer layer formed on the substrate; as well as an intermediate insulating layer, located between the buffer layer and the porous insulating layer, The gate electrode is located between the intermediate insulating layer and the porous insulating layer.

3. The display device of claim 1 , wherein the perforated insulating layer further comprises a second undercut, wherein the second undercut surrounds the first through hole in the plan view of the display device, and wherein the first groove surrounds the second undercut in the plan view of the display device.

4. The display device according to claim 1, further comprising: An intermediate insulating layer is located between the substrate and the porous insulating layer, wherein the gate electrode is located between the intermediate insulating layer and the porous insulating layer, and wherein a wall of the first undercut directly contacts the intermediate insulating layer.

5. The display device according to claim 1, wherein the transistor further comprises a source electrode, and The display device further comprises: An intermediate insulating layer is located between the substrate and the perforated insulating layer, wherein the source electrode is located between the perforated insulating layer and the organic light emitting layer, and wherein a wall of the first undercut directly contacts the intermediate insulating layer.

6. The display device according to claim 1, further comprising: The overlapping insulating layer overlaps the perforated insulating layer, is located between the perforated insulating layer and the organic light emitting layer, and comprises a second groove, wherein the second groove is directly connected to the first groove.

7. The display device according to claim 6, wherein the transistor further comprises a source electrode, and The source electrode is located between the overlapping insulating layer and the organic light-emitting layer.

8. The display device according to claim 1, further comprising: an overlapping insulating layer, the overlapping insulating layer overlapping the porous insulating layer and being located between the porous insulating layer and the organic light emitting layer, wherein the perforated insulating layer further comprises a second undercut, wherein in the plan view of the display device, the second undercut surrounds the first through hole, wherein in the plan view of the display device, the first groove surrounds the second undercut, wherein the overlapping insulating layer comprises a second groove, a third undercut and a fourth undercut, wherein the position of the second groove overlaps with the position of the first groove, wherein the fourth undercut is closer to the first through hole than the second groove, and The second groove is closer to the first through hole than the third undercut.

9. The display device according to claim 8, wherein the transistor further comprises a source electrode, and The source electrode is located between the overlapping insulating layer and the organic light-emitting layer.

10. The display device according to claim 1, further comprising: a storage capacitor comprising a first capacitor electrode, wherein the transistor further comprises a source electrode, and The porous insulating layer is located between at least one of the source electrode and the first capacitor electrode and the organic light emitting layer.

11. The display device according to claim 1, further comprising: An overlapping insulating layer is located between the perforated insulating layer and the organic light emitting layer, overlaps the perforated insulating layer, is partially located inside the first groove, and includes an additional undercut, wherein the additional undercut is at least partially located inside the first groove.

12. A method for manufacturing a display device, the method comprising: forming a transistor, wherein the transistor includes a gate electrode located on a substrate; forming a perforated insulating layer, wherein the perforated insulating layer overlaps the substrate and comprises a first through hole, a first groove, and a first undercut, wherein the first groove surrounds the first through hole in a plan view of the display device, and wherein the first undercut surrounds the first groove in the plan view of the display device; as well as An organic light emitting layer including an opening is formed, wherein the holey insulating layer is located between the gate electrode and the organic light emitting layer, and wherein a position of the opening overlaps a position of the first groove.

13. The method according to claim 12, further comprising: forming a storage capacitor, wherein the storage capacitor comprises a first capacitor electrode and a second capacitor electrode, and wherein the first capacitor electrode is located between the substrate and the second capacitor electrode; forming a first conductive member, wherein at least one of a material of the first capacitor electrode and a material of the gate electrode is the same as a material of the first conductive member; forming the first undercut using the first conductive member; and The first conductive member is removed.

14. The method according to claim 12, further comprising: forming a buffer layer, wherein the buffer layer is located between the substrate and the porous insulating layer and comprises a buffer layer groove, wherein a position of the buffer layer groove overlaps a position of the first groove; An organic component is formed inside the groove of the buffer layer, wherein a material of the organic component is the same as a material of the organic light emitting layer.

15. The method according to claim 12, further comprising: forming a storage capacitor, wherein the storage capacitor comprises a first capacitor electrode and a second capacitor electrode, and wherein the first capacitor electrode is located between the substrate and the second capacitor electrode; forming a first conductive member, wherein a material of the first conductive member is the same as a material of the second capacitor electrode; forming the first undercut using the first conductive member; and The first conductive member is removed.

16. The method according to claim 12, further comprising: forming a storage capacitor, wherein the storage capacitor comprises a first capacitor electrode and a second capacitor electrode, and wherein the first capacitor electrode is located between the substrate and the second capacitor electrode; forming a first conductive member, wherein at least one of a material of the first capacitor electrode and a material of the gate electrode is the same as a material of the first conductive member; forming both the first undercut and the second undercut using the first conductive member, wherein the apertured insulating layer further includes the second undercut, and wherein the first undercut is closer to the first capacitor electrode than the second undercut; and The first conductive member is removed.

17. The method according to claim 16, further comprising: An organic member is formed inside the first groove, wherein a material of the organic member is the same as a material of the organic light emitting layer.

18. The method according to claim 16, further comprising: forming an overlapping insulating layer, wherein the overlapping insulating layer overlaps the holey insulating layer, is located between the holey insulating layer and the organic light emitting layer, and includes a third undercut; forming a second conductive member, wherein a material of the second conductive member is the same as a material of the second capacitor electrode; forming the third undercut using the second conductive member; as well as The second conductive member is removed.

19. The method according to claim 12, further comprising: forming an included insulating member inside the first groove, wherein the material of the included insulating member is the same as the material of the perforated insulating layer, wherein the included insulating member includes an included undercut, and wherein the included undercut is opposite to the first undercut; forming a storage capacitor, wherein the storage capacitor comprises a first capacitor electrode and a second capacitor electrode, wherein the second capacitor electrode is spaced apart from the first capacitor electrode; forming a first conductive member, wherein at least one of a material of the first capacitor electrode and a material of the gate electrode is the same as a material of the first conductive member; forming both the first undercut and the included undercut using the first conductive member; removing the first conductive member; forming a second conductive member, wherein the material of the second conductive member is the same as the material of the second capacitor electrode, wherein a first portion of the second conductive member is located inside the recess of the included insulating member, and wherein a second portion of the second conductive member is located outside the recess of the included insulating member and overlaps the first conductive member; as well as The first portion of the second conductive member and the second portion of the second conductive member are removed.

20. The method according to claim 12, wherein the transistor further comprises a source electrode, and Wherein the method further comprises: forming a first conductive member, wherein the material of the first conductive member is the same as that of the source electrode; forming the first undercut using the first conductive member; as well as The first conductive member is removed.

21. The method of claim 12, wherein the transistor further comprises a source electrode, and Wherein the method further comprises: forming a storage capacitor, wherein the storage capacitor comprises a first capacitor electrode and a second capacitor electrode; forming a connection electrode, wherein the source electrode is electrically connected to the second capacitor electrode through the connection electrode; forming an overlapping insulating layer, wherein the overlapping insulating layer overlaps the perforated insulating layer, is located between the perforated insulating layer and the organic light emitting layer, and comprises an additional undercut and an additional groove, wherein a position of the additional groove overlaps a position of the first groove; forming a first conductive member, wherein at least one of a material of the first capacitor electrode and a material of the gate electrode is the same as a material of the first conductive member; forming a second conductive member, wherein a material of the second conductive member is the same as a material of the connection electrode, and wherein the second conductive member partially overlaps with the first conductive member; forming the first undercut using the first conductive member; removing the first conductive member; forming the additional undercut using the second conductive member; as well as The second conductive member is removed.

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