Capacitance detection circuit, integrated circuit and capacitance detection method

Abstract

The embodiments of the present application provide a capacitance detection circuit, an integrated circuit, and a capacitance detection method. The capacitance detection circuit includes an integration circuit, an excitation source, a first switch capacitor circuit, a second switch capacitor circuit, and a switching control circuit; the excitation source is used to input two different excitation signals to the first switch capacitor circuit and the second switch capacitor circuit respectively; the first switch capacitor circuit and the second switch capacitor circuit are symmetrical in structure and opposite in integration direction; the switching control circuit is used to switch the integration direction of the first switch capacitor circuit and the second switch capacitor circuit, and control the excitation source to exchange the excitation signal output to the first switch capacitor circuit with the excitation signal output to the second switch capacitor circuit. The capacitance detection circuit provided in the embodiments of the present application can eliminate the dynamic nonlinear error caused by the asymmetry of the branch in the integration process, and improve the detection accuracy.

Description

Technical Field

[0001] The present application relates to the field of touch detection technology, and in particular to a capacitance detection circuit, an integrated circuit, and a capacitance detection method. Background Art

[0002] After years of technological evolution and mass production testing, touch button technology is becoming more and more mature. Due to its advantages such as ease of use, fashion and low cost, more and more electronic products are turning from traditional mechanical buttons to touch buttons. Touch buttons use a capacitive detection chip to detect the change in capacitance on the button to determine the occurrence of a touch event. The change in button capacitance will cause the capacitance change on the detection pin of the capacitive detection chip, and then detect the touch event.

[0003] At present, the implementation of capacitance detection technology generally adopts the charge sharing principle based on switched capacitors. In traditional capacitance detection technology, the two branches are adapted to each other to eliminate the static error in the integration process. However, due to the asymmetry of the two branches in the integration process, when the capacitance on the detection pin changes, dynamic nonlinear errors will be reintroduced, resulting in a decrease in detection accuracy. Summary of the invention

[0004] In view of the above problems, the embodiments of the present application provide a capacitance detection circuit, an integrated circuit and a capacitance detection method to solve the above technical problems.

[0005] The embodiment of the present application is implemented by adopting the following technical solutions:

[0006] A capacitance detection circuit comprises an integration circuit, an excitation source, a first switch capacitor circuit, a second switch capacitor circuit and a switching control circuit; the excitation source is used to output two excitation signals different from each other; one end of the first switch capacitor circuit is connected to the excitation source to receive one of the excitation signals, and the other end is connected to the integration circuit; one end of the second switch capacitor circuit is connected to the excitation source to receive the other excitation signal, and the other end is connected to the integration circuit, the structure of the second switch capacitor circuit is symmetrical to that of the first switch capacitor circuit, and the integration direction is opposite to that of the first switch capacitor circuit; the switching control circuit is connected to the excitation source, the first switch capacitor circuit and the second switch capacitor circuit, the switching control circuit is used to switch the integration direction of the first switch capacitor circuit and the second switch capacitor circuit, and control the excitation source to exchange the excitation signal output to the first switch capacitor circuit with the excitation signal output to the second switch capacitor circuit.

[0007] In some embodiments, the first switched capacitor circuit includes a first capacitor, and the second switched capacitor circuit includes a second capacitor; the first capacitor and the second capacitor each include a first number of unit capacitors; wherein the unit capacitors in the first capacitor and the second capacitor are randomly selected from a plurality of preset unit capacitors.

[0008] In some embodiments, the capacitance detection circuit further includes a dynamic element matching circuit, which is connected to each unit capacitor and is used to randomly select a unit capacitor in the first capacitor and the second capacitor from a plurality of preset unit capacitors.

[0009] In some implementations, the integration circuit includes an integration capacitor, and the integration capacitor includes a second number of unit capacitors; wherein the second number of unit capacitors are randomly selected from a plurality of preset unit capacitors.

[0010] In some embodiments, the capacitance detection circuit further includes a dynamic element matching circuit, which is connected to each unit capacitor and is used to randomly select a unit capacitor among the first capacitor, the second capacitor and the integral capacitor from a plurality of preset unit capacitors.

[0011] In some embodiments, the first switch capacitor circuit includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch and a first capacitor; one end of the first switch is connected to the excitation source, and the other end is connected to the integration circuit through the fourth switch, the first capacitor and the seventh switch connected in sequence; one end of the second switch is connected between the first switch and the fourth switch, and the other end is grounded; one end of the third switch is connected between the first switch and the fourth switch, and the other end is connected to the second switch capacitor circuit; one end of the fifth switch is connected between the fourth switch and the first capacitor, and the other end is grounded; one end of the sixth switch is connected between the first capacitor and the seventh switch, and the other end is grounded; the second switch capacitor circuit includes an eighth switch, a ninth switch, a tenth switch, an eleventh switch, a twelfth switch, a thirteenth switch, a fourteenth switch and a second capacitor; one end of the eighth switch is connected to the excitation source, and the other end is connected to the integration circuit by sequentially connecting the eleventh switch, the second capacitor and the fourteenth switch; one end of the ninth switch is connected between the eighth switch and the eleventh switch, and the other end is grounded; one end of the tenth switch is connected between the eighth switch and the eleventh switch, and the other end is connected to the third switch; one end of the twelfth switch is connected between the eleventh switch and the first capacitor, and the other end is grounded; one end of the thirteenth switch is connected between the first capacitor and the fourteenth switch, and the other end is grounded; a connection node between the third switch and the tenth switch is used to connect a detection pin.

[0012] In some embodiments, the switching control circuit includes a pulse PWM generator and a clock controller, the PWM generator is used to generate a PWM signal with an adjustable duty cycle; the clock controller is used to control the on and off of the second switch, the third switch, the fourth switch, the fifth switch, the ninth switch, the tenth switch, the eleventh switch and the twelfth switch according to the duty cycle of the PWM signal to switch the integration direction of the first switch capacitor circuit and the second switch capacitor circuit.

[0013] In some embodiments, the PWM generator is also connected to an excitation source, and the PWM generator is used to output a PWM signal to the excitation source to control the excitation source to exchange the excitation signal output to the first switched capacitor circuit with the excitation signal output to the second switched capacitor circuit.

[0014] An integrated circuit comprises any one of the above capacitance detection circuits.

[0015] A capacitance detection method is applied to the above-mentioned capacitance detection circuit, the method comprising inputting two different excitation signals into a first switch capacitor circuit and a second switch capacitor circuit respectively; and switching the integration direction of the first switch capacitor and the second switch capacitor, and controlling the excitation source to exchange the excitation signal output to the first switch capacitor circuit with the excitation signal output to the second switch capacitor circuit.

[0016] The capacitance detection circuit, integrated circuit and capacitance detection method provided in the embodiments of the present application are configured by setting an integration circuit, an excitation source for outputting two excitation signals different from each other, a first switch capacitor circuit and a second switch capacitor circuit with mutually symmetrical structures and opposite integration directions, and then switching the integration directions of the first switch capacitor circuit and the second switch capacitor circuit through a switching control circuit, and controlling the excitation source to exchange the excitation signal output to the first switch capacitor circuit with the excitation signal output to the second switch capacitor circuit, thereby eliminating the dynamic nonlinear error caused by the asymmetry of the branch in the integration process and improving the detection accuracy.

[0017] These and other aspects of the present application will become more clearly understood in the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 A schematic structural diagram of a capacitance sensing system provided in an embodiment of the present application is shown.

[0020] Figure 2 A module block diagram of a capacitance detection circuit provided in an embodiment of the present application is shown.

[0021] Figure 3 A circuit structure schematic diagram of a capacitance detection circuit provided in an embodiment of the present application is shown.

[0022] Figure 4A working schematic diagram of a capacitance detection circuit provided in an embodiment of the present application is shown.

[0023] Figure 5 Another working schematic diagram of the capacitance detection circuit provided in an embodiment of the present application is shown.

[0024] Figure 6 A circuit structure schematic diagram of another capacitance detection circuit provided in an embodiment of the present application is shown.

[0025] Figure 7 A working schematic diagram of a dynamic element matching circuit provided in an embodiment of the present application is shown.

[0026] Figure 8 A circuit structure schematic diagram of another capacitance detection circuit provided in an embodiment of the present application is shown.

[0027] Fig. 9 Another working schematic diagram of the dynamic element matching circuit provided in an embodiment of the present application is shown.

[0028] Fig.10 A schematic structural diagram of an integrated circuit provided in an embodiment of the present application is shown.

[0029] Fig.11 A flow chart of a capacitance detection method provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0030] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0031] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application.

[0032] like Figure 1 As shown, Figure 1 like Figure 1 As shown, Figure 1The capacitance sensing system 10 provided by the embodiment of the present application is schematically shown. The system 10 includes a capacitance voltage conversion (Capacitor-to-Voltage Converter, CVC) unit 11 and an analog signal processing (Analog Signal Process, ASP) unit 12 connected in sequence. Among them, the CVC unit 11 includes a detection pin TK, and the detection pin TK is connected to an external sensor 20, and the sensor 20 can be a capacitance sensor. When a touch event occurs, the signal output by the sensor 20 will cause the capacitance change on the detection pin TK. The CVC unit 11 converts the capacitance change on the detection pin TK into a voltage signal and outputs a signal Vout, and the ASP unit 12 quantizes the output signal Vout, and the ASP unit 12 is connected to an external judgment circuit 30, so that the external judgment circuit 30 judges the occurrence of a touch event based on this. Specifically, when no touch event occurs, the ASP unit 12 outputs a reference signal, and the judgment circuit 30 records the reference signal; the judgment circuit 30 simultaneously detects the current signal output by the ASP unit 12, and judges whether a touch event occurs at this time according to the voltage difference between the current signal and the reference signal. For example, when the voltage difference between the current signal and the reference signal is higher than a preset threshold, it can be determined that a touch event occurs at this time. In the embodiment of the present application, the capacitance change caused by the touch event on the detection pin TK is collectively referred to as the touch capacitance Ctk.

[0033] The ASP unit 12 may be, but is not limited to, an analog-to-digital converter (ADC), a comparator, and a voltage-controlled oscillator (VCO). The ASP unit 12 may be selected based on the needs of the analog back-end circuit and is not limited here.

[0034] like Figure 2 As shown, Figure 2 A capacitance detection circuit 100 provided in an embodiment of the present application is shown. The capacitance detection circuit 100 is applied to the above-mentioned CVC unit 11 and is used to convert a capacitance signal into a voltage signal for output.

[0035] The capacitance detection circuit 100 includes an integration circuit 110 , an excitation source 120 , a first switched capacitor circuit 130 , a second switched capacitor circuit 140 , and a switching control circuit 150 . The excitation source 120 is used to output two excitation signals different from each other; one end of the first switched capacitor circuit 130 is connected to the excitation source 120 to receive one of the excitation signals, and the other end is connected to the integration circuit 110; one end of the second switched capacitor circuit 140 is connected to the excitation source 120 to receive the other excitation signal, and the other end is connected to the integration circuit 110, the structure of the second switched capacitor circuit 140 is symmetrical to the structure of the first switched capacitor circuit 130, and the integration direction is opposite to the integration direction of the first switched capacitor circuit 130; the switching control circuit 150 is connected to the excitation source 120, the first switched capacitor circuit 130 and the second switched capacitor circuit 140, the switching control circuit 150 is used to switch the integration direction of the first switched capacitor circuit 130 and the second switched capacitor circuit 140, and control the excitation source 120 to exchange the excitation signal output to the first switched capacitor circuit 130 with the excitation signal output to the second switched capacitor circuit 140.

[0036] The capacitance detection circuit 100 provided in the embodiment of the present application is adapted by two mutually symmetrical switch capacitor circuits with opposite integration directions to eliminate the static error on the detection pin TK. The first switch capacitor circuit 130 in the present embodiment can be a positive-phase switch capacitor circuit with positive integration or a negative-phase switch capacitor circuit with negative integration; similarly, the second switch capacitor circuit 140 can be a negative-phase switch capacitor circuit with negative integration or a positive-phase switch capacitor circuit with positive integration. When the first switch capacitor circuit 130 is a positive-phase switch capacitor circuit, the second switch capacitor circuit 140 is a negative-phase switch capacitor circuit; when the first switch capacitor circuit 140 is a negative-phase switch capacitor circuit, the second switch capacitor circuit 140 is a positive-phase switch capacitor circuit.

[0037] In this embodiment, on the basis that the first switched capacitor circuit 130 and the second switched capacitor circuit 140 are symmetrical to each other, the switching control circuit 150 switches the integration direction of the first switched capacitor circuit 130 and the second switched capacitor circuit 140, and controls the excitation source 120 to exchange the excitation signal output to the first switched capacitor circuit 130 with the excitation signal output to the second switched capacitor circuit 140, that is, the integration direction of the first switched capacitor circuit 130 and the second switched capacitor circuit 140 and the input excitation signal are exchanged at the same time during the integration process, so that the circuit structures of the positive phase switched capacitor circuit and the negative phase switched capacitor circuit before and after the integration direction is exchanged remain completely unchanged, that is, the structure of the first switched capacitor circuit 130 before the exchange is the same as the structure of the second switched capacitor circuit 140 after the exchange, and the structure of the second switched capacitor circuit 140 before the exchange is the same as the structure of the first switched capacitor circuit 130 after the exchange, thereby completely eliminating the dynamic nonlinear error caused by the asymmetry of the first switched capacitor circuit 130 and the second switched capacitor circuit 140 in the two opposite integrations, thereby improving the detection accuracy.

[0038] like Figure 3 As shown, Figure 3 A structural schematic diagram of the capacitance detection circuit 100 provided in an embodiment of the present application is shown. It should be noted that the capacitance detection circuit 100 may include a single-ended structure and a differential structure. Single-ended detection refers to that one input end of the integration circuit 110 is connected to the above-mentioned first switch capacitor circuit 130 and the second switch capacitor circuit 140, and the other input end of the integration circuit 110 is used for grounding, or connected to a preset reference voltage source. Relatively speaking, differential detection refers to that both input ends of the integration circuit 110 are connected to the above-mentioned first switch capacitor circuit 130 and the second switch capacitor circuit 140. In this embodiment, only the single-ended structure is used as an example, and the detection principle of the differential structure is consistent with the principle of single-ended detection. Of course, the detection method is not limited to single-ended detection and differential detection. No substantial improvements are made on the basis of the embodiments of the present application, which belong to the scope of protection of this application.

[0039] like Figure 3 As shown, the integration circuit 110 includes a comparator A1 and an integration capacitor Cint. The comparator A1 includes two input terminals, wherein the first input terminal is connected to the first switch capacitor circuit 130 and the second switch capacitor circuit 140, and the second input terminal is connected to a preset reference voltage source; the integration capacitor Cint is connected between the first input terminal and the output terminal of the comparator A1.

[0040] The excitation source 120 is connected to the first switched capacitor circuit 130 and the second switched capacitor circuit 140 , and inputs two different excitation signals to the first switched capacitor circuit 130 and the second switched capacitor circuit 140 , respectively.

[0041] The first switch capacitor circuit 130 includes a first switch SA1, a second switch SA2, a third switch SA3, a fourth switch SA4, a fifth switch SA5, a sixth switch SA6, a seventh switch SA7 and a first capacitor C1; one end of the first switch SA1 is connected to the excitation source 120, and the other end is connected to the integration circuit 110 through the fourth switch SA4, the first capacitor C1 and the seventh switch SA7 connected in sequence; one end of the second switch SA2 is connected between the first switch SA1 and the fourth switch SA4, and the other end is grounded; one end of the third switch SA3 is connected between the first switch SA1 and the fourth switch SA4, and the other end is connected to the second switch capacitor circuit 140; one end of the fifth switch SA5 is connected between the fourth switch SA4 and the first capacitor C1, and the other end is grounded; one end of the sixth switch SA6 is connected between the first capacitor C1 and the seventh switch SA7, and the other end is grounded.

[0042] The second switch capacitor circuit 140 includes an eighth switch SA8, a ninth switch SA9, a tenth switch SA10, an eleventh switch SA11, a twelfth switch SA12, a thirteenth switch SA13, a fourteenth switch SA14 and a second capacitor C2; one end of the eighth switch SA8 is connected to the excitation source 120, and the other end is connected to the integration circuit 110 by sequentially connecting the eleventh switch SA11, the second capacitor C2 and the fourteenth switch SA14; one end of the ninth switch SA9 is connected between the eighth switch SA8 and the eleventh switch SA11, and the other end is grounded; one end of the tenth switch SA10 is connected between the eighth switch SA8 and the eleventh switch SA11, and the other end is connected to the third switch SA3; one end of the twelfth switch SA12 is connected between the eleventh switch SA11 and the first capacitor C1, and the other end is grounded; one end of the thirteenth switch SA13 is connected between the first capacitor C1 and the fourteenth switch SA14, and the other end is grounded; the connection node between the third switch SA3 and the tenth switch SA10 is used to connect the detection pin TK.

[0043] The switching control circuit 150 includes a PWM (Pulse Width Modulation) generator 151 and a clock controller 152. The PWM generator 151 is used to generate a PWM signal with an adjustable duty cycle, and the clock controller 152 is used to control the on and off of the second switch SA2, the third switch SA3, the fourth switch SA4, the fifth switch SA5, the ninth switch SA9, the tenth switch SA10, the eleventh switch SA11 and the twelfth switch SA12 according to the duty cycle of the PWM signal to switch the integration direction of the first switch capacitor circuit 130 and the second switch capacitor circuit 140.

[0044] The PWM generator 151 is also connected to the excitation source, and the PWM generator 151 is used to output a PWM signal to the excitation source 120 to control the excitation source 120 to exchange the excitation signal output to the first switch capacitor circuit 130 with the excitation signal output to the second switch capacitor circuit 140. Specifically, through the control of the PWM signal, the connection relationship between the excitation source 120 and the first switch capacitor circuit 130 and the second switch capacitor circuit 140 can be exchanged, thereby switching the excitation signals input to the first switch capacitor circuit 130 and the second switch capacitor circuit 140. For example, the excitation source 120 outputs the first excitation signal through the first output terminal and outputs the second excitation signal through the second output terminal, and the first output terminal and the second output terminal are respectively connected to the first switch capacitor circuit 130 and the second switch capacitor circuit 140 through a selection switch (such as a two-choice switch), and the PWM signal switches the connection path of the selection switch, thereby causing the excitation signals output by the excitation source 120 to the first switch capacitor circuit 130 and the second switch capacitor circuit 140 to be exchanged with each other. In some embodiments, the output signals of the two output terminals of the excitation source 120 may be switched by controlling the PWM signal, thereby switching the excitation signals input to the first switched capacitor circuit 130 and the second switched capacitor circuit 140. For example, the excitation source 120 first outputs the first excitation signal to the first switched capacitor circuit 130 through the first output terminal, and outputs the second excitation signal to the second switched capacitor circuit 140 through the second output terminal, and the PWM signal controls the on and off of the internal switch of the excitation source 120, thereby switching the excitation source 120 to output the second excitation signal to the first switched capacitor circuit 130 through the first output terminal, and outputting the first excitation signal to the second switched capacitor circuit 140 through the second output terminal.

[0045] The principle of the above capacitance detection circuit 100 is as follows:

[0046] The switches (SA1, SA2, SA3, SA4, SA5, SA6, SA7, SA8, SA9, SA10, SA11, SA12, SA13, SA14) are all electronic switches, which may be, but are not limited to, triodes, MOS tubes, and thyristors. The PWM generator 151 outputs a PWM signal to the clock controller 152, so that the clock controller 152 outputs a clock signal to the second switch SA2, the third switch SA3, the fourth switch SA4, the fifth switch SA5, the ninth switch SA9, the tenth switch SA10, the eleventh switch SA11, and the twelfth switch SA12, thereby switching the integration direction of the first switch capacitor circuit 130 and the second switch capacitor circuit 140.

[0047] like Figure 4As shown, when the duty cycle of the PWM signal output by the PWM generator 151 is 1, the clock controller 152 outputs a clock signal to control the second switch SA2 to remain open, the third switch SA3 to remain closed, the tenth switch SA10 to remain open, the eleventh switch SA11 to remain closed, and the twelfth switch SA12 to remain open; the remaining switches (SA1, SA4, SA5, SA6, SA7, SA8, SA9, SA13, SA14) are controlled by a group of non-overlapping clock signals (Ph1, Ph2), which means that the clock signal Ph1 and the clock signal Ph2 cannot be high at the same time. At this time, the first switch capacitor circuit 130 is a positive phase switch capacitor circuit, and the second switch capacitor circuit 140 is a negative phase switch capacitor circuit. At the same time, the excitation source 120 outputs the first excitation signal Vs to the first switch capacitor circuit 130 and outputs the second excitation signal Vb to the second switch capacitor circuit 140.

[0048] like Figure 5 As shown, when the duty cycle of the PWM signal output by the PWM generator 151 is 0, the clock controller 152 outputs a clock signal to control the third switch SA3 to remain open, the fourth switch SA4 to remain closed, the fifth switch SA5 to remain open, the ninth switch SA9 to remain open, and the tenth switch SA10 to remain closed; the remaining switches ((SA1, SA2, SA6, SA7, SA8, SA11, SA12, SA13, SA14) are controlled by non-overlapping clock signals (Ph1, Ph2). At this time, the first switch capacitor circuit 130 is a negative phase switch capacitor circuit, and the second switch capacitor circuit 140 is a positive phase switch capacitor circuit. At the same time, the excitation source 120 outputs the second excitation signal Vb to the first switch capacitor circuit 130 and outputs the first excitation signal Vs to the second switch capacitor circuit 140.

[0049] It should be noted that the clock signal for controlling the first switch capacitor circuit 130 and the second switch capacitor circuit 140 to switch the integration direction is different from the non-overlapping clock signal (Ph1, Ph2). The non-overlapping clock signal (Ph1, Ph2) can be generated by the clock controller 152 or through external input.

[0050] Furthermore, if Figure 3 and Figure 4As shown, when the duty cycle D of the PWM signal is 100%, that is, the output of the PWM generator 151 is 1. The first switch capacitor circuit 130 is a positive phase switch capacitor circuit, and the second switch capacitor circuit 140 is a negative phase switch capacitor circuit. At this time, the excitation source 120 outputs the first excitation signal Vs to the first switch capacitor circuit 130 of positive integration, and the excitation source 120 outputs the second excitation signal Vb to the second switch capacitor circuit 140 of negative integration. The first switch SA1, the fifth switch SA5, the seventh switch SA7, the eighth switch SA8 and the fourteenth switch SA14 are controlled by the clock signal Ph1; the fourth switch SA4, the sixth switch SA6, the ninth switch SA9 and the thirteenth switch SA13 are controlled by the clock signal Ph2.

[0051] Due to the capacitive coupling effect in the circuit, there will be a coupled inherent capacitance Cpin on the detection pin TK. The inherent capacitance Cpin is the main factor causing static error in the integration process. When a touch event occurs, a touch capacitance Ctk is generated on the detection pin TK. At this time, the capacitance on the detection pin TK is actually the sum of the inherent capacitance Cpin and the touch capacitance Ctk.

[0052] During a single integration cycle, when the clock signal Ph1 is at a high level, the first excitation signal Vs charges the inherent capacitor Cpin, the second excitation signal Vb charges the second capacitor C2, and the first capacitor C1 converts all the charges accumulated in the previous cycle to the integration capacitor Cint, and the second capacitor C2 also transfers the charges to the integration capacitor Cint; when the clock signal Ph2 is at a high level, the charge on the inherent capacitor Cin is shared with the first capacitor C1, and part of the charge on the inherent capacitor Cpin is transferred to the first capacitor C1, and the residual charge on the second capacitor C2 is discharged. In the next integration cycle, the first capacitor C1 converts all the charges accumulated in the previous cycle to the integration capacitor Cint, and the second capacitor C2 also transfers the charges to the integration capacitor Cint.

[0053] Therefore, in a single integration period, the voltage accumulated at both ends of the integration capacitor Cint by the first switch capacitor circuit 130 in the positive direction is: Among them, C pin is the capacitance value of the inherent capacitance Cpin, C tk is the capacitance value of the touch capacitor Ctk, C int is the capacitance value of the integral capacitor Cint, C i is the capacitance value of the first capacitor C1, V s is the voltage value of the first excitation signal Vs.

[0054] The voltage accumulated at both ends of the integrating capacitor Cint by the negative integration of the second switched capacitor circuit 140 is:

[0055]

[0056] Among them, V b is the voltage value of the second excitation signal Vb, C i is the capacitance value of the second capacitor C2, and the capacitance value of the second capacitor C2 is equal to the capacitance value of the first capacitor C1.

[0057] Therefore, the total voltage accumulated across the integrating capacitor Cint in a single integration period is:

[0058]

[0059] Assuming that the asymmetric error caused by the asymmetry between the first switched capacitor circuit 130 and the second switched capacitor circuit 140 during the integration process is err%, then in fact, in a single integration cycle, the total voltage accumulated across the integration capacitor Cint is:

[0060]

[0061] Arranged:

[0062]

[0063] like Figure 3 and Figure 5 As shown, when the duty cycle D of the PWM signal is 0, that is, the output of the PWM generator 151 is 0. The first switch capacitor circuit 130 is a negative phase switch capacitor circuit, and the second switch capacitor circuit 140 is a positive phase switch capacitor circuit. At this time, the excitation source 120 outputs the first excitation signal Vs to the second switch capacitor circuit 140 of positive integration, and the excitation source 120 outputs the second excitation signal Vb to the first switch capacitor circuit 130 of negative integration. That is, the integration direction and excitation signal of the first switch capacitor circuit 130 and the second switch capacitor circuit 140 are swapped at the same time, so that the first excitation signal Vs is still input to the positive phase switch capacitor circuit, and the second excitation signal Vb is still input to the negative phase switch capacitor circuit. And at this time, the first switch SA1, the seventh switch SA7, the eighth switch SA8, the twelfth switch SA8 and the fourteenth switch SA14 are controlled by the clock signal Ph1; the second switch SA2, the sixth switch SA6, the tenth switch SA10 and the thirteenth switch SA13 are controlled by the clock signal Ph2.

[0064] Since the circuit structures of the first switched capacitor circuit 130 and the second switched capacitor circuit 140 are symmetrical, after the integration directions of the first switched capacitor circuit 130 and the second switched capacitor circuit 140 are swapped, the circuit structures of the positive-phase switched capacitor circuit for positive integration and the negative-phase switched capacitor circuit for negative integration remain unchanged. Therefore, at this time, in a single integration cycle, the voltage accumulated at both ends of the integration capacitor Cint by the positive integration of the second switched capacitor circuit 140 is:

[0065]

[0066] The voltage accumulated at both ends of the integrating capacitor Cint by the negative integration of the first switched capacitor circuit 130 is:

[0067]

[0068] Therefore, the total voltage accumulated across the integrating capacitor Cint in a single cycle is:

[0069]

[0070] Due to the asymmetry between the first switch capacitor circuit 130 and the second switch capacitor circuit 140 during the integration process, an asymmetric error err% exists. Therefore, in fact, at this time, in a single integration cycle, the total voltage accumulated across the integration capacitor Cint is:

[0071]

[0072] Arranged:

[0073]

[0074] Therefore, when the first switched capacitor circuit 130 and the second switched capacitor circuit 140 work alternately as a positive-phase switched capacitor circuit and a negative-phase switched capacitor circuit, the total voltage accumulated across the integration capacitor Cint in a single integration cycle is:

[0075]

[0076] According to formula (11), it can be seen that the asymmetric error err% caused by the asymmetry between the first switch capacitor circuit 130 and the second switch capacitor circuit 140 during the integration process has been completely eliminated. In this embodiment, the duty cycle of the PWM signal can be set to 50%, so that the first switch capacitor circuit 130 and the second switch capacitor circuit 140 work alternately as a positive phase switch capacitor circuit and an inverted phase switch capacitor circuit. In some embodiments, the duty cycle of the PWM signal can also be set according to actual conditions, so that the first switch capacitor circuit 130 and the second switch capacitor circuit 140 work alternately as a positive phase switch capacitor circuit and an inverted phase switch capacitor circuit.

[0077] Therefore, by setting up the first switch capacitor circuit 130 and the second switch capacitor circuit 140 with symmetrical structures, the circuit structures of the positive phase switch capacitor circuit and the negative phase switch capacitor circuit can remain completely unchanged after the first switch capacitor circuit 130 and the second switch capacitor circuit 140 are swapped in the integration direction, and then by repeatedly switching the branches integrated by the positive integration and the negative integration during the integration process, the first switch capacitor circuit 130 and the second switch capacitor circuit 140 can work alternately as the positive phase switch capacitor circuit and the negative phase switch capacitor circuit, thereby eliminating the dynamic nonlinear error caused by the asymmetry between the first switch capacitor circuit 130 and the second switch capacitor circuit 140 during the integration process, thereby improving the detection accuracy.

[0078] Furthermore, due to process deviations introduced during the capacitor manufacturing process, two capacitors with the same capacitance value are not completely the same. For tiny touch button capacitance detection, the process deviations between capacitors will also affect the detection accuracy.

[0079] In some embodiments, the first capacitor C1 and the second capacitor C2 respectively include a first number of unit capacitors C0; wherein the unit capacitors C0 in the first capacitor C1 and the second capacitor C2 are randomly selected from a plurality of preset unit capacitors C0. That is, the first capacitor C1 and the second capacitor C2 can be composed of the same number of unit capacitors C0, and the same number of unit capacitors C0 constitute the first capacitor C1 and the second capacitor C2 with the same capacitance value. Further, during each integration process, the same number of unit capacitors C0 are randomly selected from a plurality of preset unit capacitors C0 to constitute the first capacitor C1 and the second capacitor C2 with the same capacitance value. By expanding the first capacitor C1 and the second capacitor C2 into a plurality of unit capacitors C0, and randomly selecting a first number of unit capacitors C0 as the first capacitor C1 and the second capacitor C2, the random errors introduced by the capacitors in the manufacturing process can be eliminated during the integration process. Further, as Figure 6 As shown, the capacitance detection circuit 100 further includes a dynamic element matching circuit 160, which is connected to each unit capacitor C0 and is used to randomly select a unit capacitor C0 in the first capacitor C1 and the second capacitor C2 from a plurality of preset unit capacitors C0. Through the action of the dynamic element matching circuit 160, the same number of unit capacitors C0 can be randomly selected from a plurality of unit capacitors C0 as the first capacitor C1 and the second capacitor C2.

[0080] As shown in 7, Figure 7The working schematic diagram of the dynamic element matching circuit 160 is shown. The first capacitor C1 and the second capacitor C2 are broken up into a capacitor array composed of a plurality of unit capacitors C0. For example, assuming that the capacitance value of the first capacitor C1 and the second capacitor C2 is 50pF, the capacitor array can be composed of 100 unit capacitors C0 with a capacitance value of 1pF connected in parallel. The dynamic element matching circuit 160 switches the switch SA in the capacitor array, and then randomly selects the same number of unit capacitors C0 to form the first capacitor C1 and the second capacitor C2. In the process of each integration, the first capacitor C1 and the second capacitor C2 are formed by randomly selecting the same number of different unit capacitors C0, so that the first capacitor C1 and the second capacitor C2 can match each other, eliminating the random error introduced by the capacitor in the manufacturing process, thereby further improving the detection accuracy.

[0081] In some embodiments, the integral capacitor Cint includes a second number of unit capacitors C0; wherein the second number of unit capacitors C0 is randomly obtained from a plurality of preset unit capacitors C0. Figure 8 As shown, the dynamic element matching circuit 160 is further used to randomly select the first capacitor C1, the first capacitor C1 and the unit capacitor C0 in the integral capacitor Cint from the preset plurality of unit capacitors C0.

[0082] like Fig. 9 As shown, Fig. 9 Another working schematic diagram of the dynamic element matching circuit 160 is shown. The first capacitor C1, the second capacitor C2 and the integral capacitor Cint are broken up into a capacitor array composed of a plurality of unit capacitors C0. For example, assuming that the capacitance values ​​of the first capacitor C1 and the second capacitor C2 are 50pF, and the capacitance value of the integral capacitor Cint is 100pF, then the capacitor array can be composed of 150 unit capacitors C0 with a capacitance value of 1pF connected in parallel. The dynamic matching circuit switches the switch SA in the capacitor array, and then randomly selects a first number of unit capacitors C0 to form the first capacitor C1 and the second capacitor C2, and randomly selects a second number of unit capacitors C0 to form the integral capacitor Cint. In the process of each integration, by randomly selecting a first number of different unit capacitors C0 to form the first capacitor C1 and the second capacitor C2, and randomly selecting a second number of different unit capacitors C0 to form the integral capacitor Cint, the random error introduced by the capacitor in the manufacturing process is eliminated, thereby further improving the detection accuracy.

[0083] The capacitance detection circuit provided in the embodiment of the present application is provided with an integration circuit, an excitation source, a first switch capacitor circuit, a second switch capacitor circuit and a switching control circuit. The excitation source is used to output two excitation signals different from each other; one end of the first switch capacitor circuit is connected to the excitation source to receive one of the excitation signals, and the other end is connected to the integration circuit; the second switch capacitor circuit is symmetrical in structure with the first switch capacitor circuit, one end of which is connected to the excitation source to receive the other excitation signal, and the other end is connected to the integration circuit, and the integration direction of the first switch capacitor circuit is opposite to that of the second switch capacitor circuit; the switching control circuit is connected to the excitation source, the first switch capacitor circuit and the second switch capacitor circuit, and the switching control circuit is used to switch the integration direction of the first switch capacitor circuit and the second switch capacitor circuit, and control the excitation source to exchange the excitation signal output to the first switch capacitor circuit with the excitation signal output to the second switch capacitor circuit. The capacitance detection circuit in this embodiment can keep the positive phase switching capacitor circuit and the negative phase switching capacitor circuit unchanged before and after the switching after swapping the integration directions of the first switching capacitor circuit and the second switching capacitor circuit which are symmetrical in structure, and then make the first switching capacitor circuit and the second switching capacitor circuit work alternately as the positive phase switching capacitor circuit and the negative phase switching capacitor circuit by repeatedly switching the branches integrated by the positive integration and the negative integration during the integration process, thereby eliminating the dynamic nonlinear error caused by the asymmetry between the first switching capacitor circuit and the second switching capacitor circuit during the integration process, and improving the detection accuracy.

[0084] like Fig.10 As shown, an embodiment of the present application further provides an integrated circuit 200, and the integrated circuit 200 includes the above-mentioned capacitance detection circuit.

[0085] In this embodiment, the integrated circuit 200 may be, but is not limited to, a capacitance detection chip.

[0086] The integrated circuit provided in the embodiment of the present application is provided with an integration circuit, an excitation source, a first switch capacitor circuit, a second switch capacitor circuit and a switching control circuit. The excitation source is used to output two excitation signals different from each other; one end of the first switch capacitor circuit is connected to the excitation source to receive one of the excitation signals, and the other end is connected to the integration circuit; one end of the second switch capacitor circuit is connected to the excitation source to receive the other excitation signal, and the other end is connected to the integration circuit, the structure of the second switch capacitor circuit is symmetrical with the structure of the first switch capacitor circuit, and the integration direction is opposite to the integration direction of the first switch capacitor circuit; the switching control circuit is connected to the excitation source, the first switch capacitor circuit and the second switch capacitor circuit, and the switching control circuit is used to switch the integration direction of the first switch capacitor circuit and the second switch capacitor circuit, and control the excitation source to exchange the excitation signal output to the first switch capacitor circuit with the excitation signal output to the second switch capacitor circuit. The capacitance detection circuit in this embodiment can keep the positive phase switching capacitor circuit and the negative phase switching capacitor circuit unchanged before and after the switching after swapping the integration directions of the first switching capacitor circuit and the second switching capacitor circuit which are symmetrical in structure, and then make the first switching capacitor circuit and the second switching capacitor circuit work alternately as the positive phase switching capacitor circuit and the negative phase switching capacitor circuit by repeatedly switching the branches integrated by the positive integration and the negative integration during the integration process, thereby eliminating the dynamic nonlinear error caused by the asymmetry between the first switching capacitor circuit and the second switching capacitor circuit during the integration process, and improving the detection accuracy.

[0087] like Fig.11 As shown, the embodiment of the present application further provides a capacitance detection method 300, which is applied to the above capacitance detection circuit. The capacitance detection method may include the following steps S310 to S320.

[0088] Step S310: input two different excitation signals to the first switched capacitor circuit and the second switched capacitor circuit respectively.

[0089] The two different excitation signals include different first excitation signals and second excitation signals. In this embodiment, the first excitation signal can be input into the first switched capacitor circuit, and the second excitation signal can be input into the second switched capacitor circuit; or the second excitation signal can be input into the first switched capacitor circuit, and the first excitation signal can be input into the second switched capacitor circuit.

[0090] Step S320: switching the integration directions of the first switched capacitor circuit and the second switched capacitor circuit, and controlling the excitation source to exchange the excitation signal output to the first switched capacitor circuit with the excitation signal output to the second switched capacitor circuit.

[0091] In this embodiment, two symmetrical switching capacitor circuits with opposite integration directions are adapted to eliminate the static error on the detection pin. In this embodiment, the first switching capacitor circuit can be a positive-phase switching capacitor circuit with positive integration or a negative-phase switching capacitor circuit with negative integration; similarly, the second switching capacitor circuit can be a negative-phase switching capacitor circuit with negative integration or a positive-phase switching capacitor circuit with positive integration. When the first switching capacitor circuit is a positive-phase switching capacitor circuit, the second switching capacitor circuit is a negative-phase switching capacitor circuit; when the second switching capacitor circuit is a negative-phase switching capacitor circuit, the second switching capacitor circuit is a positive-phase switching capacitor circuit.

[0092] In this embodiment, the switching control circuit also controls the excitation source to exchange the excitation signal output to the first switch capacitor circuit with the excitation signal output to the second switch capacitor circuit. Specifically, the connection relationship between the excitation source and the first switch capacitor circuit and the second switch capacitor circuit can be exchanged, thereby switching the excitation signal input to the first switch capacitor circuit and the second switch capacitor circuit. For example, the excitation source outputs the first excitation signal to the first switch capacitor circuit through the first output terminal and outputs the second excitation signal to the second switch capacitor circuit through the second output terminal. The switching control circuit controls the on and off of the switch at the output terminal of the excitation source, thereby causing the excitation source to output the first excitation signal to the second switch capacitor circuit through the first output terminal and output the second excitation signal to the first switch capacitor circuit through the second output terminal. In some embodiments, the output signal of the excitation source can also be switched by the switching control circuit to switch the excitation signal input to the first switch capacitor circuit and the second switch capacitor circuit. For example, the excitation source outputs a first excitation signal to the first switched capacitor circuit through the first output terminal and outputs a second excitation signal to the second switched capacitor circuit through the second output terminal. The switching control circuit controls the on and off of the internal switch of the excitation source, thereby causing the excitation source to output the second excitation signal to the first switched capacitor circuit through the first output terminal and output the first excitation signal to the second switched capacitor circuit through the second output terminal.

[0093] In this embodiment, on the basis that the first switch capacitor circuit and the second switch capacitor circuit are mutually symmetric, the integration direction of the first switch capacitor circuit and the second switch capacitor circuit is switched by the switching control circuit, and the excitation source is controlled to exchange the excitation signal output to the first switch capacitor circuit with the excitation signal output to the second switch capacitor circuit, that is, the integration direction and the input excitation signal of the first switch capacitor circuit and the second switch capacitor circuit are exchanged at the same time during the integration process. In the above process, the circuit structure of the positive phase switch capacitor circuit and the negative phase switch capacitor circuit before and after the integration direction is exchanged remains completely unchanged, that is, the structure of the first switch capacitor circuit before the exchange is the same as the structure of the second switch capacitor circuit after the exchange, and the structure of the second switch capacitor circuit before the exchange is the same as the structure of the first switch capacitor circuit after the exchange; at the same time, the excitation signals of the positive phase switch capacitor circuit after the exchange and the negative phase switch capacitor circuit after the exchange are also the same. By swapping the integration direction and excitation signal of the first switched capacitor circuit and the second switched capacitor circuit, the first switched capacitor circuit performs two integrations, positive and negative, and the second switched capacitor circuit also performs two integrations, positive and negative, thereby completely eliminating the dynamic nonlinear error caused by the asymmetry between the first switched capacitor circuit and the second switched capacitor circuit in the two opposite integrations.

[0094] The capacitance detection method provided in the embodiment of the present application is applied to the above-mentioned capacitance detection circuit or integrated circuit, by respectively inputting two mutually different excitation signals into the first switch capacitor circuit and the second switch capacitor circuit, then switching the integration direction of the first switch capacitor circuit and the second switch capacitor circuit, and controlling the excitation source to exchange the excitation signal output to the first switch capacitor circuit with the excitation signal output to the second switch capacitor circuit, so that after exchanging the integration direction of the first switch capacitor circuit and the second switch capacitor circuit with symmetrical structures, the positive phase switch capacitor circuit and the negative phase switch capacitor circuit can be kept unchanged before and after the exchange, and then by repeatedly switching the branches integrated by the positive integration and the negative integration during the integration process, the first switch capacitor circuit and the second switch capacitor circuit work alternately as the positive phase switch capacitor circuit and the negative phase switch capacitor circuit, thereby eliminating the dynamic nonlinear error caused by the asymmetry of the first switch capacitor circuit and the second switch capacitor circuit during the integration process, and improving the detection accuracy.

[0095] The above are only preferred embodiments of the present application, and are not intended to limit the present application in any form. Although the present application has been disclosed as above with preferred embodiments, it is not intended to limit the present application. Any technical personnel in the field can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present application. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A capacitance detection circuit, characterized in that: include: Integrator circuit; An excitation source, used for outputting two excitation signals different from each other; A first switched capacitor circuit, one end of which is connected to the excitation source to receive one of the excitation signals, and the other end of which is connected to the integration circuit; a second switched capacitor circuit, one end of which is connected to the excitation source to receive another excitation signal, and the other end of which is connected to the integration circuit, wherein the structure of the second switched capacitor circuit is symmetrical to that of the first switched capacitor circuit, and the integration direction of the second switched capacitor circuit is opposite to that of the first switched capacitor circuit; and a switching control circuit connected to the excitation source, the first switched capacitor circuit and the second switched capacitor circuit, the switching control circuit being used to switch the integration direction of the first switched capacitor circuit and the second switched capacitor circuit, and to control the excitation source to exchange the excitation signal output to the first switched capacitor circuit with the excitation signal output to the second switched capacitor circuit; The switching control circuit includes a PWM generator and a clock controller, wherein the PWM generator is used to generate a PWM signal with an adjustable duty cycle; the clock controller is used to control the switching of the integral directions of the first switch capacitor circuit and the second switch capacitor circuit according to the duty cycle of the PWM signal; The PWM generator is also connected to the excitation source, and is used to output the PWM signal to the excitation source to control the excitation source to exchange the excitation signal output to the first switched capacitor circuit with the excitation signal output to the second switched capacitor circuit.

2. The capacitance detection circuit according to claim 1, characterized in that: The first switched capacitor circuit includes a first capacitor, and the second switched capacitor circuit includes a second capacitor; the first capacitor and the second capacitor each include a first number of unit capacitors; The unit capacitances in the first capacitor and the second capacitor are randomly selected from a plurality of preset unit capacitances.

3. The capacitance detection circuit according to claim 2, characterized in that: The capacitance detection circuit further includes a dynamic element matching circuit, which is connected to each of the unit capacitors and is used to randomly select a unit capacitor in the first capacitor and the second capacitor from the preset multiple unit capacitors.

4. The capacitance detection circuit according to claim 2, characterized in that: The integration circuit includes an integration capacitor, and the integration capacitor includes a second number of unit capacitors; wherein the second number of unit capacitors are randomly selected from the preset multiple unit capacitors.

5. The capacitance detection circuit according to claim 4, characterized in that: The capacitance detection circuit further includes a dynamic element matching circuit, which is connected to each of the unit capacitors and is used to randomly select a unit capacitor among the first capacitor, the second capacitor and the integral capacitor from the preset multiple unit capacitors.

6. The capacitance detection circuit according to any one of claims 1 to 5, characterized in that: The first switch capacitor circuit includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch and a first capacitor; one end of the first switch is connected to the excitation source, and the other end is connected to the integration circuit through the fourth switch, the first capacitor and the seventh switch connected in sequence; one end of the second switch is connected between the first switch and the fourth switch, and the other end is grounded; one end of the third switch is connected between the first switch and the fourth switch, and the other end is connected to the second switch capacitor circuit; one end of the fifth switch is connected between the fourth switch and the first capacitor, and the other end is grounded; one end of the sixth switch is connected between the first capacitor and the seventh switch, and the other end is grounded; The second switch capacitor circuit includes an eighth switch, a ninth switch, a tenth switch, an eleventh switch, a twelfth switch, a thirteenth switch, a fourteenth switch and a second capacitor; one end of the eighth switch is connected to the excitation source, and the other end is connected to the integration circuit by sequentially connecting the eleventh switch, the second capacitor and the fourteenth switch; one end of the ninth switch is connected between the eighth switch and the eleventh switch, and the other end is grounded; one end of the tenth switch is connected between the eighth switch and the eleventh switch, and the other end is connected to the third switch; One end of the twelfth switch is connected between the eleventh switch and the second capacitor, and the other end is grounded; one end of the thirteenth switch is connected between the second capacitor and the fourteenth switch, and the other end is grounded; the connection node between the third switch and the tenth switch is used to connect the detection pin.

7. The capacitance detection circuit according to claim 6, characterized in that: The clock controller is used to control the second switch, the third switch, the fourth switch, the fifth switch, the ninth switch, the tenth switch, the eleventh switch and the twelfth switch to turn on and off according to the duty cycle of the PWM signal to switch the integration direction of the first switch capacitor circuit and the second switch capacitor circuit.

8. An integrated circuit, characterized in that: The invention comprises the capacitance detection circuit as described in any one of claims 1 to 7.

9. A capacitance detection method, applied to the capacitance detection circuit according to any one of claims 1 to 7, characterized in that: include: Inputting two different excitation signals to the first switched capacitor circuit and the second switched capacitor circuit respectively; as well as The integration directions of the first switched capacitor circuit and the second switched capacitor circuit are switched, and the excitation source is controlled to exchange the excitation signal output to the first switched capacitor circuit with the excitation signal output to the second switched capacitor circuit.

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