A transmitting detection circuit based on analog-to-digital signal processing of transceiver components

Abstract

The present invention discloses a transmission detection circuit based on analog-to-digital signal processing of a transceiver component, by setting a signal processing device, an FPGA logic control circuit, a DAC module, an ADC module, a radio frequency transmission channel, a radio frequency receiving channel, a transceiver switching switch and a transceiver antenna. On the basis of the radio frequency channel, the present invention is equipped with a signal processing device for detection control, a DAC module for radio frequency transmission, an ADC module for returning a detection mark signal and an FPGA logic control circuit for outputting a detection result judgment. The purpose is to solve the technical problem that the judgment accuracy of the successful transmission of a signal on a transceiver component is not high in the prior art.

Description

Technical Field

[0001] The present invention relates to the field of communications, and in particular to a transmission detection circuit based on analog-to-digital signal processing of a transceiver component. Background Art

[0002] When the transceiver component is performing normal transmission operation, it needs to know whether the signal is actually transmitted. Detection (amplitude demodulation) is the inverse process of amplitude modulation. Through the detection operation, it can be known whether the signal is transmitted through the antenna.

[0003] At present, the circuits for realizing detection are all analog circuits. The detection circuit mainly consists of three parts: high-frequency modulated signal source, nonlinear device, and RC low-pass filter. The output of this detector depends on the amplitude of the signal (there is no definite threshold), and when the transceiver component is transmitting normally, the amplitude of the modulated wave position signal is also uncertain. If it is judged only by the output of this detector, the false alarm rate will be high. Therefore, how to improve the judgment accuracy of the successful transmission of the signal on the transceiver component is a technical problem that needs to be solved urgently.

[0004] The above contents are only used to assist in understanding the technical solution of the present invention and do not constitute an admission that the above contents are prior art. Summary of the invention

[0005] The main purpose of the present invention is to provide a transmission detection circuit based on analog-to-digital signal processing of a transceiver component, aiming to solve the technical problem in the prior art that the judgment accuracy of whether a signal is successfully transmitted on a transceiver component is low.

[0006] To achieve the above-mentioned purpose, the present invention proposes a transmission detection circuit based on analog-to-digital signal processing of a transceiver component, the transmission detection circuit comprising: a signal processing device, an FPGA logic control circuit, a DAC module, an ADC module, a radio frequency transmission channel, a radio frequency receiving channel, a transceiver switching switch and a transceiver antenna; the first signal output end of the signal processing device is connected to the input end of the DAC module, the second signal output end of the signal processing device is connected to the first input end of the FPGA logic control circuit, the output end of the DAC module is connected to the input end of the radio frequency transmission channel, the output end of the radio frequency receiving channel is connected to the input end of the ADC module, the output end of the ADC module is connected to the second input end of the FPGA logic control circuit, the output end of the FPGA logic control circuit is connected to the signal input end of the signal processing device, and the output end of the radio frequency transmission channel and the input end of the radio frequency receiving channel are connected to the transceiver antenna through the transceiver switching switch; wherein:

[0007] Preferably, the signal processing device transmits a transmission signal for transmission by the transceiver antenna to the DAC module through the first signal output terminal, and provides a transmission detection control signal to the FPGA logic control circuit through the second signal output terminal to implement the transmission detection process in the transceiver component;

[0008] Preferably, the RF transmission channel transmits the signal via the transceiver antenna according to the digital transmission signal transmitted by the received DAC module; the RF receiving channel transmits the detection mark signal returned by the receiving channel to the ADC module, and processes the signal via the FPGA logic control circuit;

[0009] Preferably, the FPGA logic control circuit connects the ADC module and the signal processing device to transmit the detection mark digital signal transmitted by the ADC module to the signal processing device, and receives the detection control signal transmitted by the signal processing device to output the transmission detection decision signal.

[0010] Preferably, the RF transmitting channel and the RF receiving channel are respectively connected to the first power supply through a RF power switch circuit; wherein: the RF power switch circuit transmits a detection control signal via the signal processing device for connection control.

[0011] Preferably, the transmitting detection circuit also includes a detection circuit, which is connected to the output end of the transmitting channel, detects the output signal, and returns the detection flag signal to the FPGA logic control circuit via the ADC module through the receiving channel.

[0012] Preferably, the signal processing device includes a detection control terminal and a transmission signal source; the detection control terminal is used to send a detection control instruction to the FPGA logic control circuit and receive a detection flag signal returned by the FPGA logic control circuit, and the transmission signal source is used to send a transmission signal to the DAC module.

[0013] Preferably, the ADC module includes an ADC chip, an ADC power switch circuit and a second power supply; wherein the ADC chip performs analog-to-digital conversion on the transmitted detection mark signal and transmits it to the FPGA logic control circuit; and the ADC power switch circuit controls the connection between the ADC chip and the second power supply.

[0014] Preferably, the DAC module includes a DAC chip, a DAC power switch circuit and a third power supply; wherein the DAC chip receives a clock signal and a chip control signal sent by a signal processing device, converts the transmitted digital transmission signal into an analog transmission signal and transmits it to the RF channel; and the DAC power switch circuit controls the connection between the DAC chip and the third power supply.

[0015] Preferably, the transceiver switching switch receives a transceiver switching control signal sent by a signal processing device to control the access of the RF transmission channel and the RF reception channel to the transceiver antenna.

[0016] Preferably, the detection control signal includes a transceiver switching control signal TR and a transmitting power switch control signal AM; wherein, the RF transmitting channel and the RF receiving channel control signal sending and detection flag signal returning according to the transceiver switching control signal TR and the transmitting power switch control signal AM, and the FPGA logic control circuit receives the detection flag signal sent by the RF receiving channel according to the transceiver switching control signal TR and the transmitting power switch control signal AM.

[0017] In the present invention, by setting a signal processing device, an FPGA logic control circuit, a DAC module, an ADC module, a radio frequency transmission channel, a radio frequency receiving channel, a transceiver switch and a transceiver antenna, the signal processing device is used to transmit a transmission signal for the transceiver antenna to transmit to the DAC module through the first signal output end, and a transmission detection control signal is provided to the FPGA logic control circuit through the second signal output end to realize the transmission detection process in the transceiver component; then, the radio frequency transmission channel transmits the signal through the transceiver antenna according to the digital transmission signal transmitted by the received DAC module; the radio frequency receiving channel transmits the detection mark signal returned through the receiving channel to the ADC module, and processes the signal through the FPGA logic control circuit; finally, the FPGA logic control circuit connects the ADC module and the signal processing device to transmit the detection mark digital signal transmitted by the ADC module to the signal processing device, and receives the detection control signal transmitted by the signal processing device to output the transmission detection judgment signal. Based on the radio frequency channel, the present invention is equipped with a signal processing device for detection control, a DAC module for radio frequency transmission, an ADC module for returning the detection mark signal, and an FPGA logic control circuit for outputting the detection result judgment. The invention aims to solve the technical problem in the prior art that the judgment accuracy of whether a signal is successfully transmitted on a transceiver component is low. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.

[0019] Figure 1 This is a structural schematic diagram of a transmission detection circuit based on analog-to-digital signal processing of a transceiver component proposed by the present invention;

[0020] Figure 2 This is a diagram of the operating principle steps of an embodiment of a transmission detection circuit based on analog-to-digital signal processing of a transceiver component proposed by the present invention.

[0021] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0022] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0023] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0024] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0025] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0026] The present invention proposes an embodiment, referring to Figure 1 , Figure 1 The present invention provides a schematic diagram of the structure of a transmitting detection circuit based on analog-to-digital signal processing of a transceiver component.

[0027] like Figure 1As shown, in this embodiment, a transmitting detection circuit based on analog-to-digital signal processing of a transceiver component, the transmitting detection circuit includes: a signal processing device, an FPGA logic control circuit, a DAC module, an ADC module, a radio frequency transmitting channel, a radio frequency receiving channel, a transceiver switching switch and a transceiver antenna; the first signal output end of the signal processing device is connected to the input end of the DAC module, the second signal output end of the signal processing device is connected to the first input end of the FPGA logic control circuit, the output end of the DAC module is connected to the input end of the radio frequency transmitting channel, the output end of the radio frequency receiving channel is connected to the input end of the ADC module, the output end of the ADC module is connected to the second input end of the FPGA logic control circuit, the output end of the FPGA logic control circuit is connected to the signal input end of the signal processing device, and the output end of the radio frequency transmitting channel and the input end of the radio frequency receiving channel are connected to the transceiver antenna through the transceiver switching switch; wherein:

[0028] It should be noted that the signal processing device transmits a transmission signal for transmission by the transceiver antenna to the DAC module through the first signal output terminal, and provides a transmission detection control signal to the FPGA logic control circuit through the second signal output terminal to implement the transmission detection process in the transceiver component;

[0029] It should be noted that the RF transmission channel transmits the signal through the transceiver antenna according to the digital transmission signal transmitted by the received DAC module; the RF receiving channel transmits the detection mark signal returned by the receiving channel to the ADC module, and processes the signal through the FPGA logic control circuit;

[0030] It should be noted that the FPGA logic control circuit connects the ADC module and the signal processing device to transmit the detection mark digital signal transmitted by the ADC module to the signal processing device, and receives the detection control signal transmitted by the signal processing device to output the transmission detection decision signal.

[0031] Furthermore, the RF transmitting channel and the RF receiving channel are respectively connected to a first power source via a RF power switch circuit; wherein: the RF power switch circuit transmits a detection control signal via the signal processing device for connection control.

[0032] Furthermore, the transmitting detection circuit also includes a detection circuit, which is connected to the output end of the transmitting channel, detects the output signal, and returns the detection mark signal to the FPGA logic control circuit via the ADC module through the receiving channel.

[0033] In another embodiment, the signal processing device includes a detection control terminal and a transmission signal source; the detection control terminal is used to send a detection control instruction to the FPGA logic control circuit and receive a detection flag signal returned by the FPGA logic control circuit, and the transmission signal source is used to send a transmission signal to the DAC module.

[0034] In this embodiment, the ADC module includes an ADC chip, an ADC power switch circuit and a second power supply; wherein the ADC chip performs analog-to-digital conversion on the transmitted detection flag signal and transmits it to the FPGA logic control circuit; and the ADC power switch circuit controls the connection between the ADC chip and the second power supply.

[0035] In this embodiment, the DAC module includes a DAC chip, a DAC power switch circuit and a third power supply; wherein the DAC chip receives a clock signal and a chip control signal sent by a signal processing device, converts the transmitted digital transmission signal into an analog transmission signal and transmits it to the RF channel; the DAC power switch circuit controls the connection between the DAC chip and the third power supply.

[0036] In this embodiment, the transceiver switch receives a transceiver switch control signal sent by a signal processing device to control the access of the RF transmission channel and the RF reception channel to the transceiver antenna.

[0037] Furthermore, the detection control signal includes a transceiver switching control signal TR and a transmitting power switch control signal AM; wherein, the RF transmitting channel and the RF receiving channel control signal sending and detection flag signal returning according to the transceiver switching control signal TR and the transmitting power switch control signal AM, and the FPGA logic control circuit receives the detection flag signal sent by the RF receiving channel according to the transceiver switching control signal TR and the transmitting power switch control signal AM.

[0038] It is important to understand that Figure 2 As shown, the transmission detection method of this embodiment mainly includes the following steps:

[0039] S1. Assume that the transceiver function of the transceiver assembly is controlled by control signals TR and AM:

[0040] TR is the control signal for switching between transmit and receive. When TR=1, it means switching to the transmit state; when TR=0, it means switching to the receive state.

[0041] AM is the transmitting power switch control signal, when AM=1, the transmitting power switch is turned on, and when AM=0, the transmitting power switch is turned off;

[0042] S2. Before transmitting the signal, first set TR = 1, switch to the transmitting state, then set the control signal AM = 1, turn on the transmitting power switch, and start transmitting the signal;

[0043] S3. When the signal is transmitted through the RF channel, the RF channel will output a detection flag signal (if the flag signal is directly used as the final judgment result of the transmission detection, the judgment will be unstable or even wrong);

[0044] S4. After the signal transmission is completed, first set AM = 0, then set the control signal TR = 0, enter the receiving state, and wait for the next transmission process to come.

[0045] S5. The controller (FPGA) executes the program running state machine according to the amplitude value of the transmit signal I / Q and the detection flag signal obtained in S3, and finally outputs the transmit detection decision signal.

[0046] In an embodiment of the present application, if the transmitting power supply is in the on state (AM=1) and switched to the receiving state (TR=0), in this case, the transmitting signal will linger in the transmitting channel and eventually burn the device, so this situation must be avoided; therefore, in the receiving state (TR=0), the transmitting power switch (AM=0) must be turned off a period of time in advance (1us in the embodiment of the present application).

[0047] In the receiving state, no signal is sent to the RF channel through the digital-to-analog converter (DAC). It is normal for the RF channel to not output a transmission detection flag signal in this state. Therefore, the program must avoid judging the transmission detection in the receiving state.

[0048] To this end, we first set a fixed threshold value d0 according to the bit width of the DAC. On the one hand, multiple experiments have proved that if the value of d0 is sent to the DAC and transmitted through the RF channel, the FPGA can receive the transmission detection flag signal; on the other hand, the I / Q value sent to the DAC in the receiving state is 0, and the amplitude value cannot exceed d0, which effectively avoids the judgment of the transmission detection in the receiving state. In addition, in order to obtain a stable and correct final judgment result, the number of detections needs to be accumulated. Therefore, the program uses a state machine to implement this process, specifically:

[0049] Specifically, the implementation of step S5 includes the following steps:

[0050] S501. Calculation (I max and Q max The bit width of the DAC is determined by the bit width of the DAC. For example, if the bit width of the DAC is 14 bits, then I max =16384,Q max =16384, d0=5793).

[0051] S502. The program sets a detection counter, and when power-on reset occurs, the detection counter is set to a fixed initial value c0 (in this example, c0 = 40).

[0052] S503. During the time when TR = 1 and AM = 1, the controller (FPGA) calculates the amplitude value of the transmitted data I / Q.

[0053] S504. For each transmission, if d1 >= d0, it is considered that the transmitted I / Q data is valid detection data. The program state machine will check the detection flag signal returned by the RF channel in the next state and increment the detection counter: if the detection flag is detected, c0 + 1 (the detection counter is set with a maximum detection count c1, in this example, c1 = 250); if the detection flag is not detected, c0 - 1 (the detection counter is set with a minimum detection count c2, in this example, c2 = 10), until the end of this transmission process; if d1 < d0, it is considered that the transmitted I / Q data is invalid detection data, and the program state machine will maintain the current state until the end of this transmission process (regardless of the relationship between d1 and d0, the I / Q data is still normally transmitted).

[0054] S505. When the system is transmitting normally (usually multiple consecutive transmissions), if the value of the detection counter is lower than c2, it is determined that the transmission detection is faulty; otherwise, it is determined that the transmission detection is normal.

[0055] In the embodiment of the present application, the specific implementation principle of the transmission detection circuit based on the detection flag signal processing of the transceiver component is as follows:

[0056] The FPGA is set at the output end of the ADC in the transceiver component, processes the signal output by the analog-to-digital converter (ADC), and outputs the obtained signal to the signal processing device. In this embodiment, the TR and AM signals are generated by the baseband processing device or an external device; the TR signal is used to control the transceiver switch. When TR = 0, the transceiver switch switches to the receive channel, connecting the receive channel to the transceiver antenna; when TR = 1, the transceiver switch switches to the transmit channel, connecting the transmit channel to the transceiver antenna; in the entire embodiment, power is supplied through an external power supply. Except for the transmit channel and the DAC, other parts are always powered as long as the transceiver component is started; and the power supply of the external power supply to the transmit channel and the DAC needs to pass through the transmit power switch, and the on / off of the transmit power switch is controlled by the AM signal; when AM = 1, the transmit power switch is turned on, and when AM = 0, the transmit power switch is turned off; in this embodiment, the TR and AM signals generated by the signal processing device or an external device need to be transmitted to the FPGA simultaneously.

[0057] The above are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A transmitting detection circuit based on analog-to-digital signal processing of a transceiver component, characterized in that: The transmitting and detecting circuit comprises: a signal processing device, an FPGA logic control circuit, a DAC module, an ADC module, a radio frequency transmitting channel, a radio frequency receiving channel, a transmitting and receiving switching switch and a transmitting and receiving antenna; the first signal output end of the signal processing device is connected to the input end of the DAC module, the second signal output end of the signal processing device is connected to the first input end of the FPGA logic control circuit, the output end of the DAC module is connected to the input end of the radio frequency transmitting channel, the output end of the radio frequency receiving channel is connected to the input end of the ADC module, the output end of the ADC module is connected to the second input end of the FPGA logic control circuit, the output end of the FPGA logic control circuit is connected to the signal input end of the signal processing device, and the output end of the radio frequency transmitting channel and the input end of the radio frequency receiving channel are connected to the transmitting and receiving antenna through the transmitting and receiving switching switch; wherein: The signal processing device transmits a transmission signal for transmission by the transceiver antenna to the DAC module through the first signal output terminal, and provides a transmission detection control signal to the FPGA logic control circuit through the second signal output terminal to implement the transmission detection process in the transceiver component; The RF transmission channel transmits the signal via the transceiver antenna according to the digital transmission signal transmitted by the received DAC module; the RF receiving channel transmits the detection mark signal returned by the receiving channel to the ADC module, and processes the signal via the FPGA logic control circuit; The FPGA logic control circuit is connected to the ADC module and the signal processing device, and is used to transmit the detection mark digital signal transmitted by the ADC module to the signal processing device, and receive the detection control signal transmitted by the signal processing device to output the transmission detection decision signal; the implementation of outputting the transmission detection decision signal includes: The program sets the detection counter, and the detection counter is set to a fixed initial value c0 when the power is reset; If the transmitted I / Q data is validly detected data, the program state machine checks the detection flag signal returned by the RF channel in the next state and counts it into the detection counter; If the detection mark is detected, c0+1 is used; if the detection mark is not detected, c0-1 is used until the end of this transmission process; If the transmitted I / Q data is invalid detected data, the program state machine will maintain the current state until the transmission process ends; When the system is transmitting normally, if the detection counter value is lower than the minimum detection count c2 set by the detection counter, the transmission detection is judged to be faulty, otherwise the transmission detection is judged to be normal.

2. A transmitting detection circuit based on analog-to-digital signal processing of a transceiver component as claimed in claim 1, characterized in that: The RF transmission channel and the RF receiving channel are respectively connected to the first power supply through a RF power switch circuit; wherein: the RF power switch circuit transmits a detection control signal via the signal processing device to perform connection control.

3. A transmitting detection circuit based on analog-to-digital signal processing of a transceiver component as claimed in claim 1, characterized in that: The transmitting detection circuit also includes a detection circuit, which is connected to the output end of the transmitting channel, detects the output signal, and returns the detection mark signal to the FPGA logic control circuit through the receiving channel via the ADC module.

4. A transmitting detection circuit based on analog-to-digital signal processing of a transceiver component as claimed in claim 1, characterized in that: The signal processing device includes a detection control terminal and a transmission signal source; the detection control terminal is used to send a detection control instruction to the FPGA logic control circuit and receive a detection flag signal returned by the FPGA logic control circuit, and the transmission signal source is used to send a transmission signal to the DAC module.

5. A transmitting detection circuit based on analog-to-digital signal processing of a transceiver component as claimed in claim 1, characterized in that: The ADC module includes an ADC chip, an ADC power switch circuit and a second power supply; wherein the ADC chip performs analog-to-digital conversion on the transmitted detection mark signal and transmits it to the FPGA logic control circuit; and the ADC power switch circuit controls the connection between the ADC chip and the second power supply.

6. A transmitting detection circuit based on analog-to-digital signal processing of a transceiver component as claimed in claim 1, characterized in that: The DAC module includes a DAC chip, a DAC power switch circuit and a third power supply; wherein the DAC chip receives a clock signal and a chip control signal sent by a signal processing device, converts the transmitted digital transmission signal into an analog transmission signal and transmits it to the RF channel; the DAC power switch circuit controls the connection between the DAC chip and the third power supply.

7. A transmitting detection circuit based on analog-to-digital signal processing of a transceiver component as claimed in claim 1, characterized in that: The transceiver switch receives a transceiver switch control signal sent by a signal processing device to control the access of a radio frequency transmission channel and a radio frequency reception channel to the transceiver antenna.

8. A transmitting detection circuit based on analog-to-digital signal processing of a transceiver component as claimed in claim 7, characterized in that: The detection control signal includes a transceiver switching control signal TR and a transmitting power switch control signal AM; wherein the RF transmitting channel and the RF receiving channel control signal sending and the detection flag signal returning according to the transceiver switching control signal TR and the transmitting power switch control signal AM, and the FPGA logic control circuit receives the detection flag signal sent by the RF receiving channel according to the transceiver switching control signal TR and the transmitting power switch control signal AM.

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