Boost Power Factor Correction Conversion

Abstract

In an example, a system (100) includes a boost power factor correction (PFC) converter (98) including a thermistor (118), an inductor (106), and a transistor (108) coupled to a common node (119). The system (100) also includes a PFC controller (110) coupled to the common node (119). The PFC controller (110) includes: a comparator coupled to a threshold voltage source and a non-control terminal of a transistor (108); a first flip-flop coupled to the comparator and a control terminal (109) of the transistor (108); a zero current detector coupled to the inductor (106); a timer coupled to the comparator and the zero current detector; a second flip-flop coupled to the timer and a control terminal (109) of the transistor (108); an AND gate coupled to the first flip-flop and the second flip-flop; a third flip-flop coupled to the second flip-flop and a control terminal (109) of the transistor (108); and a fourth flip-flop coupled to the AND gate and the control terminal (109) of the transistor (108).

Description

Technical Field

[0001] The present disclosure relates to boost power factor correction conversion. Summary of the invention

[0002] In one example, a system includes a boost power factor correction (PFC) converter including a thermistor, an inductor, and a transistor coupled to a common node. The system also includes a PFC controller coupled to the common node. The PFC controller includes: a comparator coupled to a threshold voltage source and a non-control terminal of the transistor; a first trigger coupled to the comparator and a control terminal of the transistor; a zero current detector coupled to the inductor; a timer coupled to the comparator and the zero current detector; a second trigger coupled to the timer and a control terminal of the transistor; an AND gate coupled to the first trigger and the second trigger; a third trigger coupled to the second trigger and a control terminal of the transistor; and a fourth trigger coupled to the AND gate and a control terminal of the transistor.

[0003] In one example, a system includes a boost power factor correction (PFC) converter including a thermistor, an inductor, and a transistor coupled to a common node. The system also includes a PFC controller coupled to the common node and configured to determine whether a current through the inductor reaches approximately zero within a predetermined amount of time after a voltage at the common node drops below a threshold.

[0004] In one example, a system includes a comparator having a first input configured to receive a voltage of a non-control terminal of a transistor, a second input configured to receive a threshold voltage, and an output. The system also includes a first flip-flop having a set input coupled to the output of the comparator, a data input configured to receive a low signal, an inverted clock input coupled to the control terminal of the transistor, and an output. The system also includes a timer having an inverted enable input coupled to the output of the comparator, a clear input coupled to a zero current detector, and an output. The system also includes a second flip-flop having a set input coupled to the output of the timer, a data input configured to receive a low signal, an inverted clock input coupled to the control terminal of the transistor, and an inverted output. The system also includes an AND gate having a first input coupled to the output of the first flip-flop, a second input coupled to the inverted output of the second flip-flop, and an output. The system also includes a third flip-flop having a data input coupled to the output of the first flip-flop, a clock input coupled to the control terminal, and an output. The system also includes a fourth flip-flop having a data input coupled to the output of the AND gate, a clock input coupled to the control terminal, and an output. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a circuit diagram of a boost power factor correction (PFC) converter system according to one example.

[0006] Figure 2 is a circuit diagram of a boost PFC controller detector according to one example.

[0007] Figure 3-Figure 6 It is described based on an example Figure 2 Timing diagram of the boost PFC controller detector behavior.

[0008] Figure 7 is described based on an example for Figure 2 A flow chart of the operating method of the boost PFC controller detector.

[0009] Figure 8 is based on an example description and Figure 2 A flow chart of a method associated with a boost PFC controller detector.

[0010] Fig. 9 is a block diagram of an electronic device including a boost PFC converter system according to one example. DETAILED DESCRIPTION

[0011] The power factor of an alternating current (AC) electrical power system is defined as the ratio of the real power absorbed by the load to the apparent power flowing in the circuit. Electrical systems with a power factor less than 1.0 suffer from inefficiencies that negatively impact the performance of the electronic equipment in which the power system is implemented, as well as the performance of the electrical grid. These inefficiencies may be corrected. Certain types of power converters can be used to improve the power factor. One such type of power converter is a boost power factor correction (PFC) converter, which includes a switch that is quickly turned on and off with a variable duty cycle to make the input current sinusoidal and in phase with the input voltage. A boost PFC converter typically includes an AC source, a rectifier, an inductor, one or more filter or smoothing capacitors, a diode, and the aforementioned switch.

[0012] One problem commonly encountered in boost PFC converters occurs when the converter is first switched on. At this point, a large inrush current flows from the AC source through the converter. This current is undesirable for a number of reasons, one of which is the fact that such high current levels can damage the converter. To overcome this problem, a thermistor is sometimes placed in the current path of the converter to mitigate the inrush current. The thermistor provides a high resistance when the converter is first switched on and is cold, and the resistance of the thermistor decreases once the converter has warmed up and the risk of a larger inrush current is low.

[0013] A disadvantage of using such a thermistor is that during the initial operation of the converter, the voltage across the thermistor may reach a high level. Such a high voltage may, for example, damage the transistor switch of the converter. Therefore, it would be useful to monitor the voltage at the thermistor and take preventive action when the voltage becomes too high. However, a high voltage at the thermistor may indicate different conditions that require different preventive measures. For example, in some cases, a high thermistor voltage may indicate an overvoltage condition that may be damaging, and such a condition should be addressed by, for example, disconnecting the converter and / or adjusting the duty cycle of the transistor switch. In other cases, a high thermistor voltage may indicate a transient condition (known as a cold start condition) that occurs during the initial operation of the converter, and such a condition may be addressed simply by adjusting the duty cycle of the transistor switch. The ability to distinguish between these two conditions would be useful.

[0014] The present disclosure describes various examples of boost PFC converter systems that are configured to distinguish between true overvoltage conditions and transient high voltage conditions (also referred to as cold start conditions). Advantages provided by such boost PFC converter systems include the ability to accurately diagnose high voltage situations and take appropriate actions to mitigate damage to the boost PFC converter system, electronic devices containing the converter system, and the electrical grid. Other PFC converter systems do not have the ability to accurately distinguish between true overvoltage conditions and cold start conditions, and therefore do not have the ability to effectively and efficiently take preventive measures to mitigate damage to the converter system.

[0015] In some examples, the boost PFC converter system described herein includes a boost PFC converter and a PFC controller coupled to a node between an inductor and a thermistor in the boost PFC converter. The PFC controller is configured to determine whether the current through the inductor reaches approximately zero within a predetermined amount of time after the voltage at the node drops below a threshold. If the current reaches approximately zero within a predetermined amount of time, the PFC controller outputs a signal indicating that the converter is in a true overvoltage condition and takes appropriate mitigation steps, such as reducing the switch duty cycle and / or disconnecting the converter for an extended predetermined period of time. Otherwise, if the current does not reach approximately zero within a predetermined amount of time, the PFC controller outputs a signal indicating that the converter is in a cold start condition, and the PFC controller can reduce the duty cycle. Other situations are also possible, for example, the PFC controller determines that the voltage at the node does not exceed the threshold, in which case the controller does not take mitigation action. In this way, the PFC controller described herein alleviates the above-mentioned problems.

[0016] Figure 11 is a circuit diagram of a boost power factor correction (PFC) converter system 100 according to one example. The boost PFC converter system 100 includes a boost PFC converter 98 and a PFC controller 110. The boost PFC converter 98 includes an AC source 101 coupled to a rectifier 102, a capacitor 104 coupled to the rectifier 102, an inductor 106 coupled to the capacitor 104, a thermistor 118 coupled to the inductor 106 at a node 119, a diode 120 coupled to the thermistor 118, and a capacitor 122 coupled to the diode 120. The boost PFC converter system 100 also includes a switch 108, such as a transistor (e.g., a metal oxide semiconductor field effect transistor (MOSFET)). For the purposes of the remainder of this description, it is assumed that the switch 108 is a MOSFET. The drain of the MOSFET 108 is coupled to the node 119. The source of the MOSFET 108 is coupled to a resistor 116, which in turn is coupled to a capacitor 122. Rectifier 102, capacitor 104, and resistor 116 are coupled to ground. Diode 120 is coupled to output node VOUT.

[0017] Boost PFC converter system 100 also includes a PFC controller 110. An input of PFC controller 110 is coupled to node 119. An output of PFC controller 110 is coupled to gate 109 of MOSFET 108. (The gate of MOSFET 108 is sometimes referred to herein as a control terminal, and the drain and source of MOSFET 108 are sometimes referred to herein as non-control terminals.) PFC controller 110 includes a detector 112 coupled to node 119 and a driver 114. Driver 114 is coupled to gate 109.

[0018] In operation, AC source 101 generates an AC signal, which is rectified by rectifier 102 to generate a rectified signal, which is smoothed by capacitor 104. Inductor 106 accumulates charge based on the current provided from rectifier 102. When MOSFET 108 is turned on, the current in inductor 106 increases. When MOSFET 108 is turned off, current flows through thermistor 118 and diode 120, and the current in inductor 106 decreases. An output voltage is provided at output node VOUT. Thermistor 118 alleviates large inrush currents at startup. Diode 120 prevents current from flowing when the voltage at the anode is low relative to the output voltage at output node VOUT. Capacitor 122 is a filter capacitor. Resistor 116 is optional and can be used, for example, to monitor the current flowing through MOSFET 108.

[0019] The detector 112 monitors the voltage at the node 119. When the detector 112 determines that the voltage at the node 119 has dropped below the threshold voltage, the detector 112 starts a timer to measure a predetermined amount of time. If the detector 112 determines that the current flowing through the inductor 106 reaches approximately zero within the predetermined amount of time from the time when the voltage at the node 119 drops below the threshold voltage, the detector 112 recognizes a true overvoltage condition and takes appropriate action to protect the converter system 100. For example, the detector 112 outputs one or more signals to the driver 114 that cause the driver 114 to turn off the MOSFET 108 for an extended period of time and / or manipulate the MOSFET 108 to reduce the duty cycle of the converter system 100. If the detector 112 determines that the current flowing through the inductor 106 reaches approximately zero after the predetermined amount of time, the detector 112 recognizes a transient cold start condition and takes appropriate action. For example, the detector 112 outputs one or more signals to the driver 114, which causes the driver 114 to manipulate the MOSFET 108 to reduce the duty cycle of the converter system 100. If the voltage at the node 119 does not exceed the threshold voltage, the detector 112 does not take mitigation action. If the voltage at the node 119 exceeds the threshold and remains above the threshold, the detector 112 causes the driver 114 to turn off the MOSFET 108 and / or manipulate the MOSFET 108 to reduce the duty cycle of the converter system 100. As used herein, approximately zero current can refer to the current through the inductor being at a level that will trigger a zero current detector. It can refer to a current between -5mA and +5mA (including terminal values). It can refer to a current between -1mA and +1mA (including terminal values).

[0020] Figure 2 1 is a circuit diagram of a PFC controller detector 112 according to one example. The detector 112 includes a comparator 201 including inputs 202 and 203. Input 202 is an inverting input and receives a threshold voltage OVP2TH. Input 203 is a non-inverting input and is coupled to Figure 1 108. The output of comparator 201 is coupled to node 206. Node 206 is coupled to input 211 of blanking circuit 204. Inverting input 205 is coupled to gate 109. Blanking circuit 204 has an output 222 that can be a logic high if the drain voltage is above a threshold voltage and a logic low if the drain voltage is below the threshold voltage. Output 222 is coupled to a set input 223 of flip-flop 221. Flip-flop 221 has a data input 224 that receives a logic low signal, an inverted clock input 225 coupled to gate 109, a clear input 226 that is configured to receive a reset signal, and an output 227 coupled to node 228.

[0021] Node 206 is also coupled to an inverting enable input 210 of a timeout timer (or simply timer) 209. Timer 209 has a clear input 212 coupled to an output 213 of a zero current detector (ZCD) 207. ZCD 207, in turn, has an input 208 coupled to the drain of MOSFET 108. Timer 209 has an output 214 coupled to a set input 215 of a flip-flop 216. Flip-flop 216 has a data input 217 that receives a low signal. Flip-flop 216 has an inverting clock input 218 coupled to gate 109. Flip-flop 216 has a clear input 220 that is configured to receive a reset signal. Flip-flop 216 includes an inverting output 219.

[0022] Detector 112 includes an AND gate 229 having an input 230 coupled to inverted output 219. AND gate 229 also has an input 231 coupled to node 228. Flip-flop 237 has a data input 238 coupled to node 228, a set input 243 receiving a logic low, and a clock input 239 coupled to gate 109. A clear input 240 is configured to receive a reset signal, and an output 241 provides a signal REDUCED_ON_TIME. Flip-flop 232 has a data input 233 coupled to the output of AND gate 229 and a clock input 234 coupled to gate 109. Flip-flop 232 has a clear input 235 configured to receive a reset signal, and an output 236 providing a signal OVP2_FAULT. Flip-flop 232 includes a set input 242 receiving a logic low. Figure 3-Figure 4 The timing diagram describes the operation of the detector 112.

[0023] Figure 3 It is described based on an example Figure 2 1. A timing diagram 300 of the behavior of the detector 112 for a cold start condition. Waveform 302 depicts the drain voltage of the MOSFET 108. Dashed line 304 depicts the threshold voltage received by the comparator 201 on the input 202. Waveform 306 depicts the output of the blanking circuit 204. When the drain voltage exceeds the threshold voltage, the waveform 306 goes high, and when the drain voltage is less than the threshold voltage, the waveform 306 goes low. The exception to this behavior of waveform 306 is during the blanking time provided by the blanking circuit 204. After the blanking time expires (e.g., determined by a timer within the blanking circuit 204), the output of the comparator 201 is released to the flip-flop 221. Waveform 308 depicts the output 213 of the ZCD 207.

[0024] When MOSFET 108 is turned on, inductor 106 ( Figure 1) increases, and when MOSFET 108 is turned off, inductor 106 ( Figure 1 ) decreases. Because the activation and deactivation of MOSFET 108 depends on the signal provided to gate 109, the aforementioned increase in inductor 106 current coincides with a high gate voltage, while the decrease in inductor 106 current coincides with a low gate voltage. At time 310, gate 109 switches to low, which means that the inductor 106 current (and therefore, the drain voltage) begins to decrease, as depicted by waveform 302. Because the drain voltage (waveform 302) is above the threshold voltage (waveform 304), the signal at node 206 is high. The signal at node 206 is provided to blanking circuit 204, which is activated when inverting input 205 goes low as gate 109 goes low. One reason for the blanking time is to remove noise that appears in the signal at node 206 during the switching of MOSFET 108. After the appropriate blanking time has been provided, output 222 goes high, as indicated by waveform 306 at time 314.

[0025] Because output 222 is high, input 223 is high, setting output 227 of flip-flop 221 high. Because input 223 is a set input, output 227 remains high regardless of changes at input 223 until a falling edge of the voltage at gate 109 is received at input 225, at which time a low signal provided to input 225 is provided at output 227. For purposes of timing diagram 300, after time 310, the voltage at gate 109 does not experience another falling edge.

[0026] At time 318, the drain voltage (waveform 302) drops below the threshold voltage (dashed line 304). At this point, output 222 goes low, but as described above, this has no effect on output 227 of flip-flop 221. Output 227 remains high. However, the result of the drain voltage dropping below the threshold voltage is that input 210 receives a low signal, thereby enabling timer 209. As indicated by number 312, an example duration of timer 209 is 600ns. If ZCD waveform 308 goes high during this time window, a true overvoltage condition is identified. However, as described above, timing diagram 300 depicts a cold start condition, and therefore ZCD 308 goes high at time 324 after the 600ns time window has expired. Reference Figure 2Detector 112 in, at time 318, output 214 is low, which has no effect on flip-flop 216. At time 320, the 600ns time window expires. Because the ZCD signal at the clear input 212 remains low, and therefore has no effect on output 214, output 214 goes high. Because input 215 is a set input, the received high signal causes the inverting output 219 to go low. Regardless of any further changes to the set input 215, the inverting output 219 will remain low. Therefore, from time 320, node 228 is fixed high, and the inverting output 219 is fixed low. Therefore, input 238 is high, and input 233 is low. At time 324, the ZCD signal at input 212 rises, but as explained, this has no effect on the output of flip-flop 216. At time 326, the voltage at gate 109 rises, and the rising edge is provided to clock inputs 239 and 234. As a result, flip-flops 237, 232 are triggered to capture their inputs 238, 233. Therefore, REDUCED_ON_TIME goes high, and OVP2_FAULT goes low. These outputs indicate a cold start condition, which means that driver 114 should reduce the duty cycle of the system until REDUCED_ON_TIM goes low. However, there is no true overvoltage condition that should cause MOSFET 109 to turn off and remain off for an extended period of time.

[0027] Figure 4 A timing diagram 400 depicting a true overvoltage condition is shown. Timing diagram 400 is substantially identical to timing diagram 300, with similar numbers representing similar waveforms and events within detector 112. However, timing diagram 400 differs from timing diagram 300 in that the ZCD signal goes high during the 600ns period started by timer 209. Specifically, because the drain voltage is above the threshold voltage at one time, output 227 is high, and therefore node 228 is high. However, the period of time that the drain voltage remains above the threshold voltage is longer than in timing diagram 300, and therefore timer 209 is triggered at time 418, which is later than in timing diagram 300. This triggering of timer 209 is closer to the time when ZCD 207 detects that the inductor 106 ( Figure 1) in the time of about zero current. Therefore, the ZCD signal provided at input 212 goes high at time 424, which is within the example 600ns time window indicated by number 412. Because input 212 goes high before timer 209 expires, output 214 remains low. Therefore, the set input 215 remains low, and therefore the inverting output 219 remains high. Therefore, node 228 is high, and the inverting output 219 is also high. As a result, input 238 is high, and input 233 is also high. When the voltage at gate 109 goes high at time 426, REDUCED_ON_TIME goes high, and OVP2_FAULT also goes high. These signals together indicate a true overvoltage condition. In response, driver 114 can adjust the signal provided to gate 109 to reduce the duty cycle and / or turn off MOSFET 108 for an extended predetermined time period.

[0028] Figure 5 Included is a timing diagram 500 depicting various scenarios for system 100. Timing diagram 500 includes an inductor 106 current waveform 502, a drain voltage waveform 504, a threshold voltage dashed line 506, a gate voltage waveform 508, a waveform 510 depicting output 222, a waveform 512 depicting output 219, and a waveform 514 depicting output 213. Timing diagram 500 also includes a waveform 516 depicting a signal REDUCED_ON_TIME, a waveform 518 depicting a signal OVP2_FAULT, and a waveform 520 depicting a RESET signal provided to inputs 220, 226, 235, and 240.

[0029] At time 522, the drain voltage drops rapidly to zero, at which point the current of inductor 106 is approximately zero. At time 524, the voltage at gate 109 goes high (waveform 508). This causes MOSFET 108 to turn on, which in turn causes the inductor 106 current to rise and the drain voltage to remain approximately zero. At time 526, the voltage at gate 109 goes low. This causes the drain voltage and inductor 106 current to begin to decrease. At time 528 after the blanking time, output 222 (waveform 510) goes high and remains high until the drain voltage drops below the threshold voltage at time 530. Although brief, this rise in output 222 causes output 227 to go high and remain high. When the drain voltage drops below the threshold voltage at time 530, timer 209 is triggered. Timer 209 expires at time 532, at which point output 214 (waveform 512) goes high. (If ZCD output 213 has become valid / asserted before timer 209 expires at time 532, output 214 will not go high, but this is not the case for this situation.) Because output 214 goes high, set input 215 also goes high, causing inverting output 219 to be low and remain low. Because output 227 is high and inverting output 219 is low, input 238 is high and input 233 is low. ZCD output 213 (waveform 514) goes high at time 534, but this does not matter because trigger 216 has been set to high. At time 536, the voltage at gate 109 rises (waveform 508), thus causing triggers 237 and 232 to capture their corresponding inputs. Therefore, at time 536, REDUCED_ON_TIME signal (waveform 516) goes high, and OVP2_FAULT signal (waveform 518) remains low. Thus, the drain voltage behavior beginning at time 526 and ending at time 536 represents a cold start condition. As described above, the driver 114 takes appropriate action. For example, the duty cycle of the system may be reduced, which is reflected as a reduced duration that the voltage at the gate 109 is high in the next cycle (times 536 to 538). The reset signal (waveform 520) may be asserted (asserted) at time 554 to clear the flip-flop.

[0030] When the voltage at the gate 109 is high, the drain voltage is low, and the inductor 106 current rises. At time 538, the voltage at the gate 109 drops to low, thus causing the drain voltage to rise quickly and begin to decline, and also causing the inductor 106 current to begin to decline. However, unlike the previous cold start condition, the drain voltage behavior between time 538 and 544 indicates normal operation because the drain voltage does not exceed the threshold voltage. When the voltage at the gate 109 drops (time 538), the triggers 221, 216 capture their corresponding inputs 224, 217 (both are low). Therefore, the output 227 is low and the inverted output 219 is also low, while the outputs 241 and 236 remain unchanged because they are changed by the rising edge gate signal. Since the outputs 227, 219 are low, the input 238 is low, and the input 233 is low. When the voltage of gate 109 rises at time 544, the signals at inputs 238, 233 are captured and output in the form of low REDUCED_ON_TIME and OVP2_FAULT signals. Driver 114 receives these signals and takes appropriate action. For example, driver 114 can increase the duty cycle of the system, as indicated by the increased duration of the gate pulse starting at time 544.

[0031] At time 546, the voltage at gate 109 goes low, causing outputs 227 and 219 to go low and high, respectively. The drain voltage rises above the threshold voltage, causing output 227 to rise. When the drain voltage drops below the voltage threshold at time 550, timer 209 is started. Because ZCD output 213 goes high before the timer expires, clear input 212 receives a high signal, thus causing output 214 to remain low even after timer 209 expires. Therefore, output 219 remains high. Because output 219 is high and node 228 is high, inputs 238 and 233 are high. When the voltage at gate 109 drops at time 554, inputs 238 and 233 are captured, and REDUCED_ON_TIME and OVP2_FAULT signals are both high. This indicates that there is a real overvoltage situation, and driver 114 takes appropriate action. For example, the driver 114 turns off the MOSFET 108 for an extended predetermined length of time, and after restarting the MOSFET 108, the driver 114 reduces the duty cycle.

[0032] Figure 6 In fact, Figure 5 624, where similar waveform numbers represent similar waveforms. However, the drain voltage behavior starting at time 624 shows a drop below the voltage threshold, which is similar in timing to Figure 5630, the drain voltage drops below the threshold voltage, thus triggering the timer 209. Number 638 depicts a time window in which the ZCD output 213 goes high (waveform 614), thus causing the set input 215 to remain low, and the inverting output 219 to remain high. As a result, input 237 is high, and input 233 is also high. At time 636, the voltage at gate 109 drops, and the falling edge causes inputs 237, 233 to be captured and output as high REDUCED_ON_TIME signal and high OVP2_FAULT signal. Driver 114 receives these signals and takes appropriate action. For example, driver 114 can turn off MOSFET 108 for a predetermined amount of time that is extended, and after restarting MOSFET 108, driver 114 can reduce the duty cycle.

[0033] Figure 7 A flow chart of a method 700 according to an example is depicted. The method 700 describes the operation of the detector 112. The method 700 begins by receiving a drain voltage and a threshold voltage at a comparator (such as the comparator 201) (702). The method 700 next includes providing the comparator output to a blanking circuit (e.g., the blanking circuit 204) and a timer (e.g., the timer 209) (704). The method then includes waiting for the blanking time to elapse (706) and providing the comparator output to a first flip-flop (such as the flip-flop 221) (708). The method 700 also includes determining whether the drain voltage is greater than the threshold voltage (710). If not, the method includes providing a low output from the first flip-flop 221 (712). Then, control of the method returns to 710. Otherwise, the method 700 includes setting the output of the first flip-flop 221 high until the next falling edge of the voltage at the gate 109 (714).

[0034] Some or all of steps 716-732 are performed in parallel with some or all of steps 706-714 because the two sets of steps represent different paths in the detector 112. Method 700 includes determining whether a timer (e.g., timer 209) receives a low comparator input (716). If not, the method includes providing a second trigger (e.g., trigger 216) output (718) that remains low, and returning control of the method to 716. Otherwise, method 700 includes starting timer 209 (720) and determining whether the timer expires (722). If not, method 700 includes providing a low output (724) from the second trigger 216, and determining whether the ZCD output (e.g., output 213) is high (726). If not, control of the method returns to 722. Otherwise, if the ZCD output 213 is high (726), the method 700 includes setting the timer 209 output 214 to low (728) and keeping the output of the second flip-flop 216 high until the next falling edge of the voltage at the gate 109 (730). However, if the timer has expired (722), the method 700 includes setting the output of the second flip-flop 216 to low until the next falling edge of the voltage at the gate 109 (734). The method 700 describes the operation of the detector 112 until the flip-flops 221 and 216. The circuits downstream of these flip-flops (e.g., AND gate 229 and flip-flops 232, 237) operate as follows. The AND gate 229 provides an output based on the output of the flip-flops 221, 216. At the next rising edge of the voltage at the gate 109, the inputs at the flip-flops 237, 232 are captured and used to generate the signals REDUCED_ON_TIME and OVP2_FAULT.

[0035] Figure 8 Depicted with Figure 2 Flowchart of method 800 associated with detector 112 of the embodiment of the present invention. Method 800 begins by receiving a drain voltage and a threshold voltage at a comparator (802). Method 800 includes providing the comparator output to a blanking circuit and a timer (804). Method 800 next includes waiting for a blanking time of the blanking circuit to elapse (806), and comparing the drain voltage to the threshold voltage (808). Method 800 includes determining whether the drain voltage is greater than the threshold voltage (810). If not, 810 is repeated. However, if the drain voltage is greater than the threshold voltage, method 800 includes outputting a REDUCED_ON_TIME (e.g., Figure 2 The output of the flip-flop 237 in ( 812 ) is set high. Then, the method 800 includes determining whether the drain voltage is less than the threshold voltage ( 814 ). If not, the method 800 includes determining whether the inductor (e.g., Figure 1814. If the drain voltage is less than the threshold voltage at 814, the method 800 includes starting a timer (818) and determining whether the timer has expired (820). If not, the method 800 includes determining whether zero current has been detected in the inductor (822). If not, repeat 820, but if yes, perform 824. If it is determined at 820 that the timer has expired, the method 800 includes performing the next switching cycle with a reduced on-time (e.g., reduced duty cycle) (826).

[0036] Fig. 9 8 is a block diagram of an electronic device 800 including a boost PFC converter system 100 according to an example. Specifically, the electronic device 900 (e.g., a mobile device, an automotive subsystem, or any other powered device) includes a power source 902 including the boost PFC converter system 100 and a load 904 powered by the power source 902.

[0037] In this specification, elements or features that are "configured to" or "used to" perform a task or function may be configured (e.g., by programming or structural design) by the manufacturer at the time of manufacturing to perform a function, and / or these elements or features may be configurable (or reconfigurable) by the user after manufacturing to perform a function and / or other additional or alternative functions. Configuration may be performed through firmware and / or software programming of the device, through the construction and / or layout of the hardware components and interconnections of the device, or a combination thereof. Moreover, in this specification, the use of the phrase "ground / ground" or similar phrases includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of grounding suitable or applicable to the teachings of this specification. Unless otherwise specified, "about", "approximately" or "substantially" preceding a value refers to + / -10% of the value.

[0038] Modifications in the described embodiments are possible, and other embodiments are possible, within the scope of the claims.

Claims

1. A system comprising: a boost power factor correction converter, namely a boost PFC converter, comprising a thermistor having a terminal coupled to a common node, an inductor having a terminal coupled to the common node, and a transistor having a drain terminal coupled to the common node and a source terminal connected to ground; as well as A PFC controller is coupled to the common node and comprises: a comparator coupled to a threshold voltage source and a non-control terminal of the transistor; a first flip-flop coupled to the comparator and a control terminal of the transistor; a zero current detector coupled to the inductor; a timer coupled to the comparator and the zero current detector; a second flip-flop coupled to the timer and the control terminal of the transistor; An AND gate coupled to the first flip-flop and the second flip-flop; a third flip-flop coupled to the second flip-flop and the control terminal of the transistor; and a fourth flip-flop coupled to the AND gate and the control terminal of the transistor. 2 . The system of claim 1 , wherein the first flip-flop comprises an inverting clock input coupled to the control terminal of the transistor. 3 . The system of claim 1 , wherein the first flip-flop comprises a data input configured to receive a low signal. 4 . The system of claim 1 , wherein the timer comprises an inverting enable input coupled to the output of the comparator and a clear input coupled to the output of the zero current detector. 5 . The system of claim 1 , wherein a first input of the AND gate is coupled to an output of the first flip-flop, and a second input of the AND gate is coupled to an inverting output of the second flip-flop.

6. The system of claim 1, wherein the third flip-flop comprises a data input coupled to the output of the first flip-flop and a clock input coupled to the control terminal of the transistor.

7. The system of claim 1, wherein the fourth flip-flop comprises a data input coupled to the output of the AND gate and a clock input coupled to the control terminal of the transistor.

8. A system comprising: A boost power factor correction converter, namely a boost PFC converter, includes a thermistor, an inductor and a transistor coupled to a common node; as well as a PFC controller coupled to the common node and configured to determine whether a current through the inductor reaches approximately zero within a predetermined amount of time after a voltage at the common node drops below a threshold, wherein the PFC controller comprises: a comparator coupled to the blanking circuit; a plurality of flip-flops including a first flip-flop having a set input coupled to the blanking circuit and an inverted clock input coupled to a gate terminal of the transistor; AND gate; A timer has an enable input coupled to the comparator, a clear input coupled to a zero current detector, and an output, wherein the zero current detector is configured to detect current flowing through the inductor.

9. The system of claim 8, wherein the PFC controller comprises a second flip-flop having a set input coupled to the output of the timer, an inverted clock input coupled to the gate terminal of the transistor, and a data input configured to receive a low signal. 10 . The system of claim 9 , wherein the PFC controller comprises an AND gate coupled to an output of the first flip-flop and an inverted output of the second flip-flop.

11. The system of claim 10, wherein the PFC controller comprises a third flip-flop having a data input coupled to the output of the first flip-flop, and a clock input coupled to the gate terminal of the transistor. 12 . The system of claim 11 , wherein the PFC controller is configured to control switching of the transistor based on an output of the third trigger.

13. The system of claim 11, wherein the PFC controller comprises a fourth flip-flop having a data input coupled to the output of the AND gate and a clock input coupled to the gate terminal of the transistor. 14 . The system of claim 13 , wherein the PFC controller is configured to control switching of the transistor based on an output of the fourth flip-flop.

15. A system comprising: A boost power factor correction converter, namely a boost PFC converter, comprising a thermistor having a terminal coupled to a common node, an inductor having a terminal coupled to the common node, and a transistor having a drain terminal, a source terminal and a control terminal, the drain terminal being coupled to the common node; a comparator having a first input configured to receive a voltage at a non-control terminal of the transistor, a second input configured to receive a threshold voltage, and an output; a first flip-flop having a set input coupled to the output of the comparator, a data input configured to receive a low signal, an inverting clock input coupled to a control terminal of the transistor, and an output; a timer having an inverting enable input coupled to the output of the comparator, a clear input coupled to the zero current detector, and an output; a second flip-flop having a set input coupled to the output of the timer, a data input configured to receive a low signal, an inverting clock input coupled to the control terminal of the transistor, and an inverting output; an AND gate having a first input coupled to the output of the first flip-flop, a second input coupled to the inverted output of the second flip-flop, and an output; a third flip-flop having a data input coupled to the output of the first flip-flop, a clock input coupled to the control terminal, and an output; as well as a fourth flip-flop having a data input coupled to the output of the AND gate, a clock input coupled to the control terminal, and an output.

16. The system of claim 15, further comprising a thermistor coupled to the common node.

17. A method comprising: performing a first comparison of the transistor drain voltage with a threshold voltage; In response to the transistor drain voltage exceeding the threshold voltage in the first comparison, reducing a duty cycle of a boost power factor correction converter (boost PFC converter); performing a second comparison of the transistor drain voltage with the threshold voltage after reducing the duty cycle; in response to the transistor drain voltage exceeding the threshold voltage and detecting approximately zero current in the inductor of the boost PFC converter in the second comparison, stopping switching operation of the boost PFC converter; in response to the threshold voltage exceeding the transistor drain voltage in the second comparison, a timer in the boost PFC converter not expiring, and approximately zero current being detected in the inductor, stopping the switching operation; as well as In response to the threshold voltage exceeding the transistor drain voltage in the second comparison and the timer expiring, the duty cycle is reduced.

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