Methods for monitoring chamber drift

Abstract

A method for monitoring drift in a plasma processing chamber for semiconductor processing is provided. A plurality of cycles are provided, wherein each cycle includes depositing a deposition layer above a chuck in the plasma processing chamber, plasma etching the deposition layer, and measuring the time for plasma etching the deposition layer to etch through the deposition layer. The measured time for plasma etching is used to determine the drift of the plasma processing chamber.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Application No. 15 / 906,332, filed on February 27, 2018, which is incorporated herein by reference for all purposes. Technical Field

[0003] The present disclosure relates to the formation of semiconductor devices. More particularly, the present disclosure relates to the formation of semiconductor devices in a plasma processing chamber for depositing and etching layers. Background Art

[0004] In semiconductor processing, blank wafers may be processed and then removed from the chamber to be measured using metrology tools to determine the condition and performance of the chamber. Summary of the invention

[0005] To achieve the aforementioned objectives and in accordance with the purposes of the present disclosure, a method for monitoring drift in a plasma processing chamber for semiconductor processing is provided. A plurality of cycles are provided, wherein each cycle includes depositing a deposition layer above a chuck in a plasma processing chamber, plasma etching the deposition layer, and measuring the time for plasma etching the deposition layer to etch through the deposition layer. The measured time for plasma etching is used to determine the drift of the plasma processing chamber.

[0006] These and other features of the present disclosure will be described in more detail below in the detailed description of the disclosure and in conjunction with the following figures. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present disclosure is illustrated by way of example and not limitation in the accompanying figures and in which like reference numerals indicate similar elements and in which:

[0008] Figure 1 is a high-level flow chart of an implementation scheme.

[0009] Figure 2 is a schematic diagram of a plasma processing chamber that may be used in one embodiment.

[0010] Figure 3 is a schematic diagram of a computer system that can be used to implement one embodiment.

[0011] Figure 4A -B is a cross-sectional view of a portion of an ESC processed according to one embodiment.

[0012] Figure 5A -B is a cross-sectional view of a portion of a stack processed according to another embodiment. DETAILED DESCRIPTION

[0013] The present disclosure will now be described in detail with reference to several preferred embodiments shown in the accompanying drawings. In the following description, many specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be implemented without some or all of these specific details. In other cases, well-known process steps and / or structures are not described in detail to avoid unnecessarily making the present disclosure unclear.

[0014] Integrated circuit manufacturers monitor tool parameters, such as deposition and etch rates, to maintain control over yield. Deposition rates are collected by depositing material and then measuring the thickness of the deposition or some other parameter at a location outside the deposition chamber to determine the thickness using a metrology tool. The etch rate is determined by loading a pre-deposited wafer with a known thickness (measured by a metrology tool) into an etching module. The wafer is then etched and measured ex situ with a metrology tool to determine the amount of material removed. Using such test wafers to monitor wafers increases costs and reduces the utilization of tools in the factory. Enhanced monitoring can help find tool problems faster, resulting in reduced product losses. But increased monitoring also means less product run time. In addition, there is the cost of using test wafers to monitor tools. The wafer fab needs to purchase or spend time on a deposition tool to create a test wafer for the etching tool. The deposition tool needs to give up operating space or tool time to run deposition monitoring. The cost of maintaining a regeneration cycle for reusing wafers is also high.

[0015] If a fab can monitor tool performance parameters such as flow rate, power, pressure, etc. and correlate them to etch and deposition rates, this provides the fab with a measure to monitor tool health without always running monitoring test wafers. The disadvantage is that the deposition and etch rates are unknown. As a result, drifts in deposition and etch rates due to chamber adjustments, idle time of the tool, and contamination are not detected through the tool performance parameters.

[0016] For ease of understanding, Figure 1 1 is a high level flow chart of one embodiment. A deposited layer is deposited (step 104). The deposited layer is etched by plasma etching (step 108). The time used to etch the deposited layer is measured (step 112). Steps 104 to 112 may be repeated one or more times (step 116). The measured time is used to determine the drift of the plasma processing chamber (step 120). Steps 104 to 120 may be repeated one or more times (step 124). When it is determined that the plasma processing chamber has drifted too far, the plasma processing chamber is adjusted (step 128).

[0017] Example

[0018] Figure 2 2 is a schematic diagram of a plasma processing chamber that can be used in one embodiment. In one or more embodiments, the plasma processing chamber 200 includes a gas distribution plate 206 and an electrostatic chuck (ESC) 208 that provide a gas inlet in a chamber 249 surrounded by a chamber wall 252. In the chamber 249, the wafer 203 is positioned above the ESC 208, which is a substrate support. The edge ring 209 surrounds the ESC 208. The ESC source 248 can provide a bias to the ESC 208. The gas source 210 is connected to the chamber 249 through the gas distribution plate 206. The ESC temperature controller 250 is connected to the ESC 208. The radio frequency (RF) source 230 provides RF power to the lower electrode and / or the upper electrode, which is the ESC 208 and the gas distribution plate 206 in this embodiment. In an exemplary embodiment, a 400kHz power supply, a 60MHz power supply, and optionally a 2MHz power supply, a 27MHz power supply constitute the RF source 230 and the ESC source 248. In this embodiment, the upper electrode is grounded. In this embodiment, one generator is provided for each frequency. In other embodiments, the generators may be in separate RF sources, or separate RF generators may be connected to different electrodes. For example, the upper electrode may have inner and outer electrodes connected to different RF sources. Other arrangements of RF sources and electrodes may be used in other embodiments. The optical detector is optically connected to the chamber 249. The controller 235 is controllably connected to the RF source 230, the ESC source 248, the exhaust pump 220, the optical detector 240, and the gas source 210. An example of such a chamber is the Striker 240 manufactured by Lam Research Corporation (Fremont, CA). TM Oxide system.

[0019] Figure 3 300 is a high-level block diagram showing a computer system 300 suitable for implementing the controller 235 used in the embodiment. The computer system can have many physical forms from integrated circuits, printed circuit boards, and small handheld devices to supercomputers. The computer system 300 includes one or more processors 302, and may also include an electronic display device 304 (for displaying graphics, text, and other data), a main memory 306 (e.g., random access memory (RAM)), a storage device 308 (e.g., a hard drive), a removable storage device 310 (e.g., an optical drive), a user interface device 312 (e.g., a keyboard, a touch screen, a keypad, a mouse or other pointing device, etc.) and a communication interface 314 (e.g., a wireless network interface). The communication interface 314 allows software and data to be transmitted between the computer system 300 and external devices via a link. The system may also include a communication infrastructure 316 (e.g., a communication bus, a cross-connect bar, or a network) connected to the above-mentioned devices / modules.

[0020] The information transmitted via the communication interface 314 may be in the form of signals such as electronic signals, electromagnetic signals, optical signals, or other signals that can be received by the communication interface 314 via a communication link that carries the signals and may be implemented using wires or cables, optical fibers, telephone lines, cellular phone links, radio frequency links, and / or other communication channels. Using such a communication interface, it is contemplated that the one or more processors 302 may receive information from a network during the execution of the above-described method steps, or may output information to a network. Furthermore, the method embodiments may be executed solely on a processor, or may be executed over a network such as the Internet with a remote processor that shares a portion of the processing.

[0021] The term "non-transitory computer-readable medium" is generally used to refer to media such as main memory, secondary memory, removable storage devices, and storage devices such as hard disks, flash memory, disk drive memory, CD-ROMs, and other forms of persistent memory, and should not be interpreted as covering transient subject matter such as carrier waves or signals. Examples of computer code include machine code (such as produced by a compiler) and files containing higher-level code executed by a computer using an interpreter. Computer-readable media may also be computer code that is transmitted by a computer data signal embodied in a carrier wave and represents a sequence of instructions that can be executed by a processor.

[0022] In one embodiment, a deposited layer is deposited on a chuck (step 104). In this example, the deposition is done without a wafer in the plasma processing chamber 200. In this example, the deposited layer is silicon oxide. An example recipe for depositing silicon oxide may first provide a silicon-containing precursor, such as polysilane (H 3 Si-(SiH 2 ) n -SiH 3 ), where n≥0, silane (SiH 4 ), disilane (Si 2 H 6 ) and organosilane, such as methylsilane, ethylsilane, isopropylsilane, tert-butylsilane, dimethylsilane, diethylsilane, di-tert-butylsilane, allylsilane, sec-butylsilane, tert-hexylsilane, isopentylsilane, tert-butyldisilane, di-tert-butyldisilane, etc. A silicon-containing precursor can be provided to deposit a silicon-containing layer. An oxidant also flows into the plasma treatment chamber 200. The oxidant can include one or more of oxygen, water, carbon dioxide, nitrous oxide or carbon monoxide. In some embodiments, the silicon-containing precursor and the oxidant can flow simultaneously. In other embodiments, the silicon-containing precursor and the oxidant can flow sequentially. Figure 4Ais a cross-sectional view of a portion of ESC 208, wherein deposited layer 404 has been deposited directly on the top surface of ESC 208. In other embodiments, other layers may be between ESC 208 and deposited layer 404, wherein a wafer is not between ESC 208 and deposited layer 404.

[0023] The deposited layer is plasma etched (step 108). An example of an etching recipe for etching the deposited silicon oxide layer provides an etchant gas containing a halogen-containing component to the plasma processing chamber 200. The halogen-containing component may include a fluorine-containing component, such as nitrogen trifluoride (NF 3 ), fluoroform (CHF 3 ), octafluorocyclobutane (C 4 F 8 ) and tetrafluoromethane (CF 4 ). The etchant gas is formed into an in-situ plasma in the plasma processing chamber 200, which etches the silicon oxide deposited layer. When the endpoint is detected, the etching stops. This can be done by stopping the flow of the etchant gas or by stopping the RF power that energizes the plasma.

[0024] The time for plasma etching the deposited layer is measured (step 112). In this example, the optical detector 240 uses optical emission spectroscopy (OES) to measure the optical emission spectrum to determine the time when the deposited layer has been etched through. Optical emission spectroscopy can be used to detect when the concentration of the substance from the etched silicon oxide decreases or when the concentration of the substance from the layer below the silicon oxide increases. In some embodiments, the silicon nitride layer can be between the surface of the ESC 208 and the silicon oxide deposited layer. In such an embodiment, the presence of the substance from the silicon nitride layer can be used to indicate that the silicon oxide deposited layer has been etched through. When the endpoint is detected, etching stops. This can be done by stopping the flow of the etchant gas or by stopping the RF power that energizes the plasma. Figure 4B is a cross-sectional view of a portion of the ESC 208 after the deposited layers have been etched.

[0025] Depositing the deposited layer (step 104), plasma etching the deposited layer (step 108), and measuring the time for plasma etching (step 112) can be repeated one or more times in a cycle (step 116). The measured time is used to determine the drift of the plasma processing chamber (step 120). In this embodiment, after each cycle, the measured time is compared with the reference time. If the measured time is not outside the threshold distance from the reference time, steps 104 to 120 are repeated (step 124). If the measured time is outside the threshold distance from the reference time, thereby indicating a threshold plasma drift, a flag can be raised to indicate that the plasma processing chamber needs to be adjusted. In this case, the plasma processing chamber is adjusted (step 128), such as cleaning, so as to obtain an etching time within the threshold distance from the reference time. Other embodiments may provide an adjustment that cleans the plasma processing chamber 200 and then deposits a layer on a portion of the interior of the plasma processing chamber 200. Between each cycle, one or more production wafers can be processed.

[0026] In another embodiment, after multiple cycles of steps 104 to 116, multiple measured times are plotted relative to the cycles into a graph, wherein the graph is used to determine the drift of the plasma processing chamber (step 120). If the graph does not indicate that the plasma processing chamber needs to be adjusted, steps 104 to 120 are repeated (step 124). The graph may show a sudden change in etching time. Such a sudden change may indicate a failure of a plasma processing chamber component. The chamber may be repaired. A gradual change in etching time may indicate a buildup of deposits in the plasma processing chamber, which may need to be cleaned at a particular point. The shape of the graph can be used to indicate the type of cleaning and the location of the required cleaning. After the chamber is adjusted (step 128), the wafer can be processed.

[0027] This embodiment allows the condition of a plasma processing chamber to be measured while minimizing the combination of downtime and production wafer defects. The condition of the plasma processing chamber can be determined quickly, thereby reducing or eliminating the need and waiting time for test wafers to be checked off-site by a metrology device. In addition, because test wafers are not used, the time required to load and unload test wafers is eliminated. In addition, the cost of preparing such test wafers is eliminated.

[0028] In another embodiment, a deposition layer is deposited on the chuck (step 104). In this example, the deposition is performed using a production wafer in a plasma processing chamber 200. In this example, the deposited layer is silicon nitride over a silicon oxide layer. Figure 5A5 is a cross-sectional view of a portion of a stack 500 in which a substrate 504 is below a silicon oxide layer 508 on which a silicon nitride layer 512 has been deposited. In this example, an etched feature 516 having sidewalls is formed in the silicon oxide layer 508. The etched feature 516 may be a groove or a hole or some other type of hole. The silicon nitride layer 512 is deposited on the sidewalls of the etched feature 516 and on the horizontal surfaces of the stack. When processing a production wafer, part of the processing will be to etch away the silicon nitride layer 512 formed on the horizontal surfaces, leaving only the silicon nitride deposited on the sidewalls. In other embodiments, one or more layers may be between the substrate 504 and the silicon nitride layer 512. In other embodiments, other layers of other materials may be used in place of the silicon nitride layer 512, as long as the endpoint of the etching of the deposited layer can be determined during the etching process.

[0029] The deposited layer is plasma etched (step 108). Figure 5B is a cross-sectional view of a portion of stack 500 after deposition layer 512 has been etched. Portions of silicon nitride layer 512 on horizontal surfaces have been etched away, while at least a portion of the vertical sidewalls remain.

[0030] The time for plasma etching the deposited layer is measured (step 112). In this example, an optical detector 240 is used for the OES to determine when the deposited layer has been etched through. The OES can be used to detect when the concentration of the species from the etched silicon nitride decreases or when the concentration of the species from the silicon oxide increases.

[0031] Depositing the deposited layer (step 104), plasma etching the deposited layer (step 108), and measuring the time for plasma etching (step 112) can be repeated one or more times in a cycle (step 116). For each cycle, the production wafer is taken out and a new production wafer is provided. The measured time is used to determine the drift of the plasma processing chamber (step 120). In one embodiment, after multiple cycles of steps 104 to 116, multiple measured times are plotted into a graph, wherein the graph is used to determine the drift of the plasma processing chamber (step 120). If the graph does not indicate that the plasma processing chamber needs to be adjusted, steps 104 to 120 are repeated (step 124). The graph may show a sudden change in etching time. Such a sudden change may indicate a failure of a plasma processing chamber component. The chamber can be repaired. A gradual change in etching time may indicate an accumulation of deposits in the plasma processing chamber, which may need to be cleaned at a specific point. The shape of the graph can be used to indicate the type of cleaning and the location of the required cleaning. After adjusting the chamber (step 128), additional production wafers can be processed.

[0032] Various embodiments enable increased throughput with fewer defective production wafers by reducing or eliminating the need for ex-situ measurements on metrology tools while measuring chamber performance more frequently using in-situ processing. By measuring performance more frequently, problems are detected more quickly, thereby reducing the number of defective wafers. Some embodiments do not require test wafers, thereby reducing cost and testing time. Some embodiments are able to measure how changes in processing parameters affect chamber performance. In another embodiment, the target deposition thickness can be a target in a recipe, so that the embodiment can be used in a plasma processing chamber to determine a recipe for obtaining the deposition target thickness.

[0033] Various embodiments may use different processes to determine when etching has penetrated the deposited layer. In one embodiment, optical emission spectroscopy will be used. In another embodiment, laser interferometry will be used.

[0034] Although the present disclosure has been described according to several preferred embodiments, there are changes, modifications, permutations, and various alternative equivalents that fall within the scope of the present disclosure. It should also be noted that there are many alternatives to the methods and devices of the present disclosure. Therefore, the following appended claims are intended to be interpreted as including all such changes, modifications, permutations, and various alternative equivalents that fall within the true spirit and scope of the present disclosure.

Claims

1. A method for monitoring drift in a plasma processing chamber for semiconductor processing, comprising: Multiple loops, where each loop consists of: depositing a deposition layer on a chuck in the plasma processing chamber, the depositing the deposition layer being performed without a wafer, and wherein the depositing the deposition layer deposits the deposition layer directly on a surface of the chuck; plasma etching the deposited layer; and measuring the time for plasma etching the deposited layer to etch through the deposited layer; and Using the measured time to determine a drift of the plasma processing chamber, wherein using the measured time comprises: generating a graph of time for plasma etching versus each cycle of the plurality of cycles; determining a condition of the chamber using the graph; and Using the graph to determine whether the plasma processing chamber requires maintenance; and wherein using the measured time further comprises: The measured time is used to determine when to clean the plasma processing chamber, wherein at least one production wafer is processed between each of the plurality of cycles.

2. The method according to claim 1, wherein: The measuring the time for plasma etching the deposited layer uses at least one of optical emission spectroscopy or laser interferometry.

3. The method according to claim 1, wherein: The using the measured time for plasma etching includes comparing the measured time for plasma etching with a reference time and determining whether the measured time for plasma etching is outside a threshold distance from the reference time.

4. The method according to claim 1, further comprising: When a threshold plasma drift is determined, the plasma processing chamber is cleaned.

5. The method according to claim 1, wherein: The plasma etching the deposited layer comprises: flowing an etchant gas comprising a halogen-containing component into the plasma processing chamber; and The etchant gas is formed into a plasma in the plasma processing chamber.

6. The method according to claim 1, further comprising: When the drift is determined to exceed a threshold, the plasma processing chamber is adjusted.

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