Power semiconductor devices and their fabrication methods

Abstract

This application discloses a power semiconductor device and a method for forming the same. The method comprises: providing a substrate with a first type of doping; forming a first patterned mask layer having a first opening on the surface of the substrate; performing a first ion implantation and diffusion process on the substrate along the first opening to form a body region with a second type of doping; forming a second patterned mask layer within the first opening, with second openings between the second patterned mask layer and the first patterned mask layer on either side; and performing a second ion implantation and diffusion process on the substrate along the second opening to form a first type of doping region within the body region. The power semiconductor device formed by this method exhibits improved threshold voltage consistency and uniformity.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a power semiconductor device and a method for forming the same. Background Technology

[0002] Field-effect transistors are divided into two types: depletion-type MOSFETs and enhancement-type MOSFETs. When the gate bias voltage is zero, the channel of an enhancement-type MOSFET is turned off; when the gate bias voltage is zero, the channel of a depletion-type MOSFET is turned on.

[0003] In the fabrication process of vertical double-diffused field-effect transistors (VDMOS), such as N-channel depletion-type VDMOS, a P-type body region and an inversion layer must be formed before the gate is formed. The type-1 doped region and body region are formed through two photolithography implantations. This leads to an impact on the overlay accuracy between the two photolithography steps, making it difficult to accurately control the channel length on both sides of the gate. Consequently, the channel threshold voltages on either side of the cell within the same device will differ. Furthermore, even VDMOS devices formed on the same wafer, due to the step-scan exposure process, different regions within the wafer are not exposed simultaneously. The deviation in step distance results in differences in photolithography overlay deviations in different regions, leading to differences in the threshold voltage of devices at different locations within the wafer. This results in a highly discrete threshold voltage distribution for depletion-type products, and even for the same model, different threshold voltage distributions may exist, leading to poor product consistency.

[0004] How to achieve precise control and compact distribution of threshold voltage is a problem that urgently needs to be solved. Summary of the Invention

[0005] In view of this, this application provides a power semiconductor device and a method for forming the same, to solve the problem of discrete threshold voltage distribution in existing power semiconductor devices.

[0006] This application provides a method for forming a power semiconductor device, comprising: providing a substrate with a first type of doping; forming a first patterned mask layer having a first opening on the surface of the substrate; performing a first ion implantation and diffusion treatment on the substrate along the first opening to form a second type of doped bulk region; forming a second patterned mask layer within the first opening, wherein the second patterned mask layer and the first patterned mask layers on both sides have a second opening; and performing a second ion implantation and diffusion treatment on the substrate along the second opening to form a first type of doped region located within the bulk region.

[0007] Optionally, it further includes: removing the second patterned mask layer to form a second type of doped region located between the first type of doped regions within the body region; removing the first patterned mask layer; and forming a gate structure on the substrate between adjacent body regions.

[0008] Optionally, the doping concentration of the second type doped region is greater than the doping concentration of the second type doped bulk region, so as to reduce the resistance of the second type doped region between the second type doped region and the first type doped substrate.

[0009] Optionally, the gate structure overlaps with the first type of doped regions in the body regions on both sides.

[0010] Optionally, it also includes forming an inversion layer on the substrate surface before forming the gate structure.

[0011] Optionally, it further includes forming a conductive structure on the substrate that connects the first type of doped region and the second type of doped region.

[0012] Optionally, the first patterned mask layer uses a hard mask layer material.

[0013] Optionally, the substrate includes a peripheral region and a core region, and the method for forming the first patterned mask layer includes: forming a field oxide layer that simultaneously covers the peripheral region and the core region; patterning the field oxide layer, and simultaneously forming a first hard mask layer with a first opening on the surface of the core region while forming a patterned field oxide layer on the peripheral region.

[0014] The present invention also provides a power semiconductor device, comprising: a substrate doped with a first type; a body region doped with a second type within the substrate; two first-type doped regions within the body region, wherein the channel length from the first-type doped regions to the edge of the body region is the same; and a gate structure on the substrate between adjacent body regions.

[0015] Optionally, the gate structure overlaps with the second type of doped regions in the body regions on both sides.

[0016] Optionally, an inversion layer is formed on the surface of the channel.

[0017] Optionally, a second type of doped region may also be included between two first type doped regions located within the same bulk region.

[0018] Optionally, it also includes: a conductive structure connecting the first type of doped region and the second type of doped region.

[0019] Optionally, the doping concentration of the second type doped region is greater than the doping concentration of the second type doped bulk region, so as to reduce the resistance of the second type doped region between the second type doped region and the first type doped substrate.

[0020] The method for forming power semiconductor devices in this application employs a self-aligned process along the same mask edge to form a body region and a first type of doped region, respectively. This ensures that the length of the channel region between the first type of doped region and the body region is not affected by photolithographic alignment deviations. The threshold voltage of each cell in a single power semiconductor device, as well as the threshold voltage of different power semiconductor devices in the same wafer, are the same or close (considering other process errors), resulting in a concentrated distribution of threshold voltages for power semiconductor devices of the same type. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figures 1a to 1d This is a schematic diagram of the formation process of power semiconductor devices in the prior art;

[0023] Figures 2 to 10 This is a schematic diagram of the formation process of a power semiconductor device according to an embodiment of the present invention. Detailed Implementation

[0024] As described in the background section, power semiconductor devices manufactured in the prior art suffer from discrete threshold voltage distribution.

[0025] Please refer to Figures 1a to 1d This is a schematic diagram of a process for forming a power semiconductor device.

[0026] Please refer to Figure 1a After a patterned photoresist layer 11 with an opening 12 is formed on the surface of the substrate 10 by photolithography, a second type of doped region 13 is formed by ion implantation along the opening 12.

[0027] Please refer to Figure 1b Through thermal annealing, dopant ions diffuse and activate within the second type of doped region 13 to form a bulk region 14, and an inversion layer 15 is formed on the surface of the substrate 10.

[0028] Please refer to Figure 1cOn the surface of the substrate 10 between adjacent body regions 14, a gate structure 16 is formed by photolithography etching. A second mask layer 17 is formed on the surface of the body regions between the gate structures 16. A first type of ion implantation is performed in the body regions 14 along the second mask layer 17 and the gate structure 16 to form a first type of doped region 18.

[0029] Please refer to Figure 1d The second mask layer 17 is removed to activate and diffuse ions within the first type of doped region 18. Since the lateral diffusion rate of each of the first type of doped regions 18 is consistent, their lengths below the gate structure 16 after diffusion are the same. The region between the first type of doped region 18 and the edge of the body region 14, located below the gate structure 16, forms the channel region.

[0030] There is a photolithographic alignment deviation between the first type doped region 18 and the body region 14. The photolithographic alignment deviation will cause the length of the body region 14 located on both sides of the gate structure 16 below the gate structure 16 to be different, which will ultimately result in the different lengths of the channels 19a and 19b on both sides of the gate structure 16 and the different channel threshold voltages.

[0031] To address the above problems, the present invention provides a novel power semiconductor device and a method for forming the same.

[0032] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.

[0033] Please refer to Figures 2 to 10 This is a schematic diagram of the formation process of a power semiconductor device according to an embodiment of the present invention.

[0034] Please refer to Figure 2 Substrate 100 is provided.

[0035] The substrate 100 is a semiconductor substrate, which may be a semiconductor material such as silicon, germanium, or germanium-silicon. Specifically, the substrate 100 may be a single-crystal silicon substrate doped with the first type, or the substrate 100 may further include a first-type doped epitaxial layer. In this embodiment, the substrate 100 includes a semiconductor substrate 101 and a first-type doped epitaxial layer 102 formed on the surface of the semiconductor substrate 101. Those skilled in the art can select a suitable structure, material, and doping concentration for the substrate 100 according to the performance requirements of the power semiconductor device.

[0036] In this embodiment, the first type of doping is N-type doping, and the second type of doping is P-type doping; in other specific embodiments, the first type of doping may also be P-type doping, and the second type of doping may be N-type doping. The dopant ion of the N-type doping may be at least one of Ph, As, or Td, and the dopant ion of the P-type doping may be at least one of B, BF2, Al, In, or Ga.

[0037] In this embodiment, the substrate 100 includes an N-type heavily doped semiconductor substrate 101 and an N-type lightly doped epitaxial layer 102 located on the surface of the semiconductor substrate 101.

[0038] Please refer to Figure 3 A first patterned mask layer 201 with a first opening 202 is formed on the surface of the epitaxial layer 102 of the substrate 100, and a first ion implantation is performed on the substrate 100 along the first opening 202 to form a second type of doped implantation region 203.

[0039] The first patterned mask layer 201 is made of a hard mask material, such as silicon oxide, silicon nitride, silicon oxynitride, amorphous carbon, or other hard mask materials. The method for forming the first patterned mask layer 201 includes: after forming a first mask material layer on the surface of the epitaxial layer 102, forming a photoresist layer on the surface of the first mask material layer; performing photolithographic exposure on the photoresist to form a patterned photoresist layer; and then using the patterned photoresist layer as a mask, etching the first mask material layer to form the first opening 202 and the first patterned mask layer 201.

[0040] A self-aligned implantation process is used to perform a first ion implantation on the epitaxial layer 102 along the first opening 202. The first ion implantation uses dopant ions of the second type, forming a second type doped implantation region 203 within the epitaxial layer 102. The lateral dimension of the second type doped implantation region 203 is determined by the edge of the first opening 202.

[0041] Please refer to Figure 4 The second type of doped implantation region 203 is subjected to diffusion treatment to form the second type of doped body region 301.

[0042] The diffusion process includes a thermal annealing process to activate the second type of dopant ions and perform lateral and longitudinal diffusion to form a second type of doped body region 301, which is located within the epitaxial layer 102. In this embodiment, the body region 301 is p-type doped.

[0043] Since the second type of doped implantation region 203 is formed along the second opening 202 using a self-aligned implantation process, and the diffusion rate of doped ions in each second type of doped implantation region 203 is consistent during the diffusion process, the dimensions of the lateral diffusion of the formed body region 301 below the first patterned mask layer 201 are all the same, which is d1.

[0044] Please refer to Figure 5 A second patterned mask layer 401 is formed within the first opening 202. The second patterned mask layer 401 and the first patterned mask layers 201 on both sides have a second opening 402. The substrate 100 is implanted with second ions along the second opening 402 to form a first type of doped implantation region 403.

[0045] The second patterned mask layer 401 can be made of photoresist or other mask materials. In this embodiment, the material of the second patterned mask layer 401 is photoresist. The method for forming the second patterned mask layer 401 includes: forming a photoresist layer covering the epitaxial layer 102 and the first patterned mask layer 201, and exposing and developing the photoresist layer to form the second patterned mask layer 401. The first patterned mask layer 201 and the second patterned mask layer 402 together define the position and size of the second opening 402.

[0046] The second ion implantation is performed along the second opening 402 using self-aligned implantation. In this embodiment, the second ion implantation uses first-type doped ions to form a first-type doped implantation region 403. The position and size of the first-type doped implantation region 403 are determined by the edge of the second opening 402, that is, by the edge of the first patterned mask layer 201 and the edge of the second patterned mask layer 401. The first-type doped implantation region 403 is an N-type heavily doped region.

[0047] Please refer to Figure 6 The first type of doped implantation region 403 is subjected to diffusion treatment to form the first type of doped region 501.

[0048] The diffusion process includes a thermal annealing process to activate the first type of doped ions and perform lateral and vertical diffusion to form the first type of doped region 501. The first type of doped region 501 is the source of the VDMOS. Since each first type of doped implantation region 403 (see reference...) Figure 5The doping concentration within each of the first-type doped implantation regions 403 is the same. During diffusion, the doped ions within each first-type doped implantation region 403 have the same diffusion rate in the same direction. The first-type doped ions diffuse laterally, causing some of the first-type doped regions 501 to be located below the first patterned mask layer 201, and the length of each first-type doped region 501 below the first patterned mask layer 201 is the same. Assuming the width of the first-type doped region 501 below the first patterned mask layer 201 is c1, then the distance from each first patterned mask layer 201 to the edge of the body region 301 is the same, which is d1-c1. This region is the channel region of the VDMOS. Therefore, the channel regions of each VDMOS formed after subsequent steps have the same length, and the VDMOS at different locations have the same threshold voltage.

[0049] Prior to the diffusion process, the second patterned mask layer 401 is removed.

[0050] Please refer to Figure 7 A second type of doped region 602 is formed within the body region 301, located between the first type of doped regions 501.

[0051] In this embodiment, the second type of doped region 602 is a heavily p-type doped region. The method for forming the second type of doped region 601 includes: forming a third patterned mask layer 601 covering the first patterned mask layer 201 and a portion of the substrate surface, the third patterned mask layer 601 exposing the region between the two first type of doped regions 501 within the body region 301; using the third patterned mask layer 601 as a mask, performing second type of doped ion implantation and diffusion processing to form the second type of doped region 602. A PN junction isolation structure is formed between the second type of doped region 602 and the first type of doped region 501 to prevent leakage between the two first type of doped regions 501 within the same body region 301.

[0052] The doping concentration of the second type doped region 602 is greater than the doping concentration of the second type doped body region 301. A parasitic transistor is formed between the first type doped region 501, the body region 301, and the epitaxial layer 102 of the VDMOS, with the first type doped region 501, the body region 301, and the epitaxial layer 102 serving as the emitter, base, and collector of the parasitic transistor, respectively. By forming the second type doped region 602 within the body region 301, the resistance of the second type doped region between the first type doped region 501 and the first type doped epitaxial layer 102 can be reduced, i.e., the base bias resistance Rb of the parasitic transistor, effectively suppressing the conduction of the parasitic transistor.

[0053] Please refer to Figure 8After removing the first patterned mask layer 102 and the third patterned mask layer 601, depletion implantation is performed on the surface layer of the substrate 100 to form an inversion layer 701.

[0054] In this embodiment, a depletion-mode VDMOS is used as an example; therefore, an inversion layer 701 needs to be formed on the surface of the channel region before forming the gate structure. In other embodiments, such as when forming an enhancement-mode VDMOS, this step can be omitted.

[0055] In this embodiment, the depletion implantation uses a first type of dopant ion, namely an N-type dopant ion, to neutralize the second type of dopant ions on the surface layer of the channel region between the first type of dopant region 501 and the edge of the body region 301, so as to form an inversion layer 701 with fewer charge carriers on the channel surface layer.

[0056] Figure 8 In this diagram, the inversion layer 701 is for illustrative purposes only and does not represent that the doping type and concentration are consistent throughout the inversion layer 701. The doping condition of the substrate surface after depletion implantation is determined based on the doping condition before implantation.

[0057] Please refer to Figure 9 A gate structure 910 is formed on the substrate 100 between adjacent body regions 301.

[0058] The gate structure 910 includes a gate dielectric layer 901 and a gate 902 located on the surface of the gate dielectric layer 901. In this embodiment, the gate dielectric layer 901 is made of silicon oxide, and the gate 902 is made of polysilicon. In other embodiments, the gate dielectric layer 901 may also be made of dielectric materials such as silicon nitride, silicon oxynitride, hafnium oxide, or aluminum oxide, and the gate 902 may also be made of conductive materials such as tungsten, aluminum, or copper.

[0059] The method for forming the gate structure 910 includes: sequentially forming a gate dielectric material layer and a gate material layer covering the surface of a substrate, and patterning the gate dielectric material layer and the gate material layer to form discrete gate structures 910.

[0060] Since the channel region length at each location is d1-c1, as long as the gate structure 910 can completely cover the channel region within the two body regions 301, it can ensure that the channel length of the VDMOS structures formed on both sides is the same and that they have the same threshold voltage.

[0061] To ensure that the gate structure 910 completely covers the channel regions on both sides, the length of the gate structure 910 can be set so that it overlaps with the first type of doped regions 501 in the body regions 301 on both sides, leaving a certain alignment deviation margin for the gate structure 910. The overlap length can be 0 to 0.7 μm, preferably 0.3 μm to 0.7 μm, for example 0.5 μm. Even if, during the formation of the gate structure 910, photolithographic deviations cause the gate structure 910 to fail to symmetrically cover the body regions 301 on both sides, the gate structure 910 can still completely cover the channel regions on both sides, resulting in the same VDMOS threshold voltage on both sides of the gate structure 910 and good turn-on consistency.

[0062] Please refer to Figure 10 A conductive structure 1002 is formed on the substrate to connect the first type of doped region 501 and the second type of doped region 602.

[0063] Specifically, firstly, an interlayer dielectric layer 1001 is formed covering the surface of the substrate and the surface of the gate structure 910. Then, the interlayer dielectric layer 1001 is etched to form a via exposing the second type doped region 601 and at least a portion of the second type doped region 602 on both sides. The via is filled with conductive material to form the conductive structure 1002.

[0064] In this embodiment, the sources of each N-channel depletion-type VDMOS cell are connected together through the conductive structure 1002 to form a power MOS transistor capable of withstanding a large operating current.

[0065] Subsequently, a conductive layer is formed on the back side of the semiconductor substrate 101 as a drain connection layer.

[0066] In the power semiconductor device formed by the above method, the body region and the first type of doped region are formed separately by a self-aligned process along the same mask edge, so that the length of the channel region between the first type of doped region and the body region is not affected by the photolithographic alignment deviation. Whether it is the threshold voltage of each cell in a single power semiconductor device or the threshold voltage of different power semiconductor devices in the same wafer, they are the same or close (considering other process errors), so that the threshold voltage distribution of power semiconductor devices of the same model is concentrated.

[0067] In another embodiment of the invention, the substrate includes a peripheral region and a core region, the peripheral region being used to form a peripheral isolation ring, and the core region being used to form a VDMOS cell for a power semiconductor device. Please refer to... Figure 2The method for forming the first patterned mask layer 201 includes: forming a field oxide layer that simultaneously covers the peripheral region and the core region; patterning the field oxide layer, forming a first hard mask layer 202 with a first opening 202 on the surface of the core region while simultaneously forming a patterned field oxide layer on the peripheral region. The field oxide layer is a relatively thick silicon oxide layer, used as an isolation structure for the peripheral region. In this embodiment, the material of the first hard mask layer 202 is a field oxide layer. Forming the first mask layer 202 simultaneously with forming the terminal isolation ring in the peripheral region can reduce process steps and lower costs.

[0068] Embodiments of the present invention also provide a power semiconductor device.

[0069] Please refer to Figure 10 This is a schematic diagram of the structure of a power semiconductor device according to an embodiment of the present invention.

[0070] The power semiconductor device includes: a substrate; a second-type doped body region 301 located within the substrate; two first-type doped regions 501 located within the body region 301, wherein the channel lengths from the first-type doped regions 501 to the edges of the body region 301 are the same; and a gate structure 910 located on the substrate between adjacent body regions 301.

[0071] The substrate includes a semiconductor substrate 101 and a first-type doped epitaxial layer 102 located on the semiconductor substrate 101 and formed on the semiconductor substrate 101.

[0072] The gate structure 910 covers the channels on both sides. Since the channels have the same length, the threshold voltages of the VDMOS cells on both sides of the gate structure 910 are consistent. The gate structure 910 overlaps with the first type doped regions 501 in the body regions 301 on both sides, leaving a certain alignment deviation margin for the gate structure 910. Preferably, the overlap length can be 0 to 0.7 μm, more preferably 0.3 μm to 0.7 μm, for example 0.5 μm.

[0073] In this embodiment, the power semiconductor device is a depletion-type power semiconductor device, and an inversion layer 701 is further formed between the channel and the gate structure 910. Specifically, in this embodiment, the power semiconductor device is an N-channel depletion-type VDMOS device, the first type of doping is N-type doping, and the second type of doping is P-type doping.

[0074] The gate structure 910 includes a gate dielectric layer 901 and a gate located on the surface of the gate dielectric layer 901.

[0075] A second type doped region 602 is also formed between the two first type doped regions 501 within the same bulk region 301, which can reduce the base bias resistance of the parasitic transistor in VDMOS, suppress the conduction of the parasitic transistor, and thus improve the secondary breakdown effect.

[0076] The power semiconductor device further includes an interlayer dielectric layer covering the gate structure 910 and the substrate, and a conductive structure 1002 connecting the first type doped region 501 and the second type doped region 602 through the interlayer dielectric layer 1001, the conductive structure 1002 serving as a source connection structure.

[0077] The power semiconductor device also includes a drain connection layer (not shown in the figure) located on the back side of the semiconductor substrate 101.

[0078] The power semiconductor device is formed using the power semiconductor device formation method described in the above embodiments, which will not be repeated here.

[0079] The power semiconductor device has the same channel length for each VDMOS cell, resulting in good turn-on consistency and a concentrated threshold voltage distribution.

[0080] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, such as the combination of technical features between embodiments, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A method for forming a power semiconductor device, characterized in that, include: A first-type doped substrate is provided, the substrate comprising a peripheral region and a core region; A first patterned mask layer with a first opening is formed on the surface of the substrate. The first patterned mask layer is made of a hard mask layer material. The formation of the first patterned mask layer includes: forming a field oxide layer that simultaneously covers the peripheral region and the core region; patterning the field oxide layer, and while forming the first hard mask layer with the first opening on the surface of the core region, forming a patterned field oxide layer on the peripheral region to serve as an isolation structure for the peripheral region. A self-aligned implantation process is used to perform a first ion implantation and diffusion treatment on the substrate along the first opening to form a second type of doped bulk region, and the laterally diffused bulk regions are all the same size below the first patterned mask layer. A second patterned mask layer is formed within the first opening, and a second opening is provided between the second patterned mask layer and the first patterned mask layers on both sides; A self-aligned implantation process is used to perform a second ion implantation and diffusion treatment on the substrate along the second opening to form a first type of doped region located in the bulk region, and the first type of doped region has the same length below the first patterned mask layer. Remove the second patterned mask layer; A second type of doped region is formed within the body region between the first type of doped regions, and a PN junction isolation structure is formed between the second type of doped region and the first type of doped region. The doping concentration of the second type of doped region is greater than the doping concentration of the second type of doped body region, so as to reduce the resistance of the second type of doped region between the second type of doped region and the first type of doped substrate. After removing the first hard mask layer on the surface of the core region, the substrate surface is depleted by first type of doped ions to form an inversion layer; After the inversion layer is formed, a gate structure is formed on the substrate between adjacent body regions, the gate structure overlapping with the first type of doped regions in the body regions on both sides.

2. The method for forming a power semiconductor device according to claim 1, characterized in that, Also includes: A conductive structure connecting the first type of doped region and the second type of doped region is formed on the substrate.

3. A power semiconductor device, characterized in that, Formed by any one of claims 1 to 2, comprising: A type-first doped substrate; the substrate includes a peripheral region and a core region; The core area includes: A second type of doped bulk region located within the substrate; Two first-type doped regions are located within the body region, and the channel lengths from the first-type doped regions to the edge of the body region are the same, with an inversion layer formed on the surface of the channel; A second type of doped region located between two first type doped regions within the same bulk region; Gate structure located on a substrate between adjacent body regions; The gate structure overlaps with the first type of doped regions in the body regions on both sides; The doping concentration of the second type doped region is greater than the doping concentration of the second type doped bulk region, so as to reduce the resistance of the second type doped region between the second type doped region and the first type doped substrate; A patterned field oxygen layer is formed on the outer region, serving as an isolation structure for the outer region.

4. The power semiconductor device according to claim 3, characterized in that, Also includes: A conductive structure connecting the first type of doped region and the second type of doped region.

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