Timer used to create a stable on-time

Abstract

To create a stable on-time, the timer (120) may have a reference voltage source (650) and an input voltage source (602). The voltage sources (650, 602) provide voltages that can be applied to various circuit components such as capacitors, inductors, resistors, diodes, transistors, or other components. The reference voltage source (650) can also be modified by a transistor (680) coupled as a diode before being seen by the input of the timer comparator (654). The circuit-modifiable voltage sources (650, 602) are compared by the timer comparator (654) and then output as a timer control signal (661). The timer control signal (661) can control the voltage converter or the switching of said voltage converter.

Description

Background Art

[0001] The boost converter has issues in creating a stable on-time signal. The boost converter has a boost mode, in which V... out Boosted to a voltage greater than V in The value of V. However, during buck mode operation of the boost converter, V out It can be less than V in This leads to V in and V max The equal conditions cause the comparison to produce zero or empty signals and lead to control errors in any coupled switches. To overcome this problem, a fixed on-time is generated to reconstruct the on-time of the buck mode. This fixed on-time can be generated by a hard-wired RC network with a fixed propagation time. However, these hard-wired RC networks lack accurate timing and a stable frequency, and may react to load variations or the thermal characteristics of the circuit or load. Therefore, these hard-wired or fixed-frequency timers can lead to frequency runaway, making it impossible to control or operate the boost converter. Summary of the Invention

[0002] Examples described include timers capable of being coupled to voltage or current converters. Timers can include various circuit elements such as transistors, diodes, resistors, capacitors, amplifiers, comparators, logic chips, or inductors.

[0003] In one aspect, the described example can be directed to a timer coupled to a boost converter. The timer can respond to changes in the boost circuitry by compensating for the characteristics of the circuit elements of the boost converter. These elements can have thermally dependent and load-dependent properties.

[0004] In another aspect, the described example could be for a timer that provides a fixed or quasi-fixed frequency, which would allow the timer to generate control signals. These control signals could then be used by a voltage converter. Attached Figure Description

[0005] Figure 1 A schematic diagram of a current-controlled DC-DC boost converter is shown.

[0006] Figure 2 A graphical timeline of inductor voltage and current is shown.

[0007] Figure 3 The peak and valley current waveforms are shown.

[0008] Figure 4 A schematic diagram of the timer circuit for the boost converter is shown.

[0009] Figure 5The timing diagram of the timer voltage is shown.

[0010] Figure 6 A schematic diagram of a timer used in conjunction with a boost converter is shown.

[0011] Figure 7A The timer voltage in the old buck mode is shown.

[0012] Figure 7B The timer voltage in boost mode is shown.

[0013] Figure 7C The timer voltage in the new buck mode is shown.

[0014] Figure 7D The timer signal is shown.

[0015] Figure 8 A method for operating a boost converter with a quasi-fixed timer is shown.

[0016] Figure 9 A method for operating a quasi-fixed timer is shown. Detailed Implementation

[0017] exist Figure 1 A schematic diagram of a current-controlled DC-DC boost converter 100 is shown. The converter can be identified by two control loops 130 and 140. The external control loop 130 can be a voltage loop, which consists of a resistive feedback voltage divider and / or a voltage divider and a gm stage (or a transconductance amplifier stage or a gain stage), wherein the output can be a low-bandwidth signal V. comp The purpose of the external control loop 130 is to control the voltage variation of the converter 100. The internal current loop 140 can control the current variation of the converter 100. The internal current loop 140 includes an ideal current measurement component and can display its information V at the main current comparator 116. meas With the output V of the voltage control circuit comp A comparison is made to generate turn-on signals for two transistors or control switches 105 and 104. Using this method, the output voltage and current of the boost converter are controlled via two loops 130 and 140 to maintain stable steady-state operation of the boost converter.

[0018] Input voltage source (V inInput voltage source 102 can be the initial voltage source of boost converter 100, but examples may have more than one input voltage source. For example, multiple batteries placed in series or parallel can provide the input voltage. An inductor 103 can be connected after input voltage source 102, which can provide some (if not all) energy storage for conversion by boost converter 100. In one example, input voltage source 102 can be coupled to timer 120 or a logic block. Inductor 103 can be coupled to two switches 105 and 104, which allow control of boost converter operation. Voltage nodes 106A and / or 106B (collectively referred to as 106) after the switches can carry the output voltage (V) of the switches. out and the voltage or V seen at the load. load In at least one type, V out and V load They are equal or carried on the same node, while other alternative examples may have them in V. out and V load Additional circuit elements (such as diodes, resistors, capacitors, inductors, or transistors) between the carrying nodes.

[0019] Smoothing capacitor 107 and / or load resistor (R load 108 can be connected to voltage nodes 106A and / or 106B. Voltage node 106A can be directly coupled to comparator 116 via a measuring device, or indirectly coupled (such as a sensing device). In one embodiment of this disclosure, current can be sensed at voltage node 106A. In other examples, the sensed current can also be converted to voltage by circuit components before being coupled to comparator 116. However, voltage nodes 106A and 106B can also be directly coupled and can be considered as the same node. A smoothing capacitor allows balancing of the voltages supplied by switches 104 and 105. The voltage divider includes two resistors 109A and 109B connected in series. Resistor 109A has a first resistance Rfb1, and resistor 109B has a second resistance Rfb2. In one example, if a fixed value exists for the desired output voltage, a fixed resistor or a set of resistors can be used. In another example, when the output voltage can be selected from multiple values, a fine-tuning resistor or potentiometer can be used for one or two resistors 109A and 109B.

[0020] Voltage divider 152 provides a feedback voltage (V) that can be fed into the first input of amplifier 112. fb 110. In one embodiment, amplifier 112 may be an error amplifier. The second input of amplifier 112 may be a reference voltage (V). ref 111. The reference voltage 111 can also be the input voltage or the maximum voltage (V). maxNode V comp The frequency compensation capacitor 115 at 114 is used to ensure the stability of the control loop of the external voltage control loop before it is fed into the first input of comparator 116. In other examples, comparator 116 may be a current comparator that compares the sensed current from node 106A with the current output from amplifier 112. The comparator may also include a voltage comparator, a current comparator, an operational amplifier, an amplifier, a transconductance amplifier, logic circuitry, or a combination thereof or interchangeable with them.

[0021] Comparator 116 may have at least two inputs (positive or non-inverting input and negative or inverting input) and can compare measured voltages (V). meas )113 and comparison voltage (V comp )114. The voltage along the measured voltage line 113 can be voltage node 106, or it can come from a measuring device (such as a current sensor or from the sensed I). meas Current generates V meas The comparator 116 measures the voltage of the other similar devices. The output of comparator 116 can then be directly fed to switches 104 / 105, or a gate driver circuit 118 may include buffers, delays, and / or logic circuitry to delay or manipulate control signals to switches 104 and 105. The coupling between comparator 116 and / or gate driver circuit 118 may also include a timer. In another configuration, timer 120 may have a maximum terminal voltage (V) coupled to the comparison voltage. max ), and / or have a timer input voltage node coupled to the input voltage source 102.

[0022] In other examples of this disclosure, the output of comparator 116 may be connected to logic circuit 119. Logic circuit 119 may include state machines, protection circuits, voltage or current regulation circuits, buffers, delays, and / or other logic circuits to assist in controlling one or more transistors and / or one or more switches 104 / 105. Logic circuit 119 may also have an input (T) connected to timer 120. on 161 and / or output 121 for a reset signal. The reset signal can be used by a timer. In one embodiment of this disclosure, the reset signal 121 corresponds to when switch or transistor 105 is turned off or when switch or transistor 104 is turned on. The output of logic circuit 119 can be coupled to gate driver circuit 118. Gate driver circuit 118 can include separate drivers for individual switches and / or transistors, or can have a single driver for multiple switches and / or transistors. In one embodiment of this disclosure, gate driver circuit 118 can also have a driver for V generated by timer 120. max Signal 150 V maxInput. In at least one type, V max Signal 150 is the larger of the voltage at input voltage source 102 or voltage node 106.

[0023] Timer 120 can generate a corresponding on-time signal (T) to input 161 of the voltage converter based on the desired operation or operating mode. on The timer can use the coupling between the input voltage source 102 and the voltage node 106 as an input. In one configuration, the timer's output will be T. off Alternatively, it can be an off-time signal or an output. In one configuration, timer 120 can generate an on-time signal corresponding to the on-time of buck mode operation.

[0024] In at least one embodiment, control switch 104 is a PMOS or P-type MOSFET transistor, and control switch 105 is an NMOS or N-type MOSFET transistor. Alternatively, switches 104 and / or 105 may be PMOS, NMOS, or a combination of a PMOS transistor and an NMOS transistor.

[0025] exist Figure 2 The inductor current and voltage waveforms 200 of the boost converter are shown. These waveforms can be generated, for example, when control switch 105 is turned on and the inductor is coupled to ground. The voltage and inductor current slopes across the inductor are calculated as shown in equation (1). To discharge the inductor, control switch 105 can be turned off and control switch 104 can be turned on to connect the inductor to the output. As shown in equation (2), because V in the boost converter out >V in The corresponding inductor voltage and current slopes across the inductor were calculated. This was done during startup or at the output voltage V. out It may be less than the input voltage (V) in In applications where boost converters operate in so-called buck mode, buck mode operation indicates that one of the boost converter's V... out <V in Steady-state operation.

[0026] V L =V in >0,

[0027] V L =V in -L out <0,

[0028] The horizontal axis or time axis 226 may include a separation indicator 230 to distinguish between boost mode period 228 and buck mode period 229. The inductor voltage axis 225 shows the upper voltage 231 and / or lower voltage 232. In boost mode operation, the upper voltage 231 may be the input voltage (V... in Furthermore, the lower voltage 232 can be the input voltage (V). in Subtract the output voltage (V) out In buck mode operation, the upper voltage 231 can be the input voltage (V). in And the lower voltage 232 can be the threshold voltage (V) T The inductor current axis 227 indicates when the boost mode rise current 233, boost mode fall current 234, buck mode rise current 235, and / or buck mode fall current 236 occur. The boost mode rise current can be characterized as the input voltage (V). in Divide by the inductor value L. Similarly, the boost-mode drop current can be characterized as the input voltage (V). in Subtract the output voltage (V) out The combination of ) is divided by the inductor value L. For buck mode, the rise current 235 can be characterized as the input voltage (V). in Divide by the inductor value L, and the decreasing current 236 can be determined by the threshold voltage (V) of the corresponding control switch. T Divide by the inductance value L to characterize it.

[0029] In buck mode, inductor discharge can be coupled to V in This is accomplished by the gate of control switch 104, which carries the node. With the gate of control switch 104 coupled to the highest voltage carrying node, the transistor remains off and behaves as a passive diode. Once control switch 105 is turned off and begins to become high impedance, inductor current charges the inductor. In this case, the control switch impedance increases until it exceeds the threshold voltage (V) of control switch 104. T To reconnect control switch 104. Figure 2 The voltage and current waveforms during boost and buck modes are summarized. In buck mode, the control switch voltage can be calculated as a function of the input voltage and the threshold voltage, as shown in equation (3). As shown in equation (4), the obtained inductor voltage can be the threshold voltage (V). T The function of ). Using the negative voltage across the inductor, the current can be reduced by turning off the control switch 104 during buck mode operation using equation (5).

[0030] V sw =V in +V T (3)

[0031] V L =V in -(V in +V T )=-V T <0. (4)

[0032]

[0033] Generally, there are two methods to apply at the boost converter. Figure 1 Ideal current measurement is possible. First, measurement can be performed across the low-side transistor or control switch 105. The increased inductor current slope can be measured, and the peak inductor current can be compared with the error amplifier output signal. The converter can be within peak current control. Second, measurement can be performed across the high-side transistor or control switch 104. The decreased inductor current slope can be measured, and the valley inductor current can be compared with the error amplifier output signal. The converter can be within valley current control.

[0034] Figure 3 This is a waveform diagram 300 showing the peak and valley currents. A vertical axis or current axis 340 can be used to provide a reference for current evaluation or measurement. A horizontal axis or time axis 341 shows the passage of time relative to the data shown or plotted. The vertical axis or current axis 340 may have an upper current 342 and a lower current 343. The upper current 342 or lower current 343 can be a threshold current value, such as a comparison current value (I0). c o mp ) or measure current value (I meas In at least one type, it is possible to Figure 1 Sensing or measuring I at voltage node 106A meas In other examples, cross-... Figure 1 The voltage of the switch or transistor 164 is used to measure I. meas Electric current.

[0035] In peak current mode 344, the on-time current value 346 can be I. meas Where the comparison or threshold current I comp Trigger turn-off time 348 and / or the generated current slope 348. In valley current mode 345, the turn-off time current value 347 can be I. meas Where the comparison or threshold current I comp End of I meas Slope 347. The generated current slope and / or turn-off time 348 can be activated until a specific value or time period is reached, after which the turn-off time or I can be activated. meas Current slope.

[0036] The input and output voltage ranges of the boost converter determine whether peak current control or valley current control is used. The converter's duty cycle D can be calculated from both the input and / or output voltages and can be indicated as an on-time value, as shown in equation (6).

[0037]

[0038] Converter on-time (T) on The time period (T) is defined as the time during which the inductor can be charged and the control switch 105 can be turned on. The complete switching period (T) is defined as the time during which the control switch 104 can be turned on to discharge the inductor. s ) Determined by the connection time t on and shutdown time t off =T s -T on Composition. Regarding a given V in each application. in and V out Within the range, converter control can be either peak current control or valley current control. When the maximum input voltage V... in With minimum output voltage V out When the difference between them is large, the connection time t on It can be extended and can be controlled using peak current. When the maximum input voltage (V) in ) and minimum output voltage (V out When the difference between the two is small, the connection time t on It can be very short and can use valley current control. Once the current control method is selected, the corresponding portion of the switching period must be correctly set (which may not be under active current control). In a fixed-frequency system, the system clock resets the switching period T. s To restart converter operation. In quasi-fixed frequency systems, a constant timer signal resets converter operation. Therefore, peak current controlled converters in quasi-fixed frequency systems require a constant t... off A timer is used to generate the missing inductor discharge slope. The valley current-controlled converter requires a constant t. on A timer is used to generate the missing converter on-time t. on Or the charging slope of the missing inductor.

[0039] Furthermore, the current in the inductor can continue to rise while the transistor remains off, until at a specific point, the current causes a connection across the transistor, resulting in a voltage that can be interpreted as V TThe voltage drop can also cause a voltage drop across the load, resulting in increased power consumption and potentially more problems in the system. This is because the current across the load cannot be properly compensated for the appropriate on-time or generated by a fixed timer. The fixed timer in the problem illustrated generates on-time before or after the desired point and can lead to frequency runaway.

[0040] Figure 4 This is an example of a schematic circuit for a boost converter timer 400. Like all circuits, this circuit can be grounded via circuit ground 401. Maximum voltage (V) max 450 can be connected to ramp capacitor 451 and / or ramp resistor 452, which can provide a calculated slope value. Similarly, reset switch 453 can be controlled by a control signal and allows input from V... max The node bypasses the ramp capacitor 451 and / or ramp resistor 452 to reach the first comparator input. The timer comparator 454 can access the input from V. max The reference side 450 receives the input and may include a ramp capacitor 451 and / or a ramp resistor 452, and may also include other circuit elements. Furthermore, the timer comparator 454 may receive the timer input voltage (V) at the second comparator input. in 455 may include a current source 456 for load regulation control and / or a smoothing capacitor 457, and may also include other circuit elements (such as transistors 462 / 463). The output of timer comparator 454 may be directed to digital logic block 460, which may have multiple inputs, such as a signal from buck-mode RC delay 458, a fixed minimum on-time, or min T. on 459, and / or the output of the timer comparator. Then, digital logic block 460 can output an on-time value 461 to provide a control signal to the converter.

[0041] The goal of the timer is to ensure that the converter is at time t on When generating missing t under control (peak current mode) off , or when the converter is at t off When generating missing t under control (valley current mode) on In peak current control, the reconstructed duty cycle, as shown in equation (7), can be the off-time of the peak current control converter. Valley current control, on the other hand, can have an on-time, as shown in equation (8).

[0042]

[0043]

[0044] Capacitor C rampIt can be coupled to V max When the timer is activated, the reset switch can be turned on, and it works in conjunction with V. max Proportional current I C With a given slope, make C ramp Discharge. When voltage V C Reaching input voltage V in At that time, the comparator can be triggered and can reach the on-time t. on Duty cycle. The capacitor equation for the on-time can be shown in equation (9).

[0045]

[0046] However, for higher load currents, system efficiency and switching losses require longer turn-on times. In practical converters, the effective input voltage source (V in Charging the inductor, and can be Figure 1 The on-resistance of control switch 105 and the DC inductor current I L The effective on-time is a function of the inductor current. In other words, a longer on-time must overcome a lower effective input voltage to maintain frequency stability. Therefore, as shown in equation (10), the effective on-time t increases with the increase of the inductor current. on,eff It can be higher than t on Therefore, the timer uses a controlled current circuit I at the positive input of the comparator. loadreg Make the input voltage (V) in Reduce the current drop across resistor R.

[0047]

[0048] Figure 5 This is a timing diagram 500 that can be shown as the input waveform of the timer comparator 454. The voltage axis 570 can be used to show the operating windows for various voltages, such as the upper voltage (V). max )572 or lower voltage (V in 573. V max It can be described as being greater than the input voltage (V) in ) output voltage (V out The horizontal axis or time axis 571 shows the corresponding time period (T) of the voltage as shown by the vertical axis 570. period ).

[0049] First shutdown time or T off Part 574 and the second shutdown time (T) off Part 576 is mismatched, similarly, the first connection time (T) on Time period 575 and second connection time (T) on577 is mismatched. Off-time portions 574 and / or 576 indicate when the timer comparator can be turned off, while on-time portions 575 and / or 577 indicate when the timer comparator can be turned on during the sampling phase. In at least one embodiment of this disclosure, on-time portion 575 may indicate the input of the comparator under no-load conditions. However, when the comparator may be under load (such as in off-time portion 576 and / or on-time portion 577), the input value or waveform changes. The threshold voltage drop may be indicated by 578, where this voltage drop may be expressed as the voltage across resistor DS multiplied by the load current I. load Or load current compensation.

[0050] Figure 6 This is a schematic diagram of a timer 600 for use with a boost converter. The timer 600 can be implemented as such... Figure 1 The circuit for timer 120. Timer 600 is coupled to the V of the boost converter. in Node 602 and V out Node 606. Recalling the boost operation, V out Greater than V in V out Node 606 is coupled to the high (non-inverting) side of the first comparator 683, while V in Node 602 is coupled to the low (inverting) side of the first comparator. Comparator 683 detects V. out and V in The relative value of V during boost mode. out Greater than V in When the signal is high, the comparator produces outputs that open or close switches 684A and 684B, respectively. The comparator typically produces a binary output of 1 (or a voltage such as 3V, 3.3V, or 5V) when the high signal is greater than the low signal, and zero (or a negative voltage) otherwise. Switches 684A and 684B are also coupled to V... out Node 606 and V in Node 602. Therefore, during boost mode, switch 684A is closed, and switch 684B remains open. In this case, V max equals V out When V in Greater than V out During buck mode, the first comparator 683 generates a low signal through the inverter 679. The inverter creates a high signal output for switches 684A / 684B, causing switch 684B to close and switch 684A to open. In this case, V max equals V in In at least one version, comparator 683 and switches 684A and 684B are used as voltage selection circuits.

[0051] V max Node 650 can be coupled to ground 601 via a resistor, switch, transistor 662 / 663, or other circuit elements. In at least one configuration, transistor 662 / 663 is a current mirror. Ramp capacitor 651 and / or ramp resistor 652 can also be coupled to the maximum voltage node 650. Ramp capacitor 651 and / or ramp resistor 652 can be bypassed by reset switch 653. Ramp capacitor 651 and / or ramp resistor 652 provide the calculated slope value to second comparator 654. Reset switch 653 may include a reset signal 621, which can be provided by circuit elements coupled to the converter or from other logic circuitry. The outputs of ramp capacitor 651 and / or ramp resistor 652 and / or reset switch 653 can be fed to the first input of second comparator 654, also referred to as a timer comparator.

[0052] The second comparator 654 is used to generate a stable T. on The signal required by 661. The low (inverting) side input of the second comparator 654 is selectively coupled to the maximum voltage node 650, and the high (non-inverting) side input is selectively coupled to V via switch 681. in 602 or V in Subtract the voltage drop across transistor 680. As will be discussed in more detail below, during boost mode, switch 681 closes, thereby reducing V... in Coupled to the high side of the second comparator 654. In buck mode, switch 681 is on and V in Coupled to transistor 680, thus generating a voltage drop (V T (or threshold voltage). Therefore, in buck mode, the voltage V in -V T Coupled to the high side of the second comparator 654. In boost mode, V max It will always be greater than V. in More importantly, in buck mode, V max It will always be greater than V. in -V T .

[0053] In at least one embodiment, the input voltage node 602 may be coupled to a resistor and / or to a transistor 680 that may be configured as a diode, and to a switch 681. The switch 681 may have an input 660 configured to control the switch; in at least one embodiment, the switch may be coupled to the output of a comparator 683 or to other signals or terminals that indicate when the voltage converter is in boost or buck mode. The transistor 680 may be configured as a diode, and during boost mode operation, the switch 681 may be closed to bypass the diode-configured transistor 680. In buck mode operation, the switch 681 is open, and the current flowing through the diode-connected transistor 680 generates V0. t Voltage drop. The input of comparator 654 can be directly or indirectly coupled to the input voltage node 602 and / or the maximum voltage node 650.

[0054] Transistor 680 and / or switch 681 may be coupled to a load-regulated current source 656 and / or a buck-mode controlled current source 682 or a transistor bias-controlled current source, all of which may be coupled to ground 601. In one embodiment, transistor 680 and / or switch 681 is biased by the load-regulated current source 656 and / or the buck-mode controlled current source 682 so that transistor 680 remains in the saturation region and / or active region when switch 681 is turned on. In at least one example, transistor 680 and / or switch 681 may be a PMOS or p-type metal-oxide-semiconductor field-effect transistor. In alternative examples, transistor 680 and / or switch 681 may be an NMOS or n-type metal-oxide-semiconductor field-effect transistor, or a combination of a PMOS and an NMOS transistor.

[0055] The smoothing capacitor 657 can also be used to provide some stability to the signal supplied to the second input of the comparator 654. The smoothing capacitor can be coupled on one side to the second input of the comparator 654, transistors 680 and / or 681, the load-regulated current source 656 and / or the buck-mode controlled current source 682, while on the other side, the smoothing capacitor 657 can be coupled to ground 601. The output of the comparator 654 can generate a signal for T. on T of node 661 on The signal is provided to the boost converter. Figure 6 The timer shown may operate in an advantageous manner. Operation in boost mode can be combined with the above description and... Figure 2 and Figure 3 The same applies as shown. However, in buck mode, an additional diode voltage drop can be introduced before comparator 654 to match the diode voltage drop of the inductor current discharge slope. The diode voltage drop at the positive or second comparator input makes V in Decrease V TPressure drop. Therefore, V max -(V in -V T ) = V T During buck mode, the capacitor discharge is matched with the inductor current discharge, as shown in equation (11). While in boost mode, the capacitor equation can still be a function of the input voltage and / or output voltage, as shown in equation (12). In buck mode, however, in equation (13), the turn-on time can be a function of the threshold voltage.

[0056]

[0057]

[0058]

[0059] Buck mode on-time t on,down Matching the inductor discharge slope, and enabling the reconstruction of the correct frequency. When the converter is driven with a higher load current, the voltage drop across the implemented timer buck mode diode matches the increased voltage drop of the passive high-side power transistor diode. This can be achieved by regulating the load current I. loadreg This ensures that the current is a function of the output current and is taken from the converter error amplifier. Therefore, frequency runaway can be avoided. Figure 7A , Figure 7B and Figure 7C The timer signals in boost mode and buck mode are summarized.

[0060] Figure 7A , Figure 7B and Figure 7C The timer voltages are shown under various operating conditions, such as the old buck mode 700A, boost mode 700B, and new buck mode 700C. The vertical axis or voltage axis 785A, 785B, 785C (collectively referred to as 785) allows for the indication of various voltage values ​​based on graphical information. The horizontal axis or time axis 786A, 786B, 786C (collectively referred to as 786) allows for the indication of various actions associated with the vertical axis 785 corresponding to specific time periods. In the old buck mode 700A, the maximum voltage (V... max It can be equal to the input voltage (V) in This results in a fixed voltage of 787 V. in or V max If the voltage remains unchanged, the on-time value will also be fixed. Therefore, the on-time will not be triggered at any time.

[0061] Boost mode 700B allows when the maximum voltage (V) max ) greater than the input voltage (V in At this time, the maximum voltage (V)max ) can be the output voltage (V) out Operation of ). Maximum voltage 788 and / or input voltage (V) in 798 is the baseline value of voltage waveform 799 during boost mode operation. Voltage waveform 799 varies between maximum voltage 788 and / or input voltage 789, and the off-time (T) occurs when voltage waveform 799 drops to a specified value (such as input voltage 789). off Time period 793 begins at the moment indicated by the dashed line 790. The off-time period 793 can best be described in boost mode 700B as the period during which the timer voltage can be at its maximum. On-time (T...) on Period 794 can be best described as the period triggered at time point 791, indicated by the dashed line, during which the voltage waveform 799 drops at a specified time or trigger event. The voltage waveform 799 will continue to drop until it drops to a specified value or trigger event, such as the trigger point (dashed line 792) that will allow the shutdown time period to begin.

[0062] The buck mode operation of the 700C can be best described by its maximum voltage (V). max It can be equal to the output voltage (V) out Larger input voltage (V) in The operating period of the voltage 795 can be best described as the input voltage (V). in Subtract the threshold voltage (V) T The buck mode voltage waveform 798 can vary between a maximum voltage and a lower voltage 795. The buck mode off-time period 796 can be when the buck mode voltage waveform 798 corresponds to the maximum voltage for a period of time, or until a specific event triggers a change in the buck mode voltage waveform. When a change is likely triggered or the time period expires, the buck mode voltage waveform 798 enters the buck mode on-time period 797. The buck mode on-time period 797 can be described as when the buck mode voltage waveform 798 drops from the maximum voltage to the lower voltage 795 based on a specific time period or a triggering event. The buck mode voltage waveform 798 can drop to a specific value, such as the input voltage (V). in Subtract the threshold voltage (V) T The voltage is 795.

[0063] Figure 7D The timer signal 700D is shown. The timer signal 700D may include an on-time (T... on ) Period 797 or shutdown time (T) off Time period 796. The timer signal strength can be viewed by referring to the vertical axis or timer signal axis 785D and the horizontal axis or time axis 786D. These high and low time periods also correspond to... Figure 7A , Figure 7B and Figure 7C T on 797 and T off 796.

[0064] Figure 8 A method 800 for operating a boost converter with a quasi-fixed timer is illustrated. Step 802 illustrates applying an input voltage to an inductor or an inductor input node. The DC-to-DC boost converter relies on an inductor that can be charged and discharged to generate a voltage boost for a load. The load can be resistive, capacitive, or inductive. Step 804 illustrates controlling the inductor voltage via at least one switch. Switches can be used to charge and discharge the inductor. Step 806 illustrates connecting the output of the inductor voltage or an output voltage node or an output node to at least one load. The inductor voltage can be coupled to at least one load via at least one switch that controls the inductor voltage. During inductor charging, at least one switch can be coupled to ground, or coupled to ground via other circuit elements. To discharge the inductor, at least one switch can be decoupled from ground or coupled to the load and / or a smoothing capacitor or a charging capacitor to generate a load voltage. Step 808 illustrates receiving the load voltage through at least one amplifier input. Amplifiers and / or comparators can be used as part of a control or control circuit system to ensure that the load voltage can be maintained within a set or given value, or to respond to changing load conditions. The amplifier input can also be fed through a feedback resistor, voltage divider, and / or adjustable resistor to create a comparable voltage level. Step 810 illustrates the output generated from a timer circuit coupled to a voltage converter. The timer can be used to control at least one switch of the converter. The timer can also include multiple voltage inputs, resistors, capacitors, and / or other circuit elements. In one type, the timer can have a sensed or measured voltage input and / or a reference voltage input.

[0065] In another example, the timing may include a voltage selection or maximum voltage circuit. The maximum voltage circuit may include the input and output voltages from the voltage converter at the input and output voltage nodes, respectively coupled to the input and output voltage nodes, and / or a comparator or a first comparator for comparing the input and output voltages. The at least two switches may be controlled by the output of the comparator to generate a maximum voltage at the maximum voltage node or terminal of the timer.

[0066] For example, the comparison voltage can be used as a reference voltage for the timer, and can be a sensed or measured voltage that is measured or sensed before or after at least one switch of the converter. Step 812 illustrates operating or switching at least one switch based on the output from the timer circuit or the output of at least one comparator. In other examples, the output signal of the timer or the output signal of the comparator can be used to control at least one switch of the converter. The output signal of the timer can be an on-time signal. The switch may be controlled in a manner that maintains the converter in a specified operating state, such as boost mode, buck mode, peak control, or valley control.

[0067] Figure 9 A method 900 for operating a quasi-fixed timer is illustrated. Step 902 illustrates measuring at least one operating voltage of the timer. The operating voltage can be measured or sensed, and in one embodiment of this disclosure, the operating voltage can be measured before or after at least one control switch. The measured voltage can also be considered a measured voltage or a sensed voltage. Step 904 illustrates receiving at least one reference voltage of the timer. The reference voltage input of the timer can be a voltage provided from a converter and / or other circuit elements. In other examples, the reference voltage can be a comparison voltage generated from the converter via a comparator. The converter comparator can generate the comparison voltage based on an input from a load voltage and a fixed or varying reference load voltage. Step 906 illustrates controlling at least one bypass switch of the timer. The bypass switch can also be a reset switch, which can be controlled by a reset signal received at a reset terminal. The reference voltage can have various circuit elements or components connected thereto, including a ramp capacitor or ramp resistor that can be connected in parallel with at least one reset switch. At least one reset switch can be controlled by a signal from the timer circuitry or a signal generated from the converter. The reset switch can be used to generate a direct path from the reference voltage to the timer comparator.

[0068] Step 908 illustrates biasing at least one measuring voltage transistor or sensing voltage transistor with at least one measuring voltage or sensing voltage to create a reduced voltage at the first comparator node. To ensure stable operation of the timer, at least one transistor may be introduced between the measured or sensed voltage input and the timer comparator. The at least one transistor may be two transistors coupled to form a diode (such as a PMOS diode). Alternatively, the measured or sensed voltage will be the input voltage of the converter, and the at least one transistor will be two transistors, one connected in a diode configuration, and the other transistor acting as a bypass switch. In boost mode, the diode-configured transistor is bypassed to prevent changes in the boost mode voltage, but in buck mode, the input voltage and the corresponding current flow through the diode-configured transistor to generate a voltage drop. At least one transistor creates a voltage drop from the measured or sensed voltage to allow a voltage difference to appear when compared by the timer comparator with a reference voltage. The voltage drop may result in a reduced voltage, which can be seen at the comparator input. Step 910 illustrates applying at least one operating voltage across at least one ramp capacitor and at least one ramp resistor to create a ramp voltage at the second comparator node. At least one ramp capacitor and at least one ramp resistor can be used to create a fixed ramp value for comparison by the timer comparator. In other examples of this disclosure, the ramp value can match the desired waveform or voltage or current level desired by the converter. Step 912 illustrates comparing a decreasing voltage at the first comparator node and a ramp voltage at the second comparator node. The timer comparator can be used to compare a reference voltage and a measured or sensed voltage. Either the reference voltage or the measured or sensed voltage can also be modified by circuit elements or components preceding the comparator. The reference voltage and the measured or sensed voltage may not be the exact voltages compared by the comparator because various circuit components or components can cause variations or losses in signal and / or signal strength. Step 914 illustrates the output timer signal. The output of the timer comparator can be a control signal that can be used to control the switches of the converter. The output of the timer comparator can be modified or compared with other additional timers or digital logic circuits having multiple inputs and outputs. However, it should be noted that in other examples of this disclosure, the timer output signal can be sent directly to the control elements of the converter. The timer can be implemented in a standalone chip or as part of a voltage converter chip, and can include additional inputs, outputs, or terminals to incorporate additional circuitry or controls.

[0069] Modifications to the described embodiments are possible within the scope of the claims, and other embodiments are also possible.

Claims

1. A timer comprising: A voltage selection circuit coupled to a first terminal, a second terminal, and a third terminal, wherein the voltage selection circuit is configured to receive a first voltage at the first terminal and a second voltage at the second terminal, generate a first control signal by comparing the first voltage and the second voltage, and output the higher of the first voltage and the second voltage at the third terminal; A first comparator has a first input coupled to the third terminal and a second input selectively coupled to the second terminal; A first transistor is coupled between the second input and the second terminal of the first comparator; as well as A first switch is coupled between the second input and the second terminal of the first comparator, and the first switch is controlled based on the first control signal.

2. The timer according to claim 1, wherein the voltage selection circuit comprises: A second comparator has a first input coupled to the first terminal, a second input coupled to the second terminal, and an output configured to output the first control signal; A second switch is coupled between the first terminal and the third terminal, and the second switch is controlled by a second control signal based on the first control signal; as well as A third switch is coupled between the second terminal and the third terminal, and the third switch is controlled by a third control signal that is inverted from the second control signal.

3. The timer of claim 1, comprising a current mirror having an input coupled to the third terminal and an output.

4. The timer of claim 3, comprising a capacitor coupled between the third terminal and the output of the current mirror.

5. The timer of claim 3, wherein the current mirror includes a second transistor coupled to the third terminal and a third transistor coupled to the output of the current mirror, the output of the current mirror being coupled to the first input of the first comparator.

6. The timer of claim 4, further comprising a fourth transistor coupled between the third terminal and the output of the current mirror, and having a control terminal configured to receive a reset signal.

7. The timer of claim 1, comprising a current source coupled to the first transistor.

8. A power supply system comprising: First transistor; as well as A timer coupled to the first transistor, the timer comprising: A voltage selection circuit coupled to a first terminal, a second terminal, and a third terminal, wherein the voltage selection circuit is configured to receive a first voltage at the first terminal and a second voltage at the second terminal, generate a first control signal by comparing the first voltage and the second voltage, and output the higher of the first voltage and the second voltage at the third terminal; A first comparator has a first input coupled to the third terminal and a second input selectively coupled to the second terminal; A second transistor, coupled between the second input and the second terminal of the first comparator; and A first switch is coupled between the second input and the second terminal of the first comparator, and the first switch is controlled based on the first control signal.

9. The system of claim 8, wherein the voltage selection circuit comprises: A second comparator has a first input coupled to the first terminal, a second input coupled to the second terminal, and an output configured to output the first control signal; A second switch is coupled between the first terminal and the third terminal, and the second switch is controlled by a second control signal based on the first control signal; as well as A third switch is coupled between the second terminal and the third terminal, and the third switch is controlled by a third control signal that is inverted from the second control signal.

10. The system of claim 8, further comprising a current source coupled to the second transistor.

11. The system of claim 8, further comprising logic circuitry coupled between the output of the first transistor and the first comparator.

12. A circuit for controlling a power supply system, comprising: Logic circuits; and A timer coupled to the logic circuit, the timer comprising: A voltage selection circuit coupled to a first terminal, a second terminal, and a third terminal, wherein the voltage selection circuit is configured to receive a first voltage at the first terminal and a second voltage at the second terminal, generate a first control signal by comparing the first voltage and the second voltage, and output the higher of the first voltage and the second voltage at the third terminal; A first comparator has a first input coupled to the third terminal and a second input selectively coupled to the second terminal; A first transistor, the first transistor being coupled between the second input and the second terminal of the first comparator; and A first switch is coupled between the second input and the second terminal of the first comparator, and the first switch is controlled based on the first control signal.

13. The circuit of claim 12, wherein the voltage selection circuit comprises: A second comparator has a first input coupled to the first terminal, a second input coupled to the second terminal, and an output configured to output the first control signal; A second switch is coupled between the first terminal and the third terminal, and the second switch is controlled by a second control signal based on the first control signal; as well as A third switch is coupled between the second terminal and the third terminal, and the third switch is controlled by a third control signal that is inverted from the second control signal.

14. The circuit of claim 12, wherein the timer includes a current source coupled to the first transistor.

15. A power supply method, comprising: A control signal is generated by comparing the output voltage of the voltage converter with the input voltage of the voltage converter. The higher of the output voltage and the input voltage is provided to the first input of the comparator; Based on the control signal, the input voltage is selectively coupled to the second input of the comparator via a first transistor or switch; as well as Compare the voltage at the first input of the comparator with the voltage at the second input of the comparator; as well as The comparator outputs a timing signal.

16. The method of claim 15, further comprising controlling a second transistor of the voltage converter based on the timing signal.

17. The method of claim 15, further comprising biasing the first transistor with a current source.

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