Memory device and method for operating a memory device

Abstract

A memory device and a method for operating the memory device are provided. The memory device includes: a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines; a decoder circuit including a first bias circuit inputting a first bias voltage to a selected word line, a second bias circuit inputting a second bias voltage to a selected bit line, a first switch element connected to the selected word line, and a second switch element connected between the first switch element and the first bias circuit; and a control logic configured to control the first switch element and the second switch element when a predetermined delay time has passed after the second bias voltage is input to the selected bit line. The control logic turns off the first switch element when the second switch element is turned on.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority benefit of Korean Patent Application No. 10-2019-0040369 filed on April 5, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to a memory device and a method for operating the memory device. Background Art

[0004] Memory devices using resistors include phase change random access memory (PRAM), resistive memory (ReRAM), magnetic RAM (MRAM), etc. Unlike memory devices that write data by charging or releasing charges, memory devices using resistors can use resistance changes to write or erase data. Typically, read disturbance or read failure may occur depending on the amount of charge capacitance of the selected word line of the memory device. Therefore, it is desirable to control the charge capacitance of the selected word line by adjusting the operating time of the internal circuit of the memory device. Summary of the invention

[0005] An aspect of the inventive concept is to provide a memory device capable of controlling a floating timing of a word line or an on / off timing of a switching element connected to the word line to solve read disturbance and read failure.

[0006] According to aspects of the inventive concept, a memory device includes: a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, each of the plurality of memory cells including a selection element and an information storage element, the information storage element being connected to the selection element and having a phase change material; a decoder circuit including: a first bias circuit providing a first bias voltage to a selected word line among the plurality of word lines, a second bias circuit providing a second bias voltage to a selected bit line among the plurality of bit lines, a first switch element connected to the selected word line, and a second switch element connected between the first switch element and the first bias circuit; and a control logic configured to control the first switch element and the second switch element. When a predetermined delay time has passed after the second bias voltage is provided to the selected bit line, the control logic turns off the first switch element and the second switch element, turns off the first switch element when the second switch element is turned on, or turns off the second switch element when the first switch element is turned on.

[0007] According to aspects of the inventive concept, a memory device includes: a memory cell connected to a word line and a bit line; a first decoder circuit including a first bias circuit providing a first bias voltage to the word line during a first period; a second decoder circuit including a second bias circuit providing a second bias voltage to the bit line during a second period after the first period; and a control logic configured to electrically separate the first bias circuit from the word line when a predetermined delay time has passed from the start time of the second period. The second bias voltage may have a constant positive voltage.

[0008] According to aspects of the inventive concept, a method for operating a memory device includes: providing a first bias voltage output from a first bias circuit to a selected word line connected to a selected memory cell to read data, turning on a first switching element connected to the selected word line, turning on a second switching element connected between the first switching element and the first bias circuit, providing a second bias voltage to a selected bit line connected to the selected memory cell, and turning off the first switching element when the second switching element is turned on and a predetermined delay time elapses after the second bias voltage is input, or turning off the second switching element when the first switching element is turned on and a predetermined delay time elapses after the second bias voltage is input. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0010] Figures 1 to 3 is a view schematically illustrating a memory device according to an embodiment of the inventive concept.

[0011] Figure 4 is a view schematically illustrating a structure of a memory cell included in a memory device according to an embodiment of the inventive concept.

[0012] Figure 5 is a view illustrating an operation of a memory device according to an embodiment of the inventive concept.

[0013] Figure 6 is a view illustrating an operation of a memory device according to an embodiment of the inventive concept.

[0014] Figure 7 is a circuit diagram illustrating the operation of a memory device according to an embodiment of the inventive concept.

[0015] Figure 8 is a timing diagram illustrating a read operation of a memory device according to an embodiment of the inventive concept.

[0016] 9A to 9Cis a diagram illustrating a read operation of a memory device according to an embodiment of the inventive concept.

[0017] Fig.10 is a flowchart illustrating a read operation of a memory device according to an embodiment of the inventive concept.

[0018] Figures 11 to 14 is a timing diagram illustrating a read operation of a memory device according to an embodiment of the inventive concept.

[0019] Fig.15 is a circuit diagram illustrating the operation of a memory device according to an embodiment of the inventive concept.

[0020] Figures 16 to 18 is a timing diagram illustrating a read operation of a memory device according to an embodiment of the inventive concept.

[0021] Fig.19 is a circuit diagram illustrating the operation of a memory device according to an embodiment of the inventive concept.

[0022] Fig. 20 is a timing diagram illustrating a read operation of a memory device according to an embodiment of the inventive concept.

[0023] Fig.21 is a block diagram schematically illustrating an electronic device including a memory device according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0024] Hereinafter, preferred embodiments of the present inventive concept will be described with reference to the accompanying drawings.

[0025] Figures 1 to 3 is a view schematically illustrating a memory device according to an embodiment of the inventive concept.

[0026] First reference Figure 1 , a memory device 1 according to an embodiment of the inventive concept may have a pad region 4, a circuit region 3, and a bank region 2. The pad region 4 may be a region in which a plurality of pads for inputting and outputting control signals and data are formed, and the circuit region 3 may be a region in which various circuits required for the operation of the memory device 1 are formed. In the bank region 2, a memory cell array having memory cells may be formed, and the memory cell array may be divided into a plurality of banks.

[0027] Although there are various modifications according to example embodiments, each of the plurality of banks formed in the bank region 2 may be divided into a plurality of regions again. For example, at least a portion of the plurality of regions into which each of the plurality of banks is divided may share a decoder circuit, a read / write circuit, etc. included in the circuit region 3.

[0028] The circuit area 3 may include a decoder circuit, a read / write circuit, and control logic for controlling the decoder circuit and the read / write circuit. The decoder circuit may determine at least one of the memory cells formed in the memory bank area 2 as a selected memory cell, and the read / write circuit may read data of the selected memory cell or write data to the selected memory cell.

[0029] Next reference Figure 2 , a memory device 10 according to an embodiment of the inventive concept may include a memory control circuit 20 and a memory cell array 30. The memory control circuit 20 may include decoder circuits 21 and 22, a read / write circuit 23, a control logic 24, and the like. The memory cell array 30 may include a plurality of memory cells. The decoder circuits 21 and 22 may include a first decoder circuit 21 connected to a plurality of memory cells through word lines WL, and a second decoder circuit 22 connected to a plurality of memory cells through bit lines BL. Operations of the first decoder circuit 21, the second decoder circuit 22, and the read / write circuit 23 may be controlled by the control logic 24. In an embodiment, the read / write circuit 23 may include a programming circuit that writes data to at least one selected memory cell specified by the first decoder circuit 21 and the second decoder circuit 22, and a read circuit that reads data from the selected memory cell.

[0030] Figure 3 is a diagram schematically showing the memory cell array 30. Figure 3 , the memory cell array 30 according to an embodiment of the inventive concept may include a plurality of memory cells MC. Each of the plurality of memory cells MC may be disposed at an intersection of a plurality of bit lines BL and a plurality of word lines WL. For example, each of the plurality of memory cells MC may be connected to one of the bit lines BL and one of the word lines WL.

[0031] For example, each of the plurality of memory cells MC may include a selection element SW and an information storage element VR. In an embodiment, the selection element SW may include at least one of a PN junction diode, a Schottky diode, and an ovonic threshold switch (OTS). In an embodiment, the information storage element VR may be formed of a phase change material including a chalcogenide material, a superlattice, and the like. For example, the information storage element VR may include a phase change material capable of undergoing a phase change between an amorphous phase and a crystalline phase depending on heating time and temperature. The information storage element VR and the selection element SW may be connected in series to each other.

[0032] The memory control circuit 20 may perform a phase change of a phase change material of an information storage element VR included in each of a plurality of memory cells MC to an amorphous phase or a crystalline phase through a bit line BL and a word line WL to record or erase data. In an embodiment, the memory control circuit 20 may perform a phase change of a phase change material of an information storage element VR included in a memory cell MC to an amorphous phase to increase the resistance of the information storage element VR. At the same time, the memory control circuit 20 may perform a phase change of a phase change material of an information storage element VR included in a memory cell MC to a crystalline phase to reduce the resistance of the information storage element VR. According to example embodiments, the relationship between the resistance value of the information storage element VR and whether data is recorded may be defined differently. The memory control circuit 20 may compare a read voltage detected by a plurality of memory cells MC with a predetermined reference voltage to perform a read operation of reading data from a plurality of memory cells MC.

[0033] Figure 4 is a view schematically illustrating a structure of a memory cell included in a memory device according to an embodiment of the inventive concept.

[0034] refer to Figure 4 , a memory device 100 according to an embodiment of the present invention includes a first memory cell MC1 and a second memory cell MC2 disposed between a plurality of conductive lines 101 to 103. The first memory cell MC1 and the second memory cell MC2 may be operated as independent memory cells, respectively. For example, when the first conductive line 101 and the second conductive line 102 are word lines, the third conductive line 103 may be a bit line. In addition, when the first conductive line 101 and the second conductive line 102 are bit lines, the third conductive line 103 may be a word line. Hereinafter, for ease of explanation, the first conductive line 101 and the second conductive line 102 will be described as a first word line and a second word line, respectively.

[0035] The first memory cell MC1 may include a first heating electrode 110, a first information storage element 120, a first selection element 130, etc. The first selection element 130 may include a first switch electrode 131, a second switch electrode 132, and a first selection layer 133 disposed therebetween. In an embodiment, the first selection layer 133 may include a bidirectional threshold switch (OTS) material. When a voltage higher than the threshold voltage of the first memory cell MC1 is applied between the first switch electrode 131 and the second switch electrode 132, a current may flow through the first selection layer 133.

[0036] The first information storage element 120 may include a phase change material, and in an embodiment, may include a chalcogenide material. For example, the first information storage element 120 may include germanium-antimony-tellurium (Ge-Sb-Te, GST), and the phase change rate according to the crystallization temperature, melting point, crystallization energy, etc. of the first information storage element 120 may be determined based on the types of elements included in the first information storage element 120 and their chemical composition ratios.

[0037] The second memory cell MC2 may have a structure similar to that of the first memory cell MC1. Figure 4 , the second memory cell MC2 may include a second heating electrode 140, a second information storage element 150, a second switching element 160, etc. The structures and characteristics of the second heating electrode 140, the second information storage element 150, and the second switching element 160 may be the same as those of the first heating electrode 110, the first information storage element 120, and the first selection element 130. Hereinafter, a method of writing and erasing data with reference to the first memory cell MC1 will be described.

[0038] When a voltage is provided through the first word line 101 and the bit line 103, Joule heat may be generated at the interface between the first heating electrode 110 and the first information storage element 120. The phase change material constituting the first information storage element 120 may change from an amorphous phase to a crystalline phase, or from a crystalline phase to an amorphous phase. The first information storage element 120 may have a relatively high resistance in an amorphous phase, and a relatively low resistance in a crystalline phase. In an embodiment, data "0" or "1" may be defined depending on the resistance value of the first information storage element 120.

[0039] A programming voltage may be provided through the first word line 101 and the bit line 103 to write data into the first memory cell MC1. The programming voltage may be higher than the threshold voltage of the bidirectional threshold switch material included in the first selection element 130, and thus a current may flow through the first selection element 130. The phase change material included in the first information storage element 120 may be changed from an amorphous phase to a crystalline phase by the programming voltage, so that data may be written into the first memory cell MC1. In an embodiment, when the phase change material included in the first information storage element 120 has a crystalline phase, the state of the first memory cell MC1 may be defined as a set state.

[0040] The phase change material included in the first information storage element 120 may return from the crystalline phase to the amorphous phase to erase the data recorded in the first memory cell MC1. For example, a predetermined erase voltage may be provided through the first word line 101 and the bit line 103. Due to the erase voltage, the phase change material included in the first information storage element 120 may change from the crystalline phase to the amorphous phase. When the phase change material included in the first information storage element 120 has the amorphous phase, the state of the first memory cell MC1 may be defined as a reset state. For example, the maximum value of the erase voltage may be higher than the maximum value of the program voltage, and the duration of providing the erase voltage may be shorter than the duration of providing the program voltage.

[0041] As described above, the resistance values ​​of the information storage elements 120 and 150 may be changed according to the state of the phase change material included in the information storage elements 120 and 150, and the memory control circuit may distinguish between data "0" and "1" in the resistance values ​​of the information storage elements 120 and 150. Therefore, when the resistance difference between the information storage elements 120 and 150, which may be represented by the state of the phase change material included in the information storage elements 120 and 150, becomes larger, the memory control circuit correctly reads the data stored in the memory cells MC1 and MC2.

[0042] Figure 5 is a view illustrating an operation of a memory device according to an embodiment of the inventive concept.

[0043] The memory device 200 according to an embodiment of the inventive concept may be operated by power supplied to the memory unit 210 by the memory control circuit 220. Figure 5, the memory cell 210 may include a lower electrode 211, a heating electrode 212, an information storage element 214, a selection element 215, an upper electrode 216, etc. The lower electrode 211 and the upper electrode 216 may receive a voltage output from the memory control circuit 220 through a word line, a bit line, etc. An insulating layer 213 may be provided around the heating electrode 212, and a region 214a of the information storage element 214 adjacent to the heating electrode 212 may undergo a phase change by a power source provided by the memory control circuit 220.

[0044] In an embodiment, a read operation for identifying data in the memory cell 210 may be performed by respectively inputting (or providing) predetermined bias voltages to the lower electrode 211 and the upper electrode 216. For example, the memory control circuit 220 may read the data of the memory cell 210 by inputting a relatively low first bias voltage to the lower electrode 211 and a relatively high second bias voltage to the upper electrode 216.

[0045] For example, the memory control circuit 220 may first input a first bias voltage to the lower electrode 211, and may float the lower electrode 211 when a second bias voltage is input to the upper electrode 216. In a state where the lower electrode 211 is floating, when the second bias voltage is input to the upper electrode 216, current may flow in the memory cell 210. In an embodiment, the memory control circuit 220 may charge a capacitor with the current flowing through the memory cell 210, and may compare the voltage of the capacitor with a reference voltage to discern data of the memory cell 210.

[0046] Figure 6 is a view illustrating an operation of a memory device according to an embodiment of the inventive concept.

[0047] refer to Figure 6 , the memory device 300 according to an embodiment of the inventive concept may include a first decoder circuit 310, a second decoder circuit 320, a readout circuit 330, a control logic 340, and a memory cell array 350. The memory cell array 350 may include a plurality of memory cells MC1, MC2, MC3, and MC4. The first decoder circuit 310 may be connected to the plurality of memory cells MC1 to MC4 through word lines WL, and the second decoder circuit 320 may be connected to the plurality of memory cells MC1 to MC4 through first to fourth bit lines BL1 to BL4. For ease of explanation, in Figure 6 In the embodiment of FIG. 3 , only one word line WL is shown. The memory cell array 350 may include a plurality of word lines WL. In addition, the number of bit lines BL1 to BL4 and the number of memory cells MC1 to MC4 may be variously modified.

[0048] exist Figure 6In the illustrated embodiment, the readout circuit 330 can read the data of the selected memory cell among the memory cells MC1 to MC4. For example, when the fourth bit line BL4 is determined as the selected bit line, the first bit line BL1 to the third bit line BL3 can be unselected bit lines. The first decoder circuit 310 can connect the first bias circuit 311 to the word line WL to input the first bias voltage, and the second decoder circuit 320 can connect the second bias circuit 321 to the fourth bit line BL4 to input the second bias voltage. The second bias voltage can be higher than the first bias voltage.

[0049] The second decoder circuit 320 may also input a third bias voltage higher than the first bias voltage and lower than the second bias voltage to the first bit line BL1 to the third bit line BL3 that are not selected. In one example, the third bias voltage may be a voltage of 0V, the first bias voltage may be a negative voltage, and the second bias voltage may be a positive voltage. In one example, the second bias voltage may be a constant positive voltage (e.g., 2V). In an embodiment, the absolute values ​​of the first bias voltage and the second bias voltage may be equal to each other.

[0050] As described above, when the first bias voltage to the third bias voltage are input to the bit lines BL1 to BL4 and the word line WL, the current may flow only to the selected memory cell to which the relatively high voltage is input. The read circuit 330 may detect a read voltage corresponding to the current flowing in the selected memory cell, and compare the detected voltage with a reference voltage to determine the state of the selected memory cell as a set state or a reset state. For example, a capacitor included in the first decoder circuit 310 and / or the read circuit 330 may be charged by the current flowing through the selected memory cell, and the read circuit 330 may compare the voltage of the capacitor with the reference voltage to discern the data of the selected memory cell.

[0051] When the period of the current flowing in the selected memory cell in the read operation is long, the data stored in the selected memory cell can be accurately identified, and the read failure can be minimized. However, when the period of the current flowing in the selected memory cell in the read operation is long, read interference in which an unexpected phase change occurs in the selected memory cell may occur. For example, when the threshold voltage of the selected memory cell is relatively low, the possibility of read interference may be relatively low, and the possibility of read failure may be relatively high. When the threshold voltage of the selected memory cell is relatively high, the possibility of read failure may be relatively low, and the possibility of read interference may be relatively high.

[0052] In an embodiment of the inventive concept, after the first decoder circuit 310 inputs the first bias voltage to the word line WL, the second decoder circuit 320 may input the second bias voltage to the selected bit line among the bit lines BL1 to BL4. When the second bias voltage starts to be input to the selected bit line and a predetermined delay time has passed, at least one switching element connected between the first bias circuit 311 and the word line WL may be turned off. Therefore, read disturbance and read failure may be minimized to achieve a stable read operation.

[0053] Figure 7 is a circuit diagram illustrating the operation of a memory device according to an embodiment of the inventive concept.

[0054] refer to Figure 7 , the memory device 400 according to an embodiment of the inventive concept may include a first decoder circuit 410, a second decoder circuit 420, a readout circuit 430, a memory cell array 450, etc. Figure 7 Only two word lines WL1 and WL2 and four bit lines BL1 to BL4 are shown in the embodiment of the present invention, but the number thereof may be changed differently. The memory cell array 450 may include memory cells MC11, MC12, MC13, and MC14 and MC21, MC22, MC23, and MC24 connected to the word lines WL1 and WL2 and the bit lines BL1 to BL4.

[0055] The first decoder circuit 410 may be connected to the word lines WL1 and WL2, and for a read operation, may determine one of the word lines WL1 and WL2 as a selected word line, and input a first bias voltage to the selected word line. For example, the first bias voltage may be a negative voltage. The first bias circuit 311 (in the Figure 6 The first bias circuit 311 may be connected between the second switching element GX and the sense amplifier 431. The first bias circuit 311 may provide a first bias voltage to a selected word line, or float the selected word line by a control signal (not shown).

[0056] Each of the word lines WL1 and WL2 may be connected to at least one switching element included in the first decoder circuit 410. For example, the first word line WL1 may be connected to the sense amplifier 431 of the readout circuit 430 through the first switching element LX1 and the second switching element GX. The second word line WL2 may be connected to the sense amplifier 431 through the first switching element LX2 and the second switching element GX.

[0057] exist Figure 7In the illustrated embodiment, the first word line WL1 and the second word line WL2 may share a single second switching element GX and a single sense amplifier 431. According to example embodiments, the first word line WL1 and the second word line WL2 may be connected to second switching elements GX and sense amplifiers 431 different from each other.

[0058] Referring to the second decoder circuit 420, each of the bit lines BL1 to BL4 may be connected to a pair of switch elements. For example, the first bit line BL1 may be connected to a first selection switch element LYP1 and a first non-selection switch element LYN1. When the first bit line BL1 is determined as a selected bit line, the first selection switch element LYP1 may be turned on, and when the first bit line BL1 is determined as an unselected bit line, the first non-selection switch element LYN1 may be turned on. For example, the first selection switch element LYP1 may be a P-type metal oxide semiconductor (PMOS) transistor, and the first non-selection switch element LYN1 may be an N-type metal oxide semiconductor (NMOS) transistor. The gate terminals of the first selection switch element LYP1 and the first non-selection switch element LYN1 may receive a first bit line control signal LBL1 in common.

[0059] The bit lines BL1 to BL4 may share a common selection switch element GYP and a common non-selection switch element GYN. The common selection switch element GYP may be a PMOS transistor, and the common non-selection switch element GYN may be an NMOS transistor. The gate terminals of the common selection switch element GYP and the common non-selection switch element GYN may receive a common bit line control signal GBL in common.

[0060] The sense amplifier 431 may include a capacitor, and the voltage of the capacitor may be compared with a predetermined reference voltage. For example, the sense amplifier 431 may be implemented as an arithmetic amplifier, and a first input terminal of the arithmetic amplifier may be connected to the capacitor and the word lines WL1 and WL2, and a second input terminal thereof may be connected to a reference voltage.

[0061] Hereinafter, a read operation of the selected memory cell MC11 will be described on the assumption that the first word line WL1 and the first bit line BL1 are selected as a selected word line and a selected bit line, respectively.

[0062] When starting a read operation of a selected memory cell connected to the first bit line BL1 and the first word line WL1, the first decoder circuit 410 may turn on the first switching element LX1 and the second switching element GX connected to the first word line WL1 to input a first bias voltage to the first word line WL1. The first word line WL1 may be precharged by the first bias voltage. In this case, the first switching element LX2 connected to the second word line WL2 may be turned off.

[0063] When the first word line WL1 is precharged by the first bias voltage, the second decoder circuit 420 may use the enable signal ENB and the clamp voltage V CLAMP To turn on the enabling element M1 and the clamping element M2. Also, the second decoder circuit 420 may turn on the common selection switch element GYP shared by the bit lines BL1 to BL4, may turn off the common non-selection switch element GYN, may turn on the first selection switch element LYP1 connected to the first bit line BL1, and may turn off the first non-selection switch element LYN1. The second decoder circuit 420 may also turn on the non-selection switch elements LYN2, LYN3, and LYN4 connected to the second bit line BL2, the third bit line BL3, and the fourth bit line BL4, and may turn off the selection switch elements LYP2, LYP3, and LYP4. Therefore, the first bit line BL1 may receive the second bias voltage, and the second bit line BL2 to the fourth bit line BL4 may receive the ground voltage as the third bias voltage.

[0064] When the second bias voltage starts to be input to the first bit line BL1, precharging the first word line WL1 may end. For example, when the first decoder circuit 410 completes precharging the first word line WL1, the second decoder circuit 420 may input the second bias voltage to the first bit line BL1.

[0065] When the second bias voltage is input to the first bit line BL1, the selected memory cell MC11 may be turned on to allow a sensing current to flow through the selected memory cell MC11, and a charge capacitance of the first word line WL1, which may be a selected word line, may be charged by the sensing current. The capacitor of the sense amplifier 431 may be charged by receiving a charge from the first word line WL1 charged by the sensing current. Therefore, when the charge capacitance of the first word line WL1 connected to the selected memory cell MC11 increases, the sensing margin of the selected memory cell MC11 may be improved, and a read failure may be prevented.

[0066] When the charge capacitance of the first word line WL1 connected to the selected memory cell MC11 increases, the sensing current may increase. Therefore, when the selected memory cell MC11 has a set state, read disturbance may occur. For example, when the selected memory cell MC11 has a set state, a phase transition of the information storage element included in the selected memory cell MC11 to an amorphous phase may occur due to the increase in the sensing current. Therefore, it is desirable to reduce the charge capacitance of the first word line WL1 connected to the selected memory cell MC11 to prevent read disturbance of the selected memory cell MC11.

[0067] In an embodiment of the inventive concept, at least one of the first switching element LX1 and the second switching element GX may be maintained in a turned-on state during a predetermined delay time after precharging of the first word line WL1 is completed. When the delay time elapses, the at least one of the first switching element LX1 and the second switching element GX maintained in a turned-on state during the delay time may be turned off.

[0068] During the delay time, the first word line WL1 may be connected to at least one of the first capacitor C11, the second capacitor C12, and the third capacitor C13 through the first switching element LX1 and the first resistor R1. Therefore, the charge capacitance of the first word line WL1 connected to the selected memory cell MC11 during the delay time may be greater than the charge capacitance of the first word line WL1 connected to the selected memory cell MC11 after the delay time has passed.

[0069] Although not shown, the third resistor connected to the fourth capacitor and the fifth capacitor is located between the second switch element GX and the sense amplifier 431. Herein, the corresponding capacitors (the first capacitor C11, the second capacitor C12, and the third capacitor C13, and the fourth capacitor and the fifth capacitor) and the corresponding resistors (the first resistor R1 and the third resistor) are parasitic capacitance and parasitic resistance. In addition, for example, Figure 7 The second bit line control signal LBL2, the third bit line control signal LBL3, and the fourth bit line control signal LBL4 shown in the figure can have a similar function to the first bit line control signal LBL1, the second control signal LXL2, the second resistor R2, the sixth capacitor C21, the seventh capacitor C22, and the eighth capacitor C23 correspond to the functions of the first control signal LXL1, the first resistor R1, the first capacitor C11, the second capacitor C12, and the third capacitor C13, respectively, and VDD can represent the power supply voltage.

[0070] When the threshold voltage of the selected memory cell MC11 is relatively low and the sensing margin is relatively small, the selected memory cell MC11 can be turned on within the delay time. Since the sensing current passing through the selected memory cell MC11 starts to flow during the delay time when the first word line WL1 has a relatively high charge capacitance, the sensing margin of the selected memory cell MC11 can be improved and a read failure can be prevented.

[0071] When the threshold voltage of the selected memory cell MC11 is relatively high, the selected memory cell MC11 can be turned on after a delay time. Since the selected memory cell MC11 can be turned on and the sensing current can flow only when the first word line WL1 has a relatively low charge capacitance, the read disturbance of the selected memory cell MC11 can be prevented.

[0072] Figure 8 is a timing diagram illustrating a read operation of a memory device according to an embodiment of the inventive concept. 9A to 9C is a diagram illustrating a read operation of a memory device according to an embodiment of the inventive concept.

[0073] In the following, we will describe Figure 7 The memory device 400 is shown. Figure 8 , a first bias voltage VB1 may be input to the selected word line WL1, and a second bias voltage VB2 may be input to the selected bit line BL1. The selected word line WL1 and the selected bit line BL1 may be respectively connected to a word line connected to a selected memory cell MC11 whose data is to be read among the plurality of word lines WL and a bit line connected to a selected memory cell MC11 whose data is to be read among the plurality of bit lines BL. The selection of the selected memory cell MC11 and the selected word line WL1 and the selected bit line BL1 may be examples and may be changed variously. The selected word line WL1 may be precharged by the first bias voltage VB1 input to the selected word line WL1 during the first period T1.

[0074] When the selected word line WL1 is precharged by the first bias voltage VB1, the second bias voltage VB2 may be input to the selected bit line BL1. For example, when the first period T1 passes and the second period T2 begins, the second bias voltage VB2 may be input to the selected bit line BL. Hereinafter, the selected word line WL1 may be disconnected (or floated) from the first bias circuit after the first period T1 passes, and when the second period T2 begins, the second bias voltage VB2 may be input to the selected bit line (e.g., BL1). Although not shown, if the selected memory cell has a set state, the voltage level of the floated word line may gradually increase after the second bias voltage VB2 is supplied to the selected bit line BL1.

[0075] In an embodiment of the inventive concept, when a predetermined delay time TD has passed after the start of the second period T2, a control signal LXL1 for controlling the first switch element LX1 connected to the selected word line WL1 may turn off the first switch element LX1. Although not shown, the second switch element GX is connected between the first switch element LX1 and the first bias circuit 311. When the first switch element LX1 is turned off, the second switch element GX may be turned on. Therefore, the charge capacitance of the selected word line WL1 during the delay time TD may be greater than the charge capacitance of the selected word line WL1 during the second period T2 except for the delay time TD. For example, the delay time TD may be defined as a transition time for the second bias voltage VB2 input to the selected bit line BL1 to increase. At the end point of the delay time TD, the voltage of the selected bit line BL1 may have a magnitude of about 70% to 80% of the second bias voltage VB2.

[0076] First, refer to Fig. 9A , the threshold voltage distribution of the memory cell can be classified according to the state of the information storage element included in the memory cell. The set state distribution 500 corresponding to the threshold voltage of the memory cell having the set state can be smaller than the reset state distribution 510 corresponding to the threshold voltage of the memory cell having the reset state. The reference voltage V REF can be set to have a value higher than the set state distribution 500 and lower than the reset state distribution 510, and the sense amplifier 431 of the memory control circuit can compare the voltage detected by the selected memory cell MC11 among the memory cells with the reference voltage V REF The comparison is performed to identify the data of the selected memory cell MC11.

[0077] The set state distribution 500 may be divided into a first region 501 and a second region 502. Memory cells having a threshold voltage belonging to the first region 501 may have a relatively small sensing margin and a relatively large read disturbance margin. Memory cells belonging to the second region 502 may have a relatively large sensing margin and a relatively small read disturbance margin.

[0078] Fig. 9B It may be a graph showing a threshold voltage change according to a read disturbance that may occur in a read operation. Fig. 9B , the threshold voltage of the selected memory cell MC11 having the set state may increase due to the read disturbance, and the set state distribution 500A may move to the right. In this case, the influence of the increase in the threshold voltage in the second region 502A may be relatively greater than that in the first region 501A. For example, when the threshold voltage of the selected memory cell MC11 is included in the second region 502A, the threshold voltage may increase to the reference voltage V due to the read disturbance. REF , and the selected memory cell MC11 can be evaluated to have a relatively small read disturbance margin. When the threshold voltage of the selected memory cell MC11 is included in the first region 501A, even when read disturbance occurs, the threshold voltage and the reference voltage V REF The difference between φ and φ may also be maintained at a certain level or higher. Therefore, the selected memory cell MC11 may be evaluated to have a relatively large read disturbance margin.

[0079] Fig. 9C It may be a graph showing the sensing margin of a memory cell having a set state. Fig. 9A and Fig. 9C , memory cells having threshold voltages belonging to the first region 501 of the set state distribution 500 may have a relatively small sensing margin. In addition, memory cells having threshold voltages belonging to the second region 502 may have a relatively large sensing margin.

[0080] Reference again Figure 7 and Figure 8 In an embodiment of the inventive concept, when the second bias voltage VB2 is input to the selected bit line BL1 and during a predetermined delay time TD, the first switch element LX1 connected to the selected word line WL1 by the control signal LXL1 may be maintained in a turned-on state. Therefore, the charge capacitance of the selected word line WL1 during the delay time TD may be greater than the charge capacitance of the selected word line WL1 during the second period T2 excluding the delay time TD.

[0081] If the selected memory cell MC11 has a set state and a threshold voltage is relatively low, for example, the threshold voltage of the selected memory cell is included in Fig. 9A In the first region 501, the selected memory cell MC11 may have a relatively small sensing margin and a relatively large read disturbance margin. The selected memory cell MC11 having a relatively low threshold voltage may be turned on within the delay time TD, and when the selected word line WL1 has a relatively high charge capacitance, current may flow through the selected memory cell MC11 in the selected word line WL1. Therefore, the sensing margin of the selected memory cell MC11 may be improved, and a read failure may be prevented. The period during which the current flows through the selected memory cell MC11 increases, but because the selected memory cell MC11 has a large read disturbance margin, read disturbance may not occur.

[0082] Next, if the threshold voltage of the selected memory cell MC11 is included in Fig. 9A In the second region 502 of , the selected memory cell MC11 can have a relatively large sensing margin and a relatively small read disturbance margin. The selected memory cell MC11 with a relatively high threshold voltage can be turned on after a delay time TD, and only when the selected word line WL1 has a relatively low charge capacitance, the selected memory cell MC11 can be turned on to allow current to flow through the selected word line WL1. Therefore, since the period during which the current flows through the selected memory cell MC11 can be reduced, the problem caused by the read disturbance can be solved. In addition, since the selected memory cell MC11 has a good sensing margin, a read failure does not occur.

[0083] Fig.10 is a flowchart illustrating a read operation of a memory device according to an embodiment of the inventive concept.

[0084] refer to Fig.10 , a read operation of a memory device according to an exemplary embodiment of the inventive concept may include determining a selected word line among a plurality of word lines, and determining a selected bit line among a plurality of bit lines (S10). The selected word line and the selected bit line may be a word line and a bit line connected to a selected memory cell from which data is to be read.

[0085] The memory control circuit may input a first bias voltage to the selected word line (S20). The first bias voltage may be a negative voltage. Next, the memory control circuit may input a second bias voltage to the selected bit line (S30). The second bias voltage may be a positive voltage, and the absolute values ​​of the first bias voltage and the second bias voltage may be equal to each other. After the first bias voltage is input to the selected word line and a predetermined time has passed, the second bias voltage may be input to the selected bit line.

[0086] Next, the memory control circuit may float the selected word line (S40). The memory control circuit may separate the selected word line from the first bias circuit that outputs the first bias voltage to float the selected word line. According to example embodiments, the timing of the floating of the selected word line may vary. In one example, the selected word line may float immediately after the second bias voltage begins to be input and after a predetermined delay time has passed, or the second bias voltage may be input without a predetermined delay time. The memory control circuit may float the selected word line by turning off at least one switching element between the selected word line and the first bias circuit.

[0087] The memory control circuit may detect data of the selected memory cell (S50). After the second bias voltage is input and a predetermined time has passed, the memory control circuit may detect a first voltage corresponding to a current flowing in the selected word line by connecting the selected word line to the readout circuit. The memory control circuit may compare the first voltage with a predetermined reference voltage. When the first voltage is lower than the reference voltage, the memory control circuit may distinguish the state of the selected memory cell as a set state. When the first voltage is higher than the reference voltage, the memory control circuit may distinguish the state of the selected memory cell as a reset state.

[0088] Figures 11 to 14 is a timing diagram illustrating a read operation of a memory device according to example embodiments of the inventive concepts.

[0089] refer to Figures 11 to 14 , a first bias voltage VB1 may be input to the selected word line WL, and a second bias voltage VB2 may be input to the selected bit line BL. The first bias voltage VB1 may be a negative voltage, and the second bias voltage VB2 may be a positive voltage. The selected word line WL may be precharged by the first bias voltage VB1 input to the selected word line WL during the first period T1.

[0090] When the selected word line WL is precharged by the first bias voltage VB1, the second bias voltage VB2 may be input to the selected bit line BL. For example, when the first period T1 passes and the second period T2 begins, the second bias voltage VB2 may be input to the selected bit line BL. In addition, in an embodiment, when the second period T2 passes, the input of the second bias voltage VB2 may end, the selected bit line BL may float, and the selected bit line BL and the selected word line WL may develop.

[0091] In reference Figures 11 to 14 In the described embodiment, two or more switching elements may be connected to a selected word line WL. The switching element may include a first switching element and a second switching element, and the first switching element may be connected in series between the second switching element and the selected word line WL. A first control signal LXL for the first switching element and a second control signal GXL for the second switching element may be connected in series between the first switching element and the selected word line WL. Figures 11 to 14 The first switching element and the second switching element may be connected between a first bias circuit outputting a first bias voltage VB1 and a selected word line WL.

[0092] First reference Fig.11 , the second period T2 may start, and the second switch element may be turned off by the second control signal GXL. The first switch element may maintain a conductive state during the delay time TD, and may be turned off after the delay time TD has elapsed. During the delay time TD, by maintaining the first switch element in a conductive state, the charge capacitance of the selected word line WL may have a relatively large value. Fig.11 In the illustrated embodiment, since the second switching element is turned off after the first period T1 has elapsed, the selected word line WL may be floated immediately after the first period T1 has elapsed.

[0093] exist Fig.11 In the illustrated embodiment, when the selected word line WL floats, the first switch element may be turned off. In addition, the first switch element may be turned off after the selected word line WL floats and after a delay time TD. In some examples, the first switch element may be turned off before the floating of the selected word line WL ends.

[0094] The first switch element may remain in an off state during a development time after the second period T2, wherein the selected word line WL is developed during the development time. In some examples, the selected word line WL is developed during the second period T2. Alternatively, in one embodiment, when the development time has passed, the first switch element and the second switch element may be turned on, and the selected word line WL and the readout circuit may be connected to each other. Alternatively, in one embodiment, when the development time starts, the first switch element and the second switch element may be turned on, and the selected word line WL and the readout circuit may be connected to each other. According to an example embodiment, before the development time has completely passed, the first switch element and the second switch element may be turned on so that the selected word line WL and the readout circuit may be connected to each other.

[0095] When the threshold voltage of the selected memory cell is relatively low, the selected memory cell can be turned on within the delay time TD, and the current flowing in the selected memory cell can be charged to the selected word line WL to have a relatively high charge capacitance. Therefore, the turn-on time of the selected memory cell with a relatively low threshold voltage and a relatively small sensing margin can be increased, and read failure can be prevented. In addition, when the threshold voltage of the selected memory cell is relatively high, the selected memory cell can be turned on after the delay time TD has passed, so that the turn-on period of the selected memory cell can be reduced. Therefore, read interference can be prevented by reducing the turn-on time of the selected memory cell with a relatively high threshold voltage.

[0096] Next, refer to Fig.12 , the first bias voltage VB1 may be input to the selected word line WL during the first period T1, and the second bias voltage VB2 may be input to the selected bit line BL during the second period T2. When the second period T2 starts and during the predetermined delay time TD, both the first switching element and the second switching element may remain in the on state. Therefore, at least a portion of the first period T1 and the second period T2 may overlap each other. For example, the delay time TD may be a period included in both the first period T1 and the second period T2.

[0097] When the delay time TD has passed, the first switching element and the second switching element can be turned off together. The selected memory cell with a relatively low threshold voltage can be turned on during the delay time TD, and the current flowing through the selected memory cell can be charged to the selected word line WL to have a relatively high charge capacitance. Therefore, the sensing margin of the selected memory cell can be improved. Because the first switching element and the second switching element are turned off together after the delay time TD has passed, the selected word line WL may not float during the delay time TD, and may float after the delay time TD has passed.

[0098] A selected memory cell with a relatively high threshold voltage can be turned on later than a selected memory cell with a relatively low threshold voltage. Therefore, since the turn-on period of the selected memory cell with a relatively high threshold voltage is shortened and the period of current flow is also shortened, read disturbance can be prevented.

[0099] Next, refer to Fig.13 , the first bias voltage VB1 may be input to the selected word line WL during the first period T1, and the second bias voltage VB2 may be input to the selected bit line BL during the second period T2. Fig.12 In the embodiment shown, at the beginning of the second period T2 and during the predetermined delay time TD, the first switch element and the second switch element can both be kept in the on state. Therefore, at least a portion of the first period T1 and the second period T2 can overlap each other. Because the first switch element and the second switch element are both kept in the on state during the delay time TD, the selected word line WL can be floated until the delay time TD has passed.

[0100] When the delay time TD has passed, the first switching element may be turned off. A selected memory cell having a relatively low threshold voltage may be turned on within the delay time TD, and a selected memory cell having a relatively high threshold voltage may be turned on relatively later. For example, a selected memory cell having a relatively high threshold voltage may be turned on after the delay time TD has passed. Therefore, the sensing margin of the selected memory cell having a relatively low threshold voltage may be improved, and the read disturbance in the selected memory cell having a relatively high threshold voltage may be minimized.

[0101] refer to Fig.14 , the first bias voltage VB1 may be input to the selected word line WL during the first period T1, and the second bias voltage VB2 may be input to the selected bit line BL during the second period T2. Fig.12 and Fig.13In the embodiment shown, at the beginning of the second period T2 and during the predetermined delay time TD, the first switch element and the second switch element can both remain in the on state. Therefore, it can be understood that at least a portion of the first period T1 and the second period T2 overlap each other. And the selected word line WL can float until the delay time TD passes.

[0102] When the delay time TD has passed, the second switching element can be turned off. The selected memory cell with a relatively low threshold voltage can be turned on within the delay time TD, and the selected memory cell with a relatively high threshold voltage can be turned on relatively later. For example, the selected memory cell with a relatively high threshold voltage can be turned on after the delay time TD has passed. Therefore, the sensing margin of the selected memory cell with a relatively low threshold voltage can be improved, and the read interference in the selected memory cell with a relatively high threshold voltage can be minimized.

[0103] According to an example embodiment, the first switch element may be turned off after the selected word line WL floats, and the second switch element is turned off after the delay time TD. In one example, the first switch element may be turned off later than the second switch element. Alternatively, when the second period T2 ends and the selected bit line BL floats to start the development time, the first switch element may be turned off. Before the development time ends, or before the development time ends completely, the first switch element may be turned on again to connect the selected word line WL to the readout circuit.

[0104] Fig.15 is a circuit diagram illustrating the operation of a memory device according to an embodiment of the inventive concept.

[0105] refer to Fig.15 , the memory device 500 according to an embodiment of the inventive concept may include a first decoder circuit 510, a second decoder circuit 520, a readout circuit, a control logic 540, a memory cell array 550, etc. Fig.15 Only one word line WL and four bit lines BL1 to BL4 are shown in the embodiment of FIG. 5 , but the number thereof may be variously changed. The memory cell array 550 may include memory cells MC11 to MC14 connected to the word line WL and the bit lines BL1 to BL4 .

[0106] The first decoder circuit 510 may include a first switching element LX1, a second switching element GX1, and a plurality of capacitors C1, C2, and C3 connected to a word line WL. The first switching element LX1 and the second switching element GX1 may be connected between the word line WL and a sense amplifier 530 included in a readout circuit.

[0107] In a read operation in which one of the memory cells MC11 to MC14 is selected and data is read, the first decoder circuit 510 may input a first bias voltage to the word line WL. For example, the first bias voltage may be a negative voltage. The circuit for inputting the first bias voltage may be implemented as a current source connected between the second switching element GX1 and the sense amplifier 530, etc.

[0108] The bit lines BL1 to BL4 may be connected to the second decoder circuit 520. The configuration and operation of the second decoder circuit 520 may be similar to the above reference Figure 7 A second decoder circuit 420 is described.

[0109] The control logic 540 may include a switch control circuit 541 and a temperature compensation circuit 542. The switch control circuit 541 may output a first control signal LXL1 and a second control signal GXL1 for controlling on / off operations of a first switching element LX1 and a second switching element GX1 included in the first decoder circuit 510. The temperature compensation circuit 542 may detect an operating temperature of the memory device 500.

[0110] For example, the characteristics of the memory cells MC11 to MC14 may vary depending on the operating temperature of the memory device 500. When the operating temperature of the memory device 500 decreases, the threshold voltage and the sensing margin of the memory cells MC11 to MC14 may increase, and the read disturbance margin may decrease. When the operating temperature of the memory device 500 increases, the threshold voltage and the sensing margin of the memory cells MC11 to MC14 may decrease, and the read disturbance margin may increase.

[0111] In a read operation, the switch control circuit 541 may precharge the word line WL with a first bias voltage by turning on the first switch element LX1 and the second switch element GX1. When the word line WL is charged with the first bias voltage, at least one of the first switch element LX1 and the second switch element GX1 may be turned off. In an embodiment, based on an operating temperature detected by the temperature compensation circuit 542, the switch control circuit 541 may control an on / off timing operation of the first switch element LX1 and the second switch element GX1 connected to the word line WL, or a magnitude of an off voltage input to at least one of the first switch element LX1 and the second switch element GX1, etc.

[0112] For example, when the operating temperature decreases, the switch control circuit 541 may advance the turn-off timing operation of at least one of the first switch element LX1 and the second switch element GX1. Alternatively, the magnitude of the second bias voltage input to the selected bit line among the bit lines BL1 to BL4 may be reduced. When the operating temperature increases, the switch control circuit 541 may delay the turn-off timing operation of at least one of the first switch element LX1 and the second switch element GX1. Alternatively, the magnitude of the second bias voltage input to the selected bit line among the bit lines BL1 to BL4 may be increased.

[0113] By advancing the turn-off timing operation of at least one of the first switching element LX1 and the second switching element GX1, the period required for the word line WL connected to the selected memory cell to have a relatively high charge capacitance can be shortened. Therefore, read disturbance caused by an increase in the threshold voltage of the selected memory cell due to a decrease in the operating temperature can be prevented. An effect such as preventing read disturbance can be obtained by reducing the magnitude of the second bias voltage input to the selected bit line.

[0114] By delaying the turn-off timing operation of at least one of the first switching element LX1 and the second switching element GX1, the period required for the word line WL connected to the selected memory cell to have a relatively high charge capacitance can be increased. Therefore, by preventing the reduction in the sensing margin caused by the reduction in the threshold voltage of the selected memory cell due to the increase in the operating temperature, the sensing margin can be sufficiently ensured. An effect such as ensuring the sensing margin can be obtained by increasing the magnitude of the second bias voltage input to the selected bit line.

[0115] Alternatively, according to an example embodiment, the magnitude of the off voltage input to at least one of the first switching element LX1 and the second switching element GX1 by the switch control circuit 541 may vary depending on the operating temperature. For example, when the operating temperature decreases, the magnitude of the off voltage may decrease, and when the operating temperature increases, the magnitude of the off voltage may increase.

[0116] When the operating temperature decreases, the magnitude of the turn-off voltage can be reduced so that at least one of the first switch element LX1 and the second switch element GX1 can be turned off with certainty. Therefore, the period required for the word line WL connected to the selected memory cell to have a relatively high charge capacitance can be shortened, and read interference can be prevented. When the operating temperature increases, the magnitude of the turn-off voltage can be increased so that at least one of the first switch element LX1 and the second switch element GX1 can be turned off unreliably. Therefore, the sensing margin can be ensured by increasing the period required for the word line WL connected to the selected memory cell to have a relatively high charge capacitance.

[0117] Figures 16 to 18is a timing diagram illustrating a read operation of a memory device according to an embodiment of the inventive concept.

[0118] exist Figures 16 to 18 In the illustrated embodiment, the word line WL may be precharged by the first bias voltage VB1, and the selected bit line BL may be precharged by the second bias voltage VB2C or VB2H. The first bias voltage VB1 may be a negative voltage, and the second bias voltage VB2 may be a positive voltage. During the first period T1, the selected word line WL may be precharged by the first bias voltage VB1 input to the selected word line WL.

[0119] When the selected word line WL is precharged by the first bias voltage VB1, the second bias voltage VB2C or VB2H may be input to the selected bit line BL. For example, when the second period T2 starts, the second bias voltage VB2 may be input to the selected bit line BL. The magnitude of the second bias voltage VB2C or VB2H may vary depending on the operating temperature.

[0120] First reference Fig.16 , when the second period T2 begins, the second switch element may be turned off by the second control signal GXL. When the second switch element is turned off, the selected word line WL may float. The first switch element may remain in an on state during the first delay time TDC or the second delay time TDH, and may be turned off after the first delay time TDC or the second delay time TDH. For example, the first switch element may be turned off during the period of floating the selected word line WL. During the first delay time TDC or the second delay time TDH, the charge capacitance of the selected word line WL may change by maintaining the first switch element in an on state.

[0121] For example, when the operating temperature decreases, the threshold voltage of the memory cell may increase. Therefore, the second bias voltage VB2 may be input to the selected bit line BL as VB2C having a relatively high voltage to turn on the selected memory cell. Also, the turn-off timing of the first control signal LXL may be delayed to a first delay time TDC having a relatively long delay time.

[0122] By increasing the magnitude of the second bias voltage VB2C and delaying the turn-off timing of the first control signal LXL, in response to the threshold voltage increasing as the temperature decreases, the memory cell can be effectively turned on and the data of the selected memory cell can be correctly read. When the magnitude of the second bias voltage VB2C increases and the turn-off timing of the first control signal LXL is delayed, the possibility of read interference in the selected memory cell increases. In an embodiment of the inventive concept, the magnitude of the turn-off voltage of the first control signal LXL can be adjusted to prevent read interference caused by a change in the bias condition corresponding to the temperature decrease. This will be referred to later. Fig.18 Give a description.

[0123] When the operating temperature increases, the threshold voltage decreases and the memory cell can be turned on relatively easily, so that the second bias voltage can be VB2H with a relatively low voltage and the turn-off timing of the first control signal LXL can be delayed to a second delay time TDH with a relatively short delay time. Therefore, the magnitude of the current flowing through the selected memory cell can be reduced, or the period of time for the selected memory cell to be turned on can be reduced, so that the sensing margin of the selected memory cell can be reduced, and a read failure may occur. The magnitude of the turn-off voltage of the first control signal LXL can be adjusted to prevent a read failure caused by a change in the bias condition corresponding to the temperature increase.

[0124] In an embodiment, the voltage magnitude of the first control signal LXL during the first delay time TDC or the second delay time TDH may vary in consideration of the operating temperature. For example, the voltage magnitude of the first control signal LXL during the first delay time TDC selected when the operating temperature decreases may be smaller than the voltage magnitude of the first control signal LXL during the second delay time TDH selected when the operating temperature increases.

[0125] refer to Fig.17 , the first switch element can be kept in the on state by the first control signal LXL, and the second switch element can be turned off at a predetermined timing by the second control signal GXL. Fig.17 In the illustrated embodiment, the first period T1 and the second period T2 may partially overlap each other. According to example embodiments, when the second switching element is turned off and the selected word line WL floats, the first switching element may be turned off. For example, the first switching element may be turned off at the same time as the second switching element, or may be turned off later than the second switching element.

[0126] For example, when the operating temperature decreases, the magnitude of the second bias voltage may be VB2C, or the turn-off timing of the second control signal GXL may be delayed to the first delay time TDC. Therefore, the selected memory cell may be effectively turned on. By adjusting the turn-off voltage of the second control signal GXL, read disturbance caused by the increase of the second bias voltage VB2C and the change of the turn-off timing of the second control signal GXL may be prevented.

[0127] When the operating temperature increases, the threshold voltage of the memory cell can be reduced and the memory cell can be easily turned on, so that the second bias voltage can be VB2H or the turn-off timing of the second control signal GXL can be delayed to the second delay time TDH. Therefore, compared with the case where the operating temperature is reduced, the possibility of read failure will increase. In an embodiment of the inventive concept, the read failure can be prevented by adjusting the turn-off voltage of the second control signal GXL.

[0128] refer to Fig.17 The voltage magnitude of the second control signal GXL during the first delay time TDC may be different from the voltage magnitude of the second control signal GXL during the second delay time TDH. For example, the voltage magnitude of the second control signal GXL during the first delay time TDC, which may be selected when the operating temperature decreases, may be smaller than the voltage magnitude of the second control signal GXL during the second delay time TDH, which may be selected when the operating temperature increases.

[0129] refer to Fig.18 , the magnitude of the turn-off voltage of the first control signal LXL input to the first switch element may vary depending on the operating temperature. For example, the first control signal LXL may be input to the first switch element at a magnitude of the first turn-off voltage VOFF1 to the fourth turn-off voltage VOFF4. In this case, in some examples, the second control signal GXL may be input to the second switch element at a magnitude of the first turn-off voltage VOFF1 to the fourth turn-off voltage VOFF4. In some examples, when the first control signal LXL is input to the first switch element at a magnitude of the first turn-off voltage VOFF1, the second turn-off voltage VOFF2, the third turn-off voltage VOFF3, and the fourth turn-off voltage VOFF4, the second switch element is turned on.

[0130] As the operating temperature decreases, the threshold voltage may increase, making it difficult to turn on the selected memory cell. To solve this problem, the voltage level of the second bias voltage VB2 may increase, and due to the increase in the voltage level of the second bias voltage VB2, the possibility of read interference may increase. Therefore, the turn-off voltage of the first control signal LXL may be reduced to reduce the charge capacitance of the selected word line WL. When the operating temperature increases, the selected memory cell may be easily turned on, so that the voltage level of the second bias voltage VB2 may be reduced. The sensing margin may be reduced with the low voltage level of the second bias voltage VB2, and the possibility of read failure may increase. In an embodiment of the inventive concept, the sensing margin may be ensured by increasing the turn-off voltage of the first control signal LXL to increase the charge capacitance of the selected word line WL. For example, when the operating temperature decreases, the turn-off voltage of the first control signal LXL may have a value close to the first turn-off voltage VOFF1. When the operating temperature increases, the turn-off voltage of the first control signal LXL may have a value close to the fourth turn-off voltage VOFF4.

[0131] Fig.19 is a circuit diagram illustrating the operation of a memory device according to an embodiment of the inventive concept. Fig. 20 is a timing diagram illustrating a read operation of a memory device according to an embodiment of the inventive concept.

[0132] refer to Fig.19 , the memory device 600 according to an embodiment of the inventive concept may include a first decoder circuit 610, a second decoder circuit 620, a readout circuit 630, a memory cell array 650, etc. Fig.19 In the illustrated embodiment, only two word lines WL1 and WL2 and four bit lines BL1 to BL4 are shown, but the number thereof may be changed variously. The memory cell array 650 may include memory cells MC11 to MC14 and MC21 to MC24 connected to the word lines WL1 and WL2 and the bit lines BL1 to BL4. The configuration and operation of the first decoder circuit 610, the second decoder circuit 620, the readout circuit 630, and the memory cell array 650 may be similar to those described above with reference to Figure 7 Those described.

[0133] exist Fig.19In the illustrated embodiment, the memory device 600 may set the read operation differently depending on the position of the selected memory cell. For example, when the selected memory cell is one of the first memory cells MC11 to MC14 connected to the first word line WL1, the resistance of the selected bit line connected to the selected memory cell may be reduced so that the sensing margin of the selected memory cell may be increased. Therefore, when one of the first memory cells MC11 to MC14 is the selected memory cell, the turn-off timing operation of the first switch element LX1 or the second switch element GX connected to the first word line WL1 may be advanced. For example, as Fig. 20 As shown, the turn-off timing operation of the first switching element LX1 can be advanced by shortening the delay time (eg, by selecting the delay time TDS).

[0134] When the selected memory cell is one of the second memory cells MC21 to MC24 connected to the second word line WL2, the turn-off timing of the first switching element LX2 or the second switching element GX connected to the second word line WL2 may be delayed in consideration of a reduced sensing margin of the selected memory cell. Fig. 20 , the turn-off timing of the first switch element LX1 may be delayed by increasing the delay time (eg, by selecting the delay time TDL). In this case, the second memory cells MC21 to MC24 and the second word line WL2 may be located away from the first memory cells MC11 to MC14 and the first word line WL1.

[0135] Fig.21 is a block diagram schematically illustrating an electronic device including a memory device according to an embodiment of the inventive concept.

[0136] according to Fig.21 The electronic device 1000 of the illustrated embodiment may include a display 1010, a sensor unit 1020, a memory 1030, a processor 1040, a port 1050, etc. In addition, the electronic device 1000 may also include a wired / wireless communication unit, a power supply unit, etc. Fig.21 Among the components shown, port 1050 may be a device through which electronic device 1000 may communicate with a video card, a sound card, a memory card, a universal serial bus (USB) device, etc. Electronic device 1000 may be a concept including a general-purpose desktop computer or laptop computer as well as a smartphone, a tablet personal computer (PC), a smart wearable device, etc.

[0137] The processor 1040 may perform specific operations, commands, tasks, etc. The processor 1040 may be a central processing unit (CPU) or a microprocessor unit (MCU), a system on a chip, etc., and may be connected to the display 1010, the sensor unit 1020, the memory 1030, and other units connected to the port 1050 through a bus 1060.

[0138] The memory 1030 may be a storage medium for storing data, or multimedia data for operating the electronic device 1000. The memory 1030 may include a volatile memory (such as a random access memory (RAM)) or a non-volatile memory (such as a flash memory). The memory 1030 may also include at least one of a solid state drive (SSD), a hard disk drive (HDD), and an optical disc drive (ODD) as a storage unit. The electronic device 1000 may include an input / output unit, for example, an input device may include a keyboard, a mouse, a touch screen, etc., and an output device may include a display, an audio output, etc.

[0139] The memory 1030 may include a phase change memory device that uses a change in resistance of a phase change material to write / erase and read data. Fig.21 In the embodiment shown, the memory 1030 may include the Figures 1 to 20 Various embodiments of memory devices are described.

[0140] According to an embodiment of the present invention, a bias voltage can be sequentially input to a selected word line and a selected bit line of a selected memory cell connected to data to be read. After the bit line voltage is input to the selected bit line and a predetermined delay time has passed, an optimized read operation according to the magnitude of the threshold voltage of the selected memory cell can be implemented by turning off the switch element between the selected word line and the bias circuit. Therefore, read disturbance and read failure can be minimized, and the performance of the memory device can be improved.

[0141] Various advantageous advantages and effects of the present inventive concept may not be limited to the above description and may be more easily understood in the course of describing specific embodiments of the present inventive concept.

[0142] While the inventive concept has been shown and described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that modifications and variations may be made thereto without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A memory device, comprising: a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, each of the plurality of memory cells including a selection element and an information storage element connected to the selection element and having a phase change material; A decoder circuit comprising: a first bias circuit configured to provide a first bias voltage to a selected word line among the plurality of word lines, a second bias circuit configured to provide a second bias voltage to a selected bit line among the plurality of bit lines, a first switching element connected to the selected word line, and a second switching element connected between the first switching element and the first bias circuit; and a control logic configured to control the first switching element and the second switching element, wherein the memory device is configured such that when a predetermined delay time elapses after the second bias voltage is supplied to the selected bit line, the control logic turns off the first switch element and the second switch element, turns off the first switch element when the second switch element is turned on, or turns off the second switch element when the first switch element is turned on, and The delay time is at least a portion of a transition time for the voltage of the selected bit line to increase to the second bias voltage.

2. The memory device according to claim 1, wherein: The first switching element and the second switching element are connected in series with each other between the selected word line and the first bias circuit, and The first switch element is connected between the selected word line and the second switch element.

3. The memory device according to claim 2, wherein: The second switching element is connected to two or more word lines among the plurality of word lines.

4. The memory device according to claim 2, wherein: The memory device is configured such that the control logic turns on the first switching element and the second switching element to provide the first bias voltage to the selected word line before the second bias voltage is provided to the selected bit line.

5. The memory device according to claim 4, wherein: The memory device is configured such that when the second bias voltage is supplied to the selected bit line, the control logic maintains the first switching element and the second switching element in a conductive state, and When the delay time elapses, the control logic turns off the first switching element.

6. The memory device according to claim 1, wherein: The memory device is configured such that the control logic determines the delay time based on an operating temperature of the memory device.

7. The memory device according to claim 6, wherein: The memory device is configured such that: When the operating temperature increases, the control logic decreases the delay time, and The control logic increases the delay time as the operating temperature decreases.

8. The memory device according to claim 1, wherein: The memory device is configured such that the control logic determines the delay time based on a location of a selected memory cell.

9. The memory device according to claim 8, wherein: The memory device is configured such that: When the distance between the selected word line and the second bias circuit is a first distance, the control logic determines the delay time to be a first delay time, and When the distance between the selected word line and the second bias circuit is a second distance longer than the first distance, the control logic determines the delay time to be a second delay time longer than the first delay time.

10. The memory device of claim 1, wherein: When the predetermined delay time elapses, the second bias voltage has a constant positive voltage.

11. A memory device comprising: a memory cell connected to a word line and a bit line; a first decoder circuit comprising a first bias circuit configured to provide a first bias voltage to the word line during a first period; a second decoder circuit including a second bias circuit configured to provide a second bias voltage to the bit line during a second period after the first period; and a control logic configured to electrically separate the first bias circuit from the word line when a predetermined delay time has passed from the start time of the second period, wherein the second bias voltage has a constant positive voltage, The delay time is at least a portion of a transition time for the voltage of the bit line to increase to the second bias voltage.

12. The memory device of claim 11, wherein: The second time period overlaps with at least a portion of the first time period.

13. The memory device of claim 12, wherein: The word line receives the first bias voltage during an overlap time.

14. The memory device of claim 11, wherein: The delay time is included in the second period.

15. The memory device of claim 11, wherein: The first decoder circuit further comprises: a first switching element connected to the word line; and a second switching element connected between the first switching element and the first bias circuit, The first decoder circuit is configured such that the first bias circuit is electrically separated from the word line by providing an off voltage to the first switching element based on an operating temperature of the memory device.

16. The memory device of claim 15, wherein: When the operating temperature is a first temperature, the shutdown voltage has a first magnitude, and Wherein, when the operating temperature is a second temperature higher than the first temperature, the turn-off voltage has a second magnitude greater than the first magnitude.

17. A method for operating a memory device, comprising: supplying a first bias voltage output from a first bias circuit to a selected word line connected to a selected memory cell to read data; Turning on a first switch element connected to the selected word line; turning on a second switching element connected between the first switching element and the first bias circuit; providing a second bias voltage to a selected bit line connected to a selected memory cell; as well as When a predetermined delay time has passed after the second bias voltage is input, at least one of the first switching element and the second switching element is turned off, The delay time is at least a portion of a transition time for the voltage of the selected bit line to increase to the second bias voltage.

18. The method according to claim 17, wherein: Turning off the first switch element or the second switch element comprises: providing an off voltage to the first switching element or the second switching element, and At least one of the delay time, the magnitude of the shutdown voltage, and the magnitude of the second bias voltage is determined based on an operating temperature of the memory device.

19. The method according to claim 18, wherein: When the operating temperature is a first temperature, the magnitude of the shutdown voltage is a first magnitude, and When the operating temperature is a second temperature lower than the first temperature, the magnitude of the shutdown voltage is a second magnitude smaller than the first magnitude.

20. The method according to claim 17, wherein: When the predetermined delay time elapses, the second bias voltage has a constant positive voltage.

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