Non-volatile memory device

Abstract

A nonvolatile memory device includes a substrate, a memory cell string including a vertical channel structure and a memory cell, a voltage generator including a first transistor and configured to supply various voltages to the memory cell, and a vertical capacitor structure. The vertical capacitor structure includes a first active pattern and a second active pattern arranged apart from each other in a first horizontal direction, a first gate pattern located above a channel region between the first active pattern and the second active pattern, a first gate insulating film located between the first gate pattern and the substrate in a vertical direction, and capacitor electrodes each extending in the vertical direction. The first transistor includes a second gate pattern and a second gate insulating film located between the second gate pattern and the substrate in the vertical direction. A thickness of the first gate insulating film in the vertical direction is greater than a thickness of the second gate insulating film in the vertical direction.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0038603, filed April 2, 2019, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0003] The present inventive concept relates to a memory device, and more particularly, to a vertical capacitor structure and a nonvolatile memory device including the same. BACKGROUND

[0004] Memory devices (e.g., integrated circuits or semiconductor chips) are used to store data, and are classified into volatile memory devices and nonvolatile memory devices. As an example of a nonvolatile memory device, a flash memory device can be used in mobile phones, digital cameras, mobile computer devices, stationary computer devices, and other devices. Recently, as information communication devices have become multifunctional, large capacity and high density integration of memory devices have been required. Accordingly, a three-dimensional (3D) nonvolatile memory device including a plurality of word lines stacked in a vertical direction on a substrate has been proposed. As the number of word lines stacked on a substrate in a 3D nonvolatile memory device increases, there is a need to increase the capacity of a charge pump included in a peripheral circuit region. SUMMARY

[0005] The present inventive concept provides a vertical capacitor structure and a nonvolatile memory device including the same, which increases a capacitance per unit area by improving the integration of a capacitor.

[0006] According to an aspect of the present inventive concept, there is provided a nonvolatile memory device including: a substrate including a memory cell region and a peripheral circuit region; a memory cell string including a vertical channel structure and a plurality of memory cells located in the memory cell region; a voltage generator located in the peripheral circuit region, the voltage generator including a first transistor and configured to provide various voltages to the plurality of memory cells; and a vertical capacitor structure located in the peripheral circuit region. The vertical capacitor structure includes: a first active pattern and a second active pattern separated from each other in a first horizontal direction; a first gate pattern located above a channel region between the first active pattern and the second active pattern; a first gate insulating film located between the first gate pattern and the substrate in a vertical direction with respect to the substrate; and a plurality of capacitor electrodes each extending in the vertical direction, wherein the plurality of capacitor electrodes include: a first capacitor electrode in contact with the first gate pattern and applied with a first voltage, the first gate pattern forming a channel capacitor with the channel region; a second capacitor electrode in contact with the first active pattern and applied with a second voltage different from the first voltage; and a third capacitor electrode in contact with the second active pattern and applied with the second voltage. The first transistor includes a second gate pattern and a second gate insulating film located between the second gate pattern and the substrate in the vertical direction. A thickness of the first gate insulating film in the vertical direction is greater than a thickness of the second gate insulating film in the vertical direction.

[0007] According to another aspect of the present inventive concept, there is provided a nonvolatile memory device including: a first semiconductor layer; and a second semiconductor layer located above the first semiconductor layer in a vertical direction and including a memory cell array having a plurality of memory cells stacked with each other, wherein the first semiconductor layer includes: a substrate; first and second active patterns arranged to be separated from each other in a first horizontal direction in the substrate; a first gate pattern located above a channel region between the first and second active patterns; and a plurality of capacitor electrodes each extending in the vertical direction and including: a first capacitor electrode in contact with the first gate pattern and to which a first voltage is applied, the first gate pattern forming a channel capacitor with the channel region; a second capacitor electrode in contact with the first active pattern and to which a second voltage different from the first voltage is applied; and a third capacitor electrode in contact with the second active pattern and to which the second voltage is applied.

[0008] According to another aspect of the present inventive concept, there is provided a nonvolatile memory device including a substrate, a plurality of memory cells stacked on the substrate with respect to each other, a voltage generator including a low voltage transistor and a high voltage transistor on the substrate and configured to provide various voltages to the plurality of memory cells, and a vertical capacitor structure. The vertical capacitor structure includes a first active pattern and a second active pattern arranged to be separated from each other in a first horizontal direction in the substrate, a first gate pattern above the substrate between the first active pattern and the second active pattern, a first gate insulating film between the first gate pattern and the substrate in a vertical direction with respect to the substrate, and a plurality of capacitor electrodes each extending in the vertical direction, wherein the plurality of capacitor electrodes include a first capacitor electrode in contact with the first gate pattern and to which a first voltage is applied, the first gate pattern forming a channel capacitor with the substrate, a second capacitor electrode in contact with the first active pattern, to which a second voltage different from the first voltage is applied, and forming a first vertical capacitor with the first capacitor electrode, and a third capacitor electrode in contact with the second active pattern, to which the second voltage is applied, and forming a second vertical capacitor with the first capacitor electrode. The low voltage transistor includes a second gate pattern and a second gate insulating film between the second gate pattern and the substrate in the vertical direction. The high voltage transistor includes a third gate pattern and a third gate insulating film between the third gate pattern and the substrate in the vertical direction. A thickness of the first gate insulating film in the vertical direction is greater than a thickness of the second gate insulating film in the vertical direction or equal to a thickness of the third gate insulating film in the vertical direction. BRIEF DESCRIPTION OF DRAWINGS

[0009] Embodiments of the present inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a perspective view of a vertical capacitor structure according to an embodiment of the present inventive concept;

[0011] Figure 2 is a layout of a vertical capacitor structure according to an embodiment of the present inventive concept; Figure 1

[0012] Figure 3 is a layout of a vertical capacitor structure according to an embodiment of the present inventive concept along Figure 2 ​is a cross-sectional view of a vertical capacitor structure taken along the line III-III' of

[0013] Figure 4 is a cross-sectional view of a vertical capacitor structure according to an embodiment of the inventive concept;

[0014] Figure 5 is a cross-sectional view of a non-volatile memory device according to an embodiment of the inventive concept;

[0015] Figure 6 is a perspective view of a non-volatile memory device according to an embodiment of the inventive concept;

[0016] Figure 7 is a circuit diagram illustrating an example of a memory block according to an embodiment of the inventive concept;

[0017] Figure 8 illustrates a layout of a vertical capacitor structure according to an embodiment of the inventive concept and a high voltage transistor according to a comparative embodiment;

[0018] Figure 9 illustrates a cross-sectional view of a vertical capacitor structure according to an embodiment of the inventive concept and a high voltage transistor according to a comparative embodiment;

[0019] Figure 10 illustrates a cross-sectional view of a vertical capacitor structure according to an embodiment of the inventive concept and a high voltage transistor according to a comparative embodiment;

[0020] Figure 11 illustrates a cross-sectional view of a vertical capacitor structure according to an embodiment of the inventive concept and a low voltage transistor according to a comparative embodiment;

[0021] Figure 12 is a block diagram of a non-volatile memory device according to an embodiment of the inventive concept;

[0022] Figure 13 is a schematic diagram illustrating a non-volatile memory device according to an embodiment of the inventive concept;

[0023] Figure 14 is a cross-sectional view of a non-volatile memory device according to an embodiment of the inventive concept; and

[0024] Figure 15 is a block diagram illustrating an embodiment in which a memory device according to some embodiments is applied to a solid state disk (SSD) system. DETAILED DESCRIPTION

[0025] In the following, the inventive concept will now be described more fully herein

[0026] Figure 1is a perspective view of a vertical capacitor structure 100 according to an embodiment.

[0027] Referring to Figure 1 The vertical capacitor structure 100 can include a substrate 110, a gate insulating film 120, a gate electrode 130, a first active pattern AP1, a second active pattern AP2, and a plurality of capacitor electrodes MC. The substrate 110 can be a semiconductor substrate. For example, the semiconductor substrate can include any one of silicon, silicon-on-insulator, silicon-on-sapphire, germanium, silicon-germanium, and gallium arsenide. For example, the substrate 110 can include a P-type substrate. A main surface of the substrate 110 can extend in a first horizontal direction HD1 and a second horizontal direction HD2.

[0028] The gate insulating film 120 can be located on the substrate 110. For example, the gate insulating film 120 can include a metal oxide having a high dielectric constant, for example, zirconium oxide (ZrO2), aluminum oxide (Al2O3), tantalum oxide (Ta2O3), or hafnium oxide (HfO2). However, the gate insulating film 120 is not limited thereto. The gate insulating film 120 can be formed by using an oxide-based material such as silicon oxide, silicon carbonate, or silicon oxyfluoride. The gate electrode 130 can be located on the gate insulating film 120. The gate electrode 130 can include a metal material such as tungsten (W), tantalum (Ta), etc., a nitride of the metal material, a silicide of the metal material, doped polysilicon, etc., and can be formed by using a deposition process.

[0029] A patterning process can be performed on the gate insulating film 120 and the gate electrode 130. Accordingly, the gate insulating film 120 can be patterned into a plurality of gate insulating patterns, and the gate electrode 130 can be patterned into a plurality of gate patterns including a gate pattern GP or a plurality of gate electrode patterns. Some regions of the substrate 110 can be exposed by the above-described patterning process, and the first active pattern AP1 and the second active pattern AP2 can be formed on the exposed regions of the substrate 110.

[0030] The first active pattern AP1 and the second active pattern AP2 can extend in the second horizontal direction HD2 in / on the substrate 110. For example, the first active pattern AP1 and the second active pattern AP2 can be formed by doping the exposed regions of the substrate 110 with a dopant of a first conductivity type, for example, with N+ impurities. In some examples, the first active pattern AP1 and the second active pattern AP2 can be formed by doping the exposed regions of the substrate 110 with a dopant of a second conductivity type, for example, with P+ impurities. Accordingly, the first active pattern AP1 and the second active pattern AP2 can be referred to as impurity regions. In addition, the first active pattern AP1 and the second active pattern AP2 can be located on both sides of the gate pattern GP. Accordingly, the first active pattern AP1 and the second active pattern AP2 can be referred to as source / drain regions.

[0031] The plurality of capacitor electrodes MC can be located on the gate pattern GP and the first and second active patterns AP1 and AP2, and extend in the vertical direction VD above the substrate 110. The plurality of capacitor electrodes MC can include a conductive material, for example, a metallic material. Accordingly, the plurality of capacitor electrodes MC can be referred to as a plurality of metal contacts (MC). The plurality of capacitor electrodes MC can include a first capacitor electrode MC1, a second capacitor electrode MC2, and a third capacitor electrode MC3. The first capacitor electrode MC1 can be located on the gate pattern GP, the second capacitor electrode MC2 can be located on the first active pattern AP1, and the third capacitor electrode MC3 can be located on the second active pattern AP2.

[0032] The metal layer ML can be located on the plurality of capacitor electrodes MC, and can extend in the second horizontal direction HD2. The metal layer ML can include a first metal line ML1 located above the gate pattern GP and in contact with the first capacitor electrode MC1, a second metal line ML2 located above the first active pattern AP1 and in contact with the second capacitor electrode MC2, and a third metal line ML3 located above the second active pattern AP2 and in contact with the third capacitor electrode MC3. Although not shown in the drawings, another metal layer can be further located above the metal layer ML, and a pillar or a contact including a conductive material can be located between the metal layer ML and the another metal layer.

[0033] For example, the plurality of capacitor electrodes MC or the metal layer ML can include a metallic material including tungsten (W), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), cobalt (Co), and aluminum (Al), or a silicide material including polysilicon, tungsten silicide (WSi), cobalt silicide (CoSi), and nickel silicide (NiSi), or a combination of the metallic material and the silicide material.

[0034] The vertical capacitor structure 100 can use the gate pattern GP and the first and second active patterns AP1 and AP2 as a lower structure, and use the plurality of capacitor electrodes MC as an upper structure. Here, the lower structure of the vertical capacitor structure 100 can have a structure similar to that of a metal-oxide-semiconductor (MOS) transistor. However, unlike the MOS transistor, the same voltage (for example, a second voltage V2 in the first and second active patterns AP1 and AP2) can be applied to the first and second active patterns AP1 and AP2. Accordingly, the lower structure of the vertical capacitor structure 100 can not be used as the MOS transistor, and a conduction current can not flow in a channel region between the first and second active patterns AP1 and AP2. Figure 2

[0035] Figure 2 is a vertical capacitor structure according to an embodiment​Figure 1 The layout of the vertical capacitor structure 100.

[0036] Reference Figure 2 The active pattern AP, including the first active pattern AP1 and the second active pattern AP2, can be separated from each other in the first horizontal direction HD1 and can extend in the second horizontal direction HD2. The gate pattern GP can be located in the upper part between the first active pattern AP1 and the second active pattern AP2 and can extend in the second horizontal direction HD2. Although in Figure 2 The first active pattern AP1 and the gate pattern GP are shown separated in the first horizontal direction HD1; however, the embodiment is not limited thereto. In the embodiment, in terms of layout, the edge of the first active pattern AP1 may contact the edge of the gate pattern GP. Additionally, in the embodiment, some areas of the first active pattern AP1 may overlap with the gate pattern GP.

[0037] A plurality of capacitor electrodes MC, including a first capacitor electrode MC1 and a sixth capacitor electrode MC6, located on the gate pattern GP, ​​are separated from each other in the second horizontal direction HD2. A plurality of capacitor electrodes MC, including a second capacitor electrode MC2 and a fourth capacitor electrode MC4, located on the first active pattern AP1, are separated from each other in the second horizontal direction HD2. A plurality of capacitor electrodes MC, including a third capacitor electrode MC3 and a fifth capacitor electrode MC5, located on the second active pattern AP2, are separated from each other in the second horizontal direction HD2. In an embodiment, the number of capacitor electrodes MC on the gate pattern GP can be equal to the number of capacitor electrodes MC on the first active pattern AP1 or the number of capacitor electrodes MC on the second active pattern AP2.

[0038] A first voltage V1 is applied to the gate pattern GP through multiple capacitor electrodes MC. A second voltage V2, different from the first voltage V1, is applied to the first active pattern AP1 and the second active pattern AP2 through the same multiple capacitor electrodes MC. In some examples, the first voltage V1 is a higher voltage than the power supply voltage VCC, and the second voltage V2 may be lower than the first voltage V1. In some examples, the first voltage V1 is a higher voltage than the power supply voltage VCC, and the second voltage V2 may be equal to the power supply voltage VCC or the ground voltage GND. Here, the power supply voltage VCC can be provided from outside the memory device. Figure 12 The specific circuitry of the peripheral circuitry 720 is shown. In some examples, an internal voltage (e.g., a voltage less than VCC) can be generated internally and supplied to the specific circuitry of the peripheral circuitry 720. Therefore, a plurality of vertical capacitors, including a first vertical capacitor VC1 to a fifth vertical capacitor VC5, can be formed between capacitor electrodes MC to which different voltages are applied.

[0039] For example, a first vertical capacitor VC1 can be formed between a first capacitor electrode MC1 and a second capacitor electrode MC2, and a second vertical capacitor VC2 can be formed between a first capacitor electrode MC1 and a third capacitor electrode MC3. Additionally, a third vertical capacitor VC3 can be formed between a first capacitor electrode MC1 and a fourth capacitor electrode MC4, and a fourth vertical capacitor VC4 can be formed between a first capacitor electrode MC1 and a fifth capacitor electrode MC5. Furthermore, a fifth vertical capacitor VC5 can be formed between a sixth capacitor electrode MC6 and a fifth capacitor electrode MC5. As described above, according to the embodiment, since the plurality of capacitor electrodes MC are located over the entire area of ​​the gate pattern GP, ​​the number of vertical capacitors can be increased.

[0040] Additionally, the gate pattern GP can form a channel region between the first active pattern AP1 and the second active pattern AP2. Figure 3 The vertical capacitor structure 100 includes not only the vertical capacitor VC but also the channel capacitor CC, thus improving the integration density of the capacitors in the vertical capacitor structure 100 and further increasing the capacitance per unit area.

[0041] In an embodiment, the first capacitor electrode MC1 and the second capacitor electrode MC2 may not be adjacent to each other in the first horizontal direction HD1, and the first capacitor electrode MC1 and the third capacitor electrode MC3 may also not be adjacent to each other in the first horizontal direction HD1. For example, the first capacitor electrode MC1, the second capacitor electrode MC2, and the third capacitor electrode MC3 may be arranged in a zigzag pattern in the first horizontal direction HD1. However, the inventive concept is not limited to this. In an embodiment, the first capacitor electrode MC1, the second capacitor electrode MC2, and the third capacitor electrode MC3 may be arranged in a row in the first horizontal direction HD1.

[0042] Figure 3 It is according to the embodiment along Figure 2 A cross-sectional view of the vertical capacitor structure 100 taken from line III-III'.

[0043] Reference Figure 3The first active pattern AP1 and the second active pattern AP2 can be defined in the substrate 110, and the channel region CH can be defined between the first active pattern AP1 and the second active pattern AP2. The first capacitor electrode MC1, the second capacitor electrode MC2, and the third capacitor electrode MC3 can be located on the gate pattern GP and the first active pattern AP1 and the second active pattern AP2, respectively, and the first metal line ML1, the second metal line ML2, and the third metal line ML3 can be located on the first capacitor electrode MC1, the second capacitor electrode MC2, and the third capacitor electrode MC3, respectively. The vertical capacitor structure 100 can further include an interlayer insulating film 140 located above the substrate 110.

[0044] In an embodiment, a first voltage V1 can be applied to the first metal line ML1, and a second voltage V2 different from the first voltage V1 can be applied to the second metal line ML2 and the third metal line ML3. Accordingly, the first voltage V1 can be applied to the gate pattern GP, and the second voltage V2 can be applied to the first active pattern AP1 and the second active pattern AP2. As described above, since the same second voltage V2 is applied to the first active pattern AP1 and the second active pattern AP2, the on-current does not flow in the channel region CH, and the charges in the channel region CH can be in a trapped state. Accordingly, the gate pattern GP can not form a MOS transistor with the first active pattern AP1 and the second active pattern AP2.

[0045] According to an embodiment, the gate pattern GP and the channel region CH can form a channel capacitor CC. The first capacitor electrode MC1 and the second capacitor electrode MC2 can form a first vertical capacitor VC1. The first capacitor electrode MC1 and the third capacitor electrode MC3 can form a second vertical capacitor VC2. As described above, since the vertical capacitor structure 100 can implement the channel capacitor CC, the first vertical capacitor VC1, and the second vertical capacitor VC2 by including the gate pattern GP, the first active pattern AP1, the second active pattern AP2, the first capacitor electrode MC1, the second capacitor electrode MC2, and the third capacitor electrode MC3, the capacitance per unit area can be increased.

[0046] The vertical capacitor structure of the related technology, by excluding the first and second active patterns and only including a gate pattern and capacitor electrodes located on the gate pattern, can only realize a vertical capacitor between the capacitor electrodes. However, the vertical capacitor structure 100 according to the embodiment, by further including the first active pattern AP1 and the second active pattern AP2, and the second capacitor electrode MC2 and the third capacitor electrode MC3 located on the first active pattern AP1 and the second active pattern AP2 respectively, can also obtain a channel capacitor CC located between the channel region CH between the first active pattern AP1 and the second active pattern AP2 and the gate pattern GP. Therefore, the vertical capacitor structure 100 can increase the capacitance that can be obtained in the same area.

[0047] In an embodiment, the voltage level of the second voltage V2 may be lower than the voltage level of the first voltage V1. For example, the voltage level of the second voltage V2 may be similar to that applied to a low-voltage transistor (e.g., Figure 11 The voltage level of the voltage (600 in the text). Here, a low voltage equal to or less than the supply voltage VCC can be applied to the low-voltage transistor (e.g., if VCC is 3V, then the low voltage is equal to or less than 3V). For example, the voltage level of the second voltage V2 can be similar to that applied to the low-voltage transistor ( Figure 11 The first active pattern of 600 in the middle ( Figure 11 The source voltage of 610a) in Figure 11 The voltage level of V_S in the middle or applied to the low-voltage transistor ( Figure 11 The second active pattern of 600) Figure 11 The drain voltage of 610b in the middle ( Figure 11 The voltage level of V_D). Thus, junction breakdown between the first active pattern AP1 and the second active pattern AP2 and the substrate 110 and / or breakdown between the first active pattern AP1 and the second active pattern AP2 can be prevented.

[0048] In an example embodiment, the charge pump 725 (in...) Figure 12 The structure may include a vertical capacitor structure 100 to generate a high voltage. For example, a charge pump 725 may be connected to a first metal line ML1 of the vertical capacitor structure 100 to apply a first voltage V1. A clock buffer (not shown) may output a clock signal CLK or an inverted clock signal CLKB connected to a second metal line ML2 and a third metal line ML3 of the vertical capacitor structure 100 to apply a second voltage V2. The clock signal CLK may be a multiple pulse signal with multiple rising and falling edges between a low voltage level (e.g., ground voltage GND) and a high voltage level (e.g., power supply voltage VCC).

[0049] Figure 4is a cross-sectional view of a vertical capacitor structure 200 according to an embodiment.

[0050] Referring to Figure 4 , the vertical capacitor structure 200 can include a substrate 210, a plurality of active patterns 220, and a plurality of gate patterns 230. The active patterns 220 and the gate patterns 230 can be referred to as a lower structure of the vertical capacitor structure 200. The active patterns 220 can be formed in the substrate 210 by doping a first conductive type, for example, N+ impurities. In some examples, the active patterns 220 can be formed in the substrate 210 by doping a second conductive type, for example, P+ impurities. The active patterns 220 can be arranged to be separated from each other at a certain interval in a first horizontal direction HD1 and can extend in a second horizontal direction HD2. The gate patterns 230 can be located above the substrate 210, and a gate insulating film (for example, 120 in FIG. 1) can be located between the gate patterns 230 and the substrate 210. The gate patterns 230 can be arranged to be separated from each other at a certain interval in the first horizontal direction HD1 and can extend in the second horizontal direction HD2. Figure 1

[0051] The vertical capacitor structure 200 can further include capacitor electrodes 240 and a metal layer 250. The capacitor electrodes 240 and the metal layer 250 can be referred to as an upper structure of the vertical capacitor structure 200. In an embodiment, a first voltage V1 can be applied to the capacitor electrodes 240 located on the gate patterns 230, respectively, and a second voltage V2 can be applied to the capacitor electrodes 240 located on the active patterns 220, respectively.

[0052] Different voltages (for example, the first voltage V1 and the second voltage V2) can be applied to the capacitor electrodes 240 adjacent to each other in the first horizontal direction HD1. Accordingly, the adjacent capacitor electrodes 240 can form a vertical capacitor VC. In addition, since the second voltage V2 is applied to all the active patterns 220, on-current does not flow in a channel region CH between the adjacent active patterns 220. Accordingly, each of the gate patterns 230 and the channel region CH can form a channel capacitor CC.

[0053] Figure 5 is a cross-sectional view of a nonvolatile memory device 300 according to an embodiment. Figure 6 is a perspective view of the nonvolatile memory device 300 according to an embodiment.

[0054] Referring to Figure 5 and Figure 6 ​The substrate 310 can have a memory cell region 310a and a peripheral circuit region 310b. Although not illustrated in the drawing, an element isolation film can be arranged between the memory cell region 310a and the peripheral circuit region 310b. The element isolation film can extend in the second horizontal direction HD2. The element isolation film can include an insulating material including a silicon oxide film or a silicon nitride film.

[0055] A plurality of memory cell strings (for example, Figure 7 MCSs in FIG. 1) can be located above the memory cell region 310a, and each memory cell string can include a vertical channel structure or pillar P and a plurality of memory cells. The vertical channel structure P can extend in the vertical direction VD, and the plurality of memory cells can be arranged adjacent to each other in the vertical direction VD along the vertical channel structure P.

[0056] A plurality of insulating films IL can be provided above the memory cell region 310a, for example, the plurality of insulating films IL can include an insulating material such as silicon oxide. The plurality of vertical channel structures P can penetrate the plurality of insulating films IL in the vertical direction VD. For example, the plurality of vertical channel structures P can penetrate the plurality of insulating films IL to contact the substrate 310.

[0057] In detail, the surface layer S of each vertical channel structure P can include a silicon material of a first type (for example, P-type) and can function as a channel region CH. Meanwhile, the inner layer I of each vertical channel structure P can include an insulating material such as silicon oxide or an air gap. The plurality of vertical channel structures P can be arranged to be separated from each other in the first horizontal direction HD1 and the second horizontal direction HD2. For example, the plurality of vertical channel structures P can be formed in a ring shape. However, the present inventive concept is not limited thereto. The plurality of vertical channel structures P can be formed in the form of an elliptic cylinder or a square pillar.

[0058] A charge storage layer CS can be provided along exposed surfaces of the plurality of insulating films IL and exposed surfaces of the plurality of vertical channel structures P. The charge storage layer CS can include a gate insulating layer (or also referred to as a "tunnel insulating layer"), a charge trapping layer, and a blocking insulating layer. For example, the charge storage layer CS can have an oxide-nitride-oxide (ONO) structure. In addition, gate electrodes GE including a ground select line GSL, word lines WL1 to WLn, and a string select line SSL can be provided on the exposed surfaces of the charge storage layer CS. Here, n can be a positive integer.

[0059] The word lines WL1 to WLn, the charge storage layer CS, and the vertical channel structure P can form a memory cell transistor or a memory cell (for example, Figure 7 MCT1 to MCT8 in FIG. 1). The ground select line GSL, the charge storage layer CS, and the vertical channel structure P can form a ground select transistor (for example, Figure 7In GST). A string select line (SSL), a charge storage layer (CS), and a vertical channel structure (P) can form a string select transistor (e.g., GST). Figure 7 SST in (the context of SST).

[0060] Multiple insulating films IL can be located between word lines that are adjacent to each other in the vertical direction VD.

[0061] The drain or drain contact DR can be disposed on multiple vertical channel structures P. For example, the drain or drain contact DR can comprise silicon material doped with impurities of a second conductivity type (e.g., N-type). Bit lines can be disposed on the drain contact DR.

[0062] In the peripheral circuit region 310b, for example, a circuit such as... Figures 1 to 3 Vertical capacitor structure 100 or Figure 4 Vertical capacitor structures such as the vertical capacitor structure 200. Therefore, the above refers to... Figures 1 to 4 The given description applies to this embodiment, and redundant descriptions will be omitted. Specifically, a first active pattern 320a and a second active pattern 320b doped with impurities of a second conductivity type (N+) can be defined in the peripheral circuit region 310b. In some examples, the first active pattern 320a and the second active pattern 320b doped with impurities of a first conductivity type (P+) can be defined in the peripheral circuit region 310b. A channel region CH can be formed between the first active pattern 320a and the second active pattern 320b, and a gate pattern 330 can be located above the channel region CH.

[0063] Gate insulating film (e.g., Figure 1 The 120 in the diagram can be located between the gate pattern 330 and the channel region CH. A channel capacitor CC can be formed between the gate pattern 330 and the channel region CH. In embodiments, such as... Figures 1 to 3 Vertical capacitor structure 100 or Figure 4 The thickness of the gate insulating film in a vertical capacitor structure such as 200 can be greater than the distance between two adjacent word lines in the vertical direction VD. The distance between two adjacent word lines in the vertical direction VD can be the thickness of the corresponding insulating film IL.

[0064] Multiple capacitor electrodes 340 may be located on the gate pattern 330 and the first active pattern 320a and the second active pattern 320b, and may extend in the vertical direction VD. An interlayer insulating film 360 may be located above the substrate 310, and the multiple capacitor electrodes 340 may penetrate the interlayer insulating film 360 in the vertical direction VD. A metal layer 350 may be located on the multiple capacitor electrodes 340.

[0065] Figure 7is an exemplary circuit diagram illustrating a memory block BLK according to an embodiment.

[0066] Referring to Figure 7 , the memory block BLK can be located Figure 5 or Figure 6 in the memory cell region 310a. The memory block BLK can include memory cell strings MCS11 to MCS31, MCS12 to MCS32, and MCS13 to MCS33, word lines WL1 to WL8, ground select lines GSL1 to GSL3, string select lines SSL1 to SSL3, and a common source line CSL.

[0067] The memory cell strings MCS11 to MCS31 are disposed between the first bit line BL1 and the common source line CSL. The memory cell strings MCS12 to MCS32 are disposed between the second bit line BL2 and the common source line CSL. The memory cell strings MCS13 to MCS33 are disposed between the third bit line BL3 and the common source line CSL. Each memory cell string (e.g., MCS11) can include a string select transistor SST, a plurality of memory cells MC1 to MC8, and a ground select transistor GST connected in series.

[0068] The string select transistor SST is connected to a corresponding one of the string select lines SSL1 to SSL3. The plurality of memory cells MC1 to MC8 are connected to corresponding ones of the word lines WL1 to WL8, respectively. The ground select transistor GST is connected to a corresponding one of the ground select lines GSL1 to GSL3. The string select transistor SST is connected to a corresponding one of the bit lines BL1 to BL3, and the ground select transistor GST is connected to the common source line CSL.

[0069] In the present embodiment, the same height word lines (e.g., WL1) are commonly connected to each other, the string select lines SSL1 to SSL3 are separated from each other, and the ground select lines GSL1 to GSL3 are separated from each other. Although three string select lines SSL1 to SSL3 are shown to share the same height word lines in Figure 7 , the inventive concept is not limited thereto. For example, two string select lines can share the same height word lines. As another example, four string select lines can share the same height word lines.

[0070] Figure 8 Layouts of a vertical capacitor structure 400 according to an embodiment and a high voltage transistor 500 according to a comparative embodiment are shown. Here, a high voltage greater than the power supply voltage VCC (e.g., greater than 3V if VCC is 3V) can be applied to the high voltage transistor.

[0071] Referring to Figure 8The vertical capacitor structure 400 can include the active pattern 410 and the gate pattern 420 both extending in the second horizontal direction HD2. The active pattern 410 can include a first active pattern 410a and a second active pattern 410b separated from each other in the first horizontal direction HD1. The gate pattern 420 can include a first gate pattern 420a, a second gate pattern 420b, and a third gate pattern 420c separated from each other in the first horizontal direction HD1.

[0072] The plurality of first capacitor electrodes 430 extending in the vertical direction VD can be located above each of the first gate pattern 420a, the second gate pattern 420b, and the third gate pattern 420c. The plurality of second capacitor electrodes 440 extending in the vertical direction VD can be located above the first active pattern 410a. The plurality of third capacitor electrodes 450 extending in the vertical direction VD can be located above the second active pattern 410b. In an embodiment, the number of the first capacitor electrodes 430 located above each of the first gate pattern 420a, the second gate pattern 420b, and the third gate pattern 420c can be the same as or similar to the number of the corresponding second capacitor electrodes 440 and the number of the third capacitor electrodes 450.

[0073] In an embodiment, a first voltage V1 can be applied to the gate pattern through the plurality of first capacitor electrodes 430, a second voltage V2 can be applied to the first active pattern 410a through the plurality of second capacitor electrodes 440, and the second voltage V2 can be applied to the second active pattern 410b through the plurality of third capacitor electrodes 450. Accordingly, the on-current does not flow in the channel region between the first active pattern 410a and the second active pattern 410b, and the first gate pattern 420a can form the channel region and the channel capacitor CC at the lower portion.

[0074] In addition, the first capacitor electrode 430 and the second capacitor electrode 440 adjacent to each other can form the vertical capacitor VC, and the first capacitor electrode 430 and the third capacitor electrode 450 adjacent to each other can form the vertical capacitor VC. According to the present embodiment, since the first capacitor electrode 430 is located on the entire area of each of the first gate pattern 420a, the second gate pattern 420b, and the third gate pattern 420c, the number of the vertical capacitors can also be increased. Accordingly, the capacitance of the vertical capacitor structure 400 can be very large.

[0075] Meanwhile, the high voltage transistor 500 can include the active pattern 510 and the gate pattern 520 both extending in the second horizontal direction HD2. The active pattern 510 can include a first active pattern 510a and a second active pattern 510b separated from each other in the first horizontal direction HD1. The gate pattern 520 can include a first gate pattern 520a, a second gate pattern 520b, and a third gate pattern 520c separated from each other in the first horizontal direction HD1.

[0076] The first metal contact 530 extending in the vertical direction VD can be located above each of the first gate pattern 520a, the second gate pattern 520b, and the third gate pattern 520c. The second metal contact 540 extending in the vertical direction VD can be located above the first active pattern 510a. The third metal contact 550 extending in the vertical direction VD can be located above the second active pattern 510b. Here, the number of the first metal contact 530 located above each of the first gate pattern 520a, the second gate pattern 520b, and the third gate pattern 520c is limited in consideration of plasma damage. Accordingly, the number of the first metal contact 530 located above each of the first gate pattern 520a, the second gate pattern 520b, and the third gate pattern 520c can be much less than the number of the second metal contact 540 and the number of the third metal contact 550.

[0077] In addition, a high voltage V_H can be applied to the gate pattern 520 through the plurality of first metal contacts 530, a source voltage V_S can be applied to the first active pattern 510a through the plurality of second metal contacts 540, and a drain voltage V_D can be applied to the second active pattern 510b through the plurality of third metal contacts 550. Here, the source voltage V_S and the drain voltage V_D can be different from each other, and thus, a conduction current can flow in a channel region between the first active pattern 510a and the second active pattern 510b adjacent to each other. Accordingly, the first gate pattern 520a can form a MOS transistor with the first active pattern 510a and the second active pattern 510b, and the first gate pattern 520a can not form a channel region and a channel capacitor CC in a lower structure of the high voltage transistor 500. Here, a voltage level of the high voltage V_H can be higher than a power supply voltage VCC.

[0078] Figure 9 A cross-sectional view of a vertical capacitor structure 400 according to an embodiment and a high voltage transistor 500 according to a comparative embodiment are illustrated.

[0079] Referring to Figure 8 and Figure 9In the vertical capacitor structure 400, the first gate pattern 420a can have a first length L along the first horizontal direction HD1. For example, the first length L can be as short as a gate length of a low voltage transistor of the related art. A spacing S between the first active pattern 410a and the second active pattern 410b can be the same as a length of the channel region CH along the first horizontal direction HD1. In an embodiment, the spacing S between the first active pattern 410a and the second active pattern 410b can be smaller than the first length L of the first gate pattern 420a. However, the inventive concept is not limited thereto. In some embodiments, the spacing S between the first active pattern 410a and the second active pattern 410b can be equal to the first length L of the first gate pattern 420a.

[0080] The first, second, and third capacitor electrodes 430, 440, and 450 can be located on the first gate pattern 420a, the first active pattern 410a, and the second active pattern 410b, respectively, and the metal layer ML can be located on the first, second, and third capacitor electrodes 430, 440, and 450. A first voltage V1 can be applied to the first gate pattern 420a through the first capacitor electrode 430, and a second voltage V2 can be applied to the first and second active patterns 410a and 410b through the second and third capacitor electrodes 440 and 450, respectively.

[0081] Meanwhile, the high voltage transistor 500 can include an impurity doped region, for example, an N-doped region 505 (e.g., a lightly doped drain (LDD)), defined in the substrate SUB, and first and second active patterns 510a and 510b (e.g., N + doped regions) can be defined in the N-doped region 505. The first gate pattern 520a can have a second length L' along the first horizontal direction HD1. Since a high voltage V_H is applied to the first gate pattern 520a, the second length L' can be greater than the first length L. Here, a spacing S' between the first and second active patterns 510a and 510b can be greater than the length L' of the first gate pattern 520a.

[0082] The first, second, and third metal contacts 530, 540, and 550 can be located on the first gate pattern 520a, the first active pattern 510a, and the second active pattern 510b, respectively, and the metal layer ML can be located on the first, second, and third metal contacts 530, 540, and 550. A high voltage V_H can be applied to the first gate pattern 520a through the first metal contact 530, and a source voltage V_S and a drain voltage V_D can be applied to the first and second active patterns 510a and 510b through the second and third metal contacts 540 and 550, respectively.

[0083] Although not shown, the thickness of the gate insulating film between the first gate pattern 420a and the channel region CH of the vertical capacitor structure 400 in the vertical direction VD can be the same as or similar to the thickness of the gate insulating film between the first gate pattern 520a and the channel region CH' of the high-voltage transistor 500 in the vertical direction VD.

[0084] Figure 10 Cross-sectional views of a vertical capacitor structure 400 according to an embodiment and a high-voltage transistor 500 according to a comparative embodiment are shown.

[0085] Referring to Figures 8 to 10 In the vertical capacitor structure 400, a first spacing SI between an edge of the first active pattern 410a and a first edge of the first gate pattern 420a along the first horizontal direction HD1 can be very small. Also, a first spacing SI' between an edge of the second active pattern 410b and a second edge of the first gate pattern 420a opposite the first edge along the first horizontal direction HD1 can be very small. Although not shown, an N-doped (e.g., a lightly doped drain (LDD)) region can be located within (e.g., extend completely across the first horizontal direction HD1) each of the first spacing SI and the first spacing SI'. Further, a first gate spacer can be formed on (and cover) the first edge of the first gate pattern 420a and the first edge of the gate insulating film, and a second gate spacer can be formed on (and cover) the second edge of the first gate pattern 420a opposite the first edge and the second edge of the gate insulating film opposite the first edge. In an embodiment, the vertical capacitor structure 400 can not include the first spacing SI and the first spacing SI'. In an example embodiment, a right-side partial region of the first active pattern 410a can overlap a left-side partial region of the first gate pattern 420a. Likewise, a left-side partial region of the second active pattern 410b can overlap a right-side partial region of the first gate pattern 420a.

[0086] A second spacing S2 between the first edge of the first gate pattern 420a and the second capacitor electrode 440 along the first horizontal direction HD1 can be relatively small (e.g., smaller than the fourth spacing S4 of the high-voltage transistor 500). Thus, a spacing between the first capacitor electrode 430 and the second capacitor electrode 440 can be relatively small, and a capacitance of a first capacitor electrode VC1 formed by the first capacitor electrode 430 and the second capacitor electrode 440 can be relatively large.

[0087] Likewise, a second spacing S2' between a second edge of the first gate pattern 420a and the third capacitor electrode 450 along the first horizontal direction HD1 can be relatively small. Accordingly, a spacing between the first capacitor electrode 430 and the third capacitor electrode 450 can be relatively small, and a capacitance of a second vertical capacitor VC2 formed by the first capacitor electrode 430 and the third capacitor electrode 450 can be relatively large.

[0088] Meanwhile, the high voltage transistor 500 can include an impurity doped region, e.g., an N doped region 505, defined in the substrate SUB, and the first active pattern 510a and the second active pattern 510b can be defined in the substrate SUB. A third spacing S3 between an edge of the first active pattern 510a and a first edge of the first gate pattern 520a along the first horizontal direction HD1 can be greater than the first spacing S1. Also, a third spacing S3' between an edge of the second active pattern 510b and a second edge of the first gate pattern 520a opposite to the first edge along the first horizontal direction HD1 can be greater than the first spacing S1'. In an example embodiment, when the vertical capacitor structure 400 includes an N doped (e.g., a lightly doped drain LDD) region within the first spacing S1 and the first spacing S1', the first spacing S1 can be smaller than the third spacing S3, and the first spacing S1' can be smaller than the third spacing S3'.

[0089] A fourth spacing S4 between the first edge of the first gate pattern 520a and the second metal contact 540 along the first horizontal direction HD1 can be greater than the second spacing S2. Accordingly, a spacing between the first metal contact 530 and the second metal contact 540 can be relatively large, and a capacitance between the first metal contact 530 and the second metal contact 540 can be relatively small.

[0090] Likewise, a fourth spacing S4' between a second edge of the first gate pattern 520a and the third metal contact 550 along the first horizontal direction HD1 can be greater than the second spacing S2'. Accordingly, a spacing between the first metal contact 530 and the third metal contact 550 can be relatively large, and a capacitance between the first metal contact 530 and the third metal contact 550 can be relatively small.

[0091] In an example embodiment, when the vertical capacitor structure 400 includes an N doped (e.g., a lightly doped drain LDD) region within the first spacing S1 and the first spacing S1', the second spacing S2 can be smaller than the fourth spacing S4, and the second spacing S2' can be smaller than the fourth spacing S4'.

[0092] Figure 11 is a cross-sectional view illustrating a vertical capacitor structure 400 according to an embodiment and a low voltage transistor 600 according to a comparative embodiment.

[0093] Referring toFigure 11 In the vertical capacitor structure 400, a length along the vertical direction VD between the first gate pattern 420a and the channel region CH (i.e., a first thickness TH1 of the gate insulating film 120) can be large (e.g., the first thickness TH1 is larger than a second thickness TH2 of the gate insulating film in the low voltage transistor 600). For example, the first thickness TH1 is at least 2 times larger than the second thickness TH2. Thus, the first voltage V1 as a high voltage can be applied to the first gate pattern 420a through the metal layer ML and the first capacitor electrode 430. Meanwhile, the second voltage V2 can be applied to the first active pattern 410a and the second active pattern 410b, respectively, through the metal layer ML, the second capacitor electrode 440, and the third capacitor electrode 450. In an embodiment, a voltage level of the second voltage V2 can be significantly lower than a voltage level of the first voltage V1. Figure 1 Meanwhile, the low voltage transistor 600 can include a substrate SUB, a first active pattern 610a, a second active pattern 610b, a gate pattern 620, a first metal contact 630, a second metal contact 640, a third metal contact 650, and a metal layer ML. Here, the first active pattern 610a and the second active pattern 610b can be defined in a well 605 in the substrate SUB. A low voltage V_L can be applied to the gate pattern 620 through the metal layer ML and the first metal contact 630. Here, a voltage level of the low voltage V_L can be a power supply voltage VCC or less than VCC. Thus, a length in the vertical direction VD between the gate pattern 620 and the channel region CH" (i.e., a second thickness TH2 of the gate insulating film 120) can be smaller than the first thickness TH1 of the gate insulating film in the vertical capacitor structure 400.

[0094] Figure 1 Meanwhile, the low voltage transistor 600 can include a substrate SUB, a first active pattern 610a, a second active pattern 610b, a gate pattern 620, a first metal contact 630, a second metal contact 640, a third metal contact 650, and a metal layer ML. Here, the first active pattern 610a and the second active pattern 610b can be defined in a well 605 in the substrate SUB. A low voltage V_L can be applied to the gate pattern 620 through the metal layer ML and the first metal contact 630. Here, a voltage level of the low voltage V_L can be a power supply voltage VCC or less than VCC. Thus, a length in the vertical direction VD between the gate pattern 620 and the channel region CH" (i.e., a second thickness TH2 of the gate insulating film 120) can be smaller than the first thickness TH1 of the gate insulating film in the vertical capacitor structure 400.

[0095] In addition, a source voltage V_S can be applied to the first active pattern 610a through the second metal contact 640, and a drain voltage V_D can be applied to the second active pattern 610b through the third metal contact 650. Here, the source voltage V_S and the drain voltage V_D can be different from each other, and a current can flow in the channel region CH". Thus, a channel capacitor can not be formed between the gate pattern 620 and the channel region CH".

[0096] In an embodiment, a voltage level of the second voltage V2 can be lower than a voltage level of the first voltage V1. For example, the voltage level of the second voltage V2 can be similar to a voltage level of the source voltage V_S or the drain voltage V_D of the low voltage transistor 600. By doing so, junction breakdown between the first active pattern 410a and the second active pattern 410b and / or breakdown between the first active pattern 410a and the second active pattern 410b can be prevented. ​

[0097] Although not shown, in the first horizontal direction HD1, the gate length of the first gate pattern 420a of the vertical capacitor structure 400 can be the same as or similar to the gate length of the gate pattern 620 of the low voltage transistor 600. In this case, the gate length of the gate pattern 620 can be the minimum length used for the low voltage transistor in the memory device (e.g., the critical feature size of the memory device).

[0098] Figure 12 is a block diagram of a non-volatile memory device 700 according to an embodiment.

[0099] Referring to Figure 12 , the non-volatile memory device 700 can include a memory cell array 710 and a peripheral circuit 720, where the peripheral circuit 720 can include a row decoder 721, a page buffer unit 722, a control logic 723, and a voltage generator 724. Although not shown in Figure 12 , the peripheral circuit 720 can further include a data input / output circuit or an input / output interface, etc. In addition, the peripheral circuit 720 can further include column logic, a pre-decoder, a temperature sensor, a command decoder, an address decoder, etc. A power supply voltage VCC can be applied to the non-volatile memory device 700. Voltages such as the power supply voltage VCC, a low voltage, and a high voltage can be applied to the peripheral circuit 720. The voltage level of the low voltage can be equal to or less than the power supply voltage VCC, and the voltage level of the high voltage can be greater than the power supply voltage VCC.

[0100] The memory cell array 710 can be connected to the page buffer unit 722 through a bit line BL, and can be connected to the row decoder 721 through a word line WL, a string selection line SSL, and a ground selection line GSL. The memory cell array 710 can include a plurality of memory cells. For example, the plurality of memory cells can be flash memory cells. Hereinafter, embodiments of the inventive concept will now be described in detail taking the case where the plurality of memory cells are NAND flash memory cells as an example. However, the inventive concept is not limited thereto. In some embodiments, the plurality of memory cells can be resistive memory cells such as resistive RAM (ReRAM), phase change RAM (PRAM), or magnetic RAM (MRAM).

[0101] In an embodiment, the memory cell array 710 can include a three-dimensional memory cell array, where the three-dimensional memory cell array can include a plurality of NAND strings, and each NAND string can include memory cells connected to word lines that are vertically stacked on a substrate, respectively. Suitable configurations of three-dimensional memory arrays, where the three-dimensional memory arrays are configured as a plurality of horizontal levels sharing word lines and / or bit lines between the horizontal levels, are described in the following patent documents, which are incorporated herein by reference: U.S. Patent Publication No. 7,679,133; U.S. Patent Publication No. 8,553,466; U.S. Patent Publication No. 8,654,587; U.S. Patent Publication No. 8,559,235; and U.S. Patent Application Publication No. 2011 / 0233648.

[0102] The control logic 723 can program data to and read data from the memory cell array 710 based on the command CMD, the address ADDR, and the control signal CTRL, or can output various control signals such as a voltage control signal CTRL_vol, a row address X-ADDR, and a column address Y-ADDR to erase data stored in the memory cell array 710. Thereby, the control logic 723 can generally control various operations in the nonvolatile memory device 700.

[0103] The peripheral circuit 720 can include a plurality of high-voltage transistors 500 and a plurality of low-voltage transistors 600. For example, the voltage generator 724 can include a plurality of high-voltage transistors 500 and a plurality of low-voltage transistors 600.

[0104] The voltage generator 724 can generate various types of voltages to perform programming, reading, and erasing operations on the memory cell array 710 based on the voltage control signal CTRL_vol. In detail, the voltage generator 724 can generate a word line voltage (VWL), e.g., a program voltage, a read voltage, a pass voltage, an erase verify voltage, or a program verify voltage, etc. In addition, the voltage generator 724 can also generate a string selection line voltage and a ground selection line voltage based on the voltage control signal CTRL_vol.

[0105] In an embodiment, the voltage generator can include a charge pump 725. The charge pump 725 can perform a positive charge pump operation or a negative charge pump operation based on the voltage control signal CTRL_vol. The charge pump 725 can generate, for example, a program voltage or an erase voltage according to the charge pump operation. In the present embodiment, the charge pump 725 can include a vertical capacitor structure. For example, the charge pump 725 can include Figures 1 to 3 the vertical capacitor structure 100 shown in FIG. 1, Figure 4 the vertical capacitor structure 200 shown in FIG. 2, Figure 5 and Figure 6 the vertical capacitor structure 300 shown in FIG. 3, andFigures 8 to 11 The vertical capacitor structure 400 is shown.

[0106] In detail, the charge pump 725 can include a vertical capacitor structure including a gate pattern, a gate insulating film between the gate pattern and a substrate, an active pattern in the substrate, and a plurality of capacitor electrodes extending in a vertical direction on the gate pattern and the active pattern. Here, a first voltage can be applied to the gate pattern, and a second voltage different from the first voltage can be applied to the active pattern. In an embodiment, the charge pump 725 can be connected to the gate pattern of the vertical capacitor structure, and a clock buffer (not shown) in the peripheral circuit 720 can be connected to a first active pattern and a second active pattern of the vertical capacitor structure. For example, a clock signal CLK or an inverted clock signal CLKB output from the clock buffer can be transmitted to the first active pattern and the second active pattern of the vertical capacitor structure. The voltage applied to the gate pattern can be a higher voltage (e.g., a voltage greater than 3 V) greater than the power supply voltage VCC. Accordingly, the thickness of the gate insulating film between the gate pattern and the substrate in the vertical capacitor structure according to the present embodiment can be greater than the thickness of the gate insulating film between the gate pattern and the substrate of a low-voltage transistor. In addition, the vertical capacitor structure according to the present embodiment can have a spacing between the first active pattern and the second active pattern that can be equal to or less than the length of the gate pattern. Since the on-current does not flow in the channel region between the active patterns, and the charge does not exist in a trapped state, the vertical capacitor structure can obtain a channel capacitance between the gate pattern and the channel region. In addition, since the first voltage and the second voltage as different voltages are applied between the plurality of capacitor electrodes adjacent to each other, the vertical capacitor structure can obtain a vertical capacitance between the plurality of capacitor electrodes.

[0107] Accordingly, the integration of the capacitor of the charge pump 725 can be improved to increase the capacitance per unit area. Accordingly, since the capacity of the charge pump 725 can be increased while reducing the area of the charge pump 725, the space efficiency of the charge pump 725 can be improved. In addition, the area of the nonvolatile memory device 700, i.e., the chip size, can be reduced by reducing the area of the charge pump 725.

[0108] The row decoder 721 can select one of the plurality of memory blocks in response to a row address X-ADDR, select one of the word lines WL of the selected memory block, and select one of the string selection lines SSL. The page buffer unit 722 can select some of the bit lines BL in response to a column address Y-ADDR. In detail, the page buffer unit 722 operates as a write driver or a sense amplifier according to the operation mode.

[0109] Figure 13is a view schematically showing a nonvolatile memory device 800 according to an embodiment.

[0110] Referring to Figure 13 , the nonvolatile memory device 800 can include a first semiconductor layer L1 and a second semiconductor layer L2, in which the second semiconductor layer L2 can be stacked on the first semiconductor layer L1 in a vertical direction VD. In detail, the first semiconductor layer L1 can be located at a lower portion of the second semiconductor layer L2 in the vertical direction VD. Accordingly, the first semiconductor layer L1 can be located close to a substrate.

[0111] In an embodiment, Figure 12 the memory cell array 710 can be formed in the second semiconductor layer L2, Figure 12 the peripheral circuit 720 can be formed in the first semiconductor layer L1. Accordingly, the nonvolatile memory device 800 can have a structure in which the memory cell array 710 is located above the peripheral circuit 720, i.e., a cell over periphery (COP) structure. The COP structure can effectively reduce an area in the vertical direction VD and can increase the integration of the nonvolatile memory device 800.

[0112] In an embodiment, the first semiconductor layer L1 can include a substrate, and a pattern for wiring semiconductor elements such as transistors and elements on the substrate can be formed to form a circuit including the peripheral circuit 720 in the first semiconductor layer L1. After the circuit is formed in the first semiconductor layer L1, the second semiconductor layer L2 including the memory cell array 710 can be formed, and a pattern for electrically connecting the word lines WL and the bit lines BL of the memory cell array 710 with the circuit formed in the first semiconductor layer L1 can be formed.

[0113] Figure 14 is a cross-sectional view of a nonvolatile memory device 900 according to an embodiment.

[0114] Referring to Figure 14 , the nonvolatile memory device 900 can correspond to Figure 13 an embodiment of the nonvolatile memory device 800. The nonvolatile memory device 900 can include a first semiconductor layer L1 and a second semiconductor layer L2, in which a vertical capacitor structure can be formed in the first semiconductor layer L1 and a memory cell array can be formed in the second semiconductor layer L2.

[0115] The vertical capacitor structure formed in the first semiconductor layer L1 can correspond to Figures 1 to 3 the vertical capacitor structure 100 shown in FIG. 1, Figure 4 the vertical capacitor structure 200 shown in FIG. 2, Figure 5 and Figure 6The vertical capacitor structure 300 shown above and Figures 8 to 11 The vertical capacitor structure 400 shown above is the same. Thus, the above description can be applied to the present embodiment, and redundant descriptions will be omitted.

[0116] In detail, the first semiconductor layer L1 can include a substrate 910, a first active pattern 910a, a second active pattern 910b, a gate pattern 920, a capacitor electrode 930, a first metal layer 940, a second metal layer 950, and a third metal layer 960. A first pillar 945 can be located between the first metal layer 940 and the second metal layer 950, and a second pillar 955 can be located between the second metal layer 950 and the third metal layer 960. However, the inventive concept is not limited thereto. According to an embodiment, the number of metal layers can be variously changed. The second semiconductor layer L2 can include a metal contact 970 and a fourth metal layer 980. For example, the metal contact 970 can be implemented as a through silicon via (TSV).

[0117] In the present embodiment, a first voltage V1 can be applied to the gate pattern 920 through the metal contact 970 (i.e., TSV), and a second voltage V2 can be applied to the first active pattern 910a and the second active pattern 910b through the metal contact 970 (i.e., TSV). Thus, a conduction current does not flow in a channel region CH between the first active pattern 910a and the second active pattern 910b, and the gate pattern 920 and the channel region CH can form a channel capacitor CC. In addition, the capacitor electrodes 930 adjacent to each other can form a vertical capacitor VC.

[0118] Figure 15 is a block diagram illustrating an embodiment in which a memory device according to some embodiments is applied to a solid state drive (SSD) system 1000.

[0119] Referring to Figure 15 , the SSD system 1000 can include a host 1100 and an SSD 1200. The SSD 1200 exchanges a signal (SIG) with the host through a signal connector, and receives power (PWR) through a power connector. The SSD 1200 can include an SSD controller 1210, an auxiliary power supply 1220, and memory devices 1230, 1240, and 1250. The memory devices 1230, 1240, and 1250 can be vertically stacked NAND flash memory devices. Here, the memory devices 1230, 1240, and 1250 can be implemented by using the above-described embodiments with reference to Figures 1 to 14

[0120] ​According to the inventive concept, the vertical capacitor structure can use a gate pattern and an active pattern as a lower structure, use capacitor electrodes located on the gate pattern and the active pattern as an upper structure, and apply the same voltage to the active pattern. Accordingly, a vertical capacitance between the capacitor electrodes and a channel capacitance between the channel regions of the active patterns and the gate pattern can be obtained. Accordingly, the integration of the capacitor can be improved and the capacitance per unit area can be increased.

[0121] In addition, according to the inventive concept, a charge pump included in a peripheral circuit region of a nonvolatile memory device can have a vertical capacitor structure. Accordingly, since the capacity of the charge pump can be increased while reducing the area of the charge pump, the space efficiency of the charge pump can be improved. In addition, the area of the nonvolatile memory device, i.e., the chip size, can be reduced by reducing the area of the charge pump.

[0122] As described above, example embodiments have been disclosed in the drawings and the inventive concept. Although the embodiments in the inventive concept have been described using specific language, the specific language is used to describe the spirit of the inventive concept, and such specific language is not intended to limit the scope of the inventive concept defined by the appended claims. Although the inventive concept has been specifically shown and described with reference to embodiments of the inventive concept, it is understood that various changes in form and details can be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A nonvolatile memory device, the nonvolatile memory device comprising: a substrate including a memory cell region and a peripheral circuit region; a memory cell string including a vertical channel structure and a plurality of memory cells located in the memory cell region; a voltage generator located in the peripheral circuit region, the voltage generator including a first transistor and configured to provide various voltages to the plurality of memory cells; an interlayer insulating film located in the peripheral circuit region; and a vertical capacitor structure located in the peripheral circuit region, wherein the vertical capacitor structure includes: a first active pattern and a second active pattern arranged to be separated from each other in a first horizontal direction; a first gate pattern located above a channel region between the first active pattern and the second active pattern; a first gate insulating film located between the first gate pattern and the substrate in a vertical direction with respect to the substrate; and a plurality of capacitor electrodes each extending in the vertical direction, wherein the plurality of capacitor electrodes includes: a first capacitor electrode in contact with the first gate pattern and applied with a first voltage, the first gate pattern forming a channel capacitor with the channel region; a second capacitor electrode in contact with the first active pattern and applied with a second voltage different from the first voltage; and a third capacitor electrode in contact with the second active pattern and applied with the second voltage, wherein the first transistor includes a second gate pattern and a second gate insulating film located between the second gate pattern and the substrate in the vertical direction, wherein a thickness of the first gate insulating film in the vertical direction is greater than a thickness of the second gate insulating film in the vertical direction, wherein the plurality of capacitor electrodes penetrates the interlayer insulating film in the vertical direction, wherein the first capacitor electrode, the interlayer insulating film, and the second capacitor electrode form a first vertical capacitor, and wherein the first capacitor electrode, the interlayer insulating film, and the third capacitor electrode form a second vertical capacitor. the voltage generator further includes:

2. The nonvolatile memory device of claim 1, wherein, a second transistor including a third gate pattern and a third gate insulating film located between the third gate pattern and the substrate in the vertical direction, wherein the nonvolatile memory device is configured such that a high voltage greater than a power supply voltage is applied to the second transistor, and wherein a thickness of the third gate insulating film in the vertical direction is the same as a thickness of the first gate insulating film in the vertical direction. a length of the first gate pattern in the first horizontal direction is smaller than a length of the third gate pattern in the first horizontal direction.

3. The nonvolatile memory device of claim 2, wherein, ​ 4. The nonvolatile memory device of claim 2, wherein, The vertical capacitor structure further includes a lightly doped drain region between the first active pattern and the second active pattern at an edge of the first active pattern and an edge of the second active pattern, wherein the second transistor includes a third active pattern and a fourth active pattern in the substrate and a lightly doped drain region between the third active pattern and the fourth active pattern at an edge of the third active pattern and an edge of the fourth active pattern, and wherein a length of each lightly doped drain region of the vertical capacitor structure in the first horizontal direction is less than a length of each lightly doped drain region of the second transistor in the first horizontal direction.

5. The nonvolatile memory device of claim 1, wherein, The non-volatile memory device is configured such that no on-current flows in the channel region.

6. The nonvolatile memory device of claim 1, wherein, The first active pattern, the second active pattern, and the first gate pattern extend in a second horizontal direction different from the first horizontal direction, and wherein the non-volatile memory device is configured such that capacitor electrodes of the plurality of capacitor electrodes that are adjacent in the first horizontal direction are respectively applied with different voltages.

7. The nonvolatile memory device of claim 1, wherein, The first active pattern, the second active pattern, and the first gate pattern extend in a second horizontal direction different from the first horizontal direction, and wherein a distance between the first active pattern and the second active pattern in the first horizontal direction is less than a length of the first gate pattern in the first horizontal direction.

8. The nonvolatile memory device of claim 1, wherein, The first active pattern, the second active pattern, and the first gate pattern extend in a second horizontal direction different from the first horizontal direction, wherein the plurality of capacitor electrodes further includes: a plurality of further first capacitor electrodes that are in contact with the first gate pattern and separated from each other in the second horizontal direction; a plurality of further second capacitor electrodes that are in contact with the first active pattern and separated from each other in the second horizontal direction; and a plurality of further third capacitor electrodes that are in contact with the second active pattern and separated from each other in the second horizontal direction, and wherein the numbers of first capacitor electrodes, second capacitor electrodes, and third capacitor electrodes are equal to each other.

9. The nonvolatile memory device of claim 1, wherein, The plurality of capacitor electrodes further includes a fourth capacitor electrode that is in contact with the first active pattern and separated from the second capacitor electrode in a second horizontal direction different from the first horizontal direction, and wherein the first capacitor electrode and the fourth capacitor electrode form a third vertical capacitor.

10. The nonvolatile memory device of claim 9, wherein, The plurality of capacitor electrodes further includes a fifth capacitor electrode that is in contact with the second active pattern and separated from the third capacitor electrode in the second horizontal direction, and wherein the first capacitor electrode and the fifth capacitor electrode form a fourth vertical capacitor.

11. The nonvolatile memory device of claim 10, wherein, The first gate pattern extends in the second horizontal direction, The plurality of capacitor electrodes further includes a sixth capacitor electrode that is in contact with the first gate pattern and is separated from the first capacitor electrode in the second horizontal direction, and The fifth capacitor electrode and the sixth capacitor electrode form a fifth vertical capacitor.

12. The nonvolatile memory device of claim 1, wherein, The voltage level of the second voltage is lower than the voltage level of the first voltage.

13. A nonvolatile memory device, the nonvolatile memory device comprising: a first semiconductor layer; a second semiconductor layer that is located above the first semiconductor layer in a vertical direction and includes a memory cell array having a plurality of memory cells stacked with each other; and a plurality of metal contacts that penetrate the second semiconductor layer in the vertical direction, The first semiconductor layer includes: a substrate; a first active pattern and a second active pattern that are arranged to be separated from each other in a first horizontal direction in the substrate; a first gate pattern that is located above a channel region between the first active pattern and the second active pattern; and a plurality of capacitor electrodes that each extend in the vertical direction and are connected to the plurality of metal contacts, respectively, and The plurality of capacitor electrodes includes: a first capacitor electrode that is in contact with the first gate pattern and to which a first voltage is applied, the first gate pattern forming a channel capacitor with the channel region; a second capacitor electrode that is in contact with the first active pattern and to which a second voltage different from the first voltage is applied; and a third capacitor electrode that is in contact with the second active pattern and to which the second voltage is applied.

14. The nonvolatile memory device of claim 13, wherein, The first semiconductor layer further includes: a first gate insulating film between the first gate pattern and the channel region; and a voltage generator including a low-voltage transistor and configured to supply various voltages to the plurality of memory cells; The low-voltage transistor includes a second gate pattern and a second gate insulating film between the second gate pattern and the substrate in the vertical direction, The thickness of the first gate insulating film in the vertical direction is greater than the thickness of the second gate insulating film in the vertical direction, and The first gate pattern, the first gate insulating film, and the channel region form a channel capacitor.

15. The nonvolatile memory device of claim 13, wherein, The first semiconductor layer further includes: a lightly doped drain region between the first active pattern and the second active pattern at edges of the first active pattern and the second active pattern; and a voltage generator including a high-voltage transistor and configured to supply various voltages to the plurality of memory cells, wherein the high-voltage transistor includes a third active pattern and a fourth active pattern spaced apart from each other in the first horizontal direction in the substrate and a lightly doped drain region between the third active pattern and the fourth active pattern at edges of the third active pattern and the fourth active pattern, and wherein a length of each lightly doped drain region between the first active pattern and the second active pattern in the first horizontal direction is smaller than a length of each lightly doped drain region of the high-voltage transistor in the first horizontal direction.

16. The nonvolatile memory device of claim 13, wherein, the first semiconductor layer further includes an interlayer insulating film above the first active pattern, the second active pattern, and the first gate pattern, wherein the plurality of capacitor electrodes penetrate the interlayer insulating film in the vertical direction, wherein the first capacitor electrode, the interlayer insulating film, and the second capacitor electrode form a first vertical capacitor, and wherein the first capacitor electrode, the interlayer insulating film, and the third capacitor electrode form a second vertical capacitor.

17. The nonvolatile memory device of claim 13, wherein, the first active pattern, the second active pattern, and the first gate pattern extend in a second horizontal direction different from the first horizontal direction, and the nonvolatile memory device is configured such that capacitor electrodes adjacent to each other in the first horizontal direction among the plurality of capacitor electrodes are respectively applied with different voltages.

18. A nonvolatile memory device, the nonvolatile memory device comprising: a substrate; a plurality of memory cells stacked on the substrate; a voltage generator including a low-voltage transistor and a high-voltage transistor on the substrate and configured to provide various voltages to the plurality of memory cells; and a vertical capacitor structure including: a first active pattern and a second active pattern arranged to be separated from each other in a first horizontal direction in the substrate; a first gate pattern above the substrate between the first active pattern and the second active pattern; a first gate insulating film between the first gate pattern and the substrate in a vertical direction with respect to the substrate; and a plurality of capacitor electrodes each extending in the vertical direction, wherein the plurality of capacitor electrodes include: a first capacitor electrode in contact with the first gate pattern and applied with a first voltage, the first gate pattern forming a channel capacitor with the substrate; a second capacitor electrode in contact with the first active pattern, applied with a second voltage different from the first voltage, and forming a first vertical capacitor with the first capacitor electrode; and a third capacitor electrode in contact with the second active pattern, applied with the second voltage, and forming a second vertical capacitor with the first capacitor electrode. ​ wherein the low-voltage transistor includes a second gate pattern and a second gate insulating film located between the second gate pattern and the substrate in the vertical direction, wherein the high-voltage transistor includes a third gate pattern and a third gate insulating film located between the third gate pattern and the substrate in the vertical direction, and wherein a thickness of the first gate insulating film in the vertical direction is equal to a thickness of the third gate insulating film in the vertical direction.

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