Integration of graphene and boron nitride heterostructure devices on semiconductor layers

Abstract

A microelectronic device (100) includes a gated graphene assembly (102) above a semiconductor material (106). The gated graphene assembly (102) includes a graphite layer (126) having at least one layer of graphene. The graphite layer (126) has a channel region (128). A first connection (134) and a second connection (136) are electrically connected to the graphite layer (126) adjacent to the channel region (128). The graphite layer (126) is isolated from the semiconductor material (106). A back gate region (142) having a first conductivity type is disposed in the semiconductor material (106) below the channel region (128). A first contact field region (144) and a second contact field region (146) are disposed in the semiconductor material (106) below the first connection (134) and the second connection (136), respectively. At least one of the first contact field region (144) and the second contact field region (146) has an opposite second conductivity type.

Description

Technical Field

[0001] This document relates generally to microelectronics and, more particularly, to graphene in microelectronics. Background Art

[0002] Graphene is a promising material for microelectronic devices. The architecture commonly proposed for gated graphene components is a graphite layer containing graphene on a substrate with metal contacts on the graphene and a channel region in the graphene between the contacts. The architecture lacks control over the carrier density in the channel region and in the graphene below the contacts. The carrier density in the channel region can be adjusted to operate the gated graphene component, while it is desirable to maintain a high carrier density below the contacts to reduce the parasitic resistance of the device. It has been challenging to achieve independent control of the carrier density below the contacts in a structure that can be integrated into a microelectronic device with other components (such as transistors). Summary of the invention

[0003] An example microelectronic device includes a gated graphene assembly above a semiconductor material. The gated graphene assembly includes a graphite layer including one or more layers of graphene. The graphite layer has a channel region, a first contact region adjacent to the channel region, and a second contact region adjacent to the channel region. The graphite layer is isolated from the semiconductor material. A back gate region having a first conductivity type is disposed in the semiconductor material below the channel region. A first contact field region is disposed in the semiconductor material below the first contact region of the graphite layer, and a second contact field region is disposed in the semiconductor material below the second contact region of the graphite layer. At least one of the first contact field region and the second contact field region has a second opposite conductivity type. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 is a cross-section of an example microelectronic device including a gated graphene component.

[0005] FIG. 2A to FIG. 2I is a cross-section of a microelectronic device including a gated graphene component depicted at a stage in an example formation method. DETAILED DESCRIPTION

[0006] The drawings are not drawn to scale. This specification is not limited by the illustrated order of actions or events, as some actions or events can occur in a different order and / or simultaneously with other actions or events. In addition, some illustrated actions or events are optional to implement methods according to this specification.

[0007] The microelectronic device includes a gated graphene assembly having a graphite layer including one or more layers of graphene. The graphite layer includes a channel region, a first contact region adjacent to the channel region, and a second contact region adjacent to the channel region. The graphene extends from the channel region into the first contact region and the second contact region. The graphite layer is disposed above the semiconductor material and isolated from the semiconductor material. The semiconductor material below the graphite layer has a back gate region below the channel region, a first contact field region below the first contact region, and a second contact field region below the second contact region. The back gate region has a first conductivity type, and at least one of the first contact field region and the second contact field region has an opposite second conductivity type. The gated graphene assembly includes a gate opposite to the back gate region above the channel region. Electrical connections to the graphite layer are made in the first contact region and the second contact region.

[0008] Terms such as top, bottom, front, back, over, above, below, and under may be used in this specification. These terms do not limit the position or orientation of structures or elements but provide spatial relationships between structures or elements.

[0009] In this specification, if an element is referred to as being "on" another element, the element may be directly on the other element or intervening elements may be present. Similarly, if an element is referred to as being "adjacent" to another element, the element may be directly adjacent to the other element or intervening elements may be present.

[0010] Figure 1 1 is a cross-section of an example microelectronic device 100 including a gated graphene component 102. The microelectronic device 100 includes a substrate 104 having a semiconductor material 106, such as silicon or primarily silicon, silicon carbide, gallium arsenide, gallium nitride, etc. The substrate 104 can be a portion of a semiconductor wafer, such as a single crystal silicon wafer, which may have an epitaxial layer, or a portion of a silicon-on-insulator (SOI) wafer. In some versions of this example, the semiconductor material 106 can be p-type, such as Figure 1 In other versions, the semiconductor material 106 may be of n-type. In addition to the gated graphene component 102 , the microelectronic device 100 of this example also includes a p-channel metal oxide semiconductor (PMOS) transistor 108 and an n-channel metal oxide semiconductor (NMOS) transistor 110 .

[0011] An optional graphene assembly well 112 may be in the semiconductor material 106 below the gated graphene assembly 102. In some versions of this example, the graphene assembly well 112 may be p-type, as shown in FIG. 2. In other versions, the graphene assembly well 112 may be n-type. In this example, a p-type well 114 is in the semiconductor material 106 below the NMOS transistor 110. In versions of this example where the graphene assembly well 112 is p-type, the distribution of p-type dopants in the graphene assembly well 112 may be substantially equal to the distribution of p-type dopants in the p-type well 114 due to simultaneous formation. Similarly, in this example, an n-type well 116 is in the semiconductor material 106 below the PMOS transistor 108. In versions of this example where the graphene assembly well 112 is n-type, the distribution of n-type dopants in the graphene assembly well 112 may be substantially equal to the distribution of n-type dopants in the n-type well 116 due to simultaneous formation.

[0012] The gated graphene component 102 of this example includes an isolation dielectric layer 118 above the semiconductor material 106. The isolation dielectric layer 118 may include, for example, silicon dioxide, hafnium dioxide, tantalum oxide, or zirconium oxide, and may have a thickness of 2 nanometers to 10 nanometers. The PMOS transistor 108 includes a PMOS gate dielectric layer 120, and the NMOS transistor 110 includes an NMOS gate dielectric layer 122. Since they are formed simultaneously, the thickness and composition of the isolation dielectric layer 118 may be substantially equal to at least one of the PMOS gate dielectric layer 120 and the NMOS gate dielectric layer 120.

[0013] The gated graphene assembly 102 may include a lower hexagonal boron nitride (hBN) layer 124 above the isolation dielectric layer 118. The gated graphene assembly 102 includes a graphite layer 126 on the lower hBN layer 124. The graphite layer 126 includes one or more layers of graphene and may have a Bernal configuration, i.e., each atomic layer of graphene may be offset from the atomic layers immediately above and below it. The graphite layer 126 has a channel region 128, a first contact region 130 adjacent to the channel region 128, and a second contact region 132 adjacent to the channel region 128.

[0014] The gated graphene component 102 includes a first connection 134 on the graphite layer 126 in the first contact region 130 and a second connection 136 on the graphite layer 126 in the second contact region 132. The first connection 134 and the second connection 136 may include one or more metal elements suitable for hBN and graphene precipitation, such as copper, nickel, etc. A barrier metal cap 138 may be provided on each of the first connection 134 and the second connection 136. The barrier metal cap 138 may include one or more materials that reduce the diffusion of boron and nitrogen, such as titanium nitride or tantalum nitride. The barrier metal cap 138 may have a thickness of, for example, 10 nanometers to 100 nanometers. The gated graphene component 102 of this example may include an hBN layer 140 patterned on the graphite layer 126 in the channel region 128.

[0015] The semiconductor material 106 includes a back gate region 142 below the channel region 128. The back gate region 142 has a first conductivity type. In some versions of this example, the first conductivity type may be a p-type, such as Figure 1 As shown. In other versions, the first conductivity type can be n-type. Semiconductor material 106 also includes a first contact field region 144 below first contact region 130, and includes a second contact field region 146 below second contact region 132. At least one of first contact field region 144 and second contact field region 146 has a second conductivity type opposite to the first conductivity type. In some versions of this example, first contact field region 144 and second contact field region 146 can both have the second conductivity type. In versions of this example where the first conductivity type is p-type, first contact field region 144 and second contact field region 146 can both be n-type, such as Figure 1 In the example where the first conductivity type is n-type, the first contact field region 144 and the second contact field region 146 may both be p-type. The first contact field region 144 may have a conductivity greater than 1×10 19 cm -3 The average doping density of the first contact field region 144 can reduce the consumption of the first contact field region 144 when a bias is applied to the first connection 134 during operation of the microelectronic device 100, which in turn can increase the electric field in the first contact field region 144, thereby advantageously increasing the carrier density in the first contact field region 144. Similarly, the second contact field region 146 can have an average doping density greater than 1×10 19 cm -3 The average doping density has similar advantages.

[0016] The semiconductor material 106 may optionally include a well tap region 148 contacting the graphene assembly well 112. The well tap region 148 may have the same conductivity type as the graphene assembly well 112, with a higher average doping density to provide a low resistance connection to the back gate region 142 through the graphene assembly well 112.

[0017] The PMOS transistor 108 includes a p-type source region 150 and a p-type drain region 152 in the semiconductor material 106. In the version of the example in which the first contact field region 144 or the second contact field region 146 is p-type, since they are formed at the same time, the dopant distribution of the p-type first contact field region 144 or the second contact field region 146 can be substantially equal to the dopant distribution of the p-type source region 150. The NMOS transistor includes an n-type source region 154 and an n-type drain region 156. In the version of the example in which the first contact field region 144 or the second contact field region 146 is n-type, since they are formed at the same time, the dopant distribution of the n-type first contact field region 144 or the second contact field region 146 can be substantially equal to the dopant distribution of the n-type source region 154.

[0018] The gated graphene component 102 of this example may include contact spacers 158 on the side surfaces of the first connection 134 and the second connection 136. The contact spacers 158 may include silicon dioxide, silicon nitride, silicon oxynitride, etc. The gated graphene component 102 includes a gate dielectric layer 160 on the patterned hBN layer 140 above the channel region 128. The gate dielectric layer 160 may include silicon dioxide, silicon nitride, silicon oxynitride, aluminum oxide, boron nitride, hafnium oxide, tantalum oxide, zirconium oxide, or other dielectric materials. The gate dielectric layer 160 may have a thickness of, for example, 1 nanometer to 20 nanometers. The gated graphene component 102 includes a gate 162 on the gate dielectric layer 160 above the channel region 128. The gate 162 may include polysilicon, aluminum, copper, titanium, titanium nitride, tantalum, tantalum nitride, metal silicide, or other conductive materials. The gate 162 is electrically isolated from the first connection 134 and the second connection 136 by the contact spacer 158 .

[0019] The PMOS transistor 108 includes a PMOS gate 164 over the PMOS gate dielectric layer 120 and may include a PMOS gate spacer 166 on a side surface of the PMOS gate 164. The NMOS transistor 110 includes an NMOS gate 168 over the NMOS gate dielectric layer 122 and may include an NMOS gate spacer 170 on a side surface of the NMOS gate 168.

[0020] The microelectronic device 100 may include a metal silicide 172 on exposed semiconductor material of the microelectronic device 100, including, for example, portions of the first contact field region 144, the second contact field region 146, the well tap region 148, the n-type source region 154, the n-type drain region 156, the p-type source region 150, the p-type drain region 152, the NMOS gate 168, and the PMOS gate 164. The metal silicide 172 may provide low resistance connections to components of the microelectronic device 100. Components in the microelectronic device 100, including the gated graphene component 102, the PMOS transistor 108, and the NMOS transistor 110, may be laterally isolated by the field oxide 174. The field oxide 174 may have a shallow trench isolation (STI) structure, such as Figure 1 As shown, or may have a local oxidation of silicon (LOCOS) structure. Other structures for laterally separating components in microelectronic device 100 are within the scope of this example.

[0021] The dielectric layer 176 may be disposed over the substrate 104 and components in the microelectronic device 100, including the gated graphene component 102, the PMOS transistor 108, and the NMOS transistor 110. The dielectric layer 176 may be a pre-metal dielectric (PMD) layer, which may include one or more dielectric material sublayers, such as a PMD liner of silicon nitride, a silicon dioxide-based material layer formed by a high-density plasma or a chemical vapor deposition (CVD) process using tetraethylorthosilicate (TEOS) and ozone, a silicon dioxide-based material such as phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG), and a capping layer of silicon nitride, silicon oxynitride, silicon carbide, or silicon carbide nitride. Other structures and compositions of the dielectric layer 176 are within the scope of this example.

[0022] Contacts 178 are disposed on the metal silicide 172 (if present) through the dielectric layer 176 to enable electrical connection with components of the microelectronic device 100, including the gated graphene component 102, the PMOS transistor 108, and the NMOS transistor 110. The contacts 178 may include an adhesion liner of titanium, a barrier liner of titanium nitride, and a core metal of tungsten. Other structures and compositions of the contacts 178 are within the scope of this example. Contact with the semiconductor material 106 may be achieved by a backside contact 180 on the substrate 104 on the back surface of the substrate 104, which is opposite to the components of the microelectronic device 100, including the gated graphene component 102, the PMOS transistor 108, and the NMOS transistor 110. In another version of this example, the contacts 178 may be replaced with an interconnect or other electrical connection.

[0023] During operation of the microelectronic device 100, the first contact field region 144, the second contact field region 146, the back gate region 142, and the gate 162 can each be independently biased to provide a desired carrier density in the first contact region 130, the second contact region 132, and the channel region 128. The first connection 134 and the second connection 136 can be biased relative to each other to provide a desired electric field in the graphite layer 126 in the channel region 128. The back gate region 142 and the gate 162 can be biased to control the current flowing through the channel region 128. For example, in a version of this example including a graphene component well 112, or in a version in which the substrate 104 has an SOI structure, the back gate region 142 can be biased through the well tap region 148. In a version of this example without a graphene component, the back gate region 142 can be biased through the back side contact 180. Biasing the first and second contact field regions 144 and 146 independently of the back gate region 142 may enable high carrier density in the first and second contact regions 130 and 132 independent of the carrier density in the channel region 128 , which may advantageously reduce the overall resistance of the gated graphene assembly 102 .

[0024] FIG. 2A to FIG. 2I is a cross-section of a microelectronic device 200 including a gated graphene component 202 depicted at a stage in an example formation method. Figure 2A The microelectronic device 200 includes a substrate 204 having a semiconductor material 206, such as silicon, silicon carbide, gallium arsenide, gallium nitride, etc. The substrate 204 may be a semiconductor wafer, an SOI wafer, or another semiconductor-containing substrate. Figure 2A As shown, semiconductor material 206 may be of p-type, or may be of n-type. Substrate 204 includes a region for gated graphene component 202 , a region for PMOS transistor 208 , and a region for NMOS transistor 210 .

[0025] Field oxide 274 may be formed in substrate 204. Field oxide 274 may be formed, for example, by an STI process or a LOCOS process. An example STI process includes forming a CMP stop layer of silicon nitride over substrate 204, etching an isolation trench through the CMP stop layer and into substrate 204, and filling the isolation trench with silicon dioxide by a plasma enhanced chemical vapor deposition (PECVD) process using TEOS, a high density plasma (HDP) process, a high aspect ratio process (HARP) using TEOS and ozone, an atmospheric pressure chemical vapor deposition (APCVD) process using silane, or a sub-atmospheric pressure chemical vapor deposition (SACVD) process using dichlorosilane. Excess silicon dioxide is removed from over the CMP stop layer by an oxide chemical mechanical polishing (CMP) process, followed by removal of the CMP stop layer, leaving field oxide 274. An example LOCOS process includes forming a silicon nitride mask layer over the LOCOS pad oxide layer over substrate 204. The silicon nitride mask layer is removed in the area of ​​field oxide 274, exposing the LOCOS pad oxide. Silicon dioxide is formed by thermal oxidation in the areas exposed by the silicon nitride mask layer to form field oxide 274. The silicon nitride mask layer is then removed, leaving field oxide 274 in place.

[0026] An n-type well 216 may be formed in the substrate 204 in the region for the PMOS transistor 208. The n-type well 216 may be formed by implanting a 1×10 12 cm -2 to 1×10 14 cm -2 An n-type dopant such as phosphorus is implanted into the semiconductor material 206 at a cumulative dose of , followed by thermal annealing and activation operations.

[0027] A p-type well 214 may be formed in the substrate 204 in the region for the NMOS transistor 210. The p-type well 214 may be formed by implanting a 1×10 12 cm -2 to 1×10 14 cm -2 A p-type dopant such as boron is implanted into the semiconductor material 206 with a cumulative dose of , followed by thermal annealing and activation operations.

[0028] A graphene assembly well 212 may be formed in the substrate 204 in the region for the gated graphene assembly 202. In this example, the graphene assembly well 212 may be p-type and may be formed simultaneously with the p-type well 214. Alternatively, the graphene assembly well 212 may be n-type and may be formed simultaneously with the n-type well 216. Forming the graphene assembly well 212 simultaneously with the p-type well 214 or the n-type well 216 may advantageously reduce the manufacturing cost and complexity of the microelectronic device 200 compared to forming the graphene assembly well 212 separately.

[0029] A PMOS gate dielectric layer 220 is formed on the substrate 204 in the area for the PMOS transistor 208. An NMOS gate dielectric layer 222 is formed on the substrate 204 in the area for the NMOS transistor 210. An isolation dielectric layer 218 is formed on the substrate 204 in the area for the gated graphene component 202. A sacrificial oxide layer 282 may be formed on the substrate 204 in the area for connection to the graphene component well 212. The PMOS gate dielectric layer 220, the NMOS gate dielectric layer 222, the isolation dielectric layer 218, and the sacrificial oxide layer 282 may include silicon dioxide, silicon oxynitride, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, or other dielectric materials suitable for gate dielectric layers, and may be 1 nanometer to 10 nanometers thick. Any combination of PMOS gate dielectric layer 220 , NMOS gate dielectric layer 222 , isolation dielectric layer 218 , and sacrificial oxide layer 282 may be formed simultaneously, advantageously reducing manufacturing cost and complexity of microelectronic device 200 as compared to forming layers 220 , 222 , 218 , and 282 separately.

[0030] refer to Figure 2B , a PMOS gate 264 is formed on the PMOS gate dielectric layer 220. An NMOS gate 268 is formed on the NMOS gate dielectric layer 222. A portion or all of the PMOS gate 264 may be formed simultaneously with a portion or all of the NMOS gate 268. After forming the PMOS gate 264, a P-type dopant may be implanted into the substrate 204 adjacent to the PMOS gate 264 to form a p-type source / drain extension of the PMOS transistor 208. After forming the PMOS gate 264, an N-type dopant may be implanted into the substrate 204 to extend partially below the PMOS gate 264 to form an n-type halo region of the PMOS transistor 208. Similarly, after forming the NMOS gate 268, an n-type dopant may be implanted into the substrate 204 adjacent to the NMOS gate 268 to form an n-type source / drain extension of the NMOS transistor 210. After forming the NMOS gate 268 , a P-type dopant may be implanted into the substrate 204 , extending partially under the NMOS gate 268 , to form a p-type halo region of the NMOS transistor 210 .

[0031] Subsequently, a PMOS gate sidewall spacer 266 is formed on the side surface of the PMOS gate 264, and an NMOS gate sidewall spacer 270 is formed on the side surface of the NMOS gate 268. A portion or all of the PMOS gate sidewall spacer 266 may be formed simultaneously with a portion or all of the NMOS gate sidewall spacer 270. The PMOS gate sidewall spacer 266 and the NMOS gate sidewall spacer 270 may include one or more layers of dielectric material, such as silicon dioxide or silicon nitride.

[0032] Subsequently, additional p-type dopants such as boron, and optionally gallium or indium, are implanted into the substrate 204 in the region for the PMOS transistor 208 and in the region for connection with the graphene component well 212. The substrate 204 is then annealed to activate the implanted p-type dopants, thereby forming a p-type source region 250 and a p-type drain region 252 in the substrate 204 in the region for the PMOS transistor 208, and forming a well tap region 248 in the substrate 204 in the region of connection with the graphene component well 212. The substrate 204 may be formed at 1×10 14 cm -2 Up to 1×10 16 cm -2 The additional p-type dopant is implanted with a cumulative dose of 1×10 19 cm -3 The average doping density.

[0033] An implantation mask 284 is formed over the substrate 204 to expose regions for the first contact field region and the second contact field region both in the region for the gated graphene component 202, and to expose the region for the NMOS transistor 210, and to cover the region for the back gate region 242 in the substrate 204 in the region for the gated graphene component 202, the region for the PMOS transistor 208, and the region for connection with the graphene component well 212. The implantation mask 284 may include a photoresist formed by a photolithography process, and may further include an antireflective material such as an organic bottom antireflective coating (BARC). Additional n-type dopants 286 such as phosphorus, arsenic, and optionally antimony are implanted into the substrate 204 exposed by the implantation mask 284. The implantation mask 284 may be implanted at an energy of 2 keV to 40 keV, 1×10 14 cm -2 to 1×10 16 cm -2The additional n-type dopant 286 is implanted in one or more implantation steps with a cumulative dose of 1×10 . The implanted n-type dopant 286 forms a source implant region 288 and a drain implant region 290 in the region for the NMOS transistor 210 and forms a first contact field implant region 292 and a second contact field implant region 294 in the region for the gated graphene component 202. 14 cm -2 to 1×10 16 cm -2 The cumulative dose of the implanted additional n-type dopant 286 can provide greater than 1×10 19 cm -3 The average doping density, which can generate a reference Figure 1 Advantages disclosed.

[0034] Implant mask 284 is subsequently removed. Implant mask 284 may be removed, for example, by exposure to oxygen radicals in an ashing process. Residues from exposure to oxygen radicals may be removed by a wet cleaning process, such as an aqueous mixture of hydrogen peroxide and ammonium hydroxide.

[0035] refer to Figure 2C , perform a thermal annealing process, the thermal annealing process Figure 2B The substrate 204 in the source implant region 288, the drain implant region 290, the first contact field implant region 292, and the second contact field implant region 294 is annealed, and the implanted n-type dopants in the source implant region 288, the drain implant region 290, the first contact field implant region 292, and the second contact field implant region 294 are activated to form an n-type source region 254 and an n-type drain region 256 in the substrate 204 in the region for the NMOS transistor 210, and form a first contact field region 244 and a second contact field region 246 in the substrate 204 in the region for the gated graphene component 202. The first contact field region 244 and the second contact field region 246 are adjacent to the back gate region 242.

[0036] A first metal layer 296 may be formed on the isolation dielectric layer 218. The first metal layer 296 includes one or more metals suitable for subsequent deposition of a hBN layer, such as cobalt, nickel, copper, ruthenium, rhodium, palladium, silver, rhenium, iridium, platinum, gold, or any combination thereof. These metals are not an exhaustive list, but are provided by way of example. The first metal layer (296) may include a homogeneous alloy or a mixture of two or more different metals. The first metal layer (296) may include a layered structure of two or more layers with different metals (e.g., a copper / nickel / copper stack). The first metal layer (296) may be formed, for example, by a sputtering process, an evaporation process, a CVD process, a metal organic chemical vapor deposition (MOCVD) process, or an atomic layer deposition (ALD) process. The thickness of the first metal layer 296 is suitable for depositing the hBN layer onto the isolation dielectric layer 218, and therefore may be selected based on the composition of the first metal layer 296. For example, the first metal layer 296 may have a thickness of 50 nanometers to 500 nanometers. The first metal layer 296 may be patterned to extend only over the region used to gate the graphene component 202, such as Figure 2C Alternatively, the first metal layer 296 may extend over the entire substrate 204 .

[0037] Boron (at a temperature suitable for the diffusion of boron and nitrogen in the first metal layer 296 and the deposition of the hBN layer onto the isolation dielectric layer 218) may be introduced at a temperature suitable for the diffusion of boron and nitrogen in the first metal layer 296 and the deposition of the hBN layer onto the isolation dielectric layer 218 (eg, 400° C. to 800° C.). Figure 2C The nitrogen (represented as "boron" in the figure) is introduced into the first metal layer 296 in a sufficient amount to form a boron saturation condition in the first metal layer 296. The nitrogen (represented as "boron" in the figure) can be ... Figure 2C Boron (denoted as "nitrogen" in the figure) is introduced into the first metal layer 296 in a sufficient amount to form a saturated condition of nitrogen in the first metal layer 296. Boron and nitrogen can be introduced into the first metal layer 296 by any of several methods, including, for example, ion implantation, exposure to a boron-containing gas reagent and a nitrogen-containing gas reagent at an elevated temperature, or deposition of a boron nitride layer on the first metal layer 296.

[0038] Regions of the microelectronic device 200 outside the region for the gated graphene component 202 (including regions for the PMOS transistor 208 and the NMOS transistor 210) may be separated from the reference 200 by, for example, a silicon dioxide shielding layer (not shown) or other material not shown. Figure 2C The shielding layer may be removed after forming the gated graphene component 202. Other methods of protecting areas of the microelectronic device 200 outside of the area used for the gated graphene component 202 are within the scope of this example.

[0039] refer to Figure 2D , the first metal layer 296 can be heated to a temperature at which boron and nitrogen reach saturation conditions. Figure 2D The first radiant heat process 298 shown heats the first metal layer 296 by a hot plate process, a furnace process or other heating process. The first metal layer 296 is then cooled, causing boron and nitrogen to diffuse to the surface of the first metal layer 296 and precipitate a lower hBN layer 224 on the isolation dielectric layer 218. The lower hBN layer 224 can be, for example, 1 to 5 atomic layers thick. An upper hBN layer 300 can also be deposited on the top surface of the first metal layer 296, opposite the lower hBN layer 224. The upper hBN layer 300 can be removed alone or together with the first metal layer 296.

[0040] refer to Figure 2E , the second metal layer 302 may be disposed on the lower hBN layer 224. In some versions of this example, the second metal layer 302 may be Figure 2D 302. In other versions, second metal layer 302 may include a portion of first metal layer 296 and may optionally include additional metals. In other versions, first metal layer 296 may be removed before forming second metal layer 302. Second metal layer 302 includes one or more metals suitable for subsequently precipitating a graphite layer. Second metal layer 302 may have a composition, layer structure, and thickness similar to first metal layer 296.

[0041] The carbon (in the second metal layer 302) may be deposited in a sufficient amount at a temperature suitable for diffusion of the carbon in the second metal layer 302 and precipitation of the graphite layer onto the second metal layer (e.g., 400° C. to 800° C.). Figure 2E In the embodiment of the present invention, carbon (denoted as "carbon") is introduced into the second metal layer 302 to form a saturated condition of carbon in the second metal layer 302. The carbon can be introduced into the second metal layer 302 by any of several methods, including, for example, ion implantation, exposure to a carbon-containing gas reagent at high temperature, or deposition of an amorphous carbon layer on the second metal layer 302.

[0042] refer to Figure 2F , the second metal layer 302 can be heated to a temperature at which carbon reaches a saturation condition. Figure 2F The second metal layer 302 is heated by a second radiant heat process 304 as shown, or by another heating process. The second metal layer 302 is then cooled, causing carbon to diffuse to the surface of the second metal layer 302 and a graphite layer 226 to be deposited on the lower hBN layer 224. The graphite layer 226 may have a Bernal configuration. An upper graphite layer 306 may also be deposited on the top surface of the second metal layer 302, opposite the graphite layer 226. The upper graphite layer 306 may optionally be removed.

[0043] refer to Figure 2G , a first connection 234 is formed on the graphite layer 226 in the first contact region 230 of the graphite layer 226, and a second connection 236 is formed on the graphite layer 226 in the second contact region 232 of the graphite layer 226. The first connection 234 and the second connection 236 may include Figure 2F The first connection 234 and the second connection 236 may be formed at the same time. The first connection 234 and the second connection 236 may have a blocking cap 238, the material of which reduces the diffusion of boron, such as titanium nitride or tantalum nitride.

[0044] A third metal layer 308 may be formed over the first and second connections 234, 236, and over the graphite layer 226 exposed by the first and second connections 234, 236, including over the channel region 228. The third metal layer 308 includes one or more metals suitable for subsequent deposition of the hBN layer. The third metal layer 308 may have a similar Figure 2C The composition, layer structure and thickness of the first metal layer 296 have those properties described.

[0045] Boron (in the third metal layer 308) may be introduced in sufficient amount at a temperature suitable for diffusion of boron and nitrogen in the third metal layer 308 and deposition of the layer onto the graphite layer 226 (eg, 400° C. to 800° C.). Figure 2G Boron in Figure 2G In the embodiment of the present invention, boron and nitrogen are introduced into the third metal layer 308 to form a saturation condition of boron and nitrogen in the third metal layer 308. Boron and nitrogen can be introduced by referring to Figure 2C Any of the described methods is introduced into the first metal layer 296 .

[0046] refer to Figure 2H The third metal layer 308 may be heated to a temperature at which boron and nitrogen reach saturation conditions. The third metal layer 308 may be heated to a temperature at which boron and nitrogen reach saturation conditions. Figure 2D The first metal layer 296 is heated to a temperature. Figure 2D The third metal layer 308 is heated by a third radiant heat process 310 as shown, or by another heating process. The third metal layer 308 is then cooled, causing boron and nitrogen to diffuse to the surface of the third metal layer 308 and precipitate a patterned hBN layer 240 on the graphite layer 226 in the channel region 228. The blocking cap 238 blocks the formation of hBN below the first connection 234 and the second connection 236. The patterned hBN layer 240 can be, for example, 1 to 5 atomic layers thick. A second hBN layer (not shown) can also be deposited on the top surface of the third metal layer 308, opposite the patterned hBN layer 240, and deposited on the blocking cap 238. The third metal layer 308 is subsequently removed together with the second hBN layer, thereby leaving the patterned hBN layer 240 in place.

[0047] refer to Fig.2I , contact spacers 258 may be formed on side surfaces of first connection 234 and second connection 236. Contact spacers 258 may be formed by forming a conformal layer of a dielectric material such as silicon dioxide or silicon nitride over first connection 234 and second connection 236, and removing the conformal layer over channel region 228 by an anisotropic etching process such as a reactive ion etching (RIE) process.

[0048] A gate dielectric layer 260 of the gated graphene component 202 may be formed over the patterned hBN layer 240. The gate dielectric layer 260 may extend onto the contact spacers 258. The gate dielectric layer 260 may include reference Figure 1 A portion or all of the gate dielectric layer 260 may be formed by a CVD process, an ALD process, or other dielectric thin film processes. The gate dielectric layer 260 may be formed as a capping dielectric layer on the microelectronic device 200 and subsequently patterned by a mask and etch process to remove the capping dielectric layer from the outer region of the gated graphene component 202.

[0049] A gate 262 of the gated graphene component 202 is formed over the gate dielectric layer 260 over the channel region 228. The gate 262 may include a reference Figure 1 Materials disclosed about gate 162. Gate 262 may be formed by an evaporation process, a sputtering process, an ALD process, a metal organic chemical vapor deposition (MOCVD) process, or other suitable metal thin film process. Gate 262 is formed to be electrically isolated from first connection 234 and second connection 236 by contact spacer 258. Gate 262 may be formed as a capping metal layer on microelectronic device 200 and subsequently patterned by a mask and etching process to remove the capping metal layer from areas outside gated graphene component 202.

[0050] The formation of the microelectronic device 200 is followed by the formation of a metal silicide on the exposed semiconductor material of the microelectronic device 200 (not on the Fig.2I Continuing with the above, the exposed semiconductor material includes, for example, first contact field region 244, second contact field region 246, well tap region 248, n-type source region 254, n-type drain region 256, p-type source region 250, p-type drain region 252, NMOS gate 268, and portions of PMOS gate 264. Subsequently, a plurality of semiconductor layers not shown in FIG. 1 are formed on microelectronic device 200. Fig.2I The dielectric layer shown in FIG. 1 and the dielectric layer formed by the dielectric layer are not Fig.2I The contacts shown in the figure provide Figure 1 structure.

[0051] Modifications may be made in the described embodiments, and other embodiments are possible, within the scope of the claims.

Claims

1. A microelectronic device comprising: a substrate having a semiconductor material; A gate-controlled graphene component, the gate-controlled graphene component comprising: a graphite layer, the graphite layer comprising at least one layer of graphene above the substrate, the graphite layer having a channel region, a first contact region adjacent to the channel region, and a second contact region adjacent to the channel region; and a gate above the channel region; a first connection on the graphene layer in the first contact region; a second connection on the graphene layer in the second contact region; a back gate region in the semiconductor material below the channel region, the back gate region having a first conductivity type; a first contact field region in the semiconductor material below the first contact region of the graphene layer; and A second contact field region in the semiconductor material below the second contact region of the graphite layer, wherein the graphite layer is isolated from the back gate region, the first contact field region, and the second contact field region, and wherein at least one of the first contact field region and the second contact field region has a second conductivity type opposite to the first conductivity type, and wherein at least one of the first contact field region and the second contact field region has a conductivity greater than 1×10 19 cm -3 The average doping density. 2 . The microelectronic device of claim 1 , wherein the back gate region is of p-type, the first contact field region is of n-type, and the second contact field region is of n-type.

3. The microelectronic device of claim 2, wherein the semiconductor material comprises primarily silicon and the microelectronic device further comprises an n-channel metal oxide semiconductor (NMOS) transistor. 4 . The microelectronic device of claim 3 , wherein a dopant profile of the first contact field region is equal to a dopant profile of an n-type source region of the NMOS transistor.

5. The microelectronic device of claim 3, further comprising a p-channel metal oxide semiconductor transistor (PMOS transistor).

6. The microelectronic device according to claim 1, wherein the gate-controlled graphene component further comprises an isolation dielectric layer on the back gate region, the first contact field region, and the second contact field region, wherein the graphite layer is isolated from the back gate region, the first contact field region, and the second contact field region by the isolation dielectric layer.

7. The microelectronic device according to claim 6, further comprising a metal oxide semiconductor transistor (MOS transistor) having a gate dielectric layer, wherein: The thickness and composition of the isolation dielectric layer are equal to the thickness and composition of the gate dielectric layer.

8. The microelectronic device of claim 1, wherein the gated graphene assembly further comprises a lower hexagonal boron nitride layer (lower hBN layer) below the graphite layer, the graphite layer being directly disposed on the lower hBN layer.

9. The microelectronic device of claim 1, wherein the gated graphene component further comprises: a patterned hBN layer on the graphite layer directly above the channel region, opposite the back gate region; as well as A gate is formed on top of the patterned hBN layer.

10. A method of forming a microelectronic device, comprising: providing a substrate including a semiconductor material, the semiconductor material including a back gate region in the semiconductor material, the back gate region having a first conductivity type; forming a first contact field region adjacent to the back gate region in the semiconductor material; forming a second contact field region adjacent to the back gate region in the semiconductor material, wherein at least one of the first contact field region and the second contact field region has a second conductivity type opposite to the first conductivity type; forming a graphite layer of a gate-controlled graphene assembly over the substrate, the graphite layer comprising at least one layer of graphene, the graphite layer extending over the back gate region, the first contact field region, and the second contact field region, wherein the graphite layer is isolated from the back gate region, the first contact field region, and the second contact field region; forming a first connection on the graphite layer above the first contact field region; as well as forming a second connection on the graphite layer above the second contact field region, The at least one of the first contact field region and the second contact field region having the second conductivity type is formed by 1×10 14 cm -2 Up to 1×10 16 cm -2 The cumulative dose of the second conductivity type dopant is implanted, or wherein forming the at least one of the first contact field region and the second contact field region having the second conductivity type is performed so that the at least one of the first contact field region and the second contact field region having the second conductivity type has a value greater than 1×10 19 cm -3 The average doping density. 11 . The method according to claim 10 , further comprising forming a source region of a metal oxide semiconductor (MOS) transistor having the second conductivity type simultaneously with at least one of the first contact field region and the second contact field region having the second conductivity type.

12. The method according to claim 10, wherein forming the at least one of the first contact field region and the second contact field region having the second conductivity type is performed so that the at least one of the first contact field region and the second contact field region having the second conductivity type has a conductivity greater than 1×10 19 cm -3 The average doping density. 13 . The method according to claim 10 , further comprising forming an isolation dielectric layer over the substrate, so that the graphite layer is isolated from the back gate region, the first contact field region, and the second contact field region by the isolation dielectric layer.

14. The method of claim 13, further comprising forming a gate dielectric layer of a MOS transistor simultaneously with the isolation dielectric layer.

15. The method of claim 10, wherein the semiconductor material consists essentially of silicon. 16 . The method according to claim 10 , further comprising forming a lower hexagonal boron nitride layer (lower hBN layer) before forming the graphite layer, so that the graphite layer is directly formed on the lower hBN layer. 17 . The method of claim 10 , further comprising forming a patterned hBN layer directly on the graphite layer over the back gate region. 18 . The method of claim 10 , further comprising forming a gate over the graphite layer over a channel region of the graphite layer.

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