Semiconductor device and manufacturing method

Abstract

The present disclosure relates to semiconductor devices and manufacturing methods. Semiconductor devices and manufacturing methods are disclosed. Semiconductor devices and methods of manufacturing semiconductor devices are provided. In an embodiment, a treatment process is used to introduce silicon into a p-metal work function layer. By introducing silicon into the p-metal work function layer, subsequently deposited layers that may include diffusible materials such as aluminum can be prevented from diffusing through the p-metal work function layer and affecting the operation of the device.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices and methods of manufacturing. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric material layers, conductive material layers, and semiconductor material layers on a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other issues arise that should be addressed. Summary of the invention

[0004] According to one embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, the method comprising: depositing a gate dielectric over a semiconductor fin; depositing a first p-metal work function layer over the gate dielectric; treating the first p-metal work function layer with a silicon-containing gas; and depositing a first n-metal work function layer over the first p-metal work function layer.

[0005] According to another embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, the method comprising: depositing a first p-metal work function layer above a gate dielectric above a semiconductor fin; depositing a first n-metal work function layer on the first p-metal work function layer, the first n-metal work function layer comprising a first diffusion element; and preventing diffusion of the first diffusion element by introducing silicon into the first p-metal work function layer before depositing the first n-metal work function layer.

[0006] According to another embodiment of the present disclosure, a semiconductor device is provided, comprising: a semiconductor fin; a gate dielectric above the semiconductor fin; a first p-metal work function layer above the gate dielectric, the first p-metal work function layer comprising silicon; a first n-metal work function layer above the first p-metal work function layer; and aluminum located in both the first p-metal work function layer and the first n-metal work function layer, wherein a concentration gradient of the aluminum extends from the first n-metal work function layer to the first p-metal work function layer but ends before extending to the gate dielectric. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the present disclosure can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 A perspective view illustrating the formation of semiconductor fins in accordance with some embodiments.

[0009] Figure 2 The formation of source / drain regions is shown in accordance with some embodiments.

[0010] Figure 3 The formation of materials for a gate stack is shown in accordance with some embodiments.

[0011] Figure 4 A passivation process according to some embodiments is shown.

[0012] Figure 5 Deposition of a fill material according to some embodiments is shown.

[0013] Figure 6 The formation of a cap is shown according to some embodiments. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not restrictive. For example, forming a first feature on or above a second feature in the following description may include an embodiment in which the first and second features are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first and second features so that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0015] Additionally, spatially relative terms (e.g., "below," "beneath," "above," "over," etc.) may be used herein for ease of description to describe the relationship of one element or feature to another (or multiple) element or feature as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0016] Embodiments will now be described with respect to a specific example including a finFET device having multiple threshold voltages for a sub-10nm technology node, such as a 5nm or 3nm technology node. However, the embodiments are not limited to the examples provided herein, and the ideas may be implemented in a variety of embodiments.

[0017] Reference now Figure 1 , a perspective view of a semiconductor device 100 such as a finFET device is shown. In an embodiment, the semiconductor device 100 includes a substrate 101 and a first trench 103. The substrate 101 may be a silicon substrate, but other substrates such as semiconductor on insulator (SOI), strained SOI, and silicon germanium on insulator may also be used. The substrate 101 may be a p-type semiconductor, but in other embodiments, it may be an n-type semiconductor.

[0018] The first trench 103 may be formed as an initial step to eventually form the first isolation region 105. A mask layer ( Figure 1 The first trench 103 is formed by a mask layer 101 formed by a process such as chemical vapor deposition (CVD) and a suitable etching process. For example, the mask layer can be a hard mask including silicon nitride formed by a process such as chemical vapor deposition (CVD), but other materials (e.g., oxides, oxynitrides, silicon carbide, combinations of these, etc.) and other processes (e.g., plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), or even nitridation after oxide formation) can also be used. Once formed, the mask layer can be patterned by a suitable photolithography process to expose those portions of the substrate 101 that will be removed to form the first trench 103.

[0019] However, as will be appreciated by those skilled in the art, the above-described processes and materials for forming the mask layer are not the only methods that can be used to expose other portions of the substrate 101 for forming the first trench 103 while protecting a portion of the substrate 101. Any suitable process (e.g., a patterned and developed photoresist) may be used to expose the portion of the substrate 101 to be removed to form the first trench 103. All such methods are fully intended to be included within the scope of the present embodiment.

[0020] Once the mask layer has been formed and patterned, a first trench 103 is formed in the substrate 101. The exposed substrate 101 may be removed by a suitable process such as reactive ion etching (RIE) to form the first trench 103 in the substrate 101, but any suitable process may be used. In an embodiment, the first trench 103 may be formed to have a depth of less than about 100 mm from the surface of the substrate 101. The first depth, for example, is about

[0021] However, as will be appreciated by those skilled in the art, the above process for forming the first trench 103 is only one possible process and is not meant to be the only embodiment. Rather, any suitable process by which the first trench 103 can be formed can be used, and any suitable process including any number of masking and removal steps can be used.

[0022] In addition to forming the first trench 103, the masking and etching process additionally forms fins 107 from those portions of the substrate 101 that remain unremoved. For convenience, the fins 107 have been shown in the figures as being separated from the substrate 101 by dashed lines, but a physical indication of separation may or may not exist. As discussed below, these fins 107 may be used to form the channel region of a multi-gate FinFET transistor. Although Figure 1 Only three fins 107 formed from the substrate 101 are shown, but any number of fins 107 may be used.

[0023] The fins 107 may be formed so that they have a width between about 5 nm and about 80 nm, for example, about 30 nm, at the surface of the substrate 101. Additionally, the fins 107 may be spaced apart from each other by a distance between about 10 nm and about 100 nm, for example, about 50 nm. By spacing the fins 107 in this manner, the fins 107 may each form a separate channel region while still being close enough to share a common gate (discussed further below).

[0024] In addition, the fin 107 can be patterned by any suitable method. For example, the fin 107 can be patterned using one or more photolithography processes, including double patterning or multi-patterning processes. Typically, the double patterning or multi-patterning process combines photolithography and self-alignment processes, which allows the following patterns to be created: patterns with, for example, smaller pitches than can be obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin 107.

[0025] Once the first trench 103 and the fin 107 are formed, the first trench 103 may be filled with a dielectric material, and the dielectric material may be recessed within the first trench 103 to form a first isolation region 105. The dielectric material may be an oxide material, a high density plasma (HDP) oxide, etc. The dielectric material may be formed after optional cleaning and lining of the first trench 103 using a chemical vapor deposition (CVD) method (e.g., a HARP process), a high density plasma CVD method, or other suitable formation methods known in the art.

[0026] The first trench 103 may be filled by overfilling the first trench 103 and the substrate 101 with a dielectric material, and then removing excess material outside the first trench 103 and the fin 107 by a suitable process (e.g., chemical mechanical polishing (CMP), etching, a combination of these, etc.). In an embodiment, the removal process also removes any dielectric material located above the fin 107, so that the removal of the dielectric material will expose the surface of the fin 107 to further processing steps.

[0027] Once the first trench 103 has been filled with the dielectric material, the dielectric material can then be recessed away from the surface of the fin 107. The recessing can be performed to expose at least a portion of the sidewalls of the fin 107 adjacent to the top surface of the fin 107. The dielectric material can be recessed using wet etching by immersing the top surface of the fin 107 in an etchant such as HF, although other etchants (e.g., H2) and other methods (e.g., reactive ion etching, dry etching using an etchant such as NH3 / NF3, chemical oxide removal, or dry chemical cleaning) can also be used. The dielectric material can be recessed to between about 100 and 150 nm from the surface of the fin 107. Peace The distance between, for example, about Additionally, the recessing may also remove any remaining dielectric material located above the fins 107 to ensure that the fins 107 are exposed for further processing.

[0028] However, as will be appreciated by one of ordinary skill in the art, the above steps may be only a portion of the entire process flow for filling and recessing the dielectric material. For example, a lining step, a cleaning step, an annealing step, a gap filling step, a combination of these, etc. may also be used to form and fill the first trench 103 with a dielectric material. All possible processing steps are fully intended to be included within the scope of the present embodiment.

[0029] After forming the first isolation region 105, a dummy gate dielectric 109, a dummy gate electrode 111 above the dummy gate dielectric 109, and a first spacer 113 may be formed on each fin 107. In an embodiment, the dummy gate dielectric 109 may be formed by thermal oxidation, chemical vapor deposition, sputtering, or any other method known in the art and used to form a gate dielectric. Depending on the gate dielectric formation technique, the thickness of the dummy gate dielectric 109 on the top of the fin 107 may be different from the gate dielectric thickness on the sidewalls of the fin 107.

[0030] The dummy gate dielectric 109 may include a material such as silicon dioxide or silicon oxynitride having a thickness ranging from about 3 angstroms to about 100 angstroms, for example, about 10 angstroms. The dummy gate dielectric 109 may be formed of a high dielectric constant (high-k) material (e.g., a relative dielectric constant greater than about 5) (e.g., lanthanum oxide (La2O3), aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), or zirconium oxide (ZrO2), or a combination thereof) having an equivalent oxide thickness of about 0.5 angstroms to about 100 angstroms, for example, about 10 angstroms or less. In addition, any combination of silicon dioxide, silicon oxynitride, and / or high-k materials may also be used for the dummy gate dielectric 109.

[0031] The dummy gate electrode 111 may include a conductive or non-conductive material and may be selected from the group consisting of polysilicon, W, Al, Cu, AlCu, W, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Co, Ni, combinations thereof, etc. The dummy gate electrode 111 may be deposited by chemical vapor deposition (CVD), sputtering deposition, or other techniques known in the art and used to deposit conductive materials. The thickness of the dummy gate electrode 111 may be about 1000 Å. to about The top surface of the dummy gate electrode 111 may have a non-planar top surface and may be planarized before patterning or gate etching the dummy gate electrode 111. At this time, ions may or may not be introduced into the dummy gate electrode 111. For example, ions may be introduced by ion implantation technology.

[0032] Once formed, the dummy gate dielectric 109 and the dummy gate electrode 111 can be patterned to form a series of stacks 115 above the fin 107. The stacks 115 define a plurality of channel regions on each side of the fin 107 below the dummy gate dielectric 109. The stacks 115 can be formed by depositing and patterning a gate mask ( Figure 1 The gate mask may include commonly used mask and sacrificial materials, such as (but not limited to) silicon oxide, silicon oxynitride, SiCON, SiC, SiOC, and / or silicon nitride, and may be deposited to about to about A dry etching process may be used to etch the dummy gate electrode 111 and the dummy gate dielectric 109 to form a patterned stack 115 .

[0033] Once the stack 115 has been patterned, the first spacer 113 may be formed. The first spacer 113 may be formed on opposite sides of the stack 115. The first spacer 113 is typically formed by blanket depositing a spacer layer ( Figure 1 The spacer layer may include SiN, oxynitride, SiC, SiON, SiOCN, SiOC, oxide, etc., and may be formed by methods for forming such layers, such as chemical vapor deposition (CVD), plasma enhanced CVD, sputtering, and other methods known in the art. The spacer layer may include a different material with different etching characteristics or the same material as the dielectric material in the first isolation region 105. The first spacer 113 may then be patterned, for example, by one or more etches to remove the spacer layer from the horizontal surface of the structure, thereby forming the first spacer 113.

[0034] In an embodiment, the first spacer 113 may be formed to have a thickness between about Peace Additionally, once the first spacers 113 have been formed, the first spacers 113 adjacent to one stack 115 may be separated from the first spacers 113 adjacent to another stack 115 by a distance between about 5 nm and about 200 nm, for example, about 20 nm. However, any suitable thickness and distance may be used.

[0035] Figure 2 The removal of the fin 107 and the regrowth of the source / drain region 201 from those areas not protected by the stack 115 and the first spacer 113 is shown. The removal of the fin 107 from those areas not protected by the stack and the first spacer 113 can be performed by reactive ion etching (RIE) using the stack 115 and the first spacer 113 as a hard mask, or any other suitable removal process. The removal can continue until the fin 107 is coplanar with the surface of the first isolation region 105 (as shown) or below the surface of the first isolation region 105.

[0036] Once these portions of the fins 107 have been removed, a hard mask (not separately shown) is placed and patterned to cover the dummy gate electrodes 111 to prevent growth, and the source / drain regions 201 can be regrown in contact with each fin 107. In an embodiment, the source / drain regions 201 can be regrown, and in some embodiments, the source / drain regions 201 can be regrown to form a stressor that will stress the channel region of the fin 107 located below the stack 115. In embodiments where the fins 107 include silicon and the FinFET is a p-type device, the source / drain regions 201 can be regrown by a selective epitaxial process using a material such as silicon or a material such as silicon germanium having a different lattice constant than the channel region. The epitaxial growth process can use precursors such as silane, dichlorosilane, germane, etc., and can last for a time between about 5 minutes and about 120 minutes, for example, about 30 minutes.

[0037] In an embodiment, the source / drain region 201 may be formed to have a thickness between about Peace and a thickness between about Peace The height between, for example, about In this embodiment, the source / drain regions 201 may be formed to have a height between about 5 nm and about 250 nm, for example, about 100 nm, above the upper surface of the first isolation region 105. However, any suitable height may be used.

[0038] Once the source / drain region 201 is formed, dopants can be implanted into the source / drain region 201 in the following manner: appropriate dopants are implanted to supplement the dopants in the fin 107. For example, p-type dopants such as boron, gallium, indium, etc. can be implanted to form a PMOS device. Alternatively, n-type dopants such as phosphorus, arsenic, antimony, etc. can be implanted to form an NMOS device. These dopants can be implanted by using the stack 115 and the first spacer 113 as a mask. It should be noted that a person of ordinary skill in the art will recognize that many other processes, steps, etc. can be used to implant dopants. For example, a person of ordinary skill in the art will recognize that multiple implants can be performed using various combinations of spacers and liners to form source / drain regions with specific shapes or characteristics suitable for specific purposes. Any of these processes can be used to implant dopants, and the above description is not meant to limit the present embodiment to the above steps.

[0039] Furthermore, at this time, the hard mask covering the dummy gate electrode 111 during the formation of the source / drain regions 201 is removed. In an embodiment, the hard mask may be removed using, for example, a wet or dry etching process selective to the material of the hard mask. However, any suitable removal process may be used.

[0040] Figure 2 Also shown is an interlayer dielectric (ILD) layer 203 formed over the stack 115 and the source / drain regions 201 (in Figure 2 The ILD layer 203 may include a material such as borophosphosilicate glass (BPSG), but any suitable dielectric may be used. The ILD layer 203 may be formed using a process such as PECVD, but other processes such as LPCVD may be used instead. The ILD layer 203 may be formed to be between about Peace Once formed, the ILD layer 203 may be planarized with the first spacer 113 using, for example, a planarization process (eg, a chemical mechanical polishing process), but any suitable process may be used.

[0041] Figure 3 Shows Figure 2 A cross-sectional view along line 3-3' is provided to better illustrate the removal and replacement of the material of the dummy gate electrode 111 and the dummy gate dielectric 109. In an embodiment, the dummy gate electrode 111 and the dummy gate dielectric 109 may be removed using, for example, one or more wet or dry etching processes utilizing an etchant that is selective to the material of the dummy gate electrode 111 and the dummy gate dielectric 109. However, any suitable removal process(es) may be used.

[0042] Once the dummy gate electrode 111 and the dummy gate dielectric 109 have been removed, the process for forming the first gate stack 603 can begin by depositing a series of layers. In an embodiment, the series of layers may include an interface layer 301, a first dielectric material 303, a first metal material 305, and a first p-metal work function layer 307.

[0043] Optionally, the interface layer 301 may be formed before forming the first dielectric material 303. In an embodiment, the interface layer 301 may be a material such as silicon dioxide formed by a process such as in situ steam generation (ISSG) or a deposition process such as chemical vapor deposition or atomic layer deposition. In another embodiment, the interface layer 301 may be a high-k material (e.g., HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, LaO, ZrO, Ta2O5, combinations thereof, etc.) having a thickness between about Peace A first thickness between, for example, about In embodiments utilizing a deposition process, the interface layer 301 may be formed uniformly as shown, whereas in embodiments utilizing ISSG, the interface layer 301 may be formed along the bottom of the opening without extending along the sidewalls of the first spacer 113 .

[0044] Once the interface layer 301 is formed, the first dielectric material 303 may be formed as a capping layer over the interface layer 301. In an embodiment, the first dielectric material 303 is a high-k material deposited by a process such as atomic layer deposition, chemical vapor deposition, etc., for example, HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, LaO, ZrO, Ta2O5, combinations thereof, etc. The first dielectric material 303 may be deposited to a thickness between about Peace A second thickness between the two, but any suitable material and thickness may be used.

[0045] The first metal material 305 or metal gate cap layer can be formed adjacent to the first dielectric material 303 as a barrier layer and can be formed of a metal material such as TaN, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ru, Mo, WN, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicate, zirconium aluminate, combinations of these, etc. The first metal material 305 can be deposited to a thickness between about 1000 Å and about 1000 Å using a deposition process such as atomic layer deposition, chemical vapor deposition, sputtering, etc. Peace A third thickness between 100 and 100 Å, but any suitable deposition process or thickness may be used.

[0046] The first p-metal work function layer 307 can be formed adjacent to the first metal material 305, and in certain embodiments, can be similar to the first metal material 305. For example, the first p-metal work function layer 307 can be formed of a metal material such as TiN, Ti, TiAlN, TaC, TaCN, TaSiN, TaSi2, NiSi2, Mn, Zr, ZrSi2, TaN, Ru, Al, Mo, MoSi2, WN, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicate, zirconium aluminate, combinations of these, etc. In addition, the first p-metal work function layer 307 can be deposited to a thickness between about 1000 and 1000 m using a deposition process such as atomic layer deposition, chemical vapor deposition, sputtering, etc. Peace A fourth thickness between 100 and 150 nm, but any suitable deposition process or thickness may be used.

[0047] In addition, after the deposition of the first p-metal work function layer 307, the opening left by removing the dummy gate electrode 111 and the dummy gate dielectric 109 has been partially filled. However, the remainder of the opening will still remain as wide as possible in order to keep the subsequent process window (e.g., gap fill process window) as wide as possible for process adjustment. However, any suitable width may be used.

[0048] Figure 4 The processing technology (in Figure 4 The first p-metal work function layer 307 is provided with a plurality of p-metal work function layers (represented by arrows labeled 401 in FIG. 1 ), which are performed to help prevent diffusion of materials from other structures (e.g., an overlying n-work function layer) and to help capture elements that may otherwise diffuse without increasing the overall thickness of the first p-metal work function layer 307. In one embodiment, the treatment process may be performed using one or more elements (e.g., silicon). However, any suitable element that can be used to capture diffusing elements may be used.

[0049] In certain embodiments using silicon, a gaseous precursor containing silicon atoms may be utilized to introduce the silicon into the first p-metal work function layer 307. For example, in some embodiments, silicon may be introduced into the first p-metal work function layer 307 by introducing a process precursor (e.g., a silicon-containing precursor such as silane (SiH4) or the like) into a process chamber that also holds the first p-metal work function layer 307.

[0050] In an embodiment, the treatment process 401 may be initiated by introducing a treatment precursor into the first p-metal work function layer 307 within the process chamber. Such introduction may be performed by carrying the treatment precursor into the process chamber using a carrier gas such as argon. The combined treatment precursor and carrier gas may be introduced into the process chamber at a flow rate between about 100 sccm and about 6,000 sccm.

[0051] In the chamber, the process precursor may contact the first p-metal work function layer 307 to initiate a chemical reaction in the first p-metal work function layer 307. In some embodiments, the chemical reaction may be performed in the process chamber at a temperature between about 25° C. and about 1000° C. (e.g., between about 400° C. and about 600° C.) and at a pressure between about 0.5 Torr and about 50 Torr. However, any suitable reaction parameters may be used.

[0052] In embodiments where a silicon precursor is used as the treatment precursor, by utilizing treatment process 401, silicon present in the silicon precursor will react with the material of the first p-metal work function layer 307 (e.g., TiN) and the silicon will be incorporated into the material of the first p-metal work function layer 307. In embodiments where the first p-metal work function layer 307 is titanium nitride and the treatment precursor is a silicon precursor, the introduction of silicon can convert the first p-metal work function layer 307 into titanium silicon nitride (TiSiN).

[0053] In some embodiments, the treatment process 401 can be performed to incorporate silicon into the first p-metal work function layer 307. Thus, the treatment process 401 can be performed for a time between about 1 second and about 1 hour, for example, between about 30 seconds and 60 seconds. For these time periods, the treatment process 401 can cause the first p-metal work function layer 307 to have a silicon concentration between about 1% atomic and about 20% atomic. However, any suitable silicon concentration and any suitable time period can be used.

[0054] By introducing silicon into the structure, process 401 will serve to prevent additional elements such as aluminum from diffusing from the overlying structure, such as first n-metal work function layer 309. By preventing the diffusion of additional elements, these additional elements cannot diffuse into other areas of the structure and interfere with the operation of the device.

[0055] In addition, by using the treatment process 401 to help prevent diffusion of materials, no other additional layers are required between the first p-metal work function layer 307 and the first n-metal work function layer 309. Moreover, by using the treatment process 401, the thickness of the first p-metal work function layer 307 can be maintained at its initial deposition thickness. Therefore, the first width W1 of the opening can be maintained, and a larger process window for subsequent deposition can be obtained.

[0056] Figure 5 3 shows the deposition of the first n-metal work function layer 309. In an embodiment, the first n-metal work function layer 309 can be a material such as TiAlN, Ti, Ag, Al, TaAl, TaAlC, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. For example, the first n-metal work function layer 309 can be deposited to a thickness between about 100 nm and about 100 nm using an atomic layer deposition (ALD) process, a CVD process, or the like. Peace The sixth thickness is between about However, any suitable materials and processes may be used to form the first n-metal work function layer 309 .

[0057] When the first n-metal work function layer 309 is deposited, there may be some elements (e.g., aluminum) present that would negatively impact the device if allowed to diffuse. However, when the treatment process 401 is used, any such elements (e.g., aluminum) that may be present within the first n-metal work function layer 309 will be reduced or prevented from completely diffusing through the structure. In certain embodiments, by reducing or preventing aluminum from diffusing to the interface between the first dielectric material 303 and the first metal material 305, the total amount of aluminum that will diffuse into these underlying layers may also be reduced, but there may be a small concentration gradient in each layer. For example, the concentration gradient of an element (e.g., aluminum) may extend from the first n-metal work function layer 309 into the first p-metal work function layer 307, but still stop before the concentration gradient reaches the first dielectric layer 303. In other embodiments, the aluminum does not penetrate into the first dielectric material 303 or the interface layer 301 at all and does not affect the threshold voltage.

[0058] Figure 5 Also shown is the deposition of an optional glue layer 501 and fill material 503. Once the first n-metal work function layer 309 has been formed, the glue layer 501 may be formed to help adhere the overlying fill material 503 to the underlying first n-metal work function layer 309, as well as provide a nucleation layer for forming the fill material 503. In an embodiment, the glue layer 501 may be a material such as titanium nitride, or may be a similar material as the first n-metal work function layer 309 and may be formed using a similar process (e.g., ALD) to between about 1000 Å and 1000 Å. Peace The seventh thickness between, for example, about However, any suitable materials and processes may be used.

[0059] Once the glue layer 501 has been formed, a fill material 503 is deposited to fill the remainder of the opening with the glue layer 501. In an embodiment, the fill material 503 may be a material such as tungsten, Al, Cu, AlCu, W, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Co, Ni, combinations of these, and the like, and may be formed using a deposition process such as electroplating, chemical vapor deposition, atomic layer deposition, physical vapor deposition, combinations of these, and the like. Additionally, the fill material 503 may be deposited to a depth between about 1000 mm and about 1000 mm. To date The thickness between, for example, about However, any suitable material may be used.

[0060] Figure 6 It is shown that after fill material 503 has been deposited to fill and overfill the openings, the material may be planarized to form a first gate stack 603. In an embodiment, the material may be planarized with the first spacer 113 using, for example, a chemical mechanical polishing process, but any suitable process may be used, such as grinding or etching.

[0061] After the material of the first gate stack 603 has been formed and planarized, the material of the first gate stack 603 may be recessed and capped with the capping layer 601. In an embodiment, the material of the first gate stack 603 may be recessed using, for example, a wet or dry etching process using an etchant that is selective to the material of the first gate stack 603. In an embodiment, the material of the first gate stack 603 may be recessed a distance between about 5 nm and about 150 nm, for example, about 120 nm. However, any suitable process and distance may be used.

[0062] Once the material of the first gate stack 603 has been recessed, the capping layer 601 may be deposited and planarized with the first spacer 113. In an embodiment, the capping layer 601 is a material such as SiN, SiON, SiCON, SiC, SiOC, combinations of these, etc., deposited using a deposition process such as atomic layer deposition, chemical vapor deposition, sputtering, etc. The capping layer 601 may be deposited to a depth between about 1000 nm and about 1000 nm. Peace and then planarized using a planarization process such as chemical mechanical polishing so that the capping layer 601 is coplanar with the first spacer 113 .

[0063] By using the embodiments described herein, diffusion of elements (e.g., aluminum) that may have a deleterious effect on the operation of the device may be reduced or prevented. Thus, the deleterious effects of the elements may be reduced. For example, in embodiments using aluminum, the diffusion of the aluminum may be minimized so that the aluminum does not affect the threshold voltage of the PFET device, thereby reducing the flatband voltage (V fb ) is increased to about 0.493 volts, an increase of 68 mV over a device not using the embodiments described herein. In this way, the threshold voltage can be modified without increasing the thickness of the p-work function metal and without affecting the subsequent gap fill window.

[0064] In an embodiment, a method of manufacturing a semiconductor device includes: depositing a gate dielectric over a semiconductor fin; depositing a first p-metal work function layer over the gate dielectric; treating the first p-metal work function layer with a silicon-containing gas; and depositing a first n-metal work function layer over the first p-metal work function layer. In an embodiment, the silicon-containing gas is silane. In an embodiment, depositing the first p-metal work function layer deposits titanium nitride. In an embodiment, the first n-metal work function layer includes titanium aluminum carbide. In an embodiment, treating the first p-metal work function layer prevents aluminum from diffusing from the titanium aluminum carbide. In an embodiment, the method further includes depositing a glue layer over the first n-metal work function layer. In an embodiment, depositing the first p-metal work function layer deposits the first p-metal work function layer to no greater than The first p-metal work function layer has a first thickness, and after the first p-metal work function layer is treated with the silicon-containing gas, the first p-metal work function layer has the first thickness.

[0065] In another embodiment, a method of manufacturing a semiconductor device includes: depositing a first p-metal work function layer over a gate dielectric over a semiconductor fin; depositing a first n-metal work function layer on the first p-metal work function layer, the first n-metal work function layer including a first diffusion element; and preventing diffusion of the first diffusion element by introducing silicon into the first p-metal work function layer before depositing the first n-metal work function layer. In an embodiment, introducing silicon includes soaking the first p-metal work function layer in a silicon-containing gas. In an embodiment, the silicon-containing gas is silane. In an embodiment, after introducing silicon, the first p-metal work function layer has a silicon concentration between about 1% atomic and about 20% atomic. In an embodiment, soaking the first p-metal work function layer in the silicon-containing gas includes soaking for between about 30 seconds and about 60 seconds. In an embodiment, soaking the first p-metal work function layer introduces the silicon-containing gas at a flow rate between about 100 sccm and about 6,000 sccm. In an embodiment, soaking the first n-metal work function layer is performed at a temperature between about 400° C. and about 600° C. and for a time between about 30 seconds and about 60 seconds.

[0066] In yet another embodiment, a semiconductor device includes: a semiconductor fin; a gate dielectric over the semiconductor fin; a first p-metal work function layer over the gate dielectric, the first p-metal work function layer including silicon; a first n-metal work function layer over the first p-metal work function layer; and aluminum within both the first p-metal work function layer and the first n-metal work function layer, wherein a concentration gradient of the aluminum extends from the first n-metal work function layer to the first p-metal work function layer but ends before extending to the gate dielectric. In an embodiment, the first n-metal work function layer includes titanium aluminum carbide. In an embodiment, the first p-metal work function layer includes titanium silicon nitride. In an embodiment, silicon has a concentration within the first p-metal work function layer between about 1% atomic and about 20% atomic. In an embodiment, the first p-metal work function layer has a concentration of no greater than about 10% atomic. In an embodiment, the semiconductor device further comprises: a glue layer above the first n-metal work function layer; a filling material above the glue layer; and a dielectric cap layer above the filling material.

[0067] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same advantages of the embodiments described herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

[0068] Example 1. A method for manufacturing a semiconductor device, the method comprising: depositing a gate dielectric over a semiconductor fin; depositing a first p-metal work function layer over the gate dielectric; treating the first p-metal work function layer with a silicon-containing gas; and depositing a first n-metal work function layer over the first p-metal work function layer.

[0069] Example 2. The method of Example 1, wherein the silicon-containing gas is silane.

[0070] Example 3. The method of Example 2, wherein depositing the first p-metal work function layer deposits titanium nitride.

[0071] Example 4. The method of Example 3, wherein the first n-metal work function layer comprises titanium aluminum carbide.

[0072] Example 5. The method of Example 4, wherein treating the first p-metal work function layer prevents aluminum from diffusing from the titanium aluminum carbide.

[0073] Example 6. The method of Example 1 further comprising depositing a glue layer over the first n-metal work function layer.

[0074] Example 7. The method of Example 1, wherein the first p-metal work function layer is deposited to a depth not greater than The first p-metal work function layer has a first thickness, and wherein after the first p-metal work function layer is treated with the silicon-containing gas, the first p-metal work function layer has the first thickness.

[0075] Example 8. A method for manufacturing a semiconductor device, the method comprising: depositing a first p-metal work function layer above a gate dielectric above a semiconductor fin; depositing a first n-metal work function layer on the first p-metal work function layer, the first n-metal work function layer including a first diffusion element; and preventing diffusion of the first diffusion element by introducing silicon into the first p-metal work function layer before depositing the first n-metal work function layer.

[0076] Example 9. The method of Example 8, wherein introducing the silicon comprises immersing the first p-metal work function layer in a silicon-containing gas.

[0077] Example 10. The method of Example 9, wherein the silicon-containing gas is silane.

[0078] Example 11. The method of Example 9, wherein, after introducing the silicon, the first p-metal work function layer has a silicon concentration between about 1% atomic and about 20% atomic.

[0079] Example 12. The method of Example 9, wherein immersing the first p-metal work function layer in a silicon-containing gas comprises immersing for between about 30 seconds and about 60 seconds.

[0080] Example 13. The method of Example 12, wherein immersing the first p-metal work function layer introduces the silicon-containing gas at a flow rate between about 100 seem and about 6,000 seem.

[0081] Example 14. The method of Example 13, wherein soaking the first n-metal work function layer is performed at a temperature between about 400° C. and about 600° C. and for a time between about 30 seconds and about 60 seconds.

[0082] Example 15. A semiconductor device comprising: a semiconductor fin; a gate dielectric above the semiconductor fin; a first p-metal work function layer above the gate dielectric, the first p-metal work function layer comprising silicon; a first n-metal work function layer above the first p-metal work function layer; and aluminum located in both the first p-metal work function layer and the first n-metal work function layer, wherein a concentration gradient of the aluminum extends from the first n-metal work function layer to the first p-metal work function layer but ends before extending to the gate dielectric.

[0083] Example 16. The semiconductor device of Example 15, wherein the first n-metal work function layer comprises titanium aluminum carbide.

[0084] Example 17. The semiconductor device of Example 16, wherein the first p-metal work function layer comprises titanium silicon nitride.

[0085] Example 18. The semiconductor device of Example 15, wherein the silicon has a concentration between about 1% atomic and about 20% atomic within the first p-metal work function layer.

[0086] Example 19. The semiconductor device of Example 15, wherein the first p-metal work function layer has a thickness not greater than Thickness.

[0087] Example 20. The semiconductor device of Example 15, further comprising: a glue layer over the first n-metal work function layer; a fill material over the glue layer; and a dielectric cap layer over the fill material.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: depositing a gate dielectric over the semiconductor fin; depositing a first p-metal work function layer over the gate dielectric; treating the first p-metal work function layer with a silicon-containing gas, wherein after the treating, the first p-metal work function layer has a silicon concentration between 1 atomic % and 20 atomic %; and depositing a first n-metal work function layer over the first p-metal work function layer; Wherein, after depositing the first n-metal work function layer, a concentration gradient of aluminum extends from the first n-metal work function layer to the first p-metal work function layer but ends before extending to the gate dielectric.

2. The method according to claim 1, wherein: The silicon-containing gas is silane.

3. The method according to claim 2, wherein: Depositing the first p-metal work function layer deposits titanium nitride.

4. The method according to claim 3, wherein: The first n-metal work function layer includes titanium aluminum carbide.

5. The method according to claim 4, wherein: Treating the first p-metal work function layer inhibits diffusion of aluminum from the titanium aluminum carbide. The method of claim 1 , further comprising depositing a glue layer over the first n-metal work function layer.

7. The method according to claim 1, wherein: Depositing the first p-metal work function layer Depositing the first p-metal work function layer to a depth not greater than The first p-metal work function layer has a first thickness, and wherein after the first p-metal work function layer is treated with the silicon-containing gas, the first p-metal work function layer has the first thickness.

8. A method for manufacturing a semiconductor device, the method comprising: depositing a first p-metal work function layer over the gate dielectric over the semiconductor fin; depositing a first n-metal work function layer on the first p-metal work function layer, wherein the first n-metal work function layer includes a first diffusion element; as well as preventing diffusion of the first diffusion element by introducing silicon into the first p-metal work function layer before depositing the first n-metal work function layer; wherein, after the introduction of the silicon, the first p-metal work function layer has a silicon concentration between 1 atomic % and 20 atomic %; After depositing the first n-metal work function layer, a concentration gradient of the first diffusion element extends from the first n-metal work function layer to the first p-metal work function layer but ends before extending to the gate dielectric.

9. The method according to claim 8, wherein: Introducing the silicon includes immersing the first p-metal work function layer in a silicon-containing gas.

10. The method according to claim 9, wherein: The silicon-containing gas is silane.

11. The method according to claim 9, wherein: Soaking the first p-metal work function layer in the silicon-containing gas includes soaking for between 30 seconds and 60 seconds.

12. The method according to claim 11, wherein: The silicon-containing gas is introduced at a flow rate between 100 sccm and 6000 sccm to immerse the first p-metal work function layer.

13. The method according to claim 12, wherein: Soaking the first p-metal work function layer is performed at a temperature between 400° C. and 600° C. and for a time between 30 seconds and 60 seconds.

14. A semiconductor device comprising: Semiconductor fins; a gate dielectric over the semiconductor fin; a first p-metal work function layer over the gate dielectric, the first p-metal work function layer comprising silicon, wherein the silicon has a concentration between 1 atomic % and 20 atomic % within the first p-metal work function layer; a first n-metal work function layer overlying the first p-metal work function layer; and Aluminum is located in both the first p-metal work function layer and the first n-metal work function layer, wherein a concentration gradient of the aluminum extends from the first n-metal work function layer to the first p-metal work function layer but ends before extending to the gate dielectric.

15. The semiconductor device according to claim 14, wherein: The first n-metal work function layer includes titanium aluminum carbide.

16. The semiconductor device according to claim 15, wherein The first p-metal work function layer includes titanium silicon nitride.

17. The semiconductor device according to claim 14, wherein: The first p-metal work function layer has a thickness not greater than Thickness.

18. The semiconductor device according to claim 14, further comprising: a glue layer, above the first n-metal work function layer; a filling material, above the glue layer; as well as A dielectric cap layer is above the filling material.

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