Semiconductor device and method for forming the same

Abstract

A semiconductor device and a method for forming the same, the method comprising: providing a semiconductor substrate; forming a drift region in the semiconductor substrate; forming an isolation structure in the drift region; forming a gate structure on the surface of the semiconductor substrate, and after forming the gate structure, forming a body region in the semiconductor substrate, the body region being adjacent to the drift region and having a gap with the isolation structure, one end of the gate structure overlapping with the body region in the width direction, and the other end of the gate structure overlapping with the isolation structure in the width direction. The scheme of the present invention helps to reduce the source-drain on-resistance of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor device and a method for forming the same. Background Art

[0002] Laterally diffused metal oxide semiconductor (LDMOS) transistors are mainly used in power integrated circuits, such as RF power amplifiers for mobile phone base stations, and can also be used in high frequency (HF), very high frequency (VHF) and ultra-high frequency (UHF) broadcast transmitters, microwave radar and navigation systems, etc. LDMOS technology brings higher peak-to-average power ratio, higher gain and linearity to the new generation of base station amplifiers, and also brings higher data transmission rates for multimedia services.

[0003] For LDMOS transistors, the on-resistance (Ron) between the source region (Source) and the drain region (Drain) and the breakdown voltage (Breakdown Voltage, BV) are two important indicators to measure performance.

[0004] There is an urgent need for a semiconductor device and a method for forming the same to effectively reduce Ron and improve device performance. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor device and a method for forming the same, which are helpful to reduce the source-drain on-resistance Ron of the semiconductor device.

[0006] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor device, comprising: providing a semiconductor substrate; forming a drift region in the semiconductor substrate; forming an isolation structure in the drift region; forming a gate structure on the surface of the semiconductor substrate, and after forming the gate structure, forming a body region in the semiconductor substrate, wherein the body region is adjacent to the drift region and has a gap with the isolation structure, one end of the gate structure overlaps with the body region in the width direction, and the other end of the gate structure overlaps with the isolation structure in the width direction; wherein the width direction is parallel to the moving direction of the carriers.

[0007] Optionally, forming a gate structure on the surface of the semiconductor substrate and forming a body region in the semiconductor substrate include: forming a gate material layer on the surface of the semiconductor substrate; etching the gate material layer to remove the gate material layer outside a reserved area, wherein the reserved area refers to an area occupied by the gate structure and the body region on the surface of the semiconductor substrate; forming a first mask layer, wherein the first mask layer exposes an area occupied by the body region on the surface of the semiconductor substrate; etching the gate material layer using the first mask layer as a mask to form the gate structure; and performing a first ion implantation using the first mask layer as a mask to form the body region.

[0008] Optionally, the method for forming a semiconductor device further includes: using the first mask layer as a mask to perform a second ion implantation to form a self-aligned region; wherein the self-aligned region is located on top of the body region, and the type of doping ions in the self-aligned region is different from the type of doping ions in the body region.

[0009] Optionally, the atomic weight of the doping ions in the self-aligned region is greater than the atomic weight of the doping ions in the body region.

[0010] Optionally, the doping ions in the body region are B ions, and the doping ions in the self-aligned region are As ions; or, the doping ions in the body region are P ions, and the doping ions in the self-aligned region are In ions.

[0011] Optionally, the method for forming a semiconductor device further includes: removing the first mask layer; and performing a first heat treatment on the semiconductor substrate.

[0012] Optionally, forming a drift region in the semiconductor substrate includes: performing a third ion implantation on the semiconductor substrate to form a drift region; performing a fourth ion implantation on at least a portion of the drift region to form a shallow heavily doped region; wherein the shallow heavily doped region is located at the top of the drift region; the type of doping ions in the shallow heavily doped region is the same as the type of doping ions in the drift region; and the atomic weight of the doping ions in the shallow heavily doped region is greater than the atomic weight of the doping ions in the drift region.

[0013] Optionally, the doping ions in the drift region are P ions, and the doping ions in the shallow heavily doped region are As ions; or, the doping ions in the drift region are B ions, and the doping ions in the shallow heavily doped region are In ions.

[0014] Optionally, before performing a fourth ion implantation on at least a portion of the drift region to form a shallow heavily doped region, the method for forming a semiconductor device further includes: performing a second heat treatment on the semiconductor substrate.

[0015] Optionally, the semiconductor device is LDMOS.

[0016] To solve the above technical problems, an embodiment of the present invention provides a semiconductor device, comprising: a semiconductor substrate; a gate structure located on the surface of the semiconductor substrate; a drift region located in the semiconductor substrate; an isolation structure located in the drift region; a body region located in the semiconductor substrate, the body region is adjacent to the drift region and has a gap with the isolation structure, one end of the gate structure overlaps with the body region in the width direction, and the other end of the gate structure overlaps with the isolation structure in the width direction; wherein the width direction is parallel to the direction of movement of carriers.

[0017] Optionally, the semiconductor device further comprises: a self-aligned region located on top of the body region, wherein the type of doping ions in the self-aligned region is different from the type of doping ions in the body region.

[0018] Optionally, the atomic weight of the doping ions in the self-aligned region is greater than the atomic weight of the doping ions in the body region.

[0019] Optionally, the semiconductor device also includes: a shallow heavily doped region, located on the top of the drift region; wherein the type of doping ions in the shallow heavily doped region is the same as the type of doping ions in the drift region; and the atomic weight of the doping ions in the shallow heavily doped region is greater than the atomic weight of the doping ions in the drift region.

[0020] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0021] In an embodiment of the present invention, a semiconductor substrate is provided; a drift region is formed in the semiconductor substrate; an isolation structure is formed in the drift region; a gate structure is formed on the surface of the semiconductor substrate, and after the gate structure is formed, a body region is formed in the semiconductor substrate, the body region is adjacent to the drift region and has a gap with the isolation structure, one end of the gate structure overlaps with the body region in the width direction, and the other end of the gate structure overlaps with the isolation structure in the width direction; wherein the width direction is parallel to the moving direction of the carriers. By adopting the above scheme, by first forming the isolation structure and the gate structure, and then forming the body region after forming the gate structure, the ion implantation position of the body region can be more accurately determined, and the controllability of the distance between the gate structure and the body region can be improved, so that the body region has an opportunity to be set to have a smaller width. Since the top of the body region is the channel between the source region and the drain region, reducing its width helps to reduce the source-drain on-resistance Ron of the device.

[0022] Furthermore, by using the same mask layer, i.e., the first mask layer, to form the gate structure and the body region, compared to using different mask layers to form the gate structure and the body region, the position of the gate structure and the body region can be more controllable, thereby further providing the opportunity to set the width of the body region to be smaller.

[0023] Furthermore, a second ion implantation is performed in the body region to form a self-aligned region. Since the self-aligned region is located at the top of the body region and has a different type of doping ions from the body region, it can occupy a portion of the channel region of the body region, thereby forming a shorter channel, which helps to further reduce the source-drain on-resistance.

[0024] Furthermore, the atomic weight of the doped ions in the self-aligned region is greater than that of the doped ions in the body region. When the semiconductor substrate is subsequently heat treated, the doped ions in the body region have a smaller atomic weight and are easy to diffuse, while the doped ions in the self-aligned region have a larger atomic weight and are not easy to diffuse. Therefore, the doping structure in the deeper region of the semiconductor substrate will not be affected. When the doping area of ​​the self-aligned region is consistent with that of the body region, a channel region can still be formed by diffusion to avoid penetration of the self-aligned region and the drift region. Moreover, since the channel of the semiconductor device is formed by diffusion, the channel width is very small, and there is an opportunity to obtain a very small source-drain on-resistance.

[0025] Furthermore, a fourth ion implantation is performed on at least a portion of the drift region to form a shallow heavily doped region. Since the shallow heavily doped region is located at the top of the drift region and has the same type of doping ions as the drift region and has a larger atomic weight and is not easy to diffuse, it helps to provide more carriers and further reduce the source-drain on-resistance. Furthermore, since the shallow heavily doped region is located at the top of the drift region, it will not affect the doping condition of the bottom region of the isolation structure, which means that it helps to maintain the breakdown voltage and avoid the occurrence of breakdown due to the increased doping process. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a schematic diagram of a cross-sectional structure of a semiconductor device in the prior art;

[0027] Figure 2 is a flow chart of a method for forming a semiconductor device in an embodiment of the present invention;

[0028] Figures 3 to 10 It is a schematic diagram of a device cross-sectional structure corresponding to each step in a method for forming a semiconductor device in an embodiment of the present invention. DETAILED DESCRIPTION

[0029] In the existing LDMOS manufacturing process, the body region is first formed by ion implantation, and then the isolation structure and the gate structure are formed. As a result, the device is limited by the manufacturing process, and Ron is usually large, which affects the operation speed.

[0030] Reference Figure 1 , Figure 1 It is a schematic diagram of the cross-sectional structure of a semiconductor device in the prior art.

[0031] The semiconductor device may include a semiconductor substrate 100 , a drift region 110 , a body region 120 , an isolation structure 102 , a gate structure 130 , and may also include a body terminal (B) 133 located in the body region 120 , a source terminal (S) 134 , and a drain terminal (D) 135 located in the drift region 110 .

[0032] In a specific implementation, an ion implantation process may be first used to form a drift region 110 and a body region 120 in the semiconductor substrate 100, respectively, and then an isolation structure 102 may be formed in the drift region 110, thereby forming a gate structure 130. One end of the gate structure 130 overlaps with the body region 120 in the width direction, and the other end of the gate structure 130 overlaps with the isolation structure 102 in the width direction.

[0033] Figure 1 The dotted line shown is used to indicate the current direction in the semiconductor device. Since the channel region T formed in the body region 120 is wider and the doping concentration of the drift region 110 is smaller or the doping concentration after diffusion due to heat treatment is smaller, the carrier movement speed is slowed down, that is, the source-drain on-resistance Ron is larger.

[0034] The inventors of the present invention have discovered through research that, in the prior art, the body region 120 is first formed by ion implantation, and then the isolation structure 102 and the gate structure 130 are formed. When forming the body region 120, the positions of the isolation structure 102 and the gate structure 130 cannot be used as a reference, which easily leads to uncontrollable distance between the body region 120 and the subsequently formed gate structure 130. Therefore, in order to ensure that the gate structure 130 can contact a portion of the top surface of the body region 120, the width of the body region 120 is usually set to be larger. As a result, since the doping type of the body region 120 is different from that of the drift region 110, the source-drain on-resistance Ron of the semiconductor device is larger.

[0035] It should be pointed out that in the prior art, since the drift region 110 and the body region 120 are respectively formed in the semiconductor substrate 100 by an ion implantation process, there is usually a gap between the drift region 110 and the body region 120, which further leads to a larger width of the semiconductor device and a larger source-drain on-resistance Ron.

[0036] The inventors of the present invention have further discovered through research that for a high voltage laterally diffused metal oxide semiconductor (LDMOS), in order to meet the requirement of high breakdown voltage, the drift region 110 needs to be lightly doped and subjected to long thermal processing, but this is not conducive to the improvement of Ron.

[0037] In an embodiment of the present invention, a semiconductor substrate is provided; a drift region is formed in the semiconductor substrate; an isolation structure is formed in the drift region; a gate structure is formed on the surface of the semiconductor substrate, and after the gate structure is formed, a body region is formed in the semiconductor substrate, the body region is adjacent to the drift region and has a gap with the isolation structure, one end of the gate structure overlaps with the body region in the width direction, and the other end of the gate structure overlaps with the isolation structure in the width direction; wherein the width direction is parallel to the moving direction of the carriers. By adopting the above scheme, by first forming the isolation structure and the gate structure, and then forming the body region after forming the gate structure, the ion implantation position of the body region can be more accurately determined, and the controllability of the distance between the gate structure and the body region can be improved, so that the body region has an opportunity to be set to have a smaller width. Since the top of the body region is the channel between the source region and the drain region, reducing its width helps to reduce the source-drain on-resistance of the device.

[0038] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0039] Reference Figure 2 , Figure 2 1 is a flow chart of a method for forming a semiconductor device in an embodiment of the present invention. The method for forming a semiconductor device may include steps S21 to S24:

[0040] Step S21: providing a semiconductor substrate;

[0041] Step S22: forming a drift region in the semiconductor substrate;

[0042] Step S23: forming an isolation structure in the drift region;

[0043] Step S24: forming a gate structure on the surface of the semiconductor substrate, and after forming the gate structure, forming a body region in the semiconductor substrate, wherein the body region is adjacent to the drift region and has a gap with the isolation structure, one end of the gate structure overlaps with the body region in the width direction, and the other end of the gate structure overlaps with the isolation structure in the width direction.

[0044] Wherein, the width direction is parallel to the moving direction of the carriers.

[0045] Combine the following Figures 3 to 10 Each of the above steps is described below.

[0046] Figures 3 to 10 It is a schematic diagram of a device cross-sectional structure corresponding to each step in a method for forming a semiconductor device in an embodiment of the present invention.

[0047] Reference Figure 3 , providing a semiconductor substrate 200, performing a third ion implantation on the semiconductor substrate to form a drift region 210, and performing a fourth ion implantation on at least a portion of the drift region 210 to form a shallow heavily doped region 212.

[0048] Among them, the shallow heavily doped region 212 can be located at the top of the drift region 210, the type of doping ions in the shallow heavily doped region 212 can be the same as the type of doping ions in the drift region 210, and the atomic weight of the doping ions in the shallow heavily doped region 212 can be greater than the atomic weight of the doping ions in the drift region 210.

[0049] In a specific implementation, the semiconductor substrate 200 can be a silicon substrate, or the material of the semiconductor substrate 200 can also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, etc., which are suitable materials for use in semiconductor devices. The semiconductor substrate 200 can also be a silicon substrate on an insulator surface or a germanium substrate on an insulator surface, or a substrate on which an epitaxial layer (Epi layer) is grown.

[0050] Furthermore, the drift region 210 and the shallow heavily doped region 212 may be formed by an ion implantation process.

[0051] Specifically, the type of doping ions in the shallow heavily doped region 212 can be the same as the type of doping ions in the drift region 210 , for example, both are P-type ions or both are N-type ions, and the atomic weight of the doping ions in the shallow heavily doped region 212 can be greater than the atomic weight of the doping ions in the drift region 210 .

[0052] In an embodiment of the present invention, a fourth ion implantation is performed on at least a portion of the drift region 210 to form a shallow heavily doped region 212. Since the shallow heavily doped region 212 is located at the top of the drift region 210 and has the same type of doping ions as the drift region 210 and has a larger atomic weight and is not easy to diffuse, it helps to provide more carriers and further reduce the source-drain on-resistance Ron. Moreover, since the shallow heavily doped region 212 is located at the top of the drift region 210, it will not affect the doping condition of the bottom region of the isolation structure formed subsequently, which helps to maintain the breakdown voltage and avoid the occurrence of breakdown due to the increased doping process.

[0053] Furthermore, the doping ion type of the shallow heavily doped region 212 and the doping ion type of the drift region 210 may both be N-type, and the doping ions of the drift region 210 may be P ions, and the doping ions of the shallow heavily doped region 212 may be As ions.

[0054] In an embodiment of the present invention, by setting the doping ions of the drift region 210 to P ions and the doping ions of the shallow heavily doped region 212 to As ions, it can be achieved that the atomic weight of the shallow heavily doped region 212 is larger and not easy to diffuse, thereby not easily affecting the doping condition of the bottom area of ​​the isolation structure formed subsequently.

[0055] Furthermore, the doping ion type of the shallow heavily doped region 212 and the doping ion type of the drift region 210 may both be P-type, and the doping ions of the drift region 210 may be B ions, and the doping ions of the shallow heavily doped region 212 may be In ions.

[0056] In an embodiment of the present invention, by setting the doping ions of the drift region 210 to B ions and the doping ions of the shallow heavily doped region 212 to In ions, it can be achieved that the atomic weight of the shallow heavily doped region 212 is larger and not easy to diffuse, thereby not easily affecting the doping condition of the bottom area of ​​the isolation structure formed subsequently.

[0057] Before performing a fourth ion implantation on at least a portion of the drift region 210 to form a shallow heavily doped region 212 , the method further includes: performing a second heat treatment on the semiconductor substrate 200 .

[0058] Specifically, performing the second heat treatment on the semiconductor substrate 200 , that is, performing heat treatment on the semiconductor substrate 200 and the drift region 210 , can allow the doped ions to diffuse deeper into the semiconductor substrate 200 , thereby improving the performance of the semiconductor device.

[0059] In an embodiment of the present invention, after the second heat treatment, the fourth ion implantation is performed on at least a portion of the drift region 210 to form a shallow heavily doped region 212, which can easily make the doping concentration of the shallow heavily doped region 212 greater than the doping concentration of the drift region 210. Furthermore, due to the concentration difference, more carriers are present in the area closer to the subsequently formed gate structure, thereby further reducing the source-drain on-resistance Ron of the semiconductor device.

[0060] Reference Figure 4 , an isolation structure 202 is formed in the drift region 210 .

[0061] In a specific implementation, the isolation structure 202 helps to increase the breakdown voltage and reduce the possibility of the semiconductor device being broken down.

[0062] Furthermore, the depth of the isolation structure 202 is greater than the depth of the shallow heavily doped region 212 , wherein the depth direction is perpendicular to the surface of the semiconductor substrate 200 .

[0063] In the embodiment of the present invention, by setting the isolation structure 202 to have a greater depth, it is possible to increase the difficulty for carriers to bypass the bottom region of the isolation structure 202 , which helps to maintain a higher breakdown voltage of the semiconductor device.

[0064] Reference Figure 5 A gate material layer 231 is formed on the surface of the semiconductor substrate 200, and a second mask layer 262 is formed on the surface of the gate material layer 231. The gate material layer is etched using the second mask layer 262 as a mask to remove the gate material layer 231 outside a reserved area, wherein the reserved area refers to an area A occupied by the gate structure on the surface of the semiconductor substrate 200 and an area B occupied by the body region on the surface of the semiconductor substrate 200.

[0065] The material of the gate material layer 231 may include a dielectric material and a gate main material. The dielectric material may be, for example, silicon oxide (SiO 2 ) to form a gate oxide layer; the gate main material may be, for example, polysilicon (Poly).

[0066] Reference Figure 6 , forming a first mask layer 261, wherein the first mask layer 261 exposes the region B occupied by the body region on the surface of the semiconductor substrate, and using the first mask layer 261 as a mask, the gate material layer 231 (refer to Figure 5 ) is etched to form the gate structure 230.

[0067] It should be noted that, in the embodiment of the present invention, the first mask layer 261 covers the gate structure 230 and a part of the non-gate structure area, and exposes the body region, so when ion implantation is performed in the body region, the first mask layer 261 can continue to be used as a mask. If only a mask layer covering the gate structure 230 is formed, the gate structure 230 needs to be used as a mask when ion implantation is performed in the body region, which is easy to damage the gate structure 230. The solution of the embodiment of the present invention is used to better protect the gate structure 230.

[0068] Reference Figure 7 , using the first mask layer 261 as a mask, performing a first ion implantation to form an initial body region 221 .

[0069] The type of doping ions in the initial body region 221 is different from the type of doping ions in the drift region 210 .

[0070] In an embodiment of the present invention, by using the same mask layer, that is, the first mask layer 261 to form the gate structure 230 and the initial body region 221, compared with using different mask layers to form the gate structure and the body region respectively, the position of the gate structure 230 and the initial body region 221 can be more controllable, thereby further having the opportunity to set the width of the subsequently formed body region to be smaller.

[0071] Reference Figure 8 , using the first mask layer 261 as a mask, a second ion implantation is performed to form an initial self-aligned region 223 .

[0072] The initial self-aligned region 223 is located on the top of the initial body region 221 , and the type of doping ions in the initial self-aligned region 223 is different from the type of doping ions in the initial body region 221 .

[0073] In an embodiment of the present invention, a second ion implantation is performed in the initial body region 221 to form an initial self-alignment region 223. Since the initial self-alignment region 223 is located at the top of the initial body region 221 and has a different type of doping ions from the initial body region 221, it can occupy a portion of the channel region of the initial body region 221, thereby forming a shorter channel, which helps to further reduce the source-drain on-resistance Ron.

[0074] Furthermore, the atomic weight of the doping ions in the initial self-aligned region 223 may be greater than the atomic weight of the doping ions in the initial body region 221 .

[0075] In an embodiment of the present invention, the atomic weight of the doped ions in the initial self-alignment region 223 is greater than the atomic weight of the doped ions in the initial body region 221. When the semiconductor substrate 200 is subsequently heat-treated, since the atomic weight of the doped ions in the initial body region 221 is small and easy to diffuse, while the atomic weight of the doped ions in the initial self-alignment region 223 is large and not easy to diffuse, it will not affect the doping structure of the deeper area of ​​the semiconductor substrate 200. When the doping area of ​​the initial self-alignment region 223 is consistent with that of the initial body region 221, a channel region can still be formed by diffusion to avoid the initial self-alignment region 223 and the drift region 210 from penetrating. Since the channel of the semiconductor device is formed by diffusion, the channel width is very small, and there is an opportunity to obtain a very small source-drain on-resistance Ron.

[0076] Furthermore, the doping ions of the initial body region 221 may be of P type, the doping ions of the initial self-aligned region 223 may be of N type, and the doping ions of the initial body region 221 may be of B ions, and the doping ions of the initial self-aligned region 223 may be of As ions.

[0077] In an embodiment of the present invention, by setting the doping ions of the initial body region 221 to be B ions and the doping ions of the initial self-alignment region 223 to be As ions, it can be achieved that the atomic weight of the initial self-alignment region 223 is larger and not easy to diffuse, and thus not easy to diffuse together with the initial body region 221, affecting the formation of the channel and increasing the risk of breakdown.

[0078] Furthermore, the doping ions of the initial body region 221 may be N-type, the doping ions of the initial self-aligned region 223 may be P-type, and the doping ions of the initial body region 221 may be P-ions, and the doping ions of the initial self-aligned region 223 may be In-ions.

[0079] In an embodiment of the present invention, by setting the doping ions of the initial body region 221 to be P ions and the doping ions of the initial self-aligned region 223 to be In ions, it can be achieved that the shallow heavily doped region 212 has a larger atomic weight and is not easy to diffuse, thereby not easily affecting the doping condition of the bottom region of the isolation structure formed subsequently.

[0080] Reference Fig. 9 , remove the first mask layer 261 (refer to Figure 8 ), performing a first heat treatment on the semiconductor substrate 200 to form a body region 220 and a self-aligned region 222 after diffusion.

[0081] Specifically, since the atomic weight of the doped ions in the self-aligned region 222 is greater than that of the body region 220 , after diffusion, the diffusion width of the self-aligned region 222 is smaller than that of the body region 220 , thereby forming a channel region L in the body region 220 .

[0082] In the embodiment of the present invention, the channel region L is formed by diffusion, so that the channel region L in the body region 220 can be made as small as possible, thereby meeting the requirement of extremely small source-drain on-resistance Ron.

[0083] Reference Fig.10 , forming a body terminal (B) 233 located in the body region 220 , a source terminal (S) 234 , and a drain terminal (D) 235 located in the drift region 210 .

[0084] Fig.10 The dashed line is used to indicate the current direction in the semiconductor device. The channel region L formed in the body region 220 is relatively narrow, especially relative to the Figure 1 The width of the channel region T and the channel region L is significantly reduced. The doping concentration of the shallow heavily doped region 212 is relatively high, which helps to increase the carrier movement speed, that is, effectively reduces the source-drain on-resistance Ron.

[0085] In an embodiment of the present invention, by first forming the isolation structure 202 and the gate structure 230, and forming the body region 220 after forming the gate structure 230, the ion implantation position of the body region 220 can be determined more accurately, and the controllability of the distance between the gate structure 230 and the body region 220 can be improved, thereby having the opportunity to set the body region 220 to have a smaller width. Since the top of the body region 220 is the channel between the source region and the drain region, reducing its width helps to reduce the source-drain on-resistance Ron of the device.

[0086] Furthermore, the semiconductor device may be LDMOS, especially high-voltage LDMOS.

[0087] In the embodiment of the present invention, by setting the channel region L to be narrower and the doping concentration of the shallow heavily doped region 212 to be higher, the source-drain on-resistance Ron of the device can be reduced and a higher breakdown voltage can be maintained, thereby better meeting the requirements of high-voltage LDMOS.

[0088] In an embodiment of the present invention, a semiconductor device is also provided. Fig.10As shown, it may include: a semiconductor substrate 200; a gate structure 230, located on the surface of the semiconductor substrate 200; a drift region 210, located in the semiconductor substrate 200; an isolation structure 202, located in the drift region 210; a body region 220, located in the semiconductor substrate 200, the body region 220 is adjacent to the drift region 210 and has a gap with the isolation structure 202, one end of the gate structure 230 overlaps with the body region 220 in the width direction, and the other end of the gate structure 230 overlaps with the isolation structure 202 in the width direction; wherein the width direction is parallel to the moving direction of the carriers.

[0089] It should be pointed out that in the prior art, since the drift region and the body region are first formed separately in the semiconductor substrate and then the isolation structure and the gate structure are formed, there is usually a gap between the drift region and the body region.

[0090] In the embodiment of the present invention, since the drift region 210 , the isolation structure 202 and the gate structure 230 are formed first, and the body region 220 is formed after the gate structure 230 is formed, the body region 220 is adjacent to the drift region 210 .

[0091] In an embodiment of the present invention, by first forming the isolation structure 202 and the gate structure 230, and forming the body region 220 after forming the gate structure 230, the ion implantation position of the body region 220 can be determined more accurately, and the controllability of the distance between the gate structure 230 and the body region 220 can be improved, thereby having the opportunity to set the body region 220 to have a smaller width. Since the top of the body region 220 is the channel between the source region and the drain region, reducing its width helps to reduce the source-drain on-resistance Ron of the device.

[0092] Furthermore, the semiconductor device may further include: a self-aligned region 222 located on the top of the body region 220 , and the type of doping ions in the self-aligned region 222 is different from the type of doping ions in the body region 220 .

[0093] Furthermore, the atomic weight of the doping ions in the self-aligned region 222 is greater than the atomic weight of the doping ions in the body region 220 .

[0094] Furthermore, the semiconductor device may also include: a shallow heavily doped region 212, located at the top of the drift region 210; wherein the type of doping ions in the shallow heavily doped region 212 is the same as the type of doping ions in the drift region 210; and the atomic weight of the doping ions in the shallow heavily doped region 212 is greater than the atomic weight of the doping ions in the drift region 210.

[0095] Furthermore, the semiconductor device may be LDMOS.

[0096] For the principle, specific implementation and beneficial effects of this semiconductor device, please refer to the previous article and Figures 2 to 10 The related description about the method for forming the semiconductor device shown is not repeated here.

[0097] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor device, characterized in that: include: providing a semiconductor substrate; forming a drift region in the semiconductor substrate; forming a shallow heavily doped region in the drift region, wherein the shallow heavily doped region is located on the top of the drift region; forming an isolation structure in the drift region; forming a gate material layer on the surface of the semiconductor substrate; forming a first mask layer on the gate material layer; Using the first mask layer as a mask, etching the gate material layer to form a gate structure on the surface of the semiconductor substrate, and after forming the gate structure, forming a body region in the semiconductor substrate, the body region is adjacent to the drift region and has a gap with the isolation structure, one end of the gate structure overlaps with the body region in the width direction, and the other end of the gate structure overlaps with the isolation structure in the width direction, the first mask layer exposes the area occupied by the body region on the surface of the semiconductor substrate, and the first mask layer covers the gate structure, wherein the shallow heavily doped region is located between the body region and the isolation structure; Wherein, the width direction is parallel to the moving direction of the carriers; Using the first mask layer as a mask, performing a second ion implantation to form a self-aligned region; Wherein, the self-aligned region is located on the top of the body region, and the type of doping ions in the self-aligned region is different from the type of doping ions in the body region; removing the first mask layer; A first heat treatment is performed on the semiconductor substrate.

2. The method for forming a semiconductor device according to claim 1, wherein: Forming a gate structure on the surface of the semiconductor substrate, and forming a body region in the semiconductor substrate comprises: forming a gate material layer on the surface of the semiconductor substrate; Etching the gate material layer to remove the gate material layer outside a reserved area, wherein the reserved area refers to an area occupied by the gate structure and the body region on the surface of the semiconductor substrate; Using the first mask layer as a mask, etching the gate material layer to form the gate structure; A first ion implantation is performed using the first mask layer as a mask to form the body region.

3. The method for forming a semiconductor device according to claim 2, wherein: The doping ions of the body region are B ions, and the doping ions of the self-aligned region are As ions; or, The doping ions of the body region are P ions, and the doping ions of the self-aligned region are In ions.

4. The method for forming a semiconductor device according to claim 1, wherein: Forming a drift region in the semiconductor substrate includes: Performing a third ion implantation on the semiconductor substrate to form a drift region; Performing a fourth ion implantation on at least a portion of the drift region to form a shallow heavily doped region; Wherein, the shallow heavily doped region is located on the top of the drift region; The type of doping ions in the shallow heavily doped region is the same as the type of doping ions in the drift region; The atomic weight of the doping ions in the shallow heavily doped region is greater than the atomic weight of the doping ions in the drift region; A drain terminal is formed in the drift region, wherein the shallow heavily doped region and the drain terminal are located on both sides of the isolation structure.

5. The method for forming a semiconductor device according to claim 4, wherein: The doping ions of the drift region are P ions, and the doping ions of the shallow heavily doped region are As ions; or, The doping ions in the drift region are B ions, and the doping ions in the shallow heavily doped region are In ions.

6. The method for forming a semiconductor device according to claim 4, wherein: Before performing a fourth ion implantation on at least a portion of the drift region to form a shallow heavily doped region, the method further comprises: A second heat treatment is performed on the semiconductor substrate.

7. The method for forming a semiconductor device according to claim 1, wherein: The semiconductor device is LDMOS.

8. A semiconductor device, characterized in that: include: Semiconductor substrate; A gate structure, located on the surface of the semiconductor substrate; A drift region located in the semiconductor substrate; A shallow heavily doped region located on top of the drift region; An isolation structure located in the drift region; a body region located in the semiconductor substrate, the body region being adjacent to the drift region and having a gap with the isolation structure, one end of the gate structure overlapping with the body region in a width direction, and the other end of the gate structure overlapping with the isolation structure in a width direction, the body region being formed after the gate structure is formed, wherein the shallow heavily doped region is located between the body region and the isolation structure; The self-aligned region is located on the top of the body region; wherein the width direction is parallel to the moving direction of the carriers.

9. The semiconductor device according to claim 8, characterized in that Also includes: The type of doping ions in the self-aligned region is different from the type of doping ions in the body region.

10. The semiconductor device according to claim 9, characterized in that The atomic weight of doping ions in the self-aligned region is greater than the atomic weight of doping ions in the body region.

11. The semiconductor device according to claim 8, characterized in that Also includes: A drain terminal is located in the drift region, and the shallow heavily doped region and the drain terminal are located on both sides of the isolation structure; Wherein, the type of doping ions in the shallow heavily doped region is the same as the type of doping ions in the drift region; The atomic weight of the doping ions in the shallow heavily doped region is greater than the atomic weight of the doping ions in the drift region.

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