Fault detection in hybrid DC-DC power converters

Abstract

This document discloses a fault detection circuit and method for an N:1 Dickson topology hybrid DC-DC power converter. The fault detection circuit includes: a first measurement circuit and a second measurement circuit configured to measure a first voltage Vsw1 and a second voltage Vsw2 at a switching node in a first state and a second state, respectively; a first calculation circuit and a second calculation circuit configured to calculate the absolute difference between a corresponding first voltage (Vsw1[n-1]) and a corresponding second voltage (Vsw2[n-1]) in one operating cycle and a corresponding first voltage (Vsw1[n]) and a corresponding second voltage (Vsw2[n]) in the next subsequent operating cycle as a first absolute error voltage and a second absolute error voltage; and a first fault circuit and a second fault circuit configured to provide a first fault output and a second fault output indicating a fault in response to the corresponding first absolute error voltage or the second absolute error voltage exceeding a short-circuit trip level. An open-circuit fault detection circuit and method are also disclosed.

Description

Technical Field

[0001] This disclosure relates to fault detection in hybrid DC-DC power converters, and more particularly to circuits and methods thereof. Background Technology

[0002] An N:1 Dickson topology hybrid DC-DC power converter is a power converter having an input terminal for receiving an input voltage, a ground terminal, and a switching node connected to a switching inductor. The switching cycle of this type of power converter includes three operating states: a first state in which a first set of capacitors is charged and a second set of capacitors is discharged, such that in normal operation, the switching node is 1 / N times the input voltage; a second state in which the first set of capacitors is discharged and the second set of capacitors is charged, again such that in normal operation, the switching node is 1 / N times the input voltage; and a third state in which the switching node is shorted to ground. Summary of the Invention

[0003] According to a first aspect of this disclosure, a fault detection circuit for an N:1 Dickson topology hybrid DC-DC power converter is provided, the power converter having at least (N-1) level-setting capacitors, an input terminal for receiving an input voltage, a ground terminal, and a switching node connected to an inductor, and operating according to an operating cycle including a first state, a second state, and a third state; the fault detection circuit includes: a first measurement circuit configured to measure a first voltage V at the switching node in the first state, in which a first group of the level-setting capacitors and a second group of the level-setting capacitors are respectively charged and discharged. SW1 The system comprises: a first calculation circuit configured to calculate a first error voltage, which is the absolute difference between the first voltage (Vsw1[n-1]) in one operating cycle and the first voltage (Vsw1[n]) in the next subsequent operating cycle; a first fault circuit configured to provide a first fault output indicating a fault in response to the first absolute error voltage exceeding the short-circuit trip level; a second measurement circuit configured to measure a second voltage Vsw2 at the switching node in a second state in which the first set of level setting capacitors and the second set of level setting capacitors are respectively discharged and charged; a second calculation circuit configured to calculate a second absolute error voltage, which is the absolute difference between the second voltage (Vsw2[n-1]) in one operating cycle and the second voltage (Vsw2[n]) in the next subsequent operating cycle; and a second fault circuit configured to provide a second fault output indicating a fault in response to the second absolute error voltage exceeding the short-circuit trip level.

[0004] Therefore, short-circuit faults occurring in the converter can be detected by measuring the voltage at a single point in the circuit (i.e., the switching node) at different times during a complete switching cycle. It should be understood that the voltages mentioned are relative to ground voltage.

[0005] The fault detection circuit may further include: a third measurement circuit configured to measure the input voltage; a third calculation circuit configured to calculate a third absolute error voltage as the absolute value of the sum of the first and second voltages in one operating cycle minus 2 / N times the input voltage; and a third fault detection circuit configured to provide a third fault output indicating a fault in response to the second absolute error voltage exceeding the open-circuit trip level. Therefore, the circuit can be easily and readily extended to measure voltages at only two points in the circuit at different times during the switching cycle to measure both open-circuit and short-circuit faults.

[0006] In one or more embodiments, the first computing circuit, the second computing circuit, and the third computing circuit, as well as the first fault circuit, the second fault circuit, and the third fault circuit, are digital circuits.

[0007] In one or more embodiments, the circuit may additionally include circuitry that provides a summary fault output in response to at least one of the first fault output, the second fault output, and the third fault output indicating a fault. Therefore, in addition to indicators specifically identifying short-circuit or open-circuit faults, a general fault indicator can be provided.

[0008] In one or more embodiments, each of the first, second, and third measurement circuits includes an analog-to-digital converter. In such embodiments, most manipulations and calculations can be performed in the digital domain.

[0009] In one or more embodiments, each of the first, second, and third measurement circuits includes the same analog-to-digital converter (ADC). This can significantly reduce the total number of components in the circuit compared to embodiments that use two or even three ADCs.

[0010] In one or more embodiments, each of the first fault circuit, the second fault circuit, and the third fault circuit includes a comparator. In one or more such embodiments, each of the first fault circuit and the second fault circuit includes the same comparator. When components are implemented as analog components, using the same comparator for more than one function can reduce the total number of components; in alternatives where functions are performed in the digital domain, this can result in reduced processing requirements.

[0011] In one or more embodiments, the first computing circuit, the second computing circuit, and the third computing circuit, as well as the first fault circuit, the second fault circuit, and the third fault circuit, are analog circuits.

[0012] According to a second aspect of the invention, a method for detecting faults in an N:1 Dickson topology hybrid DC-DC power converter is provided, the power converter having an operating cycle and having at least (N-1) level-setting capacitors, an input terminal for receiving an input voltage, a ground terminal, and a switching node connected to an inductor; the method includes: measuring the voltage at the switching node in a first state and a second state in which a first set of level-setting capacitors and a second set of level-setting capacitors are charged and discharged, and in a discharge and charge state, respectively; calculating a first absolute error voltage as the absolute difference between the voltage at the switching node in the first state in one operating cycle and in the next subsequent operating cycle; calculating a second absolute error voltage as the absolute difference between the voltage at the switching node in the second state in one operating cycle and in the next subsequent operating cycle; comparing the sum of the voltages at the switching node in the first state and the second state with half of the input voltage to determine a third absolute error voltage; and detecting a fault in response to the third absolute error voltage exceeding a first trip voltage level or the first absolute error voltage or the second absolute error voltage exceeding a second trip voltage level.

[0013] In one or more embodiments of such a method, in the first state, a first set of capacitors is charged and a second set of capacitors is discharged, such that in normal operation, the switching node is 1 / N times the voltage at the input terminal; wherein, in the second state, the first set of capacitors is discharged and the second set of capacitors is charged, such that in normal operation, the switching node is 1 / N times the voltage at the input terminal, and in the third state, the switching node is shorted to the ground terminal; and one of the normal operating cycles includes operating sequentially in the first state, the third state, the second state, and the third state.

[0014] In one or more embodiments, calculating a first absolute error voltage as the absolute difference between the voltage at the switching node in the first state during one operating cycle and during the next subsequent operating cycle includes:

[0015] The first absolute error (Vsc1, err) and the second absolute error (V) are determined by subtracting the corresponding switching node voltages (Vsw1[n-1], Vsw2[n-1]) in the first and second states during the (n-1)th cycle. SW2，ERR ):

[0016] V SW1，ERR =|V SW1 [n]-V SW1 [n-1]|, and

[0017] V SW2，ERR =|V SW2 [n]-V SW2 [n-1]|.

[0018] In one or more embodiments, comparing the sum of the voltages at the switching node in the first state and the second state with half of the input voltage to determine the third absolute error voltage includes:

[0019] The summation value (Vsum[n]) is determined by summing the switching node voltages in the first and second states during the (n)th cycle:

[0020] (Vsum[n]=Vsw1[n]+Vsw2[n]), and

[0021] The third absolute error (Vsum, err) is determined by subtracting half of the input voltage as follows:

[0022] Vsum, err = |Vsum[n] - V IN / 2|.

[0023] This document may provide a computer program that, when run on a computer, causes the computer to configure any device, including the circuits, controllers, sensors, filters, or devices disclosed herein, or to perform any of the methods disclosed herein. As a non-limiting example, the computer program may be a software implementation, and the computer may be considered any suitable hardware, including digital signal processors, microcontrollers, and implementations of read-only memory (ROM), erasable programmable read-only memory (EPROM), or electrically erasable programmable read-only memory (EEPROM). The software implementation may be an assembler.

[0024] The computer program may be located on a computer-readable medium, which may be a physical computer-readable medium such as a disk or memory device, or may be embodied in another non-transient signal.

[0025] These and other aspects of the invention will become apparent from the embodiments described below, and these aspects will be explained with reference to the embodiments described. Attached Figure Description

[0026] Embodiments will be described by way of example only with reference to the accompanying drawings, in which:

[0027] Figure 1 A 4:1 Dickson topology hybrid DC-DC power converter is shown;

[0028] Figure 2a It shows Figure 1 The first state (I) of the operation of the power converter;

[0029] Figure 2b It shows Figure 1 The second state (II) of the operation of the power converter;

[0030] Figure 2c It shows Figure 1 The third state (0) of the operation of the power converter;

[0031] Figure 2d It shows Figure 1 The truth table of the state of each of the eight switches in the three operating states of the power converter during the switching cycle;

[0032] Figure 3 This shows what happens during normal operation. Figure 1 The output current of the power converter, the switching node voltage, and the voltage across each of the three capacitors;

[0033] Figure 4 It shows Figure 1 The values ​​of various signals from the power converter that cause short-circuit faults;

[0034] Figure 5 It shows Figure 1 The values ​​of various signals from the power converter that cause short-circuit faults;

[0035] Figure 6 A circuit according to an embodiment of the present disclosure is conceptually illustrated;

[0036] Figure 7 A 6:1 Dickson topology hybrid DC-DC power converter is shown; and

[0037] Figure 8 A 7:1 Dickson topology hybrid DC-DC power converter is shown.

[0038] It should be noted that the accompanying drawings are illustrative and not drawn to scale. In the drawings, for clarity and convenience, the relative dimensions and proportions of portions have been shown in exaggerated or reduced sizes. In modified and different embodiments, the same reference numerals may generally be used to refer to corresponding or similar features. Detailed Implementation

[0039] Figure 1 A 4:1 Dickson topology hybrid DC-DC power converter is shown. This topology of the power converter is an example of a so-called hybrid topology that combines a switched capacitor stage with a conventional inductive DC-DC converter. Hybrid topologies of DC-DC converters offer several advantages in implementing fault-tolerant DC-DC converters. First, using more power switches than in a conventional inductive DC-DC converter reduces the maximum rated voltage requirement of these power switches and improves converter efficiency by reducing switching losses, for example, by reducing voltage swing at the switching nodes compared to a conventional inductive DC-DC converter. Second, because these multiple power switches are used in series, affected parts of the converter can be isolated by opening undamaged switches at the power stage. On the other hand, the increased number of required components increases the complexity of the hardware / software subsystems needed to detect faults.

[0040] Figure 1 The 4:1 Dickson topology hybrid DC-DC power converter shown is a specific example of the N:1 Dickson topology hybrid DC-DC power converter category and is used to illustrate the principles of this disclosure. However, as will be discussed in more detail below, this disclosure is not limited to a 4:1 ratio, but is generally extended to N:1, where N is greater than or equal to 4. Examples with other buck ratios will be shown below.

[0041] Figure 1 The 4:1 Dickson topology shown can be used with high V, provided fault tolerance is allowed. IN / V OUT A step-down conversion is performed using a ratio. It has been shown that, for selected designs requiring a 48V supply to provide a 3V output voltage, this topology achieves higher efficiency compared to other topologies with the same silicon area (conventional inductor step-down, 3-stage hybrid topology), and is therefore advantageous for high voltage ratio conversion. Those skilled in the art will understand that for different step-down voltage ratios V... IN ∶V OUTFor other design scenarios, different topologies can be preferred (such as 3:1 or 5:1).

[0042] Figure 1 The converter 100 shown includes a switching inductor L 110, which provides an output voltage V on its output side and across the output capacitor Cout 130. OUT 120. The input side of inductor 110 is connected to switching node 140. Switching node 140 has a switching voltage V across it. SW Due to the configuration and operation of a set of switches S1 to S8 and three capacitors C1, C2, and C3, the switching voltage V SW The voltage V at input 150 is arranged IN One-quarter. Those skilled in the art will understand that each of the capacitor elements C1, C2 and C3 can be composed of a single capacitor or a series combination and / or parallel combination of two or more capacitors.

[0043] Six switches, S1, S4, S5, ..., S8, are arranged in series such that if all switches are closed, the input voltage will be short-circuited. Starting from the beginning, the first capacitor C1 is connected in parallel with the second switch (S4) and the third switch (S5) in the series-connected switches. That is, the first capacitor C1 is connected between node 160, which connects the first switch S1 and the second switch S4 in the series-connected switches, and node 162, which is located between the third switch S5 and the fourth switch S6. As will be discussed in more detail below, this capacitor charges to the input voltage V. IN One-quarter of it.

[0044] The remaining two switches, S2 and S3, are connected in series with each other and in parallel with the first two switches (S1 and S4) in the series connection, which are counted again from the beginning. The second capacitor C2 is connected between node 164, located between the remaining two switches S2 and S3, and node 166, located between the fourth switch S6 and the fifth switch S7 in the series connection. This capacitor is charged to the input voltage V. IN Half of it.

[0045] Finally, the third capacitor is connected between node 160, located between the first and second switches in the series-connected switch, and node 168, located between the fifth and sixth switches in the series-connected switch. This capacitor is charged to the input voltage V. IN Three-quarters of it.

[0046] To understand the charging of a capacitor, and the switching voltage V SWThe voltage obtained at that point will now be used to describe the converter's operating cycle. Specifically, the operating cycle has a first state, a second state, and a third state. These are respectively in... Figure 2a , Figure 2b and Figure 2c Described in the text.

[0047] In the first state (also known as "State I"), switches S2, S4, S6, and S8 are closed, while switches S1, S3, S5, and S7 are open, as follows: Figure 2a As shown. The voltage across the input is therefore across C1, which is anti-connected to C3 and anti-connected to C2. Due to the way these switches are connected and the inductor current I... L The direction of the charge is such that capacitors C3 and C1 are charged while capacitor C2 is discharged. In a steady state, the voltage V at node 140 is switched. SW equals V IN / 4.

[0048] In the second state (also known as "State II"), switches S1, S3, S5, and S7 are closed, while switches S2, S4, S6, and S8 are open, as follows: Figure 2b As shown. Therefore, the input V is disconnected. IN Furthermore, capacitor C3 is connected in parallel with C1 and C2 in an anti-series combination. Therefore, due to the inductor current I... L The direction of discharge is such that capacitors C3 and C1 are discharged while capacitor C2 is charged. V SW The voltage at point V is equal to IN / 4.

[0049] In the third state (also known as "state 0"), switches S1, S2, S3, and S4 are closed, while switches S5, S6, S7, and S8 are open. Therefore, the switching node is short-circuited to ground. Therefore, V SW =0V.

[0050] Figure 2d The document lists the open / closed state (open-O or closed-C) of each of the eight switches in each of the three operating states (state II, state 3, and state 0) for the switching cycle.

[0051] During a complete switching cycle (cycle), the operation transitions through state I → state 0 → state II → state 0. That is, the switching cycle consists of operations performed in the order of state I, state II, and state III. This is in... Figure 3 As shown in the image. Figure 3 The inductor current I during each of the three states is shown at 310. L As shown at 320, in both the first and second states, the voltage V at node 140 is switched. SW For VIN / 4, and in the third state (“state 0”), the voltage is zero or grounded. The inductor current 310 rises during the first and second states and falls during the third state.

[0052] This produces a period of 1 / (2f) SW )325 of V SW The square waveform, wherein the period 325 is a voltage level equal to V IN The cycle frequency is twice that of / 4 and 0. Because the voltage swing at the switching node is reduced compared to conventional inductive power converters, the duty cycle is not extremely low, making this topology particularly suitable for frequency conversion at high voltage ratios.

[0053] Because, relative to the second state, the voltage V at the switching node changes in the first state. SW Due to the different capacitor and switch arrangements, for completeness, the voltage V of the first state is shown at 330 and 340 respectively. SW1 Voltage V in the second state SW2 .

[0054] at last, Figure 3 The voltage across capacitors C1, C2, and C3 in a steady state is shown at points 350, 352, and 354, respectively, and as already mentioned, these voltages are respectively equal to V. IN / 4、V IN / 2 and V IN / 4.

[0055] Figure 4 A method for detecting short-circuit faults (SCF) in a 4:1 Dickson topology hybrid DC-DC converter according to one or more embodiments is shown. Figure 4 It shows the relationship with Figure 3 The same information is present in the data—namely, the inductor current IL at 410 and the voltage V at the switching node at 420. SW The voltage (V) separated at 430 for the first state SW1 ) and the voltage (V) separated at 440 for the second state SW2 The figure also shows the voltage across each of the three capacitors C1, C2, and C3 at points 450, 452, and 454. The figure also shows two calculated error voltages (V). SW1，ERR and V SW2，ERR The value of ) will be discussed in more detail below.

[0056] The left side of the diagram shows normal operation. Figure 4The dashed line indicates time 405, during the simulation of the SCF in one of the switches (switching S8 in this example). In this example, the converter operates in the second state (state II) of the operating cycle. Typically, in this state, switching S8 is open so that a short-circuit fault in switching S8 causes a drastically different capacitor topology. Therefore, the voltage balance is affected, and the voltage V at the switching node... SW It rose rapidly.

[0057] To detect such SCFs according to one or more embodiments, the following method is used:

[0058] First, during each switching cycle in the first and second states, the switching node voltage V is adjusted. SW Sampling is performed—namely, state I (Vsw1[n]) and state II (Vsw2[n]). In Figure 4 In this process, these sampling points are obtained by switching nodes when they are in V. IN The dot at the end of each time period in 4 / 4 time is shown.

[0059] Second, compare these two values ​​with their corresponding values ​​(V) in the previous sampling period. SW1 [n-1] and V SW2 The comparison is performed using [n-1]). In normal operation, such as at positions 431 and 432, the comparison is performed using the first state V. SW1 The corresponding relationship of the measured voltages is shown below; these voltages are almost constant. However, in the event of a fault, these voltages will change, as shown at 441, comparing the voltage during the second state of normal operation with the voltage after an SCF occurs at 442.

[0060] The absolute value of the difference between two consecutive samples from the same state is calculated as V. SW1，ERR or V SW2，ERR :

[0061] Right now,

[0062] V SW1，ERR =|V SW1 [n]-V SW1 [n-1]|, and

[0063] V SW2，ERR =|V SW2 [n]-V SW2 [n-1]|.

[0064] During normal operation, this error value is very low, equal to or close to 0.

[0065] Third, if the difference is greater than a specific absolute error value V TRIP，SCF If a fault occurs, a signal is used to notify the user of the fault, because when a fault occurs, this error value becomes non-zero. Figure 4 The corresponding error signals for state I and state II are shown at 460 and 470, and the positive values ​​of the annual error threshold +V are shown at 481 and 482, respectively. TRIP，SCF and negative value V TRIP，SCF .exist Figure 4 In the specific example shown, the SCF occurs during state II of the operating cycle and before sampling in state II. Therefore, the state II error signal exceeds the trip level or threshold level (shown at 471), and then the state I error signal exceeds the trip level or threshold level (shown at 461). The error threshold V can be dynamically selected based on the anticipated voltage transients at the switching node. TRIP，SCF The magnitude of this will then typically depend on the power converter's own design parameters to ensure rapid fault detection while still providing robustness to anticipated transient changes during normal operating modes.

[0066] It should be understood that, as an alternative to determining the absolute value of the difference between two consecutive samples of the same state, a simple difference can be determined and compared with a threshold level or a trigger level.

[0067] exist Figure 4 In the example shown, the node voltage V is switched. SW The sampling occurs precisely before the end of state I and state II to avoid or reduce any switching noise that might otherwise interfere with the voltage value.

[0068] As in Figure 4 As can be seen, the method according to this disclosure allows for robust detection of SCFs within a single switching cycle of the power converter. Such rapid detection can significantly increase the chances of containing a fault and avoiding or preventing its propagation before other components of the system are affected by the fault.

[0069] Figure 5 Various signals are illustrated to show how the above methods can be adjusted, or modified or improved in alternatives, to effectively detect open-circuit faults (OCF). Typically, an open-circuit fault manifests as a slow change or deviation in voltage level at the switching node. Therefore, for proper detection of open-circuit faults, the above section on… Figure 4 The modifications to the described method may be appropriate.

[0070] Again, considering the voltage levels of the switching nodes during normal operation, specifically during states I and II (V respectively) IN / 4 and V IN The sum of ( / 4) equals the voltage across capacitor C2 (V). IN / 2). Furthermore, the voltage across capacitor C2 is always equal to or very close to V. IN / 2, even during transients, such as when the converter adapts to load changes, provided the transient is not faster than the converter's switching frequency. In normal operation, transients are not expected to be faster than the converter's switching frequency. In addition to or as an alternative to the aforementioned detection of SCF events, this feature can also be used to manipulate values ​​measured at the switching node to detect OCF events:

[0071] Essentially, the OCF in any power switch or the OCF in a floating (i.e., level-set) capacitor can be detected in the following ways:

[0072] First, as described above, in state I(V) SW1 [n]) and state II (V SW2 During each switching cycle of [n], the switching node voltage V is adjusted. SW Perform sampling.

[0073] Second, add these two values ​​to V in each sampling period. SUM [n] value = (V SUM [n] = V SW1 1[n]+V SW2 In 2[n]).

[0074] Third, calculate Vsum[n] and the input voltage (V IN The absolute value of the difference between half of ), that is:

[0075] V SUM，ERR =|V SUM [n]-V IN / 2|.

[0076] Finally, if this difference is greater than a specific error value V TRIP，OCF Then a signal can be used to notify of the fault.

[0077] As discussed above regarding the threshold for short-circuit faults, the threshold V can be optimally selected based on the design parameters of the power converter. TRIP，OCF The magnitude of the value. This allows for sufficiently rapid fault detection while still providing adequate robustness to transient changes in operating modes that might be expected due to normal operation, such as variations in load, as described above. It should be noted that the severity of open-circuit faults is generally less than that of short-circuit faults; therefore, a slower response is generally acceptable for normal applications.

[0078] Furthermore, it should be understood that, as an alternative to determining the absolute value of the difference between Vsum[n] and half of the input voltage, a simple difference can be determined and compared with the threshold level or trigger level.

[0079] Go to Figure 5 The details, the diagram shows with Figure 4 The same signal, except in this case, shows the error signal V at 560. SUM，ERR Furthermore, the positive threshold +V of the error signal is shown at points 581 and 582, respectively. TRIP，OCF and negative threshold -V TRIP，OCF .exist Figure 5 The dashed line indicates time 505, during which the OCF is simulated in one of the switches (switcheroo S8 in this example). It can be seen that, as... Figure 5 As shown, in V SUM，ERR The absolute value exceeds the threshold level +V TRIP，OCF Previously, it might have required more than one complete switchover cycle. Figure 5 In the example, fault detection occurs within two switching cycles, which is usually fast enough to protect the entire system.

[0080] Figure 6 A conceptual circuit arrangement 600 for performing the method just described for detecting one or both of SCF and OCF is shown. The circuit includes three analog-to-digital converters (ADCs) 601, 611, and 621. ADC 601 performs a switching operation once per switching cycle across V... IN The voltage is sampled (in this example, this is done when SW8 is closed, because this occurs once per switching cycle, but in other embodiments, V...). IN Sampling can be performed at other times and triggered by other different timing events. This value of Vin is halved at 602 to determine the value V. IN / 2 (which is required for open-circuit fault detection as discussed below).

[0081] The ADC 611 is triggered to re-evaluate the voltage V at the switching node once per switching cycle. SW Sampling is performed—in this case, this is determined by SW8 closing so that the converter is in state II, but in other embodiments, different switches (e.g., SW2, SW4, or SW6) can be used as trigger events.

[0082] Similarly, the ADC 621 is triggered to re-evaluate the voltage V at the switching node once per switching cycle. SW Sampling is performed—in this case, this is determined by the closure of SW7, so the converter is in state I; however, in other embodiments, different switches (e.g., SW1, SW3, or SW5) can be used as trigger events.

[0083] For the nth switching cycle, these values ​​(i.e., V) SW1 [n] and V SW2 Each value in [n] is used to determine both SCF and OCF.

[0084] To determine the SCF, the value Vsw1[n] is stored in memory element 612, which may be, for example, a flip-flop, and the value V is deferred from the previous value V at logic 613. SW1 Subtract from [n-1]. As shown at 614, determine the absolute value of the signal to determine the error signal V. SW1，ERR The error signal V SW1，ERR The threshold level V in comparator 615, which can be implemented as a Schmitt trigger as shown in the figure, is related to... TRIP，SCF A comparison is made to generate the first short-circuit fault detection signal FD. SCF，OUT Accordingly, the value V SW2 [n] is stored in memory element 622 and at logic 623 from the previous value V. SW2 Subtract from [n-1]. As shown at 624, determine the absolute value of the signal to determine the error signal V. SW1，ERR The error signal V SW1，ERR The threshold level or short-circuit trip level V at comparator 625, which can be implemented as a Schmitt trigger as shown in the figure, is related to the threshold level or short-circuit trip level. TRIP，SCF A comparison is made to generate a second short-circuit fault detection signal FD. SCF，OUT .

[0085] To determine the OCF, as shown in 631, the value V is... SW1 [n] and V SW2 Summing [n] and subtracting the value V as shown at position 632. IN / 2. Determine the absolute value at 633 to provide the signal V. SUM，ERR The signal V SUM，ERR The threshold level or open-circuit trip level V at comparator 635, which can be implemented as a Schmitt trigger as shown in the figure, is related to the threshold level or open-circuit trip level. TRIP，OCF Comparisons are made to generate an open-circuit fault detection signal FD. oCF，OUT .

[0086] Finally, the two short-circuit fault detection signals FD SCF，OUT and open circuit fault detection signal FD OCF，OUT Combined in logic 640 to provide a general fault detection signal FD.

[0087] It should be understood that the conceptual circuit described above can be implemented in many different ways. Specifically, although individual ADCs 601, 611, and 621 have been shown, the same ADC can be used to switch voltage V at different times. SW Sampling is performed to meet the requirements of 611 and 621, and the same ADC can also be used to measure the voltage V at individual moments during the switching cycle. INTherefore, three ADCs may not be necessary; instead, one or two can be used.

[0088] Similarly, three comparators 615, 625 and 635 are shown, but those skilled in the art will understand that two or more of these functions can be performed using the same circuit elements or digital processing blocks.

[0089] In addition, Figure 6 In this context, the analog-to-digital converter is used to switch the voltage V. SW and input voltage V IN The analog values ​​are converted to the digital domain. In one or more other embodiments, these values ​​can be sampled using analog techniques, and subsequent summation, subtraction, or comparison functions can be implemented using analog circuitry familiar to those skilled in the art. Furthermore, those skilled in the art will understand that the circuitry can be implemented in a hybrid signal solution combining analog and digital circuitry elements.

[0090] The above description focuses on 4:1 Dickson topology hybrid DC-DC power converters. However, as already mentioned, this disclosure extends to Dickson topology converters with other buck ratios (typically N:1).

[0091] Figure 7 This illustrates a 6:1 Dickson topology hybrid DC-DC power converter. Figure 1 The 4:1 converter shown is identical; converter 700 includes a switching inductor L 110 that provides an output voltage V on its output side. OUT 120, to supply power to the load, is shown here at 705 (in this case, the output capacitor Cout is not shown). The input side of inductor 110 is connected to switching node 140.

[0092] In the 6:1 topology shown, N equals 6; there are a total of 10 switches, SW1, SW2, ..., SW1. 10 That is, 4+N. In addition, there are 5 floating or level-setting capacitors C1, C2, ..., C5. That is, there are (n-1) capacitors. The capacitors form a modified trapezoid, in which one end of each capacitor in the successive series is connected to nodes 762, 764, ..., 770 at individual "runs" of the trapezoid—(the reader may find these related to...) Figure 1The comparison of nodes 162, 166, and 168 of the 4:1 converter shown is illustrative. Connect the other end of each of the “odd” capacitors C1, C3, and C5 to another node 760, and connect the other end of each of the “even” capacitors C2 and C4 to yet another node 740.

[0093] Each of the other nodes and yet another node can switch node V. SW Switching between 140 and ground. In the first state (state I) of the operating cycle, odd-numbered capacitors are charged (by switching node 760 to ground), while even-numbered capacitors are discharged (by switching node 764 to switching node V). SW 140). Conversely, in the first state (state II) of the operation cycle, (by switching node 760 to switching node V) SW 140) Discharge the odd-numbered capacitors and charge the even-numbered capacitors (switch node 764 to ground). In the third state (state), (by closing the switch on at least one pair of SW4 and SW1 and SW3 and SW2) the switching node is grounded. Therefore, in this case, the odd-numbered capacitors C1, C3, and C5 form a first group of capacitors that are charged during the first state (state I) and discharged during the second state (state II). The even-numbered capacitors C2 and C4 form a second group of capacitors that are discharged during the first state (state I) and charged during the second state (state II).

[0094] In the diagram, each of the switches that is closed in states I and II is indicated by adding a second subscript: that is, via SW 6(1) SW 8(1) and SW 10(1) This indicates even-numbered switches SW6, SW8, and SW 10 It is closed in state I and passes through SW. 5(2) SW 7(2) and SW 9(2) This indicates that odd-numbered switches SW5, SW7, and SW9 are closed in state II. Similarly, the open / closed states of the four switches (SW) of control nodes 760 and 764 are shown. 1(2) SW 2(1) SW 3(2) and SW 4(1) ).

[0095] As described above for the 4:1 scenario, a short-circuit fault is detected; this is achieved by adjusting the voltage V at the switching node during the first and second states. SW The sum of and 2V IN / 6 (i.e., V) IN / 3) is compared to detect open-circuit faults. In other words, the average voltage at switching node 140 during these two states is compared to the expected step-down ratio V. IN / 6 is compared.

[0096] Figure 8 A 7:1 Dickson topology hybrid DC-DC power converter 800 is shown. In this configuration, there are 11 (4+7) switches and 6 (7-1) floating or level-setting capacitors. Again, odd-numbered capacitors C1, C3, and C5 form the first group of capacitors that charge during the first state (state I) and discharge during the second state (state II). Even-numbered capacitors C2, C4, and C6 form the second group of capacitors that discharge during the first state (state I) and charge during the second state (state II).

[0097] Once again, as described above for the 4:1 case, a short-circuit fault is detected; this is achieved by checking the voltage V at the switching node during the first and second states. SW The sum of and 2V IN / 7 is compared to detect open-circuit faults. In other words, the average voltage at switching node 140 during these two states is compared to the expected buck ratio V. IN / 7 is compared.

[0098] Those skilled in the art will immediately understand that, in general, the division by two logic 602 (i.e., the division by 4 / 2 used for a 4:1 buck ratio) is modified by replacing the division by two logic 602 with the division by N / 2 logic. Figure 6 The schematic circuit is shown. Then use this value (2V) in the differential stage 632. IN / N).

[0099] Other variations and modifications will be apparent to those skilled in the art upon reading this disclosure. Such variations and modifications may involve equivalents and other features known in the field of hybrid power converters that may replace or replace the features described herein.

[0100] Although the appended claims address specific combinations of features, it should be understood that the scope of the invention also includes any novel feature or combination of novel features or any general form thereof explicitly or implicitly disclosed herein, whether or not it relates to the same invention as currently claimed in any of the claims, and whether or not it alleviates any or all of the same technical problems as the present invention.

[0101] Features described in the context of a single embodiment may also be provided in combination in a single embodiment. Conversely, for simplicity, individual features described in the context of a single embodiment may also be provided individually or in any suitable sub-combination. The applicant hereby declares that new claims may be made for such features and / or combinations of such features during the proceedings of this application or any other application derived therefrom.

[0102] For completeness, it should also be noted that the term "comprising" does not exclude other elements or steps, the term "a or an" does not exclude multiple, a single processor or other unit may perform the functions of several devices described in the claims, and the reference numerals in the claims should not be construed as limiting the scope of the claims.

[0103] Reference tag list:

[0104] 100 4:1 Dickson topology hybrid DC-DC power converter;

[0105] 110 Switching inductor L;

[0106] 120 Output voltage V OUT ;

[0107] 130 Output capacitor C OUT ;

[0108] 140 Switch node;

[0109] 150 Input voltage V IN ;

[0110] 160 The node between the first series-connected switch (S1) and the second series-connected switch (S4);

[0111] 162 The node between the third series-connected switch (S5) and the fourth series-connected switch (S6);

[0112] 164. The node between the remaining switches (S2 and S3);

[0113] 166 The node between the fourth series-connected switch (S6) and the fifth series-connected switch (S7);

[0114] 168 The node between the fifth series-connected switch (S7) and the sixth series-connected switch (S8);

[0115] 310 Inductor current IL;

[0116] 320 Switching node voltage V SW ;

[0117] 330 Switching node voltage V under state I SW1 ;

[0118] 340 Switching node voltage V under state II SW2 ;

[0119] 350V across C1;

[0120] 352 Voltage across C2;

[0121] 354. Voltage across C3;

[0122] 405 Simulates the moment of failure;

[0123] 410 Inductor current IL;

[0124] 420 Switching node voltage V SW ;

[0125] 430 Switching node voltage V under state I SW1 ;

[0126] 440 Switching node voltage V under state II SW2 ;

[0127] 450V across C1;

[0128] 452 Voltage across C2;

[0129] 454 Voltage across C3;

[0130] 460 Error Signal V SW1，SCF ;

[0131] 461 Error signal V SW1，SCF Moments of change;

[0132] 470 Error signal V SW2，SCF ;

[0133] 471 Error signal V SW2，SCF Moments of change;

[0134] 481 Short-circuit trip positive level V TRIP，OCF ;

[0135] 482 Short-circuit trip negative level V TRIP，SCF ;

[0136] 560 Error signal V SW1，OCF ;

[0137] 581 Open circuit trip positive level V TRIP，OCF ;

[0138] 582 Open circuit trip negative level VTRIP，OCF ;

[0139] 600 Conceptual Fault Detection Circuit;

[0140] 601 ADC;

[0141] 602 divided by 2 (logic);

[0142] 611 ADC;

[0143] 612 Memory element;

[0144] 613 Differential Logic;

[0145] 614 Absolute value logic;

[0146] 615 comparator;

[0147] 621 ADC;

[0148] 622 Memory element;

[0149] 623 Differential Logic;

[0150] 624 Absolute value logic;

[0151] 625 comparator;

[0152] 631 Summation Logic;

[0153] 632 Differential Logic;

[0154] 633 Absolute value logic;

[0155] 635 comparator;

[0156] 640 OR logic;

[0157] 700 6-1 Dickson topology hybrid DC-DC power converter;

[0158] 705 Load;

[0159] 760 and 764 are charging / discharging nodes;

[0160] Trapezoidal nodes 762, 766, ..., 770;

[0161] 800 7-1 Dickson topology hybrid DC-DC power converter.

Claims

1. A fault detection circuit for an N:1 Dickson topology hybrid DC-DC power converter, characterized in that, The power converter has at least (N-1) level setting capacitors, a ground terminal, an input terminal for receiving input voltage, and a switching node connected to an inductor, and operates according to an operating cycle including a first state, a second state, and a third state; The fault detection circuit includes: A first measurement circuit is configured to measure a first voltage V at the switching node during a first state in which the first set of level-setting capacitors and the second set of level-setting capacitors are charged and discharged. SW1 ; A first calculation circuit is configured to calculate the first voltage (V) in one operating cycle. SW1 [n-1]) and the first voltage (V) in the next subsequent operating cycle SW1 The first error voltage is the difference between [n]); A first fault circuit is configured to provide a first fault output indicating a fault in response to the absolute value of the first error voltage exceeding a short-circuit trip level. A second measurement circuit is configured to measure the second voltage V at the switching node in a second state where the first group of level-setting capacitors and the second group of level-setting capacitors are respectively discharged and charged. SW2 ; A second calculation circuit is configured to calculate the second voltage (V) in one operating cycle. SW2 [n-1]) and the second voltage (V) in the next subsequent operating cycle SW2 The second error voltage is the difference between [n]); and A second fault circuit is configured to provide a second fault output indicating a fault in response to the absolute value of the second error voltage exceeding the short-circuit trip level.

2. The fault detection circuit according to claim 1, characterized in that, In addition, including: A third measurement circuit is configured to measure the input voltage; A third calculation circuit is configured to calculate a third error voltage as the sum of the first voltage and the second voltage in one operating cycle minus 2 / N times the input voltage. as well as A third fault circuit is configured to provide a third fault output indicating a fault in response to the absolute value of the second error voltage exceeding the open-circuit trip level.

3. The fault detection circuit according to claim 1, characterized in that, The first computing circuit, the second computing circuit, the first fault circuit, and the second fault circuit are digital circuits.

4. The fault detection circuit according to claim 2, characterized in that, The first computing circuit, the second computing circuit, and the third computing circuit, as well as the first fault circuit, the second fault circuit, and the third fault circuit, are digital circuits.

5. The fault detection circuit according to claim 2, characterized in that, Additionally, circuitry is included that provides a summary fault output in response to at least one of the first fault output, the second fault output, and the third fault output indicating a fault.

6. The fault detection circuit according to any one of the preceding claims, characterized in that, Each measurement circuit in the measurement circuitry includes an analog-to-digital converter.

7. The fault detection circuit according to claim 6, characterized in that, The first measurement circuit and the second measurement circuit include the same analog-to-digital converter.

8. The fault detection circuit according to claim 2, characterized in that, The first measurement circuit, the second measurement circuit, and the third measurement circuit all include the same analog-to-digital converter.

9. The fault detection circuit according to any one of claims 1-5, characterized in that, Each of the fault circuits includes a comparator.

10. The fault detection circuit according to claim 9, characterized in that, Each of the first fault circuit and the second fault circuit includes the same comparator.

11. The fault detection circuit according to claim 2, characterized in that, Each of the first fault circuit, the second fault circuit, and the third fault circuit includes the same comparator.

12. The fault detection circuit according to claim 1, characterized in that, The first computing circuit and the second computing circuit, as well as the first fault circuit and the second fault circuit, are analog circuits.

13. The fault detection circuit according to claim 2, characterized in that, The first computing circuit, the second computing circuit, and the third computing circuit, as well as the first fault circuit, the second fault circuit, and the third fault circuit, are analog circuits.

14. A method for detecting faults in an N:1 Dickson topology hybrid DC-DC power converter, characterized in that, The power converter has an operating cycle and at least (N-1) level-setting capacitors, an input terminal for receiving input voltage, a ground terminal, and a switching node connected to an inductor; the method includes: The voltage at the switching node is measured in a first state where the first group of level setting capacitors and the second group of level setting capacitors are charged and discharged, and in a second state where they are discharged and charged, respectively. Calculate a first error voltage as the difference between the voltage at the switching node in the first state in one operating cycle and in the next subsequent operating cycle; Calculate a second error voltage as the difference between the voltage at the switching node in the second state during one operating cycle and during the next subsequent operating cycle; The sum of the voltages at the switching node in the first state and the second state is compared with 2 / N times the input voltage to determine the third error voltage; A fault is detected in response to the absolute value of the third error voltage exceeding the first trip voltage level, or the absolute value of the first error voltage or the second error voltage exceeding the second trip voltage level.

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