Method of manufacturing an integrated circuit device

Abstract

A method of manufacturing an integrated circuit device is provided. The method of manufacturing an integrated circuit device includes forming a device layer, a wiring insulating layer, and a hard mask layer in sequence on a semiconductor substrate. The method includes sequentially removing a first region and a second region of the hard mask layer using a first mask layer having a first opening and a second mask layer having a second opening as etching masks, respectively. The method includes forming a first wiring groove and a second wiring groove by removing a portion of the wiring insulating layer using a portion of the hard mask layer as an etching mask, the first wiring groove passing through the wiring insulating layer, the second wiring groove having a depth smaller than a depth of the first wiring groove. Further, the method includes forming a wiring structure in the first wiring groove and the second wiring groove.

Description

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS]

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0045134, filed April 17, 2019, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0003] The present disclosure relates to a method of manufacturing an integrated circuit device. BACKGROUND

[0004] Due to advances in electronic technology, scaling of integrated circuit devices is rapidly progressing. In scaled integrated circuit devices, a process margin of a process for interconnecting a wiring layer and a via plug can be reduced. SUMMARY

[0005] The present inventive concept provides a method of manufacturing an integrated circuit device that is capable of interconnecting a wiring layer and a via plug even when a process margin for forming the wiring layer and the via plug is reduced according to scaling of the integrated circuit device.

[0006] To overcome the above-described technical problems, the present inventive concept provides a method of manufacturing an integrated circuit device. According to some embodiments herein, a method of manufacturing an integrated circuit device can include sequentially forming a device layer, a wiring insulating layer, and a hard mask layer on a semiconductor substrate. The device layer can include a plurality of semiconductor devices. The method can include sequentially removing a first region and a second region of the hard mask layer using a first mask layer having a first opening extending in a first horizontal direction and a second mask layer having a second opening extending in the first horizontal direction as etching masks, respectively. A portion of the second opening can overlap a split region including a first portion of the wiring insulating layer in a vertical direction and can overlap a portion of the first opening in the vertical direction. The method can include forming a first wiring recess and a second wiring recess by removing the first portion of the wiring insulating layer using a third region of the hard mask layer remaining after the first region and the second region of the hard mask layer are removed as an etching mask, the first wiring recess passing through the wiring insulating layer, the second wiring recess having a depth smaller than a depth of the first wiring recess. Further, the method can include forming a wiring structure in the first wiring recess and the second wiring recess and electrically connected to the plurality of semiconductor devices.

[0007] According to some embodiments herein, a method of manufacturing an integrated circuit device can include forming, in sequence, a device layer, a wiring insulating layer, an etching stop film, and a hard mask layer on a semiconductor substrate including a portion located in a split region of the integrated circuit device. The device layer can include a plurality of semiconductor devices. The method can include forming a first recess in the hard mask layer by removing a first region of the hard mask layer using a first mask layer having a first opening as an etching mask, the first opening having a portion located in the split region and extending in a first horizontal direction. The method can include forming a second recess by removing a second region of the hard mask layer using a second mask layer having a second opening as an etching mask, the second opening having a portion located in the split region and extending in the first horizontal direction. The method can include removing a first portion of the etching stop film located in the split region. The method can include removing a third region of the hard mask layer and a second portion of the etching stop film via the first recess, removing a fourth region of the hard mask layer and a third portion of the etching stop film via the second recess, and removing a portion of an upper first portion of the wiring insulating layer located in the split region. Further, the method can include forming a first wiring recess through the wiring insulating layer in the split region by removing a second portion of the wiring insulating layer using a fifth region of the hard mask layer remaining after the third and fourth regions of the hard mask layer are removed as an etching mask, and forming a second wiring recess having a depth less than a depth of the first wiring recess.

[0008] According to some embodiments herein, a method of manufacturing an integrated circuit device can include sequentially forming a semiconductor substrate having a split region, a wiring insulating layer, an etching stop film, a first hard mask layer, and a second hard mask layer. The method can include forming a first recess by removing a first region of the second hard mask layer using a first mask layer having a first opening as an etching mask, the first opening extending in a first horizontal direction and having a portion located in the split region. The method can include forming a second recess by removing a second region of the second hard mask layer and a first portion of the first hard mask layer located in the split region using a second mask layer having a second opening as an etching mask, the second opening extending in the first horizontal direction and having a first portion and a second portion different from the first portion located in the split region. The method can include removing a first portion of the etching stop film located in the split region. The method can include removing a second portion of the first hard mask layer and a second portion of the etching stop film via the first recess, removing a third portion of the first hard mask layer and a third portion of the etching stop film via the second recess, and removing a portion of an upper first portion of the wiring insulating layer located in the split region. Further, the method can include forming a first wiring recess and a second wiring recess by removing a second portion of the wiring insulating layer using a fourth portion of the first hard mask layer as an etching mask, the first wiring recess passing through the wiring insulating layer, the second wiring recess having a depth less than a depth of the first wiring recess. The first wiring recess can be formed in the split region. BRIEF DESCRIPTION OF DRAWINGS

[0009] Embodiments of the present inventive concepts will be more fully understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figures 1A through 9C are plan views and cross-sectional views schematically illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to exemplary embodiments of the present inventive concepts, and particularly, Figure 1B Figure 2B Figure 3B Figure 4B Figure 5B Figure 6B Figure 7B Figure 8B , and Figure 9B Figure 1C Figure 2C Figure 3C Figure 4C Figure 5C Figure 6C Figure 7C Figure 8C , and Figure 9C are cross-sectional views taken along lines​​​​​​​​​​​​​​​Figure 1A , Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A ,and Figure 9A A cross-sectional view taken by lines B-B' and C-C' for each of them.

[0011] Figures 10A through 10C These are plan views and cross-sectional views shown to explain a method for manufacturing an integrated circuit device according to exemplary embodiments of the present invention, wherein, specifically, Figure 10B and Figure 10C It is along Figure 10A The sectional view taken from lines B-B' and C-C'.

[0012] Figures 11A through 15C These are plan views and cross-sectional views illustrating the process sequence of a method for manufacturing an integrated circuit device according to an exemplary embodiment of the present invention, wherein, specifically, Figure 11B , Figure 12B , Figure 13B , Figure 14B ,and Figure 15B Each of them and Figure 11C , Figure 12C , Figure 13C , Figure 14C ,and Figure 15C Each of them is along Figure 11A , Figure 12A , Figure 13A , Figure 14A A sectional view taken from lines B-B' and C-C' of each of 15A.

[0013] Figures 16A through 16C These are plan views and cross-sectional views shown to explain a method for manufacturing an integrated circuit device according to exemplary embodiments of the present invention, wherein, specifically, Figure 16B and Figure 16C It is along Figure 16A The sectional view taken from lines B-B' and C-C'. Detailed Implementation

[0014] Figures 1A through 9C These are plan views and cross-sectional views illustrating the process sequence for explaining an exemplary embodiment of the method for manufacturing an integrated circuit device according to the concept of the present invention. Specifically, Figure 1B , Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8Beach of Figure 9B each of Figure 1C , Figure 2C , Figure 3C , Figure 4C , Figure 5C , Figure 6C , Figure 7C , Figure 8C , and Figure 9C each of Figure 1A , Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , and Figure 9A each of

[0015] Referring to Figures 1A through 1C , a device layer 120 is formed on a semiconductor substrate 110, the device layer 120 including a plurality of semiconductor devices 150. For example, the semiconductor substrate 110 can include silicon (Si). Alternatively, the semiconductor substrate 110 can include a semiconductor element such as germanium (Ge), or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). The semiconductor substrate 110 can also include a silicon on insulator (SOI) structure. For example, the semiconductor substrate 110 can include a buried oxide (BOX) layer. The semiconductor substrate 110 can include conductive regions such as wells doped with impurities or structures doped with impurities. In addition, the semiconductor substrate 110 can include various device isolation structures such as shallow trench isolation (STI) structures. The semiconductor substrate 110 can include an active surface and a passive surface opposite the active surface.

[0016] The device layer 120 including the plurality of semiconductor devices 150 can be formed on the active surface of the semiconductor substrate 110.

[0017] At least a portion of the plurality of semiconductor devices 150 can include transistors. For example, at least a portion of the plurality of semiconductor devices 150 can include bipolar junction transistors (BJTs) or field effect transistors (FETs). For example, at least a portion of the plurality of semiconductor devices 150 can include planar transistors or Fin field effect transistors (FinFETs). When at least a portion of the plurality of semiconductor devices 150 includes FinFETs, a plurality of fin-type active regions can protrude and extend in a horizontal direction (X-direction or Y-direction) parallel to each other in the semiconductor base 110.

[0018] The plurality of semiconductor devices 150 can constitute logic cells. Logic cells can be variously configured to include a plurality of circuit elements, such as transistors, resistors, etc. Logic cells can constitute, for example, AND, NAND, OR, NOR, XOR, XNOR, inverters (INV), adders (ADD), buffers (BUF), delays (DLY), filters (FIL), multiplexers (MXT / MXIT), OAIs (or / and / inverters), AO (and / or), AOI (and / or / inverters), D flip-flops, reset flip-flops, master-slave flip-flops, latches, etc. Logic cells can also constitute standard cells that perform desired logic functions, such as counters, buffers, etc.

[0019] The plurality of semiconductor devices 150 can include various individual devices for constituting, for example, a central processing unit (CPU), a graphics processing unit (GPU), and an application processor (AP), or various individual devices for constituting, for example, a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, an electrically erasable and programmable read-only memory (EEPROM) device, a phase-change random access memory (PRAM) device, a magnetic random access memory (MRAM) device, and a resistive random access memory (RRAM).

[0020] The device layer 120 can include the semiconductor devices 150, wires and conductive plugs for connecting the semiconductor devices 150 to each other, and insulating layers filling spaces between the semiconductor devices 150. The device layer 120 can contain conductive materials, semiconductor materials, and insulating materials of various types and various shapes. Also, the insulating layers can be located on the wires and the conductive plugs.

[0021] A lower wiring structure 200 can be formed on the device layer 120. In some embodiments, the lower wiring structure 200 can be formed using a dual damascene process. The lower wiring structure 200 can be electrically connected to each of the semiconductor devices 150 such that the lower wiring structure 200 can provide electrical connections between the plurality of semiconductor devices 150 and between the plurality of semiconductor devices 150 and the reference wiring structure 300. Figures 10A through 10C The reference wiring structure 300 is described below.

[0022] The lower wiring structure 200 can include a lower wiring layer 210 and a lower via plug 220 connected to the lower wiring layer 210. A lower wiring insulating layer 250 can fill spaces between the lower wiring layer 210 and the lower via plug 220 and spaces adjacent to the lower wiring layer 210 and the lower via plug 220. In some embodiments, the lower wiring layer 210 and the lower via plug 220 can contact each other and can be integrally formed.

[0023] For example, the lower wiring layer 210 can include a plurality of lines extending in a linear shape in a first horizontal direction (X direction) parallel to each other. Figure 1A and Figure 1B The extension length of the lower wiring layer 210 in the first horizontal direction (X direction) shown in FIG. 2 is an illustrative example, and is not limited thereto.

[0024] The lower wiring structure 200 can further include a lower barrier layer 230 surrounding the bottom and side surfaces of the lower wiring layer 210 and the lower via plug 220. The lower barrier layer 230 can be disposed between (a) the lower wiring layer 210 and the lower via plug 220 and (b) the lower wiring insulating layer 250. In some embodiments, the lower barrier layer 230 can also be disposed between the lower via plug 220 and a conductive layer in contact with the bottom surface of the lower via plug 220. In some embodiments, the lower wiring structure 200 can further include a lower cap layer 240 covering the upper surface of the lower wiring layer 210.

[0025] For example, the lower wiring layer 210 and the lower via plug 220 can include a metallic material, such as tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), ruthenium (Ru), manganese (Mn), or cobalt (Co). For example, the lower barrier layer 230 can include a nitride or an oxide of a metal, such as Ti, Ta, Ru, Mn, Co, or W, or can include an alloy, such as cobalt tungsten phosphide (CoWP), cobalt tungsten boride (CoWB), cobalt tungsten boron phosphide (CoWBP), or the like. For example, the lower cap layer 240 can include a metallic material, such as W, Ti, Ta, Ru, Mn, or Co. For example, the lower wiring insulating layer 250 can include silicon oxide or an insulating material having a dielectric constant lower than that of silicon oxide. In some embodiments, the lower wiring insulating layer 250 can include a tetraethyl orthosilicate (TEOS) film or an ultra low K (ULK) film having an ultra low dielectric constant K of 2.2 to 2.4. The ULK film can include a silicon oxycarbide (SiOC) film or a carbon-doped silicon oxide (SiCOH) film.

[0026] A lower etch stop film 290 can be formed on the lower wiring structure 200 and the lower wiring insulating layer 250 to cover the upper surface of the lower wiring layer 210 and the upper surface of the lower wiring insulating layer 250. In some embodiments, when the lower cap layer 240 covers the upper surface of the lower wiring layer 210, the lower etch stop film 290 can cover the upper surface of the lower cap layer 240 and the upper surface of the lower wiring insulating layer 250. For example, the lower etch stop film 290 can include a nitride, such as silicon nitride (SiN) or aluminum nitride (AIN). In some embodiments, the lower etch stop film 290 can include a material that does not include carbon.

[0027] A reference wiring insulating layer 350 can be formed on the lower etch stop film 290 to cover the lower wiring structure 200 and the lower wiring insulating layer 250. For example, the reference wiring insulating layer 350 can include silicon oxide or an insulating material having a dielectric constant lower than that of silicon oxide. In some embodiments, the reference wiring insulating layer 350 can include a TEOS film or a ULK film having an ultra-low dielectric constant of 2.2 to 2.4. The ULK film can include a SiOC film or a SiCOH film.

[0028] In some embodiments, after the lower etch stop film 290 covering the device layer 120 is formed without forming the lower wiring structure 200 and the lower wiring insulating layer 250, the reference wiring insulating layer 350 covering the lower etch stop film 290 can be formed.

[0029] A reference etch stop film 390 and a reference hardmask layer 410 can be formed in sequence on the reference wiring insulating layer 350. For example, the reference etch stop film 390 can include silicon carbon nitride (SiCN) or can include a stack structure of SiCN / SiN or SiCN / SiN / AIN. In some embodiments, the reference etch stop film 390 can include a carbon-containing material. The reference hardmask layer 410 can include titanium nitride (TiN) or silicon oxynitride (SiON) or can include a stack structure of SiON / TiN. In some embodiments, the reference hardmask layer 410 can include a first reference hardmask layer 412 and a second reference hardmask layer 414 stacked on the first reference hardmask layer 412. For example, the first reference hardmask layer 412 can include a metal nitride such as TiN, and the second reference hardmask layer 414 can include an oxynitride such as SiON. In some embodiments, the first reference hardmask layer 412 can include a metal nitride such as TiN, and the second reference hardmask layer 414 can include a carbon-containing material such as SiC or SiCN, and in this case, the reference etch stop film 390 can include a carbon-free material, for example, a nitride such as SiN or AIN. Each of the reference etch stop film 390, the first reference hardmask layer 412, and the second reference hardmask layer 414 can include a different material among (i) a metal nitride material, (ii) an oxynitride material, and (iii) a material including carbon.

[0030] The first reference hardmask layer 412 and the second reference hardmask layer 414 can have a large etch selectivity ratio or can have similar etch characteristics depending on conditions of an etch process.

[0031] A first mask layer MK1 having a first opening MO1 can be formed on the reference hardmask layer 410. For example, the first mask layer MK1 can include or can be formed using a photoresist. In some embodiments, a first anti-reflective film 510 can be formed on the reference hardmask layer 410 before the first mask layer MK1 is formed.

[0032] For example, the first openings MO1 can be formed in a plurality of linear shapes extending in a second horizontal direction (Y direction) in parallel to each other. In some embodiments, the first horizontal direction (X direction) and the second horizontal direction (Y direction) can be perpendicular to each other. The first openings MO1 can include first cut openings MO1a and first extension openings MO1b. An extension length of the first cut openings MO1a in the second horizontal direction (Y direction) can be smaller than an extension length of the first extension openings MO1b. For example, a portion of the first cut openings MO1a can overlap a portion of a lower wiring layer 210 under the first cut openings MO1a, and one end portion of the first cut openings MO1a in the second horizontal direction (Y direction) can overlap a portion adjacent to a side surface of the lower wiring layer 210 under the first cut openings MO1a in a vertical direction (Z direction). In some embodiments, one end portion of the first cut openings MO1a can be aligned with a portion of the side surface of the lower wiring layer 210 under the first cut openings MO1a in the vertical direction (Z direction).

[0033] In the first cut openings MO1a, a portion adjacent to one end portion of the first cut openings MO1a and overlapping a portion of the lower wiring layer 210 under the first cut openings MO1a can be defined as a first mask split region MS1. The first mask split region MS1 of the first openings MO1 can correspond to a portion overlapping the second openings MO2 in the vertical direction (Z direction) as described in the second openings MO2. Figures 3A through 3C In the first cut openings MO1a, a portion adjacent to one end portion of the first cut openings MO1a and overlapping a portion of the lower wiring layer 210 under the first cut openings MO1a can be defined as a first mask split region MS1. The first mask split region MS1 of the first openings MO1 can correspond to a portion overlapping the second openings MO2 in the vertical direction (Z direction) as described in the second openings MO2.

[0034] As used herein, the term "split region" can refer to any portion of the integrated circuit device overlapping the first mask split region MS1 and / or the second mask split region MS2 in the vertical direction (Z direction). For example, the split region can include a portion of the reference wiring insulating layer 350 overlapping the first mask split region MS1 and / or the second mask split region MS2 in the vertical direction (Z direction). Also, in some embodiments, the split region can extend vertically from a top of the integrated circuit device to a bottom of the integrated circuit device.

[0035] Herein, the portion of the first openings MO1 (i.e., the first mask split region MS1) overlapping the portion of the second openings MO2 (i.e., the second mask split region MS2) can mean that a portion of the semiconductor substrate 110, a portion of the lower wiring layer 210, and a portion of the reference wiring insulating layer 350 overlapping the first mask split region MS1 in the vertical direction can be the same portion as a portion of the semiconductor substrate 110, a portion of the lower wiring layer 210, and a portion of the reference wiring insulating layer 350 overlapping the second mask split region MS2 in the vertical direction, respectively.

[0036] Meanwhile, for convenience of explanation and easy indication of the relationship with other elements, the terms "reference", "upper", and "lower" included in the names of elements are used herein. For example, in addition to the words themselves composed of the terms "reference", "upper", and "lower", elements having the same or similar names and including the terms "upper" and "lower" can be used herein to refer to elements arranged in "upper" and "lower" positions by using the element including the term "reference" as a reference. Therefore, when there is no need to compare the positional relationship with each other, the elements including the terms "reference", "upper", and "lower" can be used herein to refer to the same elements, omitting the terms "reference", "upper", and "lower". For example, each of the reference wiring insulating layer 350, the reference etching stop film 390, the reference hard mask layer 410, the first reference hard mask layer 412, and the second reference hard mask layer 414 can refer to the wiring insulating layer 350, the etching stop film 390, the hard mask layer 410, the first hard mask layer 412, and the second hard mask layer 414, respectively.

[0037] Referring to Figures 1A through 2C By removing the first region 410R1 that is a part of the reference hard mask layer 410 using the first mask layer MK1 as an etching mask, the first recess 414O1 can be formed. The first region 410R1 can be a part of the reference hard mask layer 410 located under the first opening MO1 of the first mask layer MK1 and the first recess 414O1 can be a part of the reference hard mask layer 410 from which the first region 410R1 is removed. After the first recess 414O1 is formed, the first mask layer MK1 and the first anti-reflection film 510 can be removed.

[0038] The first recess 414O1 can extend from the upper surface of the reference hard mask layer 410 toward the semiconductor substrate 110 in the vertical direction (Z direction), but the reference etching stop film 390 can not be exposed at the bottom level of the first recess 414O1 (e.g., can not be exposed by / through the lower region). That is, the depth of the first recess 414O1 in the vertical direction (Z direction) can be less than the thickness of the reference hard mask layer 410.

[0039] When the reference hard mask layer 410 includes the first reference hard mask layer 412 and the second reference hard mask layer 414 stacked on the first reference hard mask layer 412, the first recess 414O1 can pass through the second reference hard mask layer 414 and then expose the first reference hard mask layer 412 at the bottom level of the first recess 414O1. That is, the first recess 414O1 can be formed by removing a portion of the second reference hard mask layer 414 using the first mask layer MK1 as an etching mask. The depth of the first recess 414O1 in the vertical direction (Z direction) can be equal to or greater than the thickness of the second reference hard mask layer 414.

[0040] The first recess 414O1 can include a first cut recess 414O1a corresponding to the first cut opening MO1a of the first mask layer MK1 and a first extension recess 414O1b corresponding to the first extension opening MO1b of the first mask layer MK1. The extension length of the first cut recess 414O1a in the second horizontal direction (Y direction) can be less than the extension length of the first extension recess 414O1b. For example, a portion of the first cut recess 414O1a can overlap a portion of the lower wiring layer 210 under the first cut recess 414O1a, and one end of the first cut recess 414O1a in the second horizontal direction (Y direction) can overlap a portion adjacent to the side surface of the lower wiring layer 210 under the first cut recess 414O1a in the vertical direction (Z direction). In some embodiments, one end of the first cut recess 414O1a can be aligned with a portion of the side surface of the lower wiring layer 210 under the first cut recess 414O1a in the vertical direction (Z direction).

[0041] In the first cut recess 414O1a, a portion adjacent to one end of the first cut recess 414O1a and overlapping a portion of the lower wiring layer 210 under the first cut recess 414O1a can be defined as a first recess splice region 414S.

[0042] Referring to FIGS. 4A and 4B together, Figures 3A through 3C A second mask layer MK2 having a second opening MO2 can be formed on the reference hard mask layer 410 having the first recess 414O1. For example, the second mask layer MK2 can include or can be formed using a photoresist. In some embodiments, a second anti-reflective film 520 can be formed on the reference hard mask layer 410 before the second mask layer MK2 is formed.

[0043] For example, the second openings MO2 can be formed in a plurality of linear shapes extending in the second horizontal direction (Y direction) in parallel with each other. The second openings MO2 can include second cut openings MO2a and second extension openings MO2b. The second cut openings MO2a can have a smaller extension length in the second horizontal direction (Y direction) than the extension length of the second extension openings MO2b. Also, each of the first cut openings MO1a and the second cut openings MO2a can have the same value in width in the first horizontal direction (X direction).

[0044] A portion of the second openings MO2 and a portion of the first grooves 414O1 can overlap each other in the vertical direction (Z direction). For example, a portion of the second cut openings MO2a and a portion of the first cut grooves 414O1a can overlap each other in the vertical direction (Z direction), and the second extension openings MO2b and the first extension grooves 414O1b can not overlap each other in the vertical direction (Z direction). In particular, a portion of the second cut openings MO2a can overlap the first groove splice region 414S in the vertical direction (Z direction).

[0045] For example, a portion of the second cut openings MO2a can overlap a portion of the lower wiring layer 210 below the second cut openings MO2a, and one end portion of the second cut openings MO2a in the second horizontal direction (Y direction) can overlap a portion adjacent to a side surface of the lower wiring layer 210 below the second cut openings MO2a in the vertical direction (Z direction). In some embodiments, one end portion of the second cut openings MO2a can be aligned with a portion of the side surface of the lower wiring layer 210 below the second cut openings MO2a in the vertical direction (Z direction).

[0046] The portion of the second cut openings MO2a overlapping the first groove splice region 414S in the vertical direction (Z direction) can be defined as a second mask splice region MS2. The second mask splice region MS2 can be a portion overlapping a portion of the lower wiring layer 210 located below.

[0047] Referring to FIGS. 4A and 4B together, Figures 3A through 4C by using the second mask layer MK2 as an etching mask to remove a second region 410R2 that is a portion of the reference hard mask layer 410, a second groove 414O2 can be formed. The second region 410R2 can be a portion of the reference hard mask layer 410 located below the second openings MO2 of the second mask layer MK2 and the second groove 414O2 can be a portion of the reference hard mask layer 410 from which the second region 410R2 is removed. After the second groove 414O2 is formed, the second mask layer MK2 and the second anti-reflective film 520 can be removed.

[0048] The second recess 414O2 can include a second cut recess 414O2a corresponding to the second cut opening MO2a of the second mask layer MK2 and a second extension recess 414O2b corresponding to the second extension opening MO2b of the second mask layer MK2. The second cut recess 414O2a can be in communication with the first cut recess 414O1a. The first recess 414O1 and the second recess 414O2 together can constitute the reference recess 410O.

[0049] The reference recess 410O can extend from an upper surface of the reference hard mask layer 410 toward the semiconductor substrate 110 in a vertical direction (Z direction), but the reference etching stop film 390 can be exposed (e.g., can be exposed by / via a first portion) at a portion of a bottom level of the reference recess 410O, and the reference etching stop film 390 can not be exposed (e.g., can not be exposed by / via a second portion) at another portion of the bottom level of the reference recess 410O. Specifically, the reference etching stop film 390 can be exposed at the bottom level of a portion of the reference recess 410O corresponding to the second mask split region MS2, and the reference etching stop film 390 can not be exposed at the bottom level of a remaining portion of the reference recess 410O.

[0050] A portion of the reference recess 410O formed corresponding to the second mask split region MS2 can be defined as a reference recess split region 410S. The reference recess split region 410S can pass through the reference hard mask layer 410 in a vertical direction (Z direction), and then the reference etching stop film 390 can be exposed at a bottom level of the reference recess split region 410S. The reference recess split region 410S can include a first recess split region 414S passing through the second reference hard mask layer 414 in a vertical direction (Z direction) and a second recess split region 412S passing through the first reference hard mask layer 412 in a vertical direction (Z direction), where the first recess split region 414S and the second recess split region 412S can be in communication with each other. The first recess split region 414S can be a portion formed using the first mask layer MK1 shown in FIG. 4A, and the second recess split region 412S can be a portion formed using the second mask layer MK2 shown in FIG. 4B. That is, the reference recess split region 410S can be formed in a portion corresponding to a portion in which the first opening MO1 of the first mask layer MK1 and the second opening MO2 of the second mask layer MK2 overlap. Figures 1A through 1C Figures 3A through 3C The reference etching stop film 390 can be exposed at a bottom level of a first portion of the reference recess split region 410S in the reference recess 410O, and the first reference hard mask layer 412 can be exposed at a bottom level of a second portion of the reference recess region 410O.

[0051] The reference etching stop film 390 can be exposed at a bottom level of a first portion of the reference recess split region 410S in the reference recess 410O, and the first reference hard mask layer 412 can be exposed at a bottom level of a second portion of the reference recess region 410O.

[0052] Referring to FIGS. 4A and 4B together, the reference recess 410O can be formed by etching the reference hard mask layer 410 using the first mask layer MK1 shown in FIG. 4A and the second mask layer MK2 shown in FIG. 4B.​Figures 4A through 5C A portion of the removable reference hard mask layer 410 can be removed to form a hard mask opening 412O. In the process of forming the hard mask opening 412O, the second reference hard mask layer 414 of the removable reference hard mask layer 410 can be removed, and a portion of the first reference hard mask layer 412 can be retained. For example, with respect to the results shown in FIG. 4A, a blanket etch can be performed to remove the second reference hard mask layer 414 and expose a portion of the first reference hard mask layer 412. At this time, a portion of the reference etch stop film 390 exposed at the bottom of the reference groove split region 410S can also be removed to form a first etch opening 390O1 exposing the reference wiring insulating layer 350 in a portion of the reference etch stop film 390 corresponding to the reference groove split region 410S. The first etch opening 390O1 can be in communication with the hard mask opening 412O. Figures 4A through 4C With respect to the results shown in FIG. 4A, a blanket etch can be performed to remove the second reference hard mask layer 414 and expose a portion of the first reference hard mask layer 412. At this time, a portion of the reference etch stop film 390 exposed at the bottom of the reference groove split region 410S can also be removed to form a first etch opening 390O1 exposing the reference wiring insulating layer 350 in a portion of the reference etch stop film 390 corresponding to the reference groove split region 410S. The first etch opening 390O1 can be in communication with the hard mask opening 412O.

[0053] Referring to FIG. 4A and FIG. 4B together, Figures 1A through 5C The hard mask opening 412O can correspond to the first opening MO1 of the first mask layer MK1 and the second opening MO2 of the second mask layer MK2, and can be formed in a portion of the reference hard mask layer 410 (i.e., a portion of the first reference hard mask layer 412) that overlaps the reference hard mask layer 410 in the vertical direction (Z direction).

[0054] In this case, the first etch opening 390O1 can be formed in a portion of the reference etch stop film 390 corresponding to a portion of the first mask layer MK1 first opening MO1 that overlaps the second mask layer MK2 second opening MO2 in the vertical direction (Z direction), and the first etch opening 390O1 can be in communication with the hard mask opening 412O. Specifically, the first etch opening 390O1 can be formed in a portion of the reference etch stop film 390 corresponding to a portion of each of the first mask layer MK1 first cut opening MO1a and the second mask layer MK2 second cut opening MO2a adjacent to and overlapping one end portion in the vertical direction (Z direction), and the first etch opening 390O1 can be in communication with the hard mask opening 412O.

[0055] The center lines (e.g., the center line 410C1 of the first mask layer MK1 first cut opening MO1a and the center line 410C2 of the second mask layer MK2 second cut opening MO2a) of the first mask layer MK1 first cut opening MO1a and the second mask layer MK2 second cut opening MO2a partially overlapping each other in the long axis direction (e.g., the Y direction) can be parallel to each other. Figures 1A through 5CThe line C-C' in the first mask layer MK1 and the line C-C' in the second mask layer MK2 can be located on the same straight line, and the first cut opening MO1a of the first mask layer MK1 and the second cut opening MO2a of the second mask layer MK2 can have the same width in the short axis direction (for example, the X direction). That is, the center lines of the first cut opening MO1a of the first mask layer MK1 and the second cut opening MO2a of the second mask layer MK2, which partially overlap each other, can be located on the same straight line (for example, the line C-C') on the semiconductor substrate 110, the lower wiring layer 210, and the reference wiring insulating layer 350, which partially overlap each other in the vertical direction (Z direction). Figures 1A through 5C The line C-C' in the first mask layer MK1 and the line C-C' in the second mask layer MK2 can be located on the same straight line, and the first cut opening MO1a of the first mask layer MK1 and the second cut opening MO2a of the second mask layer MK2 can have the same width in the short axis direction (for example, the X direction). That is, the center lines of the first cut opening MO1a of the first mask layer MK1 and the second cut opening MO2a of the second mask layer MK2, which partially overlap each other, can be located on the same straight line (for example, the line C-C') on the semiconductor substrate 110, the lower wiring layer 210, and the reference wiring insulating layer 350, which partially overlap each other in the vertical direction (Z direction).

[0056] In this document, for the sake of understanding, the first opening MO1 of the first mask layer MK1 is separately described by dividing the first opening MO1 of the first mask layer MK1 into the first cut opening MO1a and the first extension opening MO1b, and the second opening MO2 of the second mask layer MK2 is also separately described by dividing the second opening MO2 of the second mask layer MK2 into the second cut opening MO2a and the second extension opening MO2b. That is, even though the overlapping portion of the first opening MO1 of the first mask layer MK1, which overlaps the second opening MO2 of the second mask layer MK2, and the connection portion connected to the adjacent overlapping portion thereof are conceptually referred to as the first cut opening MO1a, and another portion of the first opening MO1 of the first mask layer MK1 is conceptually referred to as the first extension opening MO1b, the first cut opening MO1a and the first extension opening MO1b in the first mask layer MK1 can be referred to in the opposite way in another region depending on the position to be shown in other drawings in addition to these drawings. Similarly, the second cut opening MO2a and the second extension opening MO2b in the second mask layer MK2 can be referred to in the opposite way in another region depending on the position to be shown in other drawings in addition to these drawings.

[0057] In this context, all of the owners of the reference groove split region 410S of the hard mask layer 410, the second groove split region 412S of the first reference hard mask layer 412, the first groove split region 414S of the second reference hard mask layer 414, the first mask split region MS1 of the first opening MO1, and the second mask split region MS2 of the second opening MO2 can substantially overlap with each other in the vertical direction (Z direction) with respect to the semiconductor substrate 110. Therefore, any portion of the integrated circuit device corresponding to (e.g., overlapping in the vertical direction (Z direction) with) the reference groove split region 410S, the first groove split region 414S, the second groove split region 412S, the first mask split region MS1, and the second mask split region MS2, which overlap with each other in the vertical direction (Z direction) with respect to the semiconductor substrate 110, can be defined as a split region.

[0058] For reference Figures 6A through 6C The first reference hard mask layer 412 with the hard mask opening 412O can be used as an etching mask to remove a portion of the reference etching stop film 390 to form a second etching opening 390O2 exposing the reference wiring insulating layer 350. In the process of forming the second etching opening 390O2, a portion of the upper portion of the reference wiring insulating layer 350 exposed under the first etching opening 390O1 can also be removed, and thus a preliminary reference wiring groove 350R1p can be formed. The preliminary reference wiring groove 350R1p can extend downward from the upper surface of the reference wiring insulating layer 350, and the lower level of the preliminary reference wiring groove 350R1p can be lower than the level of the upper surface of the reference wiring insulating layer 350, and can be higher than the lower surface of the reference wiring insulating layer 350 such that a portion of the reference wiring insulating layer 350 can be maintained in an exposed state at the lower level of the preliminary reference wiring groove 350R1p.

[0059] The first etching opening 390O1 and the second etching opening 390O2 can together constitute the reference etching opening 390O.

[0060] For reference Figures 7A through 7C The reference wiring groove 350R can be formed by removing a portion of the reference wiring insulating layer 350 using the reference etching stop film 390 (which uses the reference etching opening 390O) as an etching mask. The reference wiring groove 350R can include a first reference wiring groove 350R1 and a second reference wiring groove 350R2.

[0061] Since a portion of the reference wiring insulating layer 350 is maintained in an exposed state at the lower level of the preliminary reference wiring groove 350R1p, the first reference wiring groove 350R1 can be formed by removing a portion of the preliminary reference wiring groove 350R1p using the reference etching stop film 390 (which uses the reference etching opening 390O) as an etching mask. Figures 6A through 6CThe preliminary reference wiring recess 350R1p is removed under a condition that the preliminary reference wiring recess 350R1p is formed on the lower side of the first etching opening 390O1, and thus a depth of the first reference wiring recess 350R1, which is a portion of the reference wiring recess 350R formed on the lower side of the first etching opening 390O1, can be greater than a depth of the second reference wiring recess 350R2, which is a portion of the reference wiring recess 350R formed on the lower side of the second etching opening 390O2.

[0062] The first reference wiring recess 350R1 can extend from an upper surface of the reference wiring insulation layer 350 to a lower surface of the reference wiring insulation layer 350 such that the lower portion wiring structure 200 can be exposed through / via a lower horizontal level of the first reference wiring recess 350R1. The second reference wiring recess 350R2 can extend downward from the upper surface of the reference wiring insulation layer 350, and a lower horizontal level of the second reference wiring recess 350R2 can be lower than a horizontal level of the upper surface of the reference wiring insulation layer 350 and can be higher than the lower surface of the reference wiring insulation layer 350 such that a portion of the reference wiring insulation layer 350 can be maintained in an exposed state at the lower horizontal level of the second reference wiring recess 350R2. That is, the first reference wiring recess 350R1 can be formed by removing the reference wiring insulation layer 350 from the upper surface to the lower surface of the reference wiring insulation layer 350, and the second reference wiring recess 350R2 can be formed by removing a portion of an upper portion of the reference wiring insulation layer 350.

[0063] Referring to FIG. 3A, the reference barrier layer 330 can be formed on the exposed surface of the reference etching stop film 390 and the reference wiring insulation layer 350 having the reference wiring recess 350R. Figures 8A through 8C After the reference barrier layer 330 covering the exposed surface of the reference etching stop film 390 and the reference wiring insulation layer 350 having the reference wiring recess 350R is formed, the reference wiring material layer 315 can be formed on the reference barrier layer 330. The reference barrier layer 330 can be conformally formed on the exposed surface of the reference etching stop film 390 and the reference wiring insulation layer 350 having the reference wiring recess 350R. The reference wiring material layer 315 can be formed in the reference wiring recess 350R (e.g., fill the reference wiring recess 350R) and on the upper surface of the reference etching stop film 390 (e.g., cover the upper surface of the reference etching stop film 390).

[0064] The reference barrier layer 330 can include a nitride or an oxide of a metal such as Ti, Ta, Ru, Mn, Co, or W, or can include an alloy such as CoWP, CoWB, CoWBP, etc. The reference wiring material layer 315 can include a metal material such as W, Cu, Ti, Ta, Ru, Mn, or Co, etc.

[0065] Referring to FIG. 3A, the reference barrier layer 330 can be formed on the exposed surface of the reference etching stop film 390 and the reference wiring insulation layer 350 having the reference wiring recess 350R. Figures 8A through 9CA portion of the reference wiring material layer 315 (e.g., covering the upper surface of the reference etching stop film 390) on the upper surface of the reference etching stop film 390 can be removed to form a reference wiring layer 310 and a reference via plug 320. The reference wiring layer 310 can refer to a portion of the remaining portion of the reference wiring material layer 315 at a level higher than the bottom level of the second reference wiring groove 350R2, and the reference via plug 320 can refer to a portion of the remaining portion of the reference wiring material layer 315 at a level lower than the bottom of the second reference wiring groove 350R2 and connected to the reference wiring layer 310. Thus, the reference wiring layer 310 can have a substantially constant height and width and can extend in the second horizontal direction (Y direction), and the reference via plug 320 can have a substantially constant horizontal area below the reference wiring layer 310 or can extend in the vertical direction (Z direction) toward the semiconductor substrate 110 while the horizontal area continuously decreases or increases.

[0066] In the process of forming the reference wiring layer 310 and the reference via plug 320, a portion of the reference barrier layer 330 covering the upper surface of the reference etching stop film 390 and the reference etching stop film 390 can be removed together, so that the upper surface of the reference wiring insulating layer 350 can be exposed.

[0067] To form the reference wiring layer 310 and the reference via plug 320, the process of removing a portion of the reference wiring material layer 315 can be performed by a chemical-mechanical polishing (CMP) method. In the process of forming the reference wiring layer 310 and the reference via plug 320, the reference etching stop film 390 can be completely removed.

[0068] Figures 10A through 10C are plan views and cross-sectional views shown to explain a method of manufacturing an integrated circuit device according to an exemplary embodiment of the inventive concept. Specifically, Figure 10B and Figure 10C are cross-sectional views taken along lines B-B' and C-C' in Figure 10A In Figures 10A through 10C , the same reference numerals are used to refer to the same components as those in Figures 1A through 9C , and repetitive detailed descriptions thereof can be omitted herein.

[0069] Referring to Figures 10A through 10C , the integrated circuit device 1 can include a device layer 120 including a plurality of semiconductor devices 150, a lower wiring structure 200, and a reference wiring structure 300. The lower wiring structure 200 can be electrically connected to each of the semiconductor devices 150, so that the lower wiring structure 200 can provide electrical connections between the plurality of semiconductor devices 150 and between the plurality of semiconductor devices 150 and the reference wiring structure 300.

[0070] The lower wiring structure 200 can include a lower wiring layer 210 and a lower via plug 220 connected to the lower wiring layer 210. A lower wiring insulating layer 250 can fill a space between the lower wiring layer 210 and the lower via plug 220. In some embodiments, the lower wiring layer 210 and the lower via plug 220, which are in contact with each other, can be integrally formed.

[0071] The lower wiring layer 210 can be formed in a plurality of line shapes extending in a first horizontal direction (X direction) in parallel to each other. The lower via plug 220 can extend from a bottom surface of the lower wiring layer 210 toward the semiconductor substrate 110.

[0072] The lower wiring structure 200 can further include a lower barrier layer 230 surrounding bottom and side surfaces of the lower wiring layer 210 and the lower via plug 220. The lower barrier layer 230 can be disposed between (a) the lower wiring layer 210 and the lower via plug 220 and (b) the lower wiring insulating layer 250. In some embodiments, the lower wiring structure 200 can further include a lower cap layer 240 covering an upper surface of the lower wiring layer 210.

[0073] The lower etching stop film 290 can cover an upper surface of the lower wiring structure 200 and an upper surface of the lower wiring insulating layer 250. The lower etching stop film 290 can cover a portion of the upper surface of the lower wiring layer 210 or a portion of the upper surface of the lower cap layer 240. The reference wiring structure 300 can be connected to a portion of the upper surface of the lower wiring layer 210 or the upper surface of the lower cap layer 240 that is not covered by the lower etching stop film 290.

[0074] The reference wiring structure 300 can include a reference wiring layer 310 and a reference via plug 320 connected to the reference wiring layer 310. A reference wiring insulating layer 350 can fill a space between the reference wiring layer 310 and the reference via plug 320. In some embodiments, the reference wiring layer 310 and the reference via plug 320, which are in contact with each other, can be integrally formed.

[0075] The reference wiring layer 310 can be formed in a plurality of line shapes extending in a second horizontal direction (Y direction) in parallel to each other. The reference via plug 320 can extend from a bottom surface of the reference wiring layer 310 toward the semiconductor substrate 110 to be electrically connected to the lower wiring structure 200.

[0076] The reference wiring structure 300 can further include a reference barrier layer 330 that surrounds bottom and side surfaces of the reference wiring layer 310 and the reference via plug 320. The reference barrier layer 330 can be disposed between (a) the reference wiring layer 310 and the reference via plug 320 and (b) the reference wiring insulating layer 350. In some embodiments, the reference wiring structure 300 can further include a reference cap layer 340 that covers an upper surface of the reference wiring layer 310.

[0077] The lower etching stop film 290 can be disposed between the lower wiring insulating layer 250 and the reference wiring insulating layer 350. However, since the reference via plug 320 is formed in a portion of the reference wiring insulating layer 350 that overlaps the first opening MO1 of the first mask layer MK1 and the second opening MO2 of the second mask layer MK2, as described with reference to FIGS. 1A and 1B, the reference via plug 320 can not be covered by the lower etching stop film 290. Figures 9A through 9C Figures 1A through 8C The reference etching stop film 390 can be completely removed, and thus the reference etching stop film 390 can not remain on the reference wiring insulating layer 350 and the reference wiring structure 300. Thus, the reference etching stop film 390 can not be disposed between the reference wiring insulating layer 350 and an insulating layer (e.g., the upper wiring insulating layer 650) disposed on an upper side of the reference wiring insulating layer 350, such that an upper surface of the reference wiring insulating layer 350 and a lower surface of the upper wiring insulating layer 650 can contact each other. Figures 11A through 11C

[0078] Referring to FIGS. 1A and 1B together, Figures 1A through 10C the reference via plug 320 included in the integrated circuit device 1 according to the inventive concept can be a fully-aligned-via (FAV). The reference via plug 320 can be formed in a portion of the reference wiring insulating layer 350 corresponding to a portion in which the first opening MO1 of the first mask layer MK1 and the second opening MO2 of the second mask layer MK2 overlap each other (i.e., a portion in which the first mask stitching region MS1 and the second mask stitching region MS2 overlap each other).

[0079] Specifically, the reference via plug 320 can be aligned in width in a first horizontal direction (X direction) of each of the first opening MO1 and the second opening MO2, and thus a width of the reference via plug 320 in the first horizontal direction (X direction) can be determined / controlled, and can also be aligned in width in a second horizontal direction (Y direction) of a portion in which the first opening MO1 and the second opening MO2 overlap each other (i.e., a portion in which the first mask stitching region MS1 and the second mask stitching region MS2 overlap each other), and thus a width of the reference via plug 320 in the second horizontal direction (Y direction) can be determined / controlled.

[0080] ​​Accordingly, unlike a via plug in a self-aligned via (SAV) in which a width of an opening of a mask layer through which the via plug is inserted for forming a wiring layer is aligned and a width of the via plug is limited only in one direction (for example, limited in a first horizontal direction (X direction)), a width of the via plug 320 with reference to both a first horizontal direction (X direction) and a second horizontal direction (Y direction) perpendicular to each other can be limited, and thus the electrical reliability of the integrated circuit device 1 can be improved.

[0081] In some embodiments, the lower via plug 220 can be, but is not limited to, only a SAV, and can be a FAV.

[0082] Figures 11A through 15C are plan views and cross-sectional views shown in accordance with a process sequence for explaining a method of manufacturing an integrated circuit device according to an exemplary embodiment of the inventive concept. Specifically, Figure 11B , Figure 12B , Figure 13B , Figure 14B , and Figure 15B each of Figure 11C , Figure 12C , Figure 13C , Figure 14C , and Figure 15C each of Figure 11A , Figure 12A , Figure 13A , Figure 14A , and 15A are cross-sectional views taken along line B-B' and line C-C' of each of Figures 11A through 15C , Figures 1A through 10C In

[0083] Referring to Figures 11A through 11C , an upper wiring insulating layer 650 can be formed on the resultant structure of Figures 10A through 10C , that is, on the reference wiring structure 300 and the reference wiring insulating layer 350. An upper surface of the reference wiring insulating layer 350 and a lower surface of the upper wiring insulating layer 650 can be in contact with each other.

[0084] For example, the upper wiring insulating layer 650 can include silicon oxide or an insulating material having a dielectric constant lower than that of silicon oxide. In some embodiments, the upper wiring insulating layer 650 can include a TEOS film or a ULK film having an ultra-low dielectric constant of 2.2 to 2.4. The ULK film can include a SiOC film or a SiCOH film.

[0085] Referring to Figures 12A through 12CAn upper etching stop film 690 and an upper hard mask layer 430 can be sequentially formed on the upper wiring insulating layer 650. For example, the upper etching stop film 690 can include SiCN or can include a stack structure of SiCN / SiN or SiCN / SiN / AIN. In some embodiments, the upper etching stop film 690 can include a carbon-containing material. The upper hard mask layer 430 can include TiN or SiON or can include a stack structure of SiON / TiN. In some embodiments, the upper hard mask layer 430 can include a first upper hard mask layer 432 and a second upper hard mask layer 434 stacked on the first upper hard mask layer 432. For example, the first upper hard mask layer 432 can include a metal nitride such as TiN, and the second upper hard mask layer 434 can include an oxynitride such as SiON. The first upper hard mask layer 432 and the second upper hard mask layer 434 can have a large etching selectivity ratio or can have similar etching characteristics according to conditions of an etching process.

[0086] On the upper hard mask layer 430, a third mask layer MK3 having third openings MO3 can be formed. For example, the third mask layer MK3 can include a photoresist or can be formed using a photoresist. In some embodiments, before the third mask layer MK3 is formed, a third anti-reflection film 530 can be formed on the upper hard mask layer 430.

[0087] For example, the third openings MO3 can be formed in a plurality of line shapes extending in a first horizontal direction (X direction) in parallel to each other. The third openings MO3 can include third cut openings MO3a and third extension openings MO3b. An extension length of the third cut openings MO3a in the first horizontal direction (X direction) can be smaller than an extension length of the third extension openings MO3b. For example, a portion of the third cut openings MO3a can overlap a portion of the reference wiring layer 310, and one end portion of the third cut openings MO3a can overlap a portion adjacent to a side surface of the reference wiring layer 310 in a vertical direction (Z direction). In some embodiments, one end portion of the third cut openings MO3a can be aligned with a portion of the side surface of the reference wiring layer 310 located below in the vertical direction (Z direction).

[0088] A portion of the third cut openings MO3a adjacent to one end portion of the third cut openings MO3a and overlapping a portion of the reference wiring layer 310 below the third cut openings MO3a can be defined as a third mask split region MS3. The third mask split region MS3 of the third openings MO3 can correspond to a portion overlapping the fourth openings MO4 described in the first embodiment in the vertical direction (Z direction). A portion of the fourth openings MO4 overlapping the third mask split region MS3 in the vertical direction (Z direction) can be defined as a fourth mask split region MS4. Figures 13A through 13C A portion of the third cut openings MO3a adjacent to one end portion of the third cut openings MO3a and overlapping a portion of the reference wiring layer 310 below the third cut openings MO3a can be defined as a third mask split region MS3. The third mask split region MS3 of the third openings MO3 can correspond to a portion overlapping the fourth openings MO4 described in the first embodiment in the vertical direction (Z direction). A portion of the fourth openings MO4 overlapping the third mask split region MS3 in the vertical direction (Z direction) can be defined as a fourth mask split region MS4.

[0089] Referring to Figures 12A through 13C , similar to the method explained in Figures 2A through 3C , a third recess 43401 can be formed by removing a third region 430R1 that is part of the upper hard mask layer 430 using the third mask layer MK3 as an etching mask. The third region 430R1 can be a portion of the upper hard mask layer 430 that is located under the third opening MO3 of the third mask layer MK3, and thus the third recess 43401 can be a portion removed from the upper hard mask layer 430. After forming the third recess 43401, the third mask layer MK3 and the third anti-reflective film 530 can be removed.

[0090] The third recess 43401 can extend from an upper surface of the upper hard mask layer 430 toward the semiconductor substrate 110 in a vertical direction (Z direction), but the upper etching stopper film 690 can not be exposed at / lower level of the third recess 43401 exposed through the lower level of the third recess 43401. That is, a depth of the third recess 43401 in the vertical direction (Z direction) can have a value smaller than a thickness of the upper hard mask layer 430.

[0091] When the upper hard mask layer 430 includes the first upper hard mask layer 432 and the second upper hard mask layer 434 stacked on the first upper hard mask layer 432, the third recess 43401 can pass through the second upper hard mask layer 434 and then expose the first upper hard mask layer 432 through / lower level of the third recess 43401. That is, the third recess 43401 can be formed by removing a portion of the second upper hard mask layer 434 using the third mask layer MK3 as an etching mask. A depth of the third recess 43401 in the vertical direction (Z direction) can be equal to or greater than a thickness of the second upper hard mask layer 434.

[0092] The third recess 43401 can include a third cut recess 43401a and a third extension recess 43401b formed corresponding to the third cut opening MO3a and the third extension opening MO3b of the third mask layer MK3, respectively. An extension length of the third cut recess 43401a in the first horizontal direction (X direction) can be smaller than an extension length of the third extension recess 43401b. For example, a portion of the third cut recess 43401a can overlap with a portion of the reference wiring layer 310 located under the third cut recess 43401a, and one end of the third cut recess 43401a can overlap with a portion adjacent to a side surface of the reference wiring layer 310 located under the third cut recess 43401a in the vertical direction (Z direction). In some embodiments, one end of the third cut recess 43401a can be aligned with a portion of the side surface of the reference wiring layer 310 located under the third cut recess 43401a in the vertical direction (Z direction).

[0093] In the third cut groove 434O1a, a portion adjacent to one end of the third cut groove 434O1a and overlapping a portion of the reference wiring layer 310 located below the third cut groove 434O1a can be defined as a third groove splice region 434S.

[0094] A fourth mask layer MK4 having fourth openings MO4 can be formed on the upper hard mask layer 430 having the third grooves 434O1. For example, the fourth mask layer MK4 can include or be formed using a photoresist. In some embodiments, a fourth anti-reflective film 540 can be formed on the upper hard mask layer 430 before the fourth mask layer MK4 is formed.

[0095] For example, the fourth openings MO4 can be formed in a plurality of linear shapes extending in a first horizontal direction (X direction) in parallel to each other. The fourth openings MO4 can include fourth cut openings MO4a and fourth extension openings MO4b. The fourth cut openings MO4a can have a length of extension in the first horizontal direction (X direction) that is less than a length of extension of the fourth extension openings MO4b.

[0096] A portion of the fourth openings MO4 and a portion of the third grooves 434O1 can overlap each other in a vertical direction (Z direction). For example, a portion of the fourth cut openings MO4a and a portion of the third cut grooves 434O1a can overlap each other in the vertical direction (Z direction), and the fourth extension openings MO4b and the third extension grooves 434O1b can not overlap each other in the vertical direction (Z direction). Specifically, a portion of the fourth cut openings MO4a can overlap the third groove splice region 434S in the vertical direction (Z direction).

[0097] For example, a portion of the fourth cut openings MO4a can overlap a portion of the reference wiring layer 310 located below the fourth cut openings MO4a, and one end of the fourth cut openings MO4a can overlap a portion adjacent to a side surface of the reference wiring layer 310 located below the fourth cut openings MO4a in the vertical direction (Z direction). In some embodiments, one end of the fourth cut openings MO4a can be aligned with a portion of the side surface of the reference wiring layer 310 located below the fourth cut openings MO4a in the vertical direction (Z direction).

[0098] A portion of the fourth cut openings MO4a overlapping the third groove splice region 434S in the vertical direction (Z direction) can be defined as a fourth mask splice region MS4. The fourth mask splice region MS4 can be a portion overlapping a portion of the reference wiring layer 310 located below the fourth mask splice region MS4.

[0099] Referring to FIGS. 4A and 4B together, Figures 13A through 14CThe fourth region 430R2, which is part of the upper hard mask layer 430, can be removed using the fourth mask layer MK4 as an etching mask, similar to the description with reference to Figures 4A through 4C The fourth region 430R2 is part of the upper hard mask layer 430 located under the fourth opening MO4 of the fourth mask layer MK4, and thus the fourth recess 434O2 can be a portion formed by removing the fourth region 430R2. After the fourth recess 434O2 is formed, the fourth mask layer MK4 and the fourth anti-reflective film 540 can be removed.

[0100] The fourth recess 434O2 can include a fourth cut recess 434O2a and a fourth extension recess 434O2b formed corresponding to the fourth cut opening MO4a and the fourth extension opening MO4b of the fourth mask layer MK4, respectively. The fourth cut recess 434O2a can be in communication with the third cut recess 434O1a. The third recess 434O1 and the fourth recess 434O2 can together constitute an upper recess 430O.

[0101] The upper recess 430O can extend from an upper surface of the upper hard mask layer 430 toward the semiconductor substrate 110 in a vertical direction (Z direction), but the upper etching stop film 690 can be exposed through / via a portion of a bottom level of the upper recess 430O, and the upper etching stop film 690 can not be exposed through / via another portion of the bottom level of the upper recess 430O. Specifically, the upper etching stop film 690 can be exposed through / via the bottom level of the portion of the upper recess 430O formed corresponding to the fourth mask split region MS4, and the upper etching stop film 690 can not be exposed through / via the bottom level of the remaining portion of the upper recess 430O.

[0102] The portion of the upper recess 430O formed corresponding to the fourth mask split region MS4 can be defined as an upper recess split region 430S. The upper recess split region 430S can pass through the upper hard mask layer 430 in a vertical direction (Z direction), and a bottom level of the upper recess split region 430S can expose the upper etching stop film 690. The upper recess split region 430S can include a third recess split region 434S passing through the second upper hard mask layer 434 in a vertical direction (Z direction) and a fourth recess split region 432S passing through the first upper hard mask layer 432 in a vertical direction (Z direction), and the third recess split region 434S and the fourth recess split region 432S can be in communication with each other. The third recess split region 434S can be a portion formed using the third mask layer MK3 shown, and the fourth recess split region 432S can be a portion formed using the fourth mask layer MK4. Figures 12A through 12C Figures 13A through 13C ​A portion of the fourth mask layer MK4 is shown to form a part of the upper recess split region 430S. That is, the upper recess split region 430S can be formed in a portion corresponding to a portion of the third mask layer MK3 overlapping with the fourth mask layer MK4.

[0103] The upper etching stop film 690 can be exposed through / via a bottom level of the upper recess split region 430S in the upper recess 430O, and the first upper hard mask layer 432 can be exposed through / via a bottom level of a remaining portion of the upper recess region 430O.

[0104] Referring to FIG. 6A, the upper hard mask layer 430 can be formed on the upper etching stop film 690. The upper hard mask layer 430 can include a second upper hard mask layer 434 and a first upper hard mask layer 432. The second upper hard mask layer 434 can be formed on the upper etching stop film 690, and the first upper hard mask layer 432 can be formed on the second upper hard mask layer 434. Figures 14A through 15C Figures 5A through 7C In a similar manner as described with reference to FIG. 5A, a portion of the upper hard mask layer 430 can be removed, wherein the second upper hard mask layer 434 of the upper hard mask layer 430 can be removed, and a portion of the first upper hard mask layer 432 of the upper hard mask layer 430 can be retained. At this time, a portion of the upper etching stop film 690 exposed at a bottom of the upper recess split region 430S can also be removed to form a third etching opening 690O1 exposing the upper wiring insulating layer 650.

[0105] Thereafter, a portion of the upper etching stop film 690 can then be removed using the first upper hard mask layer 432 as an etching mask to form a fourth etching opening 690O2 exposing the upper wiring insulating layer 650. In the process of forming the fourth etching opening 690O2, a portion of the upper wiring insulating layer 650 exposed under the third etching opening 690O1 can be removed. At this time, a remaining portion of the first upper hard mask layer 432 can also be removed. The third etching opening 690O1 and the fourth etching opening 690O2 can together constitute an upper etching opening 690O.

[0106] A portion of the upper wiring insulating layer 650 can be removed using the upper etching stop film 690 having the upper etching opening 690O as an etching mask to form an upper wiring recess 650R. The upper wiring recess 650R can include a first upper wiring recess 650R1 and a second upper wiring recess 650R2.

[0107] Since a portion of the upper wiring insulating layer 650 under the third etching opening 690O1 has been removed before forming the upper wiring recess 650R, a depth of the first upper wiring recess 650R1, which can be a portion of the upper wiring recess 650R and can be formed under the third etching opening 690O1, can be greater than a depth of the second upper wiring recess 650R2, which can be a portion of the upper wiring recess 650R and can be formed under the fourth etching opening 690O2.

[0108] ​The first upper wiring recess 650R1 can extend from the upper surface of the upper wiring insulating layer 650 to the lower surface of the upper wiring insulating layer 650 so that the reference wiring structure 300 can be exposed through / via the bottom level of the first upper wiring recess 650R1. The second upper wiring recess 650R2 can extend downward from the upper surface of the upper wiring insulating layer 650, and the bottom level of the second upper wiring recess 650R2 can be lower than the level of the upper surface of the upper wiring insulating layer 650 and higher than the level of the lower surface of the upper wiring insulating layer 650 so that a portion of the upper wiring insulating layer 650 can be maintained in an exposed state at the bottom level of the second upper wiring recess 650R2.

[0109] Figures 16A through 16C are plan and sectional views shown to explain a method of manufacturing an integrated circuit device according to an exemplary embodiment of the inventive concept. Specifically, Figure 16B and Figure 16C are sectional views taken along lines B-B' and C-C' in Figure 16A In Figures 16A through 16C the same reference numerals denote the same components as in Figures 1A through 15C and repetitive detailed explanations thereof can be omitted herein.

[0110] Referring to Figures 16A through 16C together with Figures 8A through 10C , the upper wiring structure 600 can be formed to form the integrated circuit device la using a method similar to the method of forming the reference wiring structure 300 explained with reference to

[0111] Specifically, after the upper barrier layer 630 covering the exposed surface of the upper etching stop film 690 and the upper wiring insulating layer 650 having the upper wiring recess 650R as shown in Figures 11A through 15C can be formed, the upper wiring material layer can be formed on the upper barrier layer 630. The upper barrier layer 630 can be conformally formed on the exposed surface of the upper etching stop film 690 and the upper wiring insulating layer 650 having the upper wiring recess 650R. The upper wiring material layer can be formed to fill the upper wiring recess 650R and be located on (e.g., cover) the upper surface of the upper etching stop film 690.

[0112] The upper barrier layer 630 can include a nitride or an oxide of a metal such as Ti, Ta, Ru, Mn, Co, or W, or can include an alloy such as CoWP, CoWB, CoWBP, etc. The upper wiring material layer can include a metal material such as W, Cu, Ti, Ta, Ru, Mn, or Co, etc.

[0113] Thereafter, a portion of the upper wiring material layer on (e.g., covering) the upper surface of the upper etching stop film 690 can be removed to form the upper wiring layer 610 and the upper via plug 620. The upper wiring layer 610 can refer to a portion of the remaining portion of the upper wiring material layer at a level higher than the bottom level of the second upper wiring recess 650R2, and the upper via plug 620 can refer to a portion of the remaining portion of the upper wiring material layer at a level lower than the bottom of the second upper wiring recess 650R2 and connected to the upper wiring layer 610. Thus, the upper wiring layer 610 can have a substantially constant height and width and can extend in the first horizontal direction (X direction), and the upper via plug 620 can have a substantially constant horizontal area below the upper wiring layer 610 or can extend in the vertical direction (Z direction) toward the semiconductor substrate 110 while the horizontal area continuously decreases or increases.

[0114] In the process of forming the upper wiring layer 610 and the upper via plug 620, a portion of the upper barrier layer 630 covering the upper surface of the upper etching stop film 690 and the upper etching stop film 690 can be removed together so that the upper surface of the upper wiring insulating layer 650 can be exposed.

[0115] To form the upper wiring layer 610 and the upper via plug 620, the process of removing a portion of the upper wiring material layer can be performed by a CMP method. In the process of forming the upper wiring layer 610 and the upper via plug 620, the upper etching stop film 690 can be completely removed.

[0116] The integrated circuit device 1a can include a device layer 120 including a plurality of semiconductor devices 150, a lower wiring structure 200, a reference wiring structure 300, and an upper wiring structure 600. The lower wiring structure 200 can be electrically connected to each semiconductor device 150 so that the lower wiring structure 200 can provide electrical connections between the plurality of semiconductor devices 150 and between the plurality of semiconductor devices 150 and the reference wiring structure 300. The reference wiring structure 300 can provide electrical connections between the lower wiring structure 200 and the upper wiring structure 600.

[0117] The upper wiring structure 600 can include an upper wiring layer 610 and an upper via plug 620 connected to the upper wiring layer 610. An upper wiring insulating layer 650 can fill a space between the upper wiring layer 610 and the upper via plug 620. In some embodiments, the upper wiring layer 610 and the upper via plug 620 in contact with each other can be integrally formed.

[0118] The upper wiring layer 610 can be formed in a plurality of line shapes extending in the first horizontal direction (X direction) parallel to each other. The upper via plug 620 can extend from a bottom surface of the upper wiring layer 610 toward the semiconductor substrate 110 to be electrically connected to the reference wiring structure 300.

[0119] The upper wiring structure 600 can further include an upper barrier layer 630 surrounding bottom and side surfaces of the upper wiring layer 610 and the upper via plug 620. The upper barrier layer 630 can be disposed between (a) the upper wiring layer 610 and the upper via plug 620 and (b) the upper wiring insulating layer 650. In some embodiments, the upper wiring structure 600 can further include a lower cap layer 640 on (e.g., covering an upper surface of) the upper wiring layer 610.

[0120] Figures 11A through 15C All of the upper etch stop films 690 shown can be removed and thus can not be retained on the upper wiring insulating layer 650 and the upper wiring structure 600.

[0121] Referring to FIGS. 1A and 1B together Figures 11A through 15C The reference via plug 620 included in the integrated circuit device 1a according to the inventive concept can be a FAV. The upper via plug 620 can be formed in a portion of the upper wiring insulating layer 650 corresponding to a portion in which the third opening MO3 of the third mask layer MK3 and the fourth opening MO4 of the fourth mask layer MK4 overlap (i.e., a portion in which the third mask merge area MS3 and the fourth mask merge area MS4 overlap).

[0122] In particular, the upper via plug 620 can be aligned in width in the second horizontal direction (Y direction) of each of the third opening MO3 and the fourth opening MO4, and thus the width of the upper via plug 620 in the second horizontal direction (Y direction) can be determined / controlled, and can also be aligned in width in the first horizontal direction (X direction) of the portion in which the third opening MO3 and the fourth opening MO4 overlap each other (i.e., the portion in which the third mask merge area MS3 and the fourth mask merge area MS4 overlap each other), and thus the width of the upper via plug 620 in the first horizontal direction (X direction) can be determined / controlled.

[0123] Thus, since the width in the first horizontal direction (X direction) and the second horizontal direction (Y direction) perpendicular to each other can be limited, the electrical reliability of the integrated circuit device 1a having the reference via plug 620 can be improved.

[0124] Figures 16A through 16CIt is shown that the lower via plug 220 is SAV, and the reference via plug 320 and the upper via plug 620 are FAV, but not limited thereto. For example, when the integrated circuit device has a multi-layer wiring structure, all of the via plugs of each of the wiring structures can be FAV. Alternatively, for example, when the integrated circuit device has a multi-layer wiring structure, the via plugs of at least one wiring structure on the upper side can be SAV, and at least one wiring structure on the lower side can be FAV.

[0125] While the present inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details can be made therein without departing from the scope of the claims above.

Claims

1. A method of manufacturing an integrated circuit device, the method comprising: forming, in sequence, a device layer, a wiring insulating layer, and a hard mask layer on a semiconductor substrate, the device layer including a plurality of semiconductor devices; sequentially removing a first region and a second region of the hard mask layer using a first mask layer having a first opening extending in a first horizontal direction and a second mask layer having a second opening extending in the first horizontal direction as etching masks, respectively, wherein a portion of the second opening overlaps a split region including a first portion of the wiring insulating layer in a vertical direction and overlaps a portion of the first opening in the vertical direction; forming a first wiring groove and a second wiring groove by removing the first portion of the wiring insulating layer using a third region of the hard mask layer remaining after the first region and the second region of the hard mask layer are removed as an etching mask, the first wiring groove passing through the wiring insulating layer, the second wiring groove having a depth smaller than a depth of the first wiring groove; and forming a wiring structure in the first wiring groove and the second wiring groove and electrically connected to the plurality of semiconductor devices, wherein the second wiring groove is formed in: a second portion of the wiring insulating layer other than the split region and overlapping the first opening in the vertical direction; and a third portion of the wiring insulating layer other than the split region and overlapping the second opening in the vertical direction.

2. The method of manufacturing an integrated circuit device according to claim 1, wherein the first opening includes a first cut opening and a first extension opening, and the second opening includes a second cut opening and a second extension opening, and wherein the first mask layer and the second mask layer are formed so that each of a portion of the first cut opening adjacent to one end portion of the first cut opening and a portion of the second cut opening adjacent to one end portion of the second cut opening overlaps the split region in the vertical direction.

3. The method of manufacturing an integrated circuit device according to claim 2, wherein the first mask layer and the second mask layer are formed so that a center line of each of the first cut opening and the second cut opening lies on a same line on the wiring insulating layer in the first horizontal direction.

4. The method of manufacturing an integrated circuit device according to claim 3, wherein a width of each of the first cut opening and the second cut opening in a second horizontal direction perpendicular to the first horizontal direction has a same value.

5. The method of manufacturing an integrated circuit device according to claim 2, wherein the first mask layer and the second mask layer are formed so that the first extension opening and the second extension opening overlap different portions of the wiring insulating layer, respectively.

6. The method of manufacturing an integrated circuit device according to claim 1, wherein the first wiring groove is formed in the split region of the wiring insulating layer.

7. The method of manufacturing an integrated circuit device according to claim 1, ​ wherein the hard mask layer includes a first hard mask layer and a second hard mask layer stacked on the first hard mask layer, wherein the split region further includes a portion of the first hard mask layer and a first portion of the second hard mask layer overlapping the first portion of the wiring insulating layer in the vertical direction, and wherein sequentially removing the first region and the second region of the hard mask layer includes: removing the first portion of the second hard mask layer using the first mask layer as an etching mask; and removing a second portion of the second hard mask layer and the portion of the first hard mask layer using the second mask layer as an etching mask.

8. The method of manufacturing an integrated circuit device according to claim 7, further comprising: forming an etching stop film between the wiring insulating layer and the hard mask layer, wherein the split region further includes a portion of the etching stop film overlapping the first portion of the wiring insulating layer in the vertical direction; and removing the portion of the etching stop film after sequentially removing the first region and the second region of the hard mask layer.

9. The method of manufacturing an integrated circuit device according to claim 8, wherein each of the first hard mask layer, the second hard mask layer, and the etching stop film includes a different one of a metal nitride material, an oxynitride material, and a carbon-containing material.

10. A method of manufacturing an integrated circuit device, the method comprising: forming, on a semiconductor substrate including a portion in a split region of an integrated circuit device, in sequence, a device layer including a plurality of semiconductor devices, a wiring insulating layer, an etching stop film, and a hard mask layer; forming a first recess in the hard mask layer by removing a first region of the hard mask layer using a first mask layer having a first opening as an etching mask, the first opening having a portion located in the split region and extending in a first horizontal direction; forming a second recess by removing a second region of the hard mask layer using a second mask layer having a second opening as an etching mask, the second opening having a portion located in the split region and extending in the first horizontal direction; removing a first portion of the etching stop film located in the split region; removing a third region of the hard mask layer and a second portion of the etching stop film via the first recess, removing a fourth region of the hard mask layer and a third portion of the etching stop film via the second recess, and removing a portion of an upper first portion of the wiring insulating layer located in the split region; and forming a first wiring recess through the wiring insulating layer in the split region and forming a second wiring recess having a smaller depth than a depth of the first wiring recess by removing a second portion of the wiring insulating layer using a fifth region of the hard mask layer remaining after removing the third region and the fourth region of the hard mask layer as an etching mask.

11. The method of manufacturing an integrated circuit device according to claim 10, further comprising: forming a wiring material layer in the first wiring recess and the second wiring recess and on the etching stop film and the wiring insulating layer; and forming a wiring structure in the first wiring recess and the second wiring recess by removing any remaining portion of the etching stop film and a portion of the wiring material layer on the wiring insulating layer, the wiring structure being electrically connected to the plurality of semiconductor devices, wherein the first width of the wiring structure in the first horizontal direction and the second width of the wiring structure in a second horizontal direction perpendicular to the first horizontal direction are controlled by forming the first recess using the first mask layer having the first opening and forming the second recess using the second mask layer having the second opening.

12. The method of manufacturing an integrated circuit device according to claim 11, Also included are: forming an upper wiring insulating layer on the wiring insulating layer and the wiring structure.

13. The method of manufacturing an integrated circuit device according to claim 12, wherein the upper wiring insulating layer is formed such that a lower surface of the upper wiring insulating layer contacts an upper surface of the wiring insulating layer.

14. The method of manufacturing an integrated circuit device according to claim 10, wherein the hard mask layer includes a first hard mask layer and a second hard mask layer stacked on the first hard mask layer, and wherein the first recess is formed by removing the first region of the second hard mask layer using the first mask layer as an etching mask, and wherein the second recess is formed by removing the second region of the second hard mask layer and a portion of the first hard mask layer in the split region using the second mask layer as an etching mask.

15. The method of manufacturing an integrated circuit device according to claim 14, wherein the second recess is formed such that the first portion of the etching stop film in the split region is exposed by the second recess.

16. A method of manufacturing an integrated circuit device, the method comprising: sequentially forming a semiconductor substrate having a split region, a wiring insulating layer, an etching stop film, a first hard mask layer, and a second hard mask layer; forming a first recess by removing a first region of the second hard mask layer using a first mask layer having a first opening as an etching mask, the first opening extending in a first horizontal direction and having a portion in the split region; forming a second recess by removing a second region of the second hard mask layer and a first portion of the first hard mask layer in the split region using a second mask layer having a second opening as an etching mask, the second opening extending in the first horizontal direction and having a first portion and a second portion different from the first portion in the split region; removing a first portion of the etching stop film in the split region; removing a second portion of the first hard mask layer and a second portion of the etch stop film via the first recess, removing a third portion of the first hard mask layer and a third portion of the etch stop film via the second recess, and removing a portion of the upper first portion of the wiring insulating layer in the split region; and forming first and second wiring recesses by removing a second portion of the wiring insulating layer using a fourth portion of the first hard mask layer as an etch mask, the first wiring recess passing through the wiring insulating layer, the second wiring recess having a depth less than a depth of the first wiring recess, wherein the first wiring recess is formed in the split region.

17. The method of fabricating an integrated circuit device of claim 16, wherein the first hard mask layer comprises a metal nitride material and the etch stop film comprises a carbon-containing material.

18. The method of fabricating an integrated circuit device of claim 16, further comprising: forming a wiring structure in the first and second wiring recesses; and forming an upper wiring insulating layer on the wiring insulating layer and the wiring structure, the upper wiring insulating layer having a lower surface in contact with an upper surface of the wiring insulating layer.

19. The method of fabricating an integrated circuit device of claim 18, wherein forming the wiring structure includes removing any remaining portions of the etch stop film on the wiring insulating layer.

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