Capacitor layout structure

Abstract

The present invention discloses a capacitor layout structure, comprising: a substrate; an isolation region provided on the substrate for isolating noise from the substrate; a capacitor unit provided on a side of the isolation region away from the substrate; and a doped region provided on the substrate and disposed around the isolation region. An embodiment of the present invention provides a capacitor layout structure with high anti-noise interference performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and particularly to a capacitor layout structure. Background Art

[0002] A capacitor is a component widely used at present. In a traditional capacitor layout structure, a doped layer is generally provided on a substrate. The doped layer has charged carriers. Due to the interaction between the carriers in the doped layer and the charges on the capacitor plates, noise from the substrate and the outside can still be coupled to the metal plate at the bottom layer of the capacitor through the doped layer, thereby affecting the performance of the capacitor. Summary of the Invention

[0003] The object of the present invention is to improve the anti-noise interference ability of the capacitor without increasing the manufacturing cost, which is achieved through the following technical solutions:

[0004] An embodiment of the present invention provides a capacitor layout structure, including: a substrate; an isolation region provided on the substrate for isolating the influence of external noise on the capacitor unit; a capacitor unit provided on a side of the isolation region away from the substrate; a doped region provided on the substrate and surrounding the isolation region.

[0005] In another embodiment, based on the foregoing solution, the capacitor unit includes a plurality of capacitors; the capacitor layout structure includes a plurality of metal layers stacked, and an insulating medium is provided between the layers or side walls of the plurality of metal layers, so that a plurality of capacitors are formed between the layers of the connected metal layers or between adjacent side walls.

[0006] In another embodiment, based on the foregoing solution, the capacitor includes a MOM capacitor, the plurality of metal layers include a metal layer 0 to a metal layer N, N is a positive integer, the metal layer 0 is provided close to the isolation region, and a bias voltage is loaded on any layer between the metal layer 0 and the metal layer N.

[0007] In another embodiment, based on the foregoing solution, the MOM capacitor has a plurality of metal layers, and each metal layer has finger-shaped electrodes arranged oppositely, and the oppositely arranged finger-shaped electrodes are arranged staggered.

[0008] In another embodiment, based on the foregoing solution, a plurality of capacitor units are provided on a side of the isolation region away from the substrate, and the plurality of capacitor units are arranged in an array.

[0009] In another embodiment, based on the foregoing solution, the doped region includes an N-type semiconductor region and a P-type semiconductor region adjacent to the side wall of the N-type semiconductor region, and the N-type semiconductor region and the P-type semiconductor region surround the isolation region to isolate external noise.

[0010] In another embodiment, based on the foregoing solution, the N-type semiconductor region is disposed on the outer circle of the P-type semiconductor region; or the P-type semiconductor region is disposed on the outer circle of the N-type semiconductor region.

[0011] In another embodiment, based on the foregoing solution, the N-type semiconductor region is provided with a first connection potential region, and the P-type semiconductor region is provided with a second connection potential region. The first connection potential region is used to connect to a power supply, and the second connection potential region is used to ground.

[0012] In another embodiment, based on the foregoing solution, the material of the isolation region includes silicon dioxide.

[0013] An embodiment of the present invention further provides an analog-to-digital converter, and the analog-to-digital converter has the capacitance layout structure as described above.

[0014] Compared with the prior art, the technical solution provided by the embodiment of the present invention has at least the following advantages:

[0015] In the capacitance layout structure of the present invention, an isolation region is provided between the capacitance unit and the substrate, and a doped region is disposed around the isolation region. Through the mutual cooperation of the isolation region and the doped region in terms of structure, the interference of external noise to the capacitance unit can be reduced. Furthermore, on the basis of not affecting the capacitance performance, the integration degree can be improved, thereby reducing the production cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] For ease of explanation, the present invention is described in detail by the following preferred embodiments and the accompanying drawings. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained according to these drawings without creative efforts.

[0017] Figure 1 is a cross-sectional view of the capacitance layout structure in the related art of the present invention;

[0018] Figure 2 is a front view of a capacitance layout structure provided by an embodiment of the present invention;

[0019] Figure 3 is a sectional view of a capacitance layout structure provided by an embodiment of the present invention;

[0020] Figure 4 is a structural schematic diagram of another capacitance layout structure provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0021] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0022] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present invention. In the description of the present invention, it should be noted that unless otherwise clearly specified and defined, the terms "mounted", "connected", "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection. It can be a mechanical connection or an electrical connection. It can be directly connected or indirectly connected through an intermediate medium, and can be the communication inside two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0023] First of all, it should be noted that a wafer is the basic raw material for manufacturing semiconductor devices. Ultra-high purity semiconductors are prepared into wafers through processes such as crystal pulling and slicing. The wafers are formed into extremely tiny circuit structures through a series of semiconductor manufacturing processes, and then through cutting, packaging, and testing to become chips, which are thus widely used in various electronic devices. The conductivity of a semiconductor is between that of a conductor and an insulator, and it has characteristics such as thermosensitivity, doping property, and photosensitivity. The internal free electron and hole concentrations of a pure semiconductor without impurities and defects are equal, which is called an intrinsic semiconductor. If an external electric field is applied across the two ends of an intrinsic semiconductor, there will be two parts of current in the semiconductor. One is that free electrons will move directionally to form an electron current, and the other is that due to the existence of holes, valence electrons will fill the holes in a certain direction in turn, which is equivalent to the holes also having a directional flow to form a hole current. That is to say, there are two types of charge carriers, electrons and holes, that carry charges in the semiconductor at the same time.

[0024] Doping in semiconductors refers to the property that the conductivity of a semiconductor is significantly enhanced by adding impurities to a pure semiconductor material. The doping process increases the number of carriers (electrons or holes), thereby enhancing conductivity and reducing resistance. Specifically, if a trace amount of pentavalent element, such as phosphorus, is doped into an intrinsic semiconductor, the phosphorus atoms form covalent bond structures with silicon atoms, requiring only four valence electrons. However, the outermost layer of phosphorus atoms has five valence electrons, and the extra one valence electron is not bound by the covalent bond. Under conditions such as thermal resonance, it can become a free electron with very little energy. Free electrons carry negative charges. After doping a trace amount of pentavalent element into an intrinsic semiconductor, free electrons become the majority carriers, and holes are the minority carriers. An intrinsic semiconductor doped with impurities with free electrons as the main conduction mode is called an N-type semiconductor. If a trace amount of trivalent element, such as boron, is doped into an intrinsic semiconductor, when the boron atoms form covalent bonds with the surrounding silicon atoms, a hole will be generated in the crystal due to the lack of one electron. It is easy to understand that the amount of generated holes is related to the amount of doped trivalent element. This semiconductor doped with impurities with holes as the main conduction mode is called a P-type semiconductor.

[0025] When different atoms are doped in different regions on a crystal, an N-type semiconductor region and a P-type semiconductor region can be formed. If the N-type semiconductor region and the P-type semiconductor region are adjacent to each other, due to the repulsion of like charges and the attraction of opposite charges, a space charge region will be formed near the adjacent surface of the N-type semiconductor region and the P-type semiconductor region. This space charge region is the PN junction. If an external voltage is applied across the PN junction, the original balance of the PN junction will be disrupted. Specifically, when a forward voltage is applied, that is, the P-type semiconductor region is connected to the positive pole of the power supply, and the N-type semiconductor region is connected to the negative pole of the power supply or grounded. Since the direction of the external electric field is opposite to the direction of the internal electric field, the internal electric field is weakened, the space charge region becomes narrower, which is conducive to the diffusion movement of the majority carriers, forming a large forward current. Therefore, when a forward voltage is applied, the PN junction has a low resistance and is in a conducting state. If a reverse voltage is applied, the result is the opposite, which will cause the space charge region to become wider, the PN junction has a high resistance and is in a cut-off state.

[0026] It should also be noted that a capacitor consists of two conductor metal plates that are insulated from each other and parallel and close to each other. The two conductor metal plates are called electrodes, and the material of the electrodes can be aluminum. A capacitor is used to store electric charge and electric potential energy. Specifically, there are two types of charges in a conductor, protons and electrons. Among them, the negatively charged electrons can move freely. When one electrode of the capacitor is connected to the positive pole of the power supply and the other electrode is connected to the negative pole of the power supply, under the action of the power supply voltage, the electrons will move along the direction opposite to the electric field. Since the insulating medium between the two conductors prevents the movement of electrons, the electrons will deposit on the electrode connected to the negative pole of the power supply, thus achieving the effect of storing electric charge, that is, storing electric potential energy.

[0027] Figure 1This is a cross-sectional view of a capacitor layout structure in the related art of the present invention. Figure 1 As shown, a capacitor layout structure in the related art of the present invention includes a wafer 101, a doped region 102, and a capacitor 103. Among them, the doped region 102 is generally an N-type semiconductor region doped with a trace amount of pentavalent elements, or a P-type semiconductor region doped with a trivalent element. The bottom metal plate of the capacitor 103 is arranged near the doped region 102. Since the N-type semiconductor region has negatively charged carriers and the P-type semiconductor region has positively charged carriers, when the capacitor is energized, the metal plate of the capacitor will store charges. Since charges have the characteristics of like charges repelling and opposite charges attracting, the charged carriers on the N-type semiconductor region or the P-type semiconductor region will interact with the positively charged protons or negatively charged electrons on the bottom metal plate of the capacitor 103, thereby causing noise interference to the capacitor. In addition, since the circuit packaged on the wafer 101 has many other components in addition to the capacitor 103, when other components in the circuit are working, the noise generated by them, such as pulses, may also propagate on the doped region 102, thereby affecting the capacitor 103. Therefore, since the related technology of the present invention uses an N-type semiconductor region or a P-type semiconductor region as an isolation layer to isolate the wafer 101 and the capacitor 103, external noise will still be coupled to the metal layer of the capacitor 103 through the N-type semiconductor region or the P-type semiconductor region, causing the capacitor 103 to be interfered with, thereby affecting the performance of the capacitor.

[0028] Figure 2 : is a front view of a capacitor layout structure provided by an embodiment of the present invention. Figure 2 As shown, the capacitor layout structure provided by the embodiment of the present invention includes at least a substrate, an isolation region 140, a doped region 120, and a capacitor unit 130. The isolation region 140 for isolating the capacitor unit 130 from the substrate is provided on the substrate, the capacitor unit 130 is provided on the side of the isolation region 140 facing away from the substrate, and the doped region 120 is provided on the substrate and surrounds the isolation region. Through the structural interaction between the doped region 120 and the isolation region 140 and the characteristics of the doped region and the isolation region themselves that can isolate noise interference, the purpose of isolating noise from the outside is achieved.

[0029] Specifically, the substrate is a wafer made of a semiconductor single crystal material, which can be silicon. An oxide layer is formed on the surface of the silicon through oxidation, serving as an isolation region 140 that isolates the capacitor unit 130 from the substrate. Isolation region 140 can be made of silicon dioxide. Isolation region 140 is provided on the substrate. Because the substrate has essentially no electrons or holes, its resistance is very high, effectively insulating. Therefore, the substrate and isolation region themselves have minimal impact on capacitor noise.

[0030] The doped region 120 is disposed on the substrate and is disposed around the isolation region 140. Specifically, the shape of the doped region may be an annular cuboid, or may be set according to the specific shape of the isolation region. The noise from the outside will first pass through the doped region 120. After being buffered by the doped region 120, a small amount of remaining noise reaches the substrate. Since the resistance of the substrate is very large, it can further filter the noise interference, so as to achieve the purpose of isolating the noise from the outside through the mutual cooperation of the structures of the doped region 120 and the isolation region 140 and the characteristics that the doped region and the isolation region can isolate the noise interference by themselves.

[0031] In one embodiment, the doped region 120 may be a separate P-type semiconductor region, or a separate N-type semiconductor region, or a P-type semiconductor region and an N-type semiconductor region with adjacent sidewalls. Thus, compared with the capacitance layout structure in the related art of the present application described above, the position of the capacitance unit 130 in the capacitance layout structure of the present invention is relatively far from the position of the doped region, and thus is relatively less affected by the charges in the doped region 120. Therefore, the anti-noise interference performance of the capacitance unit 130 can be improved, and thus the integration degree can be enhanced and the production cost can be reduced.

[0032] Figure 3 is a cross-sectional view of a capacitance layout structure provided by an embodiment of the present invention. As Figure 3 shown, the capacitance layout result provided by the embodiment of the present invention includes a substrate 110, a P-type semiconductor region 122, an N-type semiconductor region 121, a first connection potential region 124, a second connection potential region 123, an isolation region 140, and a capacitance unit 130. In this embodiment, the doped region includes an annular P-type semiconductor region 122 and an N-type semiconductor region 121 with adjacent sidewalls, and an annular first connection potential region 124 disposed on the N-type semiconductor region and an annular second connection potential region 123 disposed on the P-type semiconductor region 122. The N-type semiconductor region may be located on the outer ring of the P-type semiconductor region. In another embodiment, the N-type semiconductor region may also be located on the inner ring of the P-type semiconductor region. As described above, the adjacent sidewalls of the P-type semiconductor region 122 and the N-type semiconductor region 121 will form a space charge region, that is, a PN junction. Connecting the first connection potential region 124 to the power supply and grounding the second connection potential region 123 can widen the space charge region, and the PN junction is in a high-resistance and cut-off state. Thus, a protection ring is formed through the doped region and the connection potential region on the doped region, thereby isolating the interference of external noise to the capacitance unit and improving the anti-interference performance of the capacitance unit.

[0033] In one embodiment, the capacitor unit 130 may include multiple MOM capacitors. Specifically, in this embodiment, the capacitor layout structure includes at least two metal layers arranged in a stacked manner. Two electrodes of the capacitor are fabricated within the same metal layer, and each electrode extends into several finger-shaped plates. The finger-shaped plates of the two electrodes are parallel to each other and placed in an interleaved form. Multiple MOM capacitors are formed with the interlayer dielectric of the current layer as the insulating layer between these interleaved finger-shaped plates. To increase the capacitance, in another embodiment, the same structure may also be fabricated in the upper metal layer or the lower metal layer of the current MOM capacitor to form a stacked structure. The electrodes on both sides of two adjacent metal layers may be the same or opposite. By stacking multiple layers of MOM capacitors, a larger capacitance value can be achieved. Each metal layer is connected in parallel or in series through metal plates, without the need to increase additional lithography levels, which is beneficial to reducing the manufacturing cost.

[0034] In one embodiment, based on the foregoing structure, the stacked multiple-layer MOM capacitors have metal layers from layer 0 to layer N, where N is a positive integer. Among them, layer 0 of the metal is disposed close to the isolation region. To achieve the performance of anti-noise interference through the multiple-layer MOM capacitors, preferably, a bias voltage is applied to any layer between layer 0 of the metal and layer N of the metal. That is to say, the bottommost layer and the topmost layer of the metal layers are not used. Thus, the distance between the metal layer of the actually used capacitor and the isolation layer and the doping layer is increased, thereby reducing the influence of noise from the doping layer or the outside on the capacitor unit.

[0035] In another embodiment, the capacitor unit may further include multiple MIM capacitors (Metal-Insulator-Metal Capacitor). The MIM capacitor may also have at least two metal layers, and an insulating medium is provided between adjacent metal layers to form multiple MIM capacitors through the interlayer insulating medium between adjacent metal layers.

[0036] Figure 4 is a schematic structural diagram of another capacitor layout structure provided by an embodiment of the present invention. As Figure 4 shown, in this embodiment, it includes an N-type semiconductor region 121, a P-type semiconductor region 122, a first potential connection region 124, a second potential connection region 123, an isolation region 140, and several capacitor units 130. To improve the anti-noise interference performance of the capacitor unit with a relatively large capacitance value, several capacitor units connected in parallel may be provided on the isolation region. The several capacitor units may be arranged in an array. The capacitor unit 130 may include multiple MOM capacitors or may include multiple MIM capacitors. The several capacitor units are connected in parallel through metal wires, and the equivalent capacitance after parallel connection is equal to the sum of the capacitance values of each capacitor unit 130. Thus, by arranging a capacitor unit array on the isolation region, the capacitance value can be increased, the integration degree can be improved, and the noise can be isolated.

[0037] Embodiments of the present invention further provide an analog-to-digital converter. The capacitors in the analog-to-digital converter have the capacitor layout structure as described above. The analog-to-digital converter, i.e., the A / D converter, or simply ADC for short, generally refers to an electronic component that converts an analog signal into a digital signal, and the capacitors thereon have the capacitor layout structure as described above.

[0038] In the description of this specification, the description referring to the term "one embodiment" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above term does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0039] The above are only the preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A capacitor layout structure, characterized in that, include: substrate; An isolation region is provided on the substrate, and is used to isolate the capacitor unit from the influence of external noise; The capacitor unit is provided on a side of the isolation region facing away from the substrate; a doped region, the doped region being provided on the substrate and being arranged around the isolation region; the doped region comprising an N-type semiconductor region and a P-type semiconductor region adjacent to a sidewall of the N-type semiconductor region, the N-type semiconductor region and the P-type semiconductor region being arranged around the isolation region to isolate noise from the outside; a first potential connection region being provided on the N-type semiconductor region, a second potential connection region being provided on the P-type semiconductor region, the first potential connection region being connected to a power supply, the second potential connection region being grounded, and both the first potential connection region and the second potential connection region being arranged around the isolation region; The capacitor unit includes a plurality of capacitors; the capacitor layout structure includes a plurality of stacked metal layers, and an insulating medium is provided between the layers or sidewalls of the plurality of metal layers, so that a plurality of capacitors are formed between the layers of the connected metal layers or between adjacent sidewalls; The capacitor includes a MOM (Metal-Oxide-Metal) capacitor, and the multiple metal layers include the 0th metal layer to the Nth metal layer, N is a positive integer, the 0th metal layer is arranged close to the isolation area, and any layer between the 0th metal layer to the Nth metal layer is used for bias voltage loading.

2. The capacitor layout structure according to claim 1, wherein The MOM capacitor has a plurality of metal layers, each of which has finger-shaped plates arranged opposite to each other, and the finger-shaped plates arranged opposite to each other are arranged in a staggered manner.

3. The capacitive layout structure according to claim 1, wherein A plurality of capacitor units are provided on a side of the isolation region facing away from the substrate, and the plurality of capacitor units are arranged in an array.

4. The capacitive layout structure according to claim 1, characterized in that The N-type semiconductor region is arranged on the outer circle of the P-type semiconductor region; or The P-type semiconductor region is arranged on the outer circle of the N-type semiconductor region.

5. The capacitor layout structure according to claim 1, characterized in that, The isolation region is made of silicon dioxide.

6. An analog-to-digital converter, characterized in that, The analog-to-digital converter has a capacitor layout structure according to any one of claims 1 to 5.

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