Semiconductor device and method for manufacturing the same

Abstract

The present invention relates to a semiconductor device and a manufacturing method thereof; the semiconductor device comprises: a first channel layer; a first barrier layer, which forms a first heterojunction between the first channel layer and the first barrier layer, and forms a vertical 2DEG or 2DHG in the first heterojunction; a first nucleation layer, which is configured to generate the first channel layer from a heterogeneous substrate, wherein the first channel layer is located above the first nucleation layer; a first electrode, which is in electrical contact with the 2DEG or 2DHG of the first heterojunction; and a second electrode, which is in electrical contact with the 2DEG or 2DHG of the first heterojunction. The conductive channel of the semiconductor device of the present invention is far away from the substrate, which can reduce the influence of the substrate on the withstand voltage of the semiconductor device and improve the performance of the device.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, in particular to a nitride semiconductor device. Background Art

[0002] Group III nitride semiconductors are important semiconductor materials, primarily including AlN, GaN, InN, and their compounds, such as AlGaN, InGaN, and AlInGaN. Due to their advantages such as direct bandgap, wide bandgap, and high breakdown electric field strength, Group III nitride semiconductors, represented by GaN, have broad application prospects in light-emitting devices, power electronics, and radio frequency devices.

[0003] Unlike traditional non-polar semiconductor materials like silicon, group III nitride semiconductors possess polarity, making them polar semiconductors. Polar semiconductors possess many unique properties. Most importantly, fixed polarization charges exist on the surface of polar semiconductors or at the interface between two different polar semiconductors. These fixed polarization charges attract mobile electron or hole carriers, forming a two-dimensional electron gas (2DEG) or a two-dimensional hole gas (2DHG). The generation of these two-dimensional electron gases (2DEG) or two-dimensional hole gases (2DHG) occurs spontaneously, without requiring an additional electric field or relying on doping within the semiconductor. The two-dimensional electron gas (2DEG) or two-dimensional hole gas (2DHG) at the interface between polar semiconductors can have a high surface charge density. Furthermore, since doping is not required, the two-dimensional electron gas or two-dimensional hole gas is significantly less susceptible to ion scattering, resulting in high mobility. These high surface charge density and mobility give these spontaneously generated two-dimensional electron or hole gases at these interfaces excellent conductivity and high response speed.

[0004] Combined with the inherent advantages of nitride semiconductors, such as their high breakdown electric field strength, this two-dimensional electron gas or hole gas can be used to fabricate high-mobility transistors, significantly outperforming traditional Si or GaAs devices in high-energy, high-voltage, or high-frequency applications. However, existing structures have numerous drawbacks that severely limit their application. Summary of the Invention

[0005] In response to the problems existing in the prior art, a semiconductor device is proposed, comprising: a first channel layer; a first barrier layer, which forms a first heterojunction between the first channel layer and the first barrier layer, and forms a vertical 2DEG or 2DHG within the first heterojunction; a first nucleation layer, which is configured to generate the first channel layer from a heterogeneous substrate, wherein the first channel layer is located above the first nucleation layer; a first electrode, which is in electrical contact with the 2DEG or 2DHG of the first heterojunction; and a second electrode, which is in electrical contact with the 2DEG or 2DHG of the first heterojunction.

[0006] In the semiconductor device as described above, the first electrode forms an ohmic contact with the first channel layer and / or the first barrier layer; and the second electrode forms a Schottky contact with the first channel layer and / or the first barrier layer.

[0007] The semiconductor device as described above further includes a third electrode configured to control current between the first electrode and the second electrode.

[0008] The semiconductor device as described above further includes: a shielding layer below the first channel layer and / or the first barrier layer.

[0009] The semiconductor device as described above further comprises: a heterogeneous substrate, wherein the first nucleation layer is formed on a vertical interface of the heterogeneous substrate.

[0010] The semiconductor device as described above further comprises: a separation layer covering the horizontal interface of the foreign substrate.

[0011] The semiconductor device as described above, wherein the first channel layer or the first barrier layer is defined by a trench above the first nucleation layer.

[0012] The semiconductor device as described above, wherein the second electrode passes through the third electrode layer and is electrically connected to the conductor interconnection layer.

[0013] The semiconductor device as described above, wherein the third electrode passes through the first electrode and is electrically connected to another conductor interconnection layer.

[0014] The semiconductor device as described above further includes: a second channel layer; a second barrier layer, which forms a second heterojunction between the second channel layer and the second barrier layer, and forms a vertical 2DEG or 2DHG within the second heterojunction; a second nucleation layer, which is configured to generate the second channel layer from a heterogeneous substrate, wherein the second channel layer is located above the second nucleation layer.

[0015] The semiconductor device as described above, wherein the second channel layer or the second barrier layer is defined by a trench above the second nucleation layer.

[0016] The semiconductor device as described above, wherein the first electrode is in electrical contact with the 2DEG or 2DHG of the first heterojunction and the second heterojunction; and the second electrode is in electrical contact with the 2DEG or 2DHG of the first heterojunction and the second heterojunction.

[0017] According to another aspect of the present invention, a semiconductor device is proposed, comprising: a first nucleation layer, comprising an upper surface; a first channel layer, grown from the upper surface of the first nucleation layer; a first barrier layer, forming a first heterojunction between the first channel layer and the first barrier layer, and forming a vertical 2DEG or 2DHG within the first heterojunction; a first electrode, electrically contacting the 2DEG or 2DHG of the first heterojunction; and a second electrode, electrically contacting the 2DEG or 2DHG of the first heterojunction.

[0018] The semiconductor device as described above further includes a third electrode configured to control current between the first electrode and the second electrode.

[0019] The semiconductor device as described above, wherein the first nucleation layer grows from a vertical surface of the foreign substrate.

[0020] According to another aspect of the present invention, a semiconductor device is proposed, comprising: a first layer, comprising a first nucleation layer; a second layer, comprising a first channel layer and a first barrier layer, wherein a first heterojunction is formed between the first channel layer and the first barrier layer, and a vertical 2DEG or 2DHG is formed within the first heterojunction, wherein the second layer is above the first layer; a third layer, comprising a plurality of conductor interconnect layers, wherein the third layer is above the second layer; a first electrode, which is at least partially in the second layer and is configured to be in electrical contact with the 2DEG or 2DHG of the first heterojunction; and a second electrode, which is at least partially in the second layer and is configured to be in electrical contact with the 2DEG or 2DHG of the first heterojunction; wherein the first electrode is electrically connected to the first conductor layer in the third layer; and the second electrode is electrically connected to the second conductor layer in the third layer.

[0021] The semiconductor device as described above further comprises a third electrode configured to control current between the first electrode and the second electrode; wherein the third electrode is electrically connected to a third conductor layer in the third layer.

[0022] The semiconductor device as described above, wherein the first layer includes a foreign substrate or a substitute thereof.

[0023] According to another aspect of the present invention, a semiconductor device is proposed, comprising: a trench formed in an insulating material; a first channel layer located in the trench; a first barrier layer located on one side of the first channel layer, a first heterojunction formed between the first barrier layer and the first channel layer, the first heterojunction comprising a vertical 2DEG or 2DHG; a first electrode electrically contacting the 2DEG or 2DHG of the first heterojunction; a second electrode electrically contacting the 2DEG or 2DHG of the first heterojunction; and a third electrode located between the first electrode and the second electrode and configured to control the current intensity between the first electrode and the second electrode.

[0024] The semiconductor device as described above further includes a substrate, wherein the trench is formed above the substrate.

[0025] According to another aspect of the present invention, a method for manufacturing a semiconductor device is proposed, comprising: forming a first trench on a substrate; forming a first nucleation layer in the first trench; forming a first shielding layer, wherein the height of the first shielding layer is higher than that of the first nucleation layer; forming a second trench on the shielding layer, the second trench exposing the first nucleation layer, wherein the bottom surface of the second trench is higher than that of the first trench; epitaxially growing a first channel layer from the first nucleation layer in the second trench; and epitaxially growing a first barrier layer on the side of the first channel layer, wherein a first heterojunction is formed between the first barrier layer and the first channel layer, and the first heterojunction includes a vertical 2DEG or 2DHG.

[0026] The method as described above further includes: forming a first separation layer at the bottom of the first trench.

[0027] The method as described above further includes: forming a first nucleation layer in the first trench while forming a second nucleation layer in the first trench; forming another second trench exposing the second nucleation layer; epitaxially growing a first channel layer from the nucleation layer in the second trench while epitaxially growing a second channel layer from the second nucleation layer in the other second trench; and epitaxially growing a second barrier layer on the side of the second channel layer, wherein a second heterojunction is formed between the second barrier layer and the second channel layer, and the second heterojunction includes a vertical 2DEG or 2DHG.

[0028] The method as described above further includes: forming a second electrode and a third electrode between the first barrier layer and the second barrier layer, wherein an insulating material is provided between the second electrode and the third electrode.

[0029] The method as described above further includes: forming a first electrode above the first heterojunction and the second heterojunction.

[0030] The conductive channel of the semiconductor device of the present invention is far away from the substrate, which can reduce the influence of the substrate on the withstand voltage of the semiconductor device and improve the performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Below, the preferred embodiments of the present invention will be further described in detail with reference to the accompanying drawings, in which:

[0032] Figure 1A 2 is a schematic diagram of a top view of a single-channel HEMT according to an embodiment of the present invention;

[0033] Figure 1B is a schematic diagram of a cross-sectional structure of a single-channel HEMT according to an embodiment of the present invention;

[0034] Figure 2A 2 is a schematic diagram of a top view of a single-channel HHMT according to an embodiment of the present invention;

[0035] Figure 2B is a schematic diagram of a cross-sectional structure of a single-channel HHMT according to an embodiment of the present invention;

[0036] Figure 3 is a schematic diagram of a cross-sectional structure of a dual-channel HEMT according to an embodiment of the present invention;

[0037] Figure 4 is a schematic structural diagram of a high hole mobility transistor (HHMT) according to an embodiment of the present invention; and

[0038] Figure 5AA-Figure 5RB FIG. 1 is a schematic flow chart of a method for preparing a dual-channel HHMT according to an embodiment of the present invention. DETAILED DESCRIPTION

[0039] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0040] In the detailed description that follows, reference may be made to the various drawings that form part of this application and illustrate specific embodiments of the present application. In the drawings, similar reference numerals describe substantially similar components in different figures. Each specific embodiment of the present application is described below in sufficient detail to enable a person of ordinary skill in the art to implement the technical solutions of the present application. It should be understood that other embodiments may be utilized or that structural, logical, or electrical changes may be made to the embodiments of the present application.

[0041] The present invention provides a semiconductor device. In some embodiments, the semiconductor device can be formed on a heterogeneous substrate. By using a nucleation layer as an intermediary, not only can the use of an expensive homogeneous substrate be avoided, but the distance between the vertical heterojunction and the heterogeneous substrate can also be increased, thereby improving the voltage resistance of the semiconductor device. Furthermore, in some embodiments, the heterogeneous substrate can be removed to further improve the performance of the semiconductor device. The heterogeneous substrate is a substrate other than a GaN intrinsic semiconductor, including but not limited to a silicon Si substrate, sapphire (Al2O3), and a silicon carbide SiC substrate.

[0042] The semiconductor device proposed in the present invention may be a Schottky diode, HEMT, HHMT or other semiconductor devices. HEMT and HHMT are used as examples for illustration below.

[0043] Figure 1A 1 is a schematic top view of a single-channel HEMT according to an embodiment of the present invention; Figure 1B 1 is a schematic diagram of the cross-sectional structure of a single-channel HEMT according to one embodiment of the present invention. HEMT 100 includes a substrate 101 and a nucleation layer 102A formed on substrate 101. In this embodiment, the substrate is a silicon (Si) substrate. In other embodiments, the substrate may also be a sapphire Al2O3 substrate, a SiC substrate, or a GaN intrinsic substrate. The lattice of the vertical surface of substrate 101 has hexagonal symmetry, so that a nitride semiconductor crystal can be subsequently epitaxially grown. For example, the exposed vertical interface of substrate 101 may be a Si(111) plane. Nucleation layer 102A is formed on vertical interface 123 of substrate 101. From a horizontal perspective, substrate 101 and nucleation layer 102A are at the same level, i.e., the first layer of HEMT 100. In some embodiments, nucleation layer 102A may be slightly higher, but its entirety is still in the first layer. In some embodiments, nucleation layer 102A may be AlN. In this document, the nucleation layer may also include a buffer layer (not shown). The buffer layer can have a single-layer or multi-layer structure and include one or more of AlN, GaN, AlGaN, InGaN, AlInN, and AlGaInN. In some embodiments, the HEMT 100 further includes a spacer layer 112 disposed horizontally and parallel to the nucleation layer 102A. Spacer layer 112 is electrically insulating and may include one or more of silicon oxide, silicon nitride, and the like. Spacer layer 112 is at the same level as nucleation layer 102A and is also located in the first layer of the HEMT. In some embodiments, the horizontal surface of the substrate 101 includes an insulating blocking layer, separating the substrate 101 from the rest of the device, thereby further improving the withstand voltage capability.

[0044] In this embodiment, the HEMT 100 further includes: a channel layer 103A and a barrier layer 104A. The barrier layer 104A is formed on the right side of the channel layer 103A. The two are arranged horizontally and form a first heterojunction between the two, and a vertical 2DEG is formed in the first heterojunction. Under normal growth conditions, the surface of the channel layer and barrier layer grown on the Si (111) surface is the (0001) plane, that is, the direction from the Si substrate to the channel layer and barrier layer is <0001> In this crystal direction, there is 2DEG in the channel layer near the interface between the channel layer and the barrier layer. In the opposite direction, that is, in the <000-1> direction, there is 2DHG in the channel layer near the interface between the channel layer and the barrier layer (see Figure 2A and Figure 2B ).

[0045] In this embodiment, the channel layer 103A and the barrier layer 104A are formed above the nucleation layer 102A. Horizontally, the channel layer 103A and the barrier layer 104A are at the same level, i.e., the second layer of the HEMT 100. Consequently, the 2DEG 105A (second layer) perpendicular thereto is also formed above the substrate 101 (first layer). Compared to a HEMT structure in which the 2DEG and the nucleation layer are at the same level, this structure allows the conductive channel to be further away from the substrate, further reducing the substrate's impact on the device's withstand voltage. Furthermore, because the channel layer 103A, the barrier layer 104A, and the nucleation layer 102A are all located above the substrate, the substrate 104A and / or the nucleation layer 102A can be more easily removed during device formation, eliminating the drawback of poor withstand voltage of heterogeneous substrates (e.g., Si).

[0046] In this embodiment, a first electrode 107 and a second electrode 108 may also be included. The first electrode 107 and the second electrode 108 are in electrical contact with the 2DEG 105A. In some embodiments, one of the first electrode 107 and the second electrode 108 forms an ohmic contact with the channel layer 103A and / or the barrier layer 104A, while the other forms a Schottky contact with the channel layer 103A and / or the barrier layer 104A, thereby forming a Schottky diode structure.

[0047] In this embodiment, the HEMT 100 further includes a third electrode 109. The third electrode 109 is provided between the first electrode 107 and the second electrode 108. It serves as a gate electrode, controlling the current flow between the first and second electrodes 107, 108, thereby forming a HEMT structure. In this embodiment, the first and second electrodes 107, 108 form ohmic contacts with the channel layer 103A and / or the barrier layer 104A. Specifically, the voltage applied to the third electrode 109 controls the depth of the heterojunction potential well formed by the channel layer and barrier layer, thereby controlling the surface charge density of the 2DEG in the potential well and, in turn, the operating current between the first and second electrodes 107, 108. In some embodiments, the horizontal extension length of the third electrode 109 is no less than the length of the 2DEG 105A to control the current flow between the first and second electrodes 107, 108. Preferably, when the second electrode 108 is connected as the drain and receives a high voltage, the third electrode 109 is located between the first and second electrodes 107, 108, and closer to the first electrode 107 (source). Such a configuration increases the distance between the drain and the gate, and can effectively improve the voltage resistance of the semiconductor device 100 .

[0048] In some embodiments, the channel layer 103A may be defined by trenches. Figure 1B Figure 1 shows a shielding layer 113 above the substrate 101 and the nucleation layer 102A. This means that the shielding layer 113 is also located in the second layer of the HEMT 100. A trench 124 can be formed in the shielding layer 113. The trench 124 extends downward, exposing the nucleation layer 102A. Furthermore, the channel layer 103A can be epitaxially grown from the upper surface of the nucleation layer 102. The channel layer 103A grows and fills the trench 124. Thus, the shape of the channel layer 103A can be defined by the trench 124. Furthermore, another trench (not shown) can be formed in the shielding layer 113, exposing the side surfaces of the channel layer 103A through this trench. Then, the barrier layer 104A can be epitaxially grown on the side surfaces of the channel layer 103A exposed in the trench, filling the trench. Thus, the shape of the barrier layer 104A can also be defined by the trench. Since the channel layer 103A and the barrier layer 104A have different energy band gaps, a heterojunction having a vertical interface 141 is formed in the trench 123. A vertical two-dimensional electron gas 2DEG 105A is formed in the heterojunction.

[0049] The trench-defined heterojunction structure of the present invention has the following advantages: according to actual needs, a trench structure that meets the needs can be formed first, and then devices that are difficult to achieve by conventional means can be gradually formed in the trench. For example, it is easy to form a low aspect ratio structure through epitaxial growth in the prior art; however, it is usually difficult to form a high aspect ratio structure. For example, Figure 1BWhen the structure is tall and narrow, conventional epitaxial growth methods are difficult to achieve. However, as disclosed in some embodiments of the present invention, such a structure can be easily realized using the trench structure proposed by the present invention. Furthermore, the trench confinement allows for the formation of a taller 2DEG 105A. This HEMT, while maintaining the same horizontal projection distance between the electrodes, exhibits a higher on-state current between the source and drain, making it easier to achieve a high-power HEMT.

[0050] In some embodiments, the aspect ratio of the channel layer to the barrier layer of the semiconductor device of the present invention can be 2:1, 5:1, or 20:1. For example, the width of the bottom of the channel layer 103A and the barrier layer 104A is 1 μm (micrometer), while the height of the channel layer 103 and the barrier layer 104 can be 2 μm, 5 μm, or 20 μm. In fact, any desired aspect ratio can be achieved with the help of the trench definition.

[0051] In general applications, the channel layer 103A and the barrier layer 104A are lower than or equal to the height of the trenches they define. In some special applications, the channel layer 103A and the barrier layer 104A may also extend above these trenches. However, without the constraints of the trenches, the growth of the channel layer 103A and the barrier layer 104A may be more difficult to control. Therefore, even if the channel layer 103A and the barrier layer 104A extend above these trenches, the height of the extension will be limited.

[0052] Figure 1B FIG1 shows an arrangement of three electrodes of the HEMT 100. The first electrode 107 is located above the first heterojunction. The second electrode 108 is located below the barrier layer 104A. The third electrode 109 is located above the electrode 108 outside the barrier layer 104A. Figure 1A From a horizontal projection, the second electrode 108 and the third electrode 109 overlap. This reduces chip area and improves integration. Furthermore, all three electrodes are located on the side of the device, which, given the same area, can increase the device's voltage resistance.

[0053] In some embodiments, HEMT 100 includes a spacer layer 111A, which extends horizontally over the horizontal surface of substrate 101 below nucleation layer 102A. The spacer layer 111A may be made of an insulating material such as SiO2. Spacer layer 111A protects the horizontal surface of substrate 101, preventing it from affecting device performance and minimizing the impact of other components on the substrate during device fabrication. This significantly improves withstand voltage and reduces dark current.

[0054] In some embodiments, HEMT 100 may include a spacer layer 111B, which extends horizontally over the horizontal surface of substrate 101 above nucleation layer 102A. The spacer layer 111B may be made of an insulating material such as SiO2. This protects the substrate's horizontal surface, preventing the substrate 101 from affecting device performance while also minimizing the impact of other components on the substrate during device fabrication. This significantly improves withstand voltage and reduces dark current.

[0055] In some embodiments, an insulating layer 114A is included between the electrode 107 and the electrode 109 on the side of the barrier layer 104A. The insulating layer 114A extends horizontally and can be made of an insulating material such as SiO2. In some embodiments, the shielding layer 114A can serve as a gate insulating layer, partially filling the space between the barrier layer 104A and the electrode 109.

[0056] In some embodiments, an insulating layer 114B is provided on the shielding layer 113. The shielding layer 114B extends horizontally and may be made of an insulating material such as SiO2. The shielding layer 114B isolates the upper surface of the channel layer 103A from the outside world, thereby reducing the impact of the outside world on device performance.

[0057] In some embodiments, a shielding layer 115 is included on one side of barrier layer 104A, above electrode 109. Shielding layer 115 also extends horizontally and can be made of an insulating material such as SiO2. Shielding layer 115 isolates the side of barrier layer 104A from the outside world, preventing external influences on device performance.

[0058] In some embodiments, Figure 1A and Figure 1B A passivation layer may be included above the semiconductor device to protect the underlying semiconductor structure. Furthermore, the passivation layer may include a first conductor interconnect layer, a second conductor interconnect layer, and a third conductor interconnect layer, which are electrically connected to the first electrode 107, the second electrode 108, and the third electrode 109, respectively. These are well known to those skilled in the art and will not be described in detail here.

[0059] In some embodiments, the first electrode, the second electrode, and the third electrode may also be arranged horizontally. In some embodiments, to reduce the occupied chip area, the second electrode extends from the third electrode and is then electrically connected to the second conductor interconnect layer. That is, the third electrode is electrically connected to the third conductor interconnect layer on the outside, and the second electrode is electrically connected to the second conductor interconnect layer on the inside. An insulating material may be included between the second and third electrodes to electrically insulate them. In some embodiments, the second electrode may also be connected to the second conductor interconnect layer from one side of the substrate, thereby forming a double-sided conductive interconnect structure.

[0060] In some embodiments, the third electrode extends from the first electrode and is electrically connected to the third conductor interconnect layer. That is, the first electrode is electrically connected to the first conductor interconnect layer on the outside, and the third electrode is electrically connected to the third conductor interconnect layer on the inside. An insulating material may be included between the second and third electrodes to electrically insulate them.

[0061] In some embodiments, the second electrode and the third electrode both realize circuit interconnection in the chip surface area defined by the first electrode, without occupying more chip area, thereby improving the integration of the semiconductor device.

[0062] As those skilled in the art will appreciate, the above description is merely an exemplary illustration of the HEMT structure. The devices described herein may also have various other structures or improvements, modifications, or variations thereon to provide different characteristics or functions. These structures and their improvements, modifications, or variations, within the technical concepts of the present invention, may also be applied to the solutions of the present invention.

[0063] In some embodiments, similar structures can also form a high hole mobility transistor (HHMT) with 2DHG. Figure 2A This is a schematic diagram of a top view of an HHMT structure according to an embodiment of the present invention. Figure 2B is a schematic diagram of a cross-sectional structure of a single-channel HHMT according to an embodiment of the present invention; Figure 1A and Figure 1B The parts with similar structures will not be described here.

[0064] As shown in the figure, the HHMT 200 includes a nucleation layer 202A formed vertically from the substrate 201. A trench layer 203A is formed above the nucleation layer 202A. Figure 1A and Figure 1B The difference between the illustrated embodiment and the embodiment is that the barrier layer 204A is formed on the left side of the channel layer 203A, and thus the electrodes 208 and 209 are also formed on the left side of the heterojunction. The nucleation layer 202A can be used to understand the crystal growth direction of the channel layer 203A and the barrier layer 204A, thereby confirming that the conductive channel between them is a 2DHG.

[0065] In some embodiments, the channel layer 203A and the barrier layer 204A may be defined by trenches. Figure 2B, a shielding layer 213 is shown above the substrate 201 and the nucleation layer 202A. A trench 224 may be formed on the shielding layer 213. The trench 224 extends downward, exposing the upper surface of the nucleation layer 202A. Further, a channel layer 203A may be epitaxially grown from the upper surface of the nucleation layer 202A and fill the trench 224. Thus, the shape of the channel layer 203A may be defined by the trench 224. Further, another trench (not shown) may be formed on the shielding layer 213, and the side of the channel layer 203A may be exposed through this trench, and then a barrier layer 204A may be epitaxially grown and fill the trench. Thus, the shape of the barrier layer 204A may also be defined by the trench.

[0066] In some embodiments, the HHMT 200 includes a first electrode 207, a second electrode 208, and a third electrode 209. The first electrode 207 and the second electrode 208 are the source and drain of the HHMT. The third electrode 209 is a gate electrode, which is located outside the barrier layer 204A. Figure 2A As shown, the electrode 207 is formed above the heterojunction and is also close to the left side of the channel layer 203A, so that it and the electrode 208 are both located on the same side of the nucleation layer 202A (ie, to the left of the center line of the nucleation layer 202A).

[0067] In this embodiment, the substrate and nucleation layer of the HHMT are both located below the channel layer and the barrier layer, which has little impact on the conductive channel, and the performance of the device can be further improved.

[0068] Based on the above structure, the present invention also proposes a dual-channel structure, which includes 2DEG or 2DHG on both sides, and can have a larger contact area and thus higher power.

[0069] Figure 3 FIG. 1 is a schematic diagram of a cross-sectional structure of a dual-channel HEMT according to an embodiment of the present invention. Figure 3 The HEMT 300 shown in FIG can also be considered as two Figure 1A and 1B The semiconductor device 100 is composed of a combination of the above-mentioned components; parts similar to the above-mentioned structures are not described in detail here.

[0070] As shown, the first layer of HEMT 300 includes a trench 321 formed in the substrate, and nucleation layers 302A and 302B are formed from vertical interfaces of silicon substrate 301. Furthermore, the first layer includes a shielding layer 312 between nucleation layers 302A and 302B.

[0071] The second layer of HEMT 300 includes a trench 322 formed in shield layer 311B. Within trench 322, a channel layer 303A is disposed on nucleation layer 302A, and a channel layer 303B is disposed on nucleation layer 302B. A barrier layer 304A is disposed to the right of channel layer 303A, and a barrier layer 304B is disposed to the left of channel layer 303B. Because channel layers 303A and 303B and barrier layers 304A and 304B have different energy band gaps, a first heterojunction and a second heterojunction with perpendicular interfaces are formed within trench 322. Vertical two-dimensional electron gases 2DEG 105A and 2DEG 105B are formed within the first and second heterojunctions.

[0072] A first electrode 307 (source) and a second electrode 308 (drain) are formed above and below the first and second heterojunctions, respectively, to electrically contact both 2DEGs 305A and 305B. A third electrode 309 (gate) is formed between the barrier layers 304A and 304B.

[0073] In this embodiment, HEMT 300 includes two conductive channels, namely 2DEG 305A and 305B. The addition of these channels increases the on-state current, resulting in higher power. Furthermore, dual channels offer superior voltage and heat resistance compared to a single channel. Furthermore, electrodes with the same properties can be shared within the dual channel structure, eliminating the need for separate electrodes. This saves space and significantly reduces manufacturing costs and time.

[0074] In some embodiments, the trench 321 may include separation layers 311A ​​and 311B, which cover the horizontal surfaces of the substrate 301 below and above the nucleation layers 302A and 302B and extend in the horizontal direction. The material of the separation layers 311A ​​and 311B may be an insulating material such as SiO2.

[0075] In some embodiments, a shielding layer 314A is included between barrier layers 304A and 304B and between electrode 307 and electrode 309. In some embodiments, a shielding layer 314B is included on shielding layer 313. Shielding layer 314B also extends horizontally to isolate the upper surfaces of channel layers 303A and 303B from the outside world, thereby preventing external factors from affecting device performance. In some embodiments, a shielding layer 315 is included between barrier layers 304A and 304B and on electrode 309.

[0076] In this embodiment, the two HEMT channels are formed within the same trench 322, sharing the nucleation layers 302A and 302B and the first electrodes 307 and 309. In some embodiments, multiple HEMT structures can be incorporated into the same trench 321. This approach reduces manufacturing costs and time. Furthermore, since the distance between upper and lower devices is reduced, higher integration density can be achieved, resulting in improved substrate utilization.

[0077] and Figure 3 Similar to the embodiment shown, the present invention can also form a dual-channel HHMT structure. Figure 4 This is a schematic diagram of the structure of a high hole mobility transistor HHMT according to an embodiment of the present invention. Figure 1A and 1B The same or similar structures are not described in detail here.

[0078] exist Figure 4 In the embodiment of Figure 3 In the structure shown, barrier layers 404A and 404B of the HHMT 400 are formed on the right and left sides of the channel layers 403A and 403B, respectively. Furthermore, two-dimensional hole gases (2DHGs) 405A and 405B are formed within the first and second heterojunctions. The HHMT 400 includes a first electrode 407 (source) and a second electrode 408 (drain) electrically contacting the 2DHGs 404A and 404B above and below the first and second heterojunctions, respectively, as well as a third electrode 409 (gate) electrically contacting the barrier layers 404A and 404B, thereby forming a high hole mobility transistor (HHMT). In some embodiments, the short distance between the bottom of the first and second heterojunctions and the substrate can easily affect the device's withstand voltage. Preferably, the substrate between the nucleation layers 402A and 402B in the first layer of the HHMT 400 is removed and filled with insulating material to form an insulating layer 412, thereby reducing the substrate's impact and improving the device's withstand voltage performance.

[0079] In some embodiments of the present invention, a semiconductor device may also include both a 2DEG and a 2DHG. The 2DEG and 2DHG may form the same semiconductor device or may form separate semiconductor devices, each functioning independently. These structures are similar to those described above and will not be further described here.

[0080] The present invention also includes a method for manufacturing a semiconductor device. The following uses the manufacturing process of a dual-channel HEMT as an example to illustrate the method for manufacturing a semiconductor device of the present invention. Semiconductor devices of other structures can also be manufactured using similar methods.

[0081] Figure 5AA-Figure 5RB FIG is a flow chart of a method for preparing a high electron mobility transistor according to an embodiment of the present invention; Figure 5AA-Figure 5RA This is a top view of each step of a method for manufacturing a high electron mobility transistor according to an embodiment of the present invention. Figure 5AB-Figure 5RB The following are cross-sectional views illustrating various steps in a method for fabricating a high electron mobility transistor according to one embodiment of the present invention. In this embodiment, the semiconductor device is fabricated on a silicon substrate. As those skilled in the art will appreciate, similar structures can be achieved using other substrates, such as intrinsic GaN, Al2O3 (sapphire), and SiC.

[0082] As shown in the figure, the preparation method 500 of HEMT includes: in step 5001, as shown in FIG. Figure 5AA and 5AB As shown, a Si substrate 501 is provided.

[0083] In step 5002, a plurality of first trenches are formed on a substrate, such as Figure 5BA and 5BB As shown. For example, a substrate 501 is etched using photolithography technology to form a plurality of rectangular first trenches 521 on the substrate 501, exposing vertical interfaces 541 and 542 of the substrate 501; wherein, the vertical interfaces 541 and 542 of the substrate in the first trenches 521 are the (111) planes of the Si substrate. Other methods exist in the art to obtain the first trenches 521, and these methods can also be applied here.

[0084] In some embodiments, the number of first trenches provided in a substrate depends on specific requirements such as the degree of integration and voltage resistance. Here, three trenches are used as an example for illustration. The method of the present invention can pre-configure the shape and size of the trenches according to actual needs. For example, when forming a semiconductor device with a relatively high voltage resistance, the trench depth is also deeper.

[0085] In step 5003, a protective layer 531 is formed on the surface of the substrate and the first groove on the substrate. Figure 5CA and 5CB A SiN protection layer 531 is grown on the substrate 501 using LPCVD or other techniques, covering the surfaces of the substrate 501 and the plurality of trenches 521 .

[0086] In step 5004, the protective layer 531 extending horizontally from the bottom surface of the first trench and the upper surface of the substrate is removed, and the protective layer 531 on the sidewall of the first trench is retained. Figure 5DA and 5DB As shown, by using a vertically oriented etching technique, only the protective layer 531 formed of SiN on the vertical interfaces 541 and 542 is retained, exposing the Si substrate 501 at the bottom of the trench 521. The protective layer 531 covers the substrate vertical interfaces 541 and 542 of the substrate trench 521.

[0087] In step 5005, a first separation layer is formed on the substrate and the first trench, such as Figure 5EA and 5EB As shown, a separation layer 511 covers the bottom surface of the first trench 521. In some embodiments, SiO2 can be formed using an oxidation technique to form the first separation layer 511 on the substrate 501. Because the vertical interfaces 541 and 542 of the substrate 501 are covered with the protective layer 531, the separation layer 511 is substantially not grown on the vertical interfaces 541 and 542 of the substrate 501.

[0088] In step 5006, the protective layer on the sidewall of the trench is removed. Figure 5FA and 5FB As shown, a mask is applied to the spacer layer 511 above the substrate 501, and the protective layer 531 on the sidewalls of the first trench 521 is partially etched using photolithography. For example, the etching process may include removing a portion of the sidewalls of the first trench 521. After etching, vertical interfaces 541 and 542 of the substrate 501 are exposed. Other methods exist in the art for removing protective layers and exposing vertical interfaces of the substrate, and these methods may also be applied here.

[0089] In step 5007, a first nucleation layer and a second nucleation layer are formed at the vertical interface, such as Figure 5GA and 5GB As shown. First and second nucleation layers 502A and 502B are grown on the exposed vertical surfaces 541 and 542 of the substrate 501. The nucleation layers 502A and 502B include AlN. In some embodiments, after AlN is formed, one or more buffer materials selected from AlN, GaN, AlGaN, InGaN, AlInN, and AlGaInN can be further grown. In some embodiments, the nucleation layer grows in a vertical direction while extending horizontally (not shown). By controlling the process parameters, the growth of the nucleation layer can be made as horizontal as possible. Although there is growth in the vertical direction, it does not affect the device structure.

[0090] In step 5008, a shielding layer is formed on the surface of the entire device, such as Figure 5HA and 5HB As shown. Figure 5GA and 5GB In the structure shown, a SiO2 shielding layer 512 is formed by a deposition process. The shielding layer 512 fills the trench 521 and forms a certain height of the SiO2 shielding layer 512 on the substrate. In some embodiments, if a semiconductor device with a larger aspect ratio is desired, the height of the shielding layer 512 will be increased accordingly.

[0091] In step 5009, the shielding layer is patterned to form a plurality of second trenches, such as Figure 5IA and Figure 5IBAs shown, vertical second trenches 523 and 524 are etched in shield layer 512 using a vertical etching technique. Essentially, second trenches 523 and 524 define the height of the second layer of the semiconductor device and limit the height of the nucleation layer to the first layer. At the bottom of trenches 523 and 524, the upper surfaces of nucleation layers 502A and 502B are exposed.

[0092] Those skilled in the art should note that the nucleation layers 502A and 502B are formed on the (111) surface of the Si substrate, and therefore, the nucleation layers 502A and 502B have hexagonal symmetry. After the upper surfaces of the nucleation layers 502A and 502B are exposed, other structures formed in the trenches 523 and 524 also have hexagonal symmetry.

[0093] In step 5010, first and second channel layers are grown in a plurality of second trenches, such as Figure 5JA and Figure 5JB As shown, channel layers 503A and 503B are formed on nucleation layer 502 through epitaxial growth. Conventional epitaxial growth is difficult to control in the horizontal direction, making it difficult for the semiconductor structure to maintain completely vertical growth, potentially resulting in multiple growth planes. The structure of the present invention maintains continuous growth on the same plane, improving the device's electrical properties.

[0094] In step 5011, a third trench is formed between the first channel layer and the second channel layer. Figure 5KA and 5KB In some embodiments, the shielding layer 512 is etched between the nucleation layers 503A and 503B to form a third trench 525. Since the third trench 525 is formed between the two second trenches 523 and 524, it can be considered that the third trench 525 and the second trenches 523 and 524 together constitute a larger trench with the shielding layer as the sidewall.

[0095] In step 5012, a first barrier layer and a second barrier layer are formed on one side of the first channel layer and the second channel layer in the third trench, respectively. Figure 5LA and 5LB As shown. Barrier layers 504A and 504B are formed by epitaxial growth in the third trench 525. In some embodiments, a barrier layer can be grown to fill the third trench 525, and then the barrier layers 504A and 504B are etched to form barrier layers 504A and 504B. In some embodiments, the barrier layer can be the same height as the channel layer. In a preferred embodiment, in order to save process and avoid unnecessary etching that damages the crystal structure, two barrier layers are epitaxially grown from the channel layer on both sides of the third trench 525, respectively, leaving a space between the two barrier layers. In this way, as shown in the figure, part of the barrier layer will also be formed on the upper surface of the channel layer.

[0096] In step 5013, a second electrode 508 is formed between the first barrier layer and the second barrier layer. Figure 5MA and 5MB As shown, a second electrode 508 is formed between the barrier layers using an electrode deposition method. In some embodiments, electrode 508 is positioned closer to the bottom, acting as a drain, for example, directly on shielding layer 112 or partially within shielding layer 112. Electrode 507, acting as a drain, is typically connected to a high voltage. This improves overall voltage resistance due to the presence of the shielding layer below.

[0097] In step 5014, a second spacer layer is formed on the entire device, such as Figure 5NA and 5NB SiO2 is deposited on the semiconductor device through a deposition process to fill the portion above the electrode 507 and cover the channel layer and the barrier layer, thereby forming a second separation layer 514.

[0098] In step 5015, the second spacer layer is patterned, and a portion of the second spacer layer between the first barrier layer and the second barrier layer is removed. Figure 5OA and 5OB The second spacer layer 513 located between the first barrier layer and the second barrier layer is partially removed by vertical etching technology. The height of the remaining second spacer layer is determined according to the insulation requirements between the gate and drain of the semiconductor device.

[0099] In step 5016, a third electrode is formed between the first barrier layer and the second barrier layer. Figure 5PA and 5PB As shown, a third electrode 509 is formed on the spacer layer 513 retained between the first and second barrier layers by an electrode deposition method. In some embodiments, electrode 509 is positioned closer to the top as a gate electrode and as far away from the second electrode 508 (drain) as possible to improve the overall voltage resistance of the device.

[0100] In step 5017, a third separation layer is formed on the third electrode, such as Figure 5QA and 5QB SiO 2 is deposited on the third electrode 509 by a deposition process, so as to fill the space between the first barrier layer and the second barrier layer above the third electrode 509 , thereby forming a third separation layer 515 .

[0101] In step 5018, the upper surfaces of the first heterojunction and the second heterojunction are exposed, and a first electrode 507 is formed on the first heterojunction and the second heterojunction. Figure 5RA and 5RBAs shown in the figure. As shown in the figure, the second separation layer above the first heterojunction and the second heterojunction and the possible horizontally extending first barrier layer and the second barrier layer are patterned and removed to expose the upper surfaces of the first heterojunction and the second heterojunction. In some embodiments, portions of the first and second channel layers and the first and second barrier layers can be further removed to ensure good electrical contact. Next, the electrode material is filled to form the first electrode 507. Although the first electrode 507 shown in the figure includes two parts that contact the first heterojunction and the second heterojunction respectively, these two parts are electrically connected to the same interconnect layer and can therefore be considered to be the same electrode.

[0102] In some embodiments, subsequent steps include forming a first conductor interconnect layer, a second conductor interconnect layer, and a third conductor interconnect layer, which are electrically connected to the first electrode, the second electrode, and the third electrode, respectively. These steps are well known to those skilled in the art and will not be described in detail here.

[0103] The aforementioned structure of the present invention is merely an exemplary description of the technical solution of the present invention. In some embodiments, the same trench may include more semiconductor structures, thereby forming a solution with a higher degree of integration.

[0104] The above embodiments are only used to illustrate the present invention, and are not intended to limit the present invention. Ordinary technicians in the relevant technical field can make various changes and modifications without departing from the scope of the present invention. Therefore, all equivalent technical solutions should also fall within the scope of the present invention.

Claims

1. A semiconductor device, comprising: a first channel layer; A first barrier layer, which forms a first heterojunction between the first channel layer and the first barrier layer, and a vertical 2DEG or 2DHG is formed in the first heterojunction; a first nucleation layer configured to generate the first channel layer from a foreign substrate, wherein the first channel layer is located above the first nucleation layer; A first electrode in electrical contact with the 2DEG or 2DHG of the first heterojunction; and a second electrode in electrical contact with the 2DEG or 2DHG of the first heterojunction; The semiconductor device also includes a first shielding layer located above the first nucleation layer, a groove exposing the first nucleation layer is formed on the first shielding layer, the first channel layer is formed by epitaxial growth from the first nucleation layer in the groove; the first barrier layer is formed by epitaxial growth on the side of the first channel layer. 2 . The semiconductor device according to claim 1 , wherein the first electrode is in ohmic contact with the first channel layer and / or the first barrier layer; and the second electrode is in Schottky contact with the first channel layer and / or the first barrier layer. 3 . The semiconductor device of claim 1 , further comprising a third electrode configured to control a current between the first electrode and the second electrode.

4. The semiconductor device according to claim 1, further comprising: A shielding layer below the first channel layer and / or the first barrier layer.

5. The semiconductor device according to claim 1, further comprising: A heterogeneous substrate, wherein the first nucleation layer is formed on a vertical interface of the heterogeneous substrate.

6. The semiconductor device according to claim 5, further comprising: A separation layer covers the horizontal interface of the foreign substrate.

7. The semiconductor device according to claim 3, wherein the second electrode passes through the third electrode and is electrically connected to a conductor interconnection layer.

8. The semiconductor device according to claim 3, wherein the third electrode passes through the first electrode and is electrically connected to another conductor interconnection layer.

9. The semiconductor device according to claim 1, further comprising: a second channel layer; A second barrier layer, which forms a second heterojunction between the second channel layer and the second barrier layer, and forms a vertical 2DEG or 2DHG in the second heterojunction; a second nucleation layer configured to generate the second channel layer from a foreign substrate, wherein the second channel layer is located above the second nucleation layer; A groove exposing the second nucleation layer is formed on the first shielding layer, and the second channel layer is formed by epitaxial growth from the second nucleation layer in the groove; and the second barrier layer is formed by epitaxial growth on the side of the second channel layer.

10. The semiconductor device of claim 9, wherein the first electrode is in electrical contact with the 2DEG or 2DHG of the first heterojunction and the second heterojunction; and the second electrode is in electrical contact with the 2DEG or 2DHG of the first heterojunction and the second heterojunction.

11. A semiconductor device comprising: a first nucleation layer comprising an upper surface; a first channel layer grown from an upper surface of the first nucleation layer; A first barrier layer, which forms a first heterojunction between the first channel layer and the first barrier layer, and a vertical 2DEG or 2DHG is formed in the first heterojunction; a first electrode in electrical contact with the 2DEG or 2DHG of the first heterojunction; as well as a second electrode in electrical contact with the 2DEG or 2DHG of the first heterojunction; The semiconductor device also includes a first shielding layer located above the first nucleation layer, a groove exposing the first nucleation layer is formed on the first shielding layer, the first channel layer is formed by epitaxial growth from the first nucleation layer in the groove; the first barrier layer is formed by epitaxial growth on the side of the first channel layer. 12 . The semiconductor device of claim 11 , further comprising a third electrode configured to control a current between the first electrode and the second electrode.

13. The semiconductor device of claim 11, wherein the first nucleation layer grows from a vertical surface of a foreign substrate.

14. A semiconductor device comprising: a first layer comprising a first nucleation layer; a second layer, comprising a first channel layer and a first barrier layer, wherein a first heterojunction is formed between the first channel layer and the first barrier layer, a vertical 2DEG or 2DHG is formed in the first heterojunction, and wherein the second layer is above the first layer; a third layer comprising a plurality of conductor interconnect layers, wherein the third layer is above the second layer; A first electrode, at least partially in the second layer, configured to be in electrical contact with the 2DEG or 2DHG of the first heterojunction; and a second electrode, at least partially in the second layer, configured to be in electrical contact with the 2DEG or 2DHG of the first heterojunction; Wherein, the first electrode is electrically connected to the first conductor layer in the third layer; the second electrode is electrically connected to the second conductor layer in the third layer; The second layer also includes a first shielding layer, a groove exposing the first nucleation layer is formed on the first shielding layer, the first channel layer is formed by epitaxial growth from the first nucleation layer in the groove; the first barrier layer is formed by epitaxial growth on the side of the first channel layer. 15 . The semiconductor device of claim 14 , further comprising a third electrode configured to control a current between the first electrode and the second electrode; wherein the third electrode is electrically connected to a third conductor layer in the third layer.

16. The semiconductor device according to claim 14, wherein the first layer comprises a foreign substrate or a substitute thereof.

17. A semiconductor device comprising: a trench formed in an insulating material; a first channel layer, which is located in the trench; A first barrier layer, which is located on one side of the first channel layer, wherein a first heterojunction is formed between the first barrier layer and the first channel layer, wherein the first heterojunction includes a vertical 2DEG or 2DHG; a first electrode in electrical contact with the 2DEG or 2DHG of the first heterojunction; a second electrode in electrical contact with the 2DEG or 2DHG of the first heterojunction; a third electrode, located between the first electrode and the second electrode, configured to control the intensity of a current between the first electrode and the second electrode; The semiconductor device also includes a substrate, and the insulating material includes a first shielding layer. The first shielding layer, the first channel layer and the first barrier layer are located above the substrate. The first shielding layer is provided with the groove, and the first channel layer is formed by epitaxial growth in the groove; the first barrier layer is formed by epitaxial growth on the side of the first channel layer.

18. A method for preparing a semiconductor device, comprising: forming a first trench on a substrate; forming a first nucleation layer in the first trench; forming a first shielding layer, wherein the height of the first shielding layer is higher than the first nucleation layer; forming a second groove on the shielding layer, wherein the second groove exposes the first nucleation layer, wherein a bottom surface of the second groove is higher than a bottom surface of the first groove; epitaxially growing a first channel layer from the first nucleation layer in the second trench; as well as A first barrier layer is epitaxially grown on the side of the first channel layer, wherein a first heterojunction is formed between the first barrier layer and the first channel layer, and the first heterojunction includes a vertical 2DEG or 2DHG.

19. The method according to claim 18, further comprising: A first separation layer is formed at the bottom of the first trench.

20. The method of claim 18, further comprising: While forming a first nucleation layer in the first trench, forming a second nucleation layer in the first trench; forming another second trench exposing the second nucleation layer; While the first channel layer is epitaxially grown from the nucleation layer in the second trench, the second channel layer is epitaxially grown from the second nucleation layer in the other second trench; and a second barrier layer is epitaxially grown on the side of the second channel layer, wherein a second heterojunction is formed between the second barrier layer and the second channel layer, and the second heterojunction includes a vertical 2DEG or 2DHG.

21. The method according to claim 20, further comprising: A second electrode and a third electrode are formed between the first barrier layer and the second barrier layer, wherein an insulating material is included between the second electrode and the third electrode.

22. The method according to claim 21, further comprising: A first electrode is formed over the first heterojunction and the second heterojunction.

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