Signal processing circuits used to reduce or eliminate correlated components of a signal

Abstract

The present invention discloses a signal processing circuit, which has a pair of input nodes and a pair of output nodes, and includes a first switch pair, a second switch pair, an amplifier, a first compensation capacitor and a second compensation capacitor. The first switch pair is coupled between the pair of input nodes and a plurality of floating nodes. The second switch pair is coupled between the plurality of floating nodes and the pair of output nodes. The amplifier is coupled between the plurality of floating nodes and the pair of output nodes. The first compensation capacitor is coupled between a first floating node among the plurality of floating nodes and a first output node among the pair of output nodes. The second compensation capacitor is coupled between a second floating node among the plurality of floating nodes and the first output node.

Description

Technical Field

[0001] The present invention relates to a signal processing circuit, and in particular to a signal processing circuit capable of receiving and processing a sensing signal from a sensor. Background Art

[0002] With the advancement of technology, various types of mobile devices, such as smart phones, tablet computers, laptops, GPS navigator systems and electronic books, have become an indispensable part of people's lives. Unlike traditional mobile phones that only have calling functions, today's mobile devices integrate communication, networking, photography, games, data processing and other functions. The multifunctional design makes mobile devices more popular with consumers. Fingerprint recognition is a common function used to deal with the security and privacy issues of various electronic devices and mobile devices. Fingerprint recognition can be achieved through various technologies, such as capacitive sensing, light sensing (image sensing), thermal energy, ultrasonic waves, etc. For example, a mobile phone may have a fingerprint recognition interface built into the home button or a specific area that can be used to detect the user's fingerprint.

[0003] Among various types of fingerprint recognition technologies, capacitive fingerprint recognition has become a more popular fingerprint recognition method. In capacitive fingerprint recognition, the sensing pixels on the fingerprint sensor can capture the capacitance value of the finger that touches it. This capacitance value is converted into a voltage signal after processing, and then transferred to the subsequent signal processing circuit (such as the analog front-end (AFE) circuit) for recognition. The analog front-end circuit needs to have a switched-capacitor integrator to continuously receive the sensing signal from the sensing pixel and convert and amplify the sensing signal.

[0004] The input signal received by the switched capacitor integrator may include the above-mentioned sensing signal and a reset signal. The reset signal is a predetermined signal received during the reset period of the sensing pixel. During the sensing period of the sensing pixel, the light-emitting diode in the sensing pixel begins to be exposed and generates an electronic signal accordingly. The corresponding switch in the sensing pixel can be turned on to transfer the electronic signal or the voltage signal corresponding to the electronic signal to the analog front-end circuit. These signals can be regarded as sensing signals, which are superimposed on the reset signal and received by the switched capacitor integrator. However, as the brightness sensed by the light-emitting diode is different, it may generate electronic signals of different values ​​in each cycle, causing the switched capacitor integrator to receive sensing signals of different sizes. The change of the sensing signal may cause the integrator to enter an abnormal voltage range, so that the voltage signal output by the back-end circuit is saturated. In addition, if the sensing signal received by the switched capacitor integrator changes greatly, a more serious charge injection problem may occur. In view of this, the prior art really needs to be improved. Summary of the invention

[0005] Therefore, the main purpose of the present invention is to provide a capacitance compensation mechanism that can be used in signal processing circuits such as switched capacitor integrators, which can reduce or eliminate signal-related components on floating nodes in the signal processing circuit, thereby maintaining the voltage level of the floating node within a small voltage range.

[0006] An embodiment of the present invention discloses a signal processing circuit, the signal processing circuit having a pair of input nodes and a pair of output nodes, and comprising a first switch pair, a second switch pair, an amplifier, a first compensation capacitor and a second compensation capacitor. The first switch pair is coupled between the pair of input nodes and a plurality of floating nodes. The second switch pair is coupled between the plurality of floating nodes and the pair of output nodes. The amplifier is coupled between the plurality of floating nodes and the pair of output nodes. The first compensation capacitor is coupled between a first floating node among the plurality of floating nodes and a first output node among the pair of output nodes. The second compensation capacitor is coupled between a second floating node among the plurality of floating nodes and the first output node.

[0007] Another embodiment of the present invention discloses a signal processing circuit, the signal processing circuit having a pair of input nodes and a pair of output nodes, and comprising a first switch pair, a second switch pair, an amplifier, a first compensation capacitor and a second compensation capacitor. The first switch pair is coupled between the pair of input nodes and a plurality of floating nodes. The second switch pair is coupled between the plurality of floating nodes and the pair of output nodes. The amplifier is coupled between the plurality of floating nodes and the pair of output nodes. The first compensation capacitor is coupled between a first floating node among the plurality of floating nodes and a reference node. The second compensation capacitor is coupled between a second floating node among the plurality of floating nodes and the reference node. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 FIG. 1 is a schematic diagram of a switched capacitor integrator according to an embodiment of the present invention.

[0009] Figure 2A and 2B The states of the switched capacitor integrator in the reset phase and the conversion phase are shown respectively.

[0010] Figure 3 FIG. 4 is a schematic diagram of another switched capacitor integrator according to an embodiment of the present invention.

[0011] Figure 4 FIG. 4 is a schematic diagram of another switched capacitor integrator according to an embodiment of the present invention.

[0012] Figure 5 FIG. 4 is a schematic diagram of yet another switched capacitor integrator according to an embodiment of the present invention.

[0013] The reference numerals are described as follows:

[0014] 10 Switched Capacitor Integrator

[0015] VON, VOP output signal

[0016] Vrst reset signal

[0017] Vsig sensing signal

[0018] SW1_1, SW1_2 Input switch pair

[0019] SW2_1, SW2_2 Reset switch pair

[0020] 100 Amplifier

[0021] C1_1, C1_2 Input capacitor pair

[0022] C2_1, C2_2 Feedback capacitor pair

[0023] C3_1, C3_2 Compensation capacitor pair

[0024] x, y floating node

[0025] Cp Parasitic capacitance

[0026] Vref Reference voltage DETAILED DESCRIPTION

[0027] Please refer to Figure 1 , Figure 1 FIG. 1 is a schematic diagram of a switched capacitor integrator 10 according to an embodiment of the present invention. Figure 1 As shown, the switched capacitor integrator 10 has a differential structure, which includes a pair of input nodes and a pair of output nodes. The pair of input nodes is used to receive an input signal pair from a sensor (such as a sensing pixel of a fingerprint sensor), and the pair of output nodes generates output signals VON and VOP, respectively. As described above, during the reset period before sensing begins, the sensor can output a reset signal Vrst, and this reset signal Vrst is received by an input node of the switched capacitor integrator 10. When sensing is completed, the sensor can output a sensing signal Vsig, which is superimposed on the reset signal Vrst, and the other input node of the switched capacitor integrator 10 is used to receive the sensing signal Vsig. According to the received sensing signal Vsig, the switched capacitor integrator 10 can output a differential output signal VOP-VON.

[0028] In detail, the switched capacitor integrator 10 includes an input switch pair SW1_1 and SW1_2, a reset switch pair SW2_1 and SW2_2, an amplifier 100, an input capacitor pair C1_1 and C1_2, a feedback capacitor pair C2_1 and C2_2, and a compensation capacitor pair C3_1 and C3_2. The input switch pair SW1_1 and SW1_2 are respectively coupled between the input node pair and the floating nodes x and y of the switched capacitor integrator 10. The reset switch pair SW2_1 and SW2_2 are respectively coupled between the floating nodes x and y and the output node pair of the switched capacitor integrator 10. The input capacitor pair C1_1 and C1_2 are respectively coupled to the input node pair. The feedback capacitor pair C2_1 and C2_2 are respectively coupled between the floating nodes x and y and the output node pair of the switched capacitor integrator 10. The compensation capacitor C3_1 is coupled between the floating node x and an output node, and the compensation capacitor C3_2 is coupled between the floating node y and the same output node. The amplifier 100 is coupled between the floating nodes x and y and the output node pair. More specifically, the amplifier 100 has a differential structure, which includes a positive input terminal, a negative input terminal, a positive output terminal and a negative output terminal. Figure 1As shown, the positive and negative input terminals of the amplifier 100 are respectively coupled to the floating nodes x and y, and the positive and negative output terminals of the amplifier 100 are respectively coupled to the output node pair of the switched capacitor integrator 10 for outputting output signals VOP and VON. Figure 1 Also shown is a parasitic capacitor Cp coupled to floating nodes x and y. The parasitic capacitor Cp affects the transfer function of the switched capacitor integrator 10. The amplifier 100 with a differential structure can be used to reduce or eliminate the effect of the parasitic capacitor Cp on the differential output signal (VOP minus VON).

[0029] In this example, the input signal pair Vrst+Vsig and Vrst are respectively received by the input node pair of the switched capacitor integrator 10 and stored in the input capacitor pair C1_1 and C1_2. When the input switch pair SW1_1 and SW1_2 are turned on, the input signals Vrst+Vsig and Vrst can be transmitted to the floating nodes x and y respectively. The amplifier 100 can receive the input signals Vrst+Vsig and Vrst, and amplify the sensing signal component Vsig to generate a differential output signal VOP-VON.

[0030] Specifically, according to the operation of the input switch pair SW1_1 and SW1_2 and the reset switch pair SW2_1 and SW2_2 of the switch, the switched capacitor integrator 10 has two operation phases, a reset phase and a conversion phase. Figure 2A and 2B The states of the switched capacitor integrator 10 in the reset phase and the conversion phase are shown respectively. Figure 2A As shown, in the reset phase, the input switch pair SW1_1 and SW1_2 are closed and the reset switch pair SW2_1 and SW2_2 are opened. The opened reset switch pair SW2_1 and SW2_2 can connect the floating nodes x and y to the output node of the switched capacitor integrator 10, so that the voltages of the floating nodes x and y are reset to a common-mode voltage Vcom of the switched capacitor integrator 10, and the common-mode voltage Vcom can be set to a fixed voltage value.

[0031] like Figure 2B As shown, in the conversion phase, the reset switch pair SW2_1 and SW2_2 are closed and the input switch pair SW1_1 and SW1_2 are opened. The opened input switch pair SW1_1 and SW1_2 can couple the input signal pair Vrst+Vsig and Vrst to the floating nodes x and y respectively, so that the amplifier 100 can amplify and convert the sensing signal Vsig.

[0032] The detailed operation of the switched capacitor integrator 10 is described as follows. The total charge of the floating nodes x and y at different stages is observed. In the reset stage, the total charge of the floating node x, q x and the total charge q of the floating node y y They are:

[0033] q x =Cp×Vcom;

[0034] q y =Cp×Vcom.

[0035] During the conversion phase, the total charge q on the floating node x x and the total charge q of the floating node y y They are:

[0036] q x =C1·Vx+C2·(Vx-VON)+C3·(Vx-VON)+Cp·Vx;

[0037] q y =C1·Vx+C2·(Vx-VOP)+C3·(Vx-VON)+Cp·Vx.

[0038] Considering that floating nodes x and y must comply with the charge conservation from the reset phase to the conversion phase, the following equation can be obtained:

[0039] C1·(Vrst+Vsig)+Cp·Vcom=C1·Vx+C2·(Vx-VON)+C3·(Vx-VON)+Cp·Vx; (1)

[0040] C1·Vrst+Cp·Vcom=C1·Vx+C2·(Vx-VOP)+C3·(Vx-VON)+Cp·Vx; (2)

[0041] Wherein, C1 is the capacitance of the input capacitor pair C1_1 and C1_2, C2 is the capacitance of the feedback capacitor pair C2_1 and C2_2, C3 is the capacitance of the compensation capacitor pair C3_1 and C3_2, Cp is the capacitance of the parasitic capacitor Cp, and Vx is the voltage of the floating nodes x and y. It should be noted that the input terminals of the amplifier 100 are in a virtually short-circuited state, so that the voltage levels of the floating nodes x and y are equal. Subtracting equation (2) from equation (1) or subtracting equation (1) from equation (2) can obtain the differential output signal VOP-VON as follows:

[0042]

[0043] According to the circuit structure of the switched capacitor integrator 10 and the above formula derivation, the amplifier 100, the input capacitor pair C1_1 and C1_2, and the feedback capacitor pair C2_1 and C2_2 work together to determine the differential output signal VOP-VON according to the opening or closing of the input switch pair SW1_1 and SW1_2 and the reset switch pair SW2_1 and SW2_2. The switched capacitor integrator 10 also includes a compensation capacitor pair C3_1 and C3_2, which is used to reduce or eliminate the correlation between the floating nodes x and y and the signal size without changing the output signal value. More specifically, the compensation capacitor pair C3_1 and C3_2 can reduce or eliminate the voltage swing generated on the floating nodes x and y due to the change in the received sensing signal caused by the different brightness sensed by the light-emitting diode. Meanwhile, the transfer function of the switched capacitor integrator 10 is not affected by the compensation capacitor pair C3_1 and C3_2. In other words, the compensation capacitor pair C3_1 and C3_2 do not change the correlation between the sensing signal Vsig and the differential output signal VOP-VON, as shown in equation (3).

[0044] The operation of the compensation capacitor pair C3_1 and C3_2 can be used to reduce or eliminate the signal correlation of the floating nodes x and y, as described in the following paragraphs. Due to common-mode feedback, the output signals VOP and VON and the common-mode voltage Vcom have the following relationship:

[0045] VOP+VON=2·Vcom;

[0046] available:

[0047]

[0048]

[0049] Substituting equations (4) and (5) into equation (1) or equation (2) yields:

[0050]

[0051] The above equation can be rewritten as the following relationship to obtain the voltage Vx of the floating nodes x and y:

[0052]

[0053] Equation (6) shows that the voltage Vx of the floating nodes x and y includes a reset-related component (related to Vrst), a common-mode voltage component (related to Vcom), and a signal-related component (related to Vsig). It is worth noting that the reset signal Vrst is a predetermined signal received during the reset period of the sensing pixel, which has a fixed value, and the common-mode voltage Vcom is a predetermined voltage of the switched capacitor integrator 10, which also has a fixed value. Therefore, the reset-related component and the common-mode voltage component are constant. However, the change of the sensing signal Vsig causes the signal-related component to be variable, making the voltage Vx of the floating nodes x and y variable, and when the sensing signal Vsig changes significantly, it may cause the voltage Vx to exceed the normal operating voltage range of the switched capacitor integrator 10. Therefore, a compensation capacitor pair C3_1 and C3_2 can be used to reduce the signal-related component. As shown in equation (6), the signal-related component A minus term -C3 is included, indicating that the signal-related component can be eliminated or compensated by the compensation capacitor pair C3_1 and C3_2. In one embodiment, the capacitance value C3 can be set equal to the capacitance value C2 to completely eliminate the signal-related component. Substituting the equation C2 = C3 into equation (6) yields the following result:

[0054]

[0055] As shown in equation (7), the voltage Vx of the floating nodes x and y does not have any signal-related components. In other words, the value of the voltage Vx is independent of the sensing signal Vsig and is not affected by the change in the sensing signal Vsig.

[0056] On the other hand, in a switched capacitor integrator without the compensation capacitor pair C3_1 and C3_2, the voltage value of the floating node is affected by the sensing signal Vsig. For example, considering the circuit structure after removing the compensation capacitor pair C3_1 and C3_2 in the switched capacitor integrator 10, the voltage Vx of the floating nodes x and y can be obtained as follows:

[0057]

[0058] It should be noted that equation (8) is obtained by substituting C3 = 0 into equation (6). It can be seen that, without including the compensation capacitor pair, the voltage Vx has a signal-related component 0.5·C1·Vsig.

[0059] As described above, the charge injection problem is more serious due to the change in the sensing signal Vsig received by the switched capacitor integrator 10. For example, the voltage change of the floating nodes x and y may lead to the deterioration of the charge injection problem. Generally speaking, the operation of the switched capacitor integrator 10 is based on the switching of the switch circuit including the input switch pair SW1_1 and SW1_2 and the reset switch pair SW2_1 and SW2_2. These switches themselves have charge injection when they are turned on. Under the ideal differential structure, the effect of charge injection can be eliminated in the differential output signal VOP-VON. However, due to the mismatch of the differential structure, the difference between the positive and negative ends of the charge injection effect is amplified, thereby generating unpredictable errors on the output signal VOP-VON. In addition, the amount of charge injection is highly related to the change in charge. For example, if there is a large voltage change on the floating nodes x and y, the parasitic capacitor Cp needs to be continuously charged and discharged, resulting in more changes in the charge injection effect. Therefore, in order to better control the impact of charge injection on the output signal VOP-VON, preferably, the voltage variation of the floating nodes x and y should be reduced or eliminated, and the compensation capacitor pair C3_1 and C3_2 can achieve this goal. In this way, the charge injection problem associated with the switched capacitor operation can be improved by setting the compensation capacitor pair C3_1 and C3_2.

[0060] It is worth noting that the purpose of the present invention is to provide a compensation capacitor pair that can be set in a switched capacitor integrator to reduce or eliminate the signal-related component of the voltage on the floating node, so that the voltage of the floating node is independent of the signal change and maintained within a smaller voltage range. Those skilled in the art may make modifications or changes accordingly, without limitation. For example, in the above embodiment, the capacitance value C3 of the compensation capacitor pair C3_1 and C3_2 is set to be equal to the capacitance value C2 of the feedback capacitor pair C2_1 and C2_2 to completely eliminate the signal-related component. However, the capacitance value C3 does not need to be set to be equal to C2. As long as there is a compensation capacitor pair coupled to the floating node in the switched capacitor integrator, the signal-related component of the voltage of the floating node can be reduced to a certain extent. As shown in equation (6), even when the value C3 is less than C2, the subtraction term -C3 can still reduce the magnitude of the signal correlation. In addition, in the above embodiment, the compensation capacitor pair can be used for the switched capacitor integrator; but in another embodiment, the compensation capacitor pair can also be used for other types of signal processing circuits. As long as the signal processing circuit has a differential structure, a compensation capacitor pair can be set to reduce or eliminate the voltage variation and signal correlation at a specific node.

[0061] In another embodiment, the compensation capacitor pair may also be implemented in other ways. For example, please refer to Figure 3 , Figure 3 FIG. 2 is a schematic diagram of another switched capacitor integrator 30 according to an embodiment of the present invention. The structure of the switched capacitor integrator 30 is similar to that of the switched capacitor integrator 10, so signals or components with similar functions are represented by the same symbols. Figure 3 As shown, the difference between the switched capacitor integrator 30 and the switched capacitor integrator 10 is that in the switched capacitor integrator 30, the sensing signal plus the reset signal Vrst+Vsig is received by the lower input node of the switched capacitor integrator 30 and transmitted to the floating node y and the negative input terminal of the amplifier 100, while the upper input node of the switched capacitor integrator 30 and the positive input terminal of the amplifier 100 receive the reset signal Vrst (without receiving the sensing signal Vsig). In this case, the compensation capacitors C3_1 and C3_2 are coupled to the positive output terminal of the amplifier 100 for outputting the output signal VOP. On the other hand, as Figure 1 As shown, in the switched capacitor integrator 10, the sense signal plus the reset signal Vrst+Vsig is received by the upper input node of the switched capacitor integrator 10 and transferred to the floating node x and the positive input terminal of the amplifier 100, while the lower input node of the switched capacitor integrator 10 and the negative input terminal of the amplifier 100 receive the reset signal Vrst but do not receive the sense signal Vsig. In this case, the compensation capacitors C3_1 and C3_2 are coupled to the negative output terminal of the amplifier 100 for outputting the output signal VON.

[0062] The compensation capacitors C3_1 and C3_2 in the switched capacitor integrator 30 can stabilize the floating node voltage by reducing or eliminating the signal-related components of the voltages of the floating nodes x and y. In other words, the compensation capacitors C3_1 and C3_2 in the switched capacitor integrator 30 can achieve the same effect as the compensation capacitors C3_1 and C3_2 in the switched capacitor integrator 10. The relevant operation method can be referred to the description in the previous paragraph, which will not be repeated here.

[0063] Please refer to Figure 4 , Figure 4 FIG. 4 is a schematic diagram of another switched capacitor integrator 40 according to an embodiment of the present invention. The structure of the switched capacitor integrator 40 is similar to that of the switched capacitor integrator 10, so signals or components with similar functions are represented by the same symbols. Figure 4 As shown, the difference between the switched capacitor integrator 40 and the switched capacitor integrator 10 is that in the switched capacitor integrator 40, the feedback capacitor C2_1 and the compensation capacitor C3_1 originally located in the switched capacitor integrator 10 are combined into a single capacitor C2_1+C3_1. Figure 1As shown, the feedback capacitor C2_1 and the compensation capacitor C3_1 are coupled between the floating node x and the upper output node of the switched capacitor integrator 10. Without affecting the operation of the capacitors and the switched capacitor integrator, the two capacitors can be combined into a single capacitor whose capacitance is equal to the sum of the capacitances of the original two capacitors.

[0064] Please refer to Figure 5 , Figure 5 FIG. 5 is a schematic diagram of another switched capacitor integrator 50 according to an embodiment of the present invention. The structure of the switched capacitor integrator 50 is similar to that of the switched capacitor integrator 10, so signals or components with similar functions are represented by the same symbols. Figure 5 As shown, the difference between the switched capacitor integrator 50 and the switched capacitor integrator 10 is that in the switched capacitor integrator 50, the compensation capacitors C3_1 and C3_2 are coupled to a reference node instead of the output node of the switched capacitor integrator 50. More specifically, the compensation capacitor C3_1 is coupled between the floating node x and the reference node, and the compensation capacitor C3_2 is coupled between the floating node y and the reference node. The compensation capacitors C3_1 and C3_2 can receive a reference voltage Vref from the reference node.

[0065] The reference voltage Vref may have any suitable voltage value to reduce or eliminate the voltage variation and signal correlation of the floating nodes x and y. In one embodiment, the reference voltage Vref may be set equal to zero potential. When Vref=0 is set, the voltage Vx of the floating nodes x and y may be obtained by similar calculation as follows:

[0066]

[0067] Comparing the equation (9) corresponding to the structure of the switched capacitor integrator 50 with the equation (8) corresponding to the structure without the compensation capacitor, it can be seen that the numerators of both equations also include the signal-related component 0.5·C1·Vsig, but the denominator of equation (9) includes the capacitance value C3 and has a larger value. The increase in the denominator reduces the signal correlation of the voltage Vx (under the same signal-related component 0.5·C1·Vsig). In this case, the voltage change of the floating nodes x and y caused by the change of the sensing signal can be reduced.

[0068] In summary, the present invention provides a signal processing circuit, which includes a pair of compensation capacitors, which are coupled between a floating node and an output node of the signal processing circuit or between a floating node and a reference node. The compensation capacitor can reduce or eliminate the voltage variation and signal correlation on the floating node of the signal processing circuit, and can avoid the voltage of the floating node from having a large voltage variation caused by the sensing signal, so as to control the floating node to maintain a smaller voltage range, so that the signal processing circuit operates within a normal voltage range. With the reduction of the voltage variation of the floating node, the charge injection problem associated with the operation of the switched capacitor can also be improved.

[0069] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A signal processing circuit having a pair of input nodes and a pair of output nodes, the signal processing circuit comprising: a first switch pair coupled between the pair of input nodes and a plurality of floating nodes; a second switch pair coupled between the plurality of floating nodes and the pair of output nodes; an amplifier coupled between the plurality of floating nodes and the pair of output nodes; a first compensation capacitor coupled between a first floating node among the plurality of floating nodes and a first output node among the pair of output nodes without switching, wherein a first end of the first compensation capacitor is coupled to the first floating node, and a second end of the first compensation capacitor is coupled to the first output node; and A second compensation capacitor is coupled between a second floating node among the plurality of floating nodes and the first output node without switching, wherein a first end of the second compensation capacitor is coupled to the second floating node, and a second end of the second compensation capacitor is coupled to the first output node.

2. The signal processing circuit according to claim 1, characterized in that The first compensation capacitor and the second compensation capacitor are used to reduce a signal-related component in a voltage of the plurality of floating nodes.

3. The signal processing circuit according to claim 1, characterized in that: Also includes: A feedback capacitor pair is coupled between the plurality of floating nodes and the pair of output nodes.

4. The signal processing circuit according to claim 3, characterized in that: The capacitance values ​​of the first compensation capacitor and the second compensation capacitor are equal to the capacitance value of the feedback capacitor pair, so as to eliminate a signal-related component in a voltage of the plurality of floating nodes.

5. The signal processing circuit according to claim 1, wherein: Also includes: An input capacitor pair is coupled to the pair of input nodes.

6. The signal processing circuit according to claim 1, characterized in that: The amplifier includes a positive input terminal, a negative input terminal, a negative output terminal and a positive output terminal, wherein the positive input terminal is coupled to the first floating node, the negative input terminal is coupled to the second floating node, the negative output terminal is coupled to the first output node of the signal processing circuit, and the positive output terminal is coupled to a second output node of the pair of output nodes of the signal processing circuit.

7. The signal processing circuit according to claim 6, characterized in that: The amplifier receives a sensing signal plus a reset signal from a first input node of the pair of input nodes through the positive input terminal, and receives the reset signal but does not receive the sensing signal from a second input node of the pair of input nodes through the negative input terminal, and the first compensation capacitor and the second compensation capacitor are coupled to the negative output terminal of the amplifier.

8. The signal processing circuit according to claim 6, characterized in that: The amplifier receives a sensing signal plus a reset signal from a first input node of the pair of input nodes through the negative input terminal, and receives the reset signal but does not receive the sensing signal from a second input node of the pair of input nodes through the positive input terminal, and the first compensation capacitor and the second compensation capacitor are coupled to the positive output terminal of the amplifier.

9. The signal processing circuit according to claim 1, characterized in that: In a reset phase, the first switch pair is turned off and the second switch pair is turned on to reset the voltages of the plurality of floating nodes to a common mode voltage.

10. The signal processing circuit according to claim 1, characterized in that: In a conversion phase, the second switch pair is closed and the first switch pair is opened to couple an input signal pair of the signal processing circuit to the plurality of floating nodes.

11. A signal processing circuit having a pair of input nodes and a pair of output nodes, the signal processing circuit comprising: a first switch pair coupled between the pair of input nodes and a plurality of floating nodes; a second switch pair coupled between the plurality of floating nodes and the pair of output nodes; an amplifier coupled between the plurality of floating nodes and the pair of output nodes; a first compensation capacitor coupled between a first floating node among the plurality of floating nodes and a reference node without switching; as well as A second compensation capacitor is coupled between a second floating node among the plurality of floating nodes and the reference node without being switched.

12. The signal processing circuit according to claim 11, characterized in that: The first compensation capacitor and the second compensation capacitor are used to reduce a signal-related component in a voltage of the plurality of floating nodes.

13. The signal processing circuit according to claim 11, characterized in that: Also includes: A feedback capacitor pair is coupled between the plurality of floating nodes and the pair of output nodes.

14. The signal processing circuit according to claim 11, characterized in that: The first compensation capacitor and the second compensation capacitor are used to receive a zero potential from the reference node.

15. The signal processing circuit according to claim 11, characterized in that: Also includes: An input capacitor pair is coupled to the pair of input nodes.

16. The signal processing circuit according to claim 11, characterized in that: The amplifier includes a positive input terminal, a negative input terminal, a negative output terminal and a positive output terminal, wherein the positive input terminal is coupled to the first floating node, the negative input terminal is coupled to the second floating node, the negative output terminal is coupled to a first output node of the pair of output nodes of the signal processing circuit, and the positive output terminal is coupled to a second output node of the pair of output nodes of the signal processing circuit.

17. The signal processing circuit according to claim 16, characterized in that: The amplifier receives a sensing signal plus a reset signal from a first input node of the pair of input nodes through the positive input terminal, and receives the reset signal but does not receive the sensing signal from a second input node of the pair of input nodes through the negative input terminal.

18. The signal processing circuit according to claim 16, characterized in that: The amplifier receives a sensing signal plus a reset signal from a first input node of the pair of input nodes through the negative input terminal, and receives the reset signal but does not receive the sensing signal from a second input node of the pair of input nodes through the positive input terminal.

19. The signal processing circuit according to claim 11, characterized in that: In a reset phase, the first switch pair is turned off and the second switch pair is turned on to reset the voltages of the plurality of floating nodes to a common mode voltage.

20. The signal processing circuit according to claim 11, characterized in that In a conversion phase, the second switch pair is closed and the first switch pair is opened to couple an input signal pair of the signal processing circuit to the plurality of floating nodes.

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