Electrostatic removal method and substrate processing device

Abstract

The present invention provides a method for removing static electricity and a substrate processing device. The method for removing static electricity includes: a step of introducing gas into a processing container in a state where a substrate is placed on an electrostatic chuck; a step of applying a DC voltage to an adsorption electrode of the electrostatic chuck while increasing the absolute value of the DC voltage until discharge based on the gas starts; a step of applying the absolute value of the DC voltage so that the charge amount of the substrate reaches a charge neutralization region that is 0 or close to 0 after the discharge based on the gas starts; and a step of applying the absolute value of the DC voltage until the charge neutralization region is reached, and then detaching the substrate from the electrostatic chuck. The present invention can fully remove static electricity from residual adsorption of the substrate.

Description

Technical Field

[0001] The present invention relates to a static elimination method and a substrate processing device. Background Art

[0002] For example, Patent Document 1 provides a method for obtaining the magnitude and polarity of the residual charge on the surface of the electrostatic chuck based on monitoring results such as the pressure of a heat-conducting gas supplied to the back side of the substrate when a substrate is detached from an electrostatic chuck, and applying a voltage of the same magnitude and opposite polarity as the residual charge to the chuck electrode to detach the substrate.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2013-149935. Summary of the invention

[0006] Technical problem to be solved by the invention

[0007] However, in the static elimination method of calculating the residual charge amount and applying a voltage of the same magnitude and opposite sign as the calculated residual charge amount to the chuck electrode, residual adsorption of the substrate caused by the residual charge of the electrostatic chuck may not be sufficiently eliminated.

[0008] The present invention provides a technology capable of sufficiently removing static electricity from residual adsorption on a substrate.

[0009] Technical solutions to the problem

[0010] According to one aspect of the present invention, a static elimination method is provided, which includes: a step of introducing gas into a processing container with a substrate placed on an electrostatic chuck; a step of applying a DC voltage to an adsorption electrode of the electrostatic chuck while increasing the absolute value of the DC voltage until discharge based on the gas begins; a step of applying the absolute value of the DC voltage so that the charge of the substrate reaches a charge neutralization region of 0 or close to 0 after the discharge based on the gas begins; and a step of applying the absolute value of the DC voltage until the charge neutralization region is reached, and then detaching the substrate from the electrostatic chuck.

[0011] Effects of the Invention

[0012] According to one aspect, residual adsorption on the substrate can be sufficiently eliminated. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a schematic cross-sectional view showing an example of a substrate processing apparatus according to an embodiment.

[0014] Figure 2A schematic diagram and an equivalent circuit showing discharge between a wafer and an upper electrode according to one embodiment.

[0015] Figure 3 This is a diagram showing an example of HV voltage control and wafer charge amount adjustment according to one embodiment.

[0016] Figure 4 This is a diagram showing an example of adjustment of the positive and negative residual charge amount and the chip charge amount according to one embodiment.

[0017] Figure 5 This is a diagram showing an example of HV voltage control and wafer charge amount according to one embodiment.

[0018] Figure 6 This is a diagram showing an example of a discharge voltage according to an embodiment.

[0019] Figure 7 This is a timing chart showing an example of the static elimination and separation process according to one embodiment.

[0020] Figure 8 This is a diagram showing an example of an execution cycle of the static elimination and separation process according to one embodiment.

[0021] Fig. 9 This is a flowchart showing an example of wafer processing including a static elimination step and a release step according to one embodiment.

[0022] Fig.10 This is a diagram showing an example of an induced current generated by displacement of a wafer according to an embodiment.

[0023] Fig.11 This is a diagram showing an example of a device model for calculating the residual charge amount according to one embodiment.

[0024] Description of Reference Numerals

[0025] 1: Substrate processing device

[0026] 10: Processing Containers

[0027] 20: mounting table (lower electrode)

[0028] 22: Electrostatic chuck

[0029] 23: Adsorption electrode

[0030] 24: Base material of electrostatic chuck

[0031] 25: Edge Ring

[0032] 32: No. 1 high frequency power supply

[0033] 34: Second high frequency power supply

[0034] 36: Power supply

[0035] 37: Switch

[0036] 40: Gas shower head (upper electrode)

[0037] 42: Diffusion Chamber

[0038] 50: Gas supply source

[0039] 65: Exhaust

[0040] 80: Phase detector

[0041] 81: Current Amplifier

[0042] 82: Pin driver

[0043] 90: Lifting pin

[0044] 100: Control Department DETAILED DESCRIPTION

[0045] Hereinafter, the mode for implementing the present invention will be described with reference to the accompanying drawings. In each of the drawings, the same components are denoted by the same reference numerals, and duplicate descriptions may be omitted.

[0046] [Configuration of substrate processing apparatus]

[0047] First, refer to Figure 1 , an example of the structure of the substrate processing device 1 is described. Figure 1 1 is a schematic cross-sectional view showing an example of a substrate processing apparatus 1 according to an embodiment. The substrate processing apparatus 1 according to the present embodiment is a capacitive coupling type parallel plate substrate processing apparatus, and has a substantially cylindrical processing container 10. Anodizing (anodizing) is performed on the inner surface of the processing container 10. A processing chamber is formed inside the processing container 10 in which a plasma processing such as etching processing and film forming processing can be performed using plasma.

[0048] The mounting table 20 is for mounting a wafer W as an example of a substrate. The mounting table 20 is formed of, for example, aluminum (Al), titanium (Ti), silicon carbide (SiC), etc. The mounting table 20 also functions as a lower electrode.

[0049] An electrostatic chuck 22 for electrostatically adsorbing the wafer W is provided on the upper side of the mounting table 20. The electrostatic chuck 22 is a structure in which an adsorption electrode 23 is sandwiched between dielectric substrates 24. The adsorption electrode 23 is connected to a power source 36 via a switch 37. When a DC voltage (hereinafter also referred to as "HV voltage") is applied to the adsorption electrode 23 from the power source 36, the wafer W is adsorbed to the electrostatic chuck 22 by the Coulomb force.

[0050] An annular edge ring 25 (also called a focus ring) is placed on the outer circumference of the electrostatic chuck 22 to surround the outer edge of the wafer W. The edge ring 25 is made of silicon, for example, and has the function of converging plasma to the surface of the wafer W to improve the efficiency of plasma processing.

[0051] The stage 20 is supported by the support body 21, whereby the stage 20 is held at the bottom of the processing container 10. A refrigerant flow path may be formed inside the support body 21. In addition, a heat transfer gas may be supplied to the back side of the wafer W. The refrigerant is circulated in the refrigerant flow path, and the heat transfer gas is supplied to the back side of the wafer W, thereby controlling the temperature of the wafer W.

[0052] A high frequency electric power HF for plasma generation of a predetermined frequency is applied to the stage 20 from the first high frequency power source 32. In addition, a high frequency electric power LF for bias voltage generation of a frequency lower than the frequency of the high frequency electric power HF for plasma generation is applied to the stage 20 from the second high frequency power source 34. The first high frequency power source 32 is electrically connected to the stage 20 via the first matching device 33. The second high frequency power source 34 is electrically connected to the stage 20 via the second matching device 35. The first high frequency power source 32 applies a high frequency electric power HF of, for example, 100 MHz to the stage 20. The second high frequency power source 34 applies a high frequency electric power LF of, for example, 13.56 MHz to the stage 20.

[0053] The first matching device 33 matches the internal (or output) impedance of the first high frequency power source 32 with the load impedance. The second matching device 35 matches the internal (or output) impedance of the second high frequency power source 34 with the load impedance. In the present embodiment, the first high frequency power is applied to the mounting table 20, but it may also be applied to the gas shower head 40.

[0054] The gas shower head 40 is installed in a manner to seal the opening of the top of the processing container 10 by means of a shielding ring 11 covering the outer edge thereof. The gas shower head 40 is grounded. The gas shower head 40 may also be formed of silicon. The gas shower head 40 also functions as a counter electrode (upper electrode) facing the mounting table 20 (lower electrode).

[0055] A gas inlet 41 for introducing gas is formed in the gas shower head 40. A diffusion chamber 42 for diffusing gas is formed inside the gas shower head 40. Gas output from the gas supply source 50 is supplied to the diffusion chamber 42 through the gas inlet 41, diffused, and introduced into the processing container 10 through a plurality of gas supply holes 43.

[0056] An exhaust port 60 is formed on the bottom surface of the processing container 10, and the processing container 10 is exhausted by an exhaust device 65 connected to the exhaust port 60. In this way, the processing container 10 can be maintained at a predetermined vacuum level. A gate valve G is provided on the side wall of the processing container 10. The gate valve G is opened and closed when the wafer W is carried in and out of the processing container 10.

[0057] The substrate processing device 1 is provided with a control unit 100 for controlling the operation of the entire device. The control unit 100 has a CPU (Central Processing Unit) 105, a ROM (Read Only Memory) 110, and a RAM (Random Access Memory) 115. The CPU 105 performs the desired processing such as etching according to the scheme stored in the storage area such as the RAM 115. In the scheme, control information of the device corresponding to the processing conditions is recorded, that is, the processing time, pressure (gas exhaust), high-frequency electric power or voltage, various gas flow rates, the temperature in the processing container (upper electrode temperature, side wall temperature of the processing container, wafer W temperature, electrostatic chuck temperature, etc.), the temperature of the refrigerant, etc. In addition, the above-mentioned program or the scheme giving the processing conditions can also be stored in a hard disk or a semiconductor memory. In addition, the scheme can also be set at a predetermined position and read in a state of being stored in a portable computer-readable storage medium such as a CD-ROM or DVD.

[0058] When the wafer is transported, the gate valve G is controlled to open and close. When the wafer W is transported from the transport outlet 19 into the processing container 10, the wafer W is transferred from the transfer arm to the lift pins 90. The lift pins 90 are provided with, for example, three ( Figure 1 Only two are shown in the figure), which penetrate the mounting table 20 and support the wafer W.

[0059] The lift pins 90 are moved up and down by the drive of the pin driver 82. When the lift pins 90 are lowered and the wafer W is placed on the mounting table 20, the power supply 36 applies HV voltage to the attraction electrode 23, and the wafer W is attracted and held on the electrostatic chuck 22.

[0060] A processing gas is supplied from a gas supply source 50 into the processing container 10. A first high-frequency electric power is applied from a first high-frequency power source 32 to the mounting table 20, and a second high-frequency electric power is applied from a second high-frequency power source 34 to the mounting table 20. Thus, a predetermined plasma process is performed on the wafer W by utilizing the action of plasma generated above the wafer W and the introduction of ions.

[0061] After the plasma treatment, a predetermined HV voltage is applied to the adsorption electrode 23 from the power supply 36 to remove the charge of the wafer W. As a result, the wafer W can be detached from the electrostatic chuck 22 and sent out of the processing container 10 through the gate valve G. The next wafer W is sent in, plasma treated, and sent out in the same manner.

[0062] [Discharge between chip and upper electrode]

[0063] Reference Figure 2 , the discharge between the chip W and the upper electrode is explained. Figure 2 (a) is a schematic diagram showing discharge between the chip W and the upper electrode. Figure 2 (b) in FIG. 1 shows an equivalent circuit between the chip W and the upper electrode.

[0064] When the surface of the electrostatic chuck 22 is denatured by plasma or the like, residual charges gradually accumulate on the surface of the electrostatic chuck 22, and the wafer W is charged accordingly. As a result, residual adsorption of the wafer W occurs ( Figure 2 If the residual charge on the chip W is not sufficiently eliminated when the chip W is released (the chip charge amount q) in (b), the chip W may be cracked or damaged by the lift pins 90.

[0065] Therefore, in this embodiment, a charge removal process of the wafer W is performed, and residual charges on the surface of the electrostatic chuck 22 are removed by adjusting the charge amount (charge amount) of the wafer W (hereinafter also referred to as a "detachment process"). Thus, when the wafer W is detached from the electrostatic chuck, damage to the wafer W can be prevented.

[0066] Specifically, in the separation process, Figure 2 As shown in (a) in the figure, first, gas is filled between the wafer W and the upper electrode (gas shower head 40). When the HV voltage is applied to the adsorption electrode 23 from the power supply 36 in the state filled with gas, the voltage is applied to the wafer W. The upper electrode is grounded, so when the voltage is applied to the wafer, a potential difference is generated between the wafer and the upper electrode. When the HV voltage applied to the adsorption electrode 23 increases, according to Paschen's law, glow discharge occurs when the potential difference exceeds a prescribed threshold value according to the pressure in the processing container 10. As a result, electrons move from the upper electrode to the wafer W. Therefore, by controlling the HV voltage after starting the glow discharge, the supply of charge to the wafer W and / or the discharge of charge from the wafer W can be continuously controlled. Thus, by adjusting the amount of charge on the wafer W, the residual charge on the surface of the electrostatic chuck 22 can be eliminated.

[0067] like Figure 2As shown in the equivalent circuit of (b) in FIG. 1 , the HV voltage applied from the power supply 36 to the adsorption electrode 23 is represented by V. The potential difference between the wafer W and the upper electrode (ground) is represented by the wafer potential V0, and the potential difference between the wafer and the adsorption electrode 23 is represented by V1.

[0068] In addition, q represents the charge of the wafer. C1 represents the electrostatic capacitance of the electrostatic chuck 22, and C0 represents the electrostatic capacitance of the space between the wafer filled with gas and the upper electrode. In addition, the discharge start voltage between the wafer W and the upper electrode is V th .

[0069] V=V0+V1……(a)

[0070] q=C0V0-C1V1……(b)

[0071] Formula (c) is derived from formula (a) and formula (b).

[0072] V0=(C1V-q) / (C0+C1)……(c)

[0073] According to formula (c), when the HV voltage V is increased, the chip potential V0 rises, and when the HV voltage V is reduced, the chip potential V0 decreases. However, when the chip potential V0 reaches the discharge start voltage, discharge occurs between the chip W and the upper electrode, and electrons begin to move between the chip W and the upper electrode. Then, when the HV voltage is further increased, electrons move from the upper electrode to the chip W side, and the chip charge q increases. As a result, power can be supplied to the chip W.

[0074] [Adjustment of the wafer charge amount when there is no residual charge]

[0075] Reference Figure 3 , the adjustment of the chip charge amount when there is no residual charge on the electrostatic chuck 22 is described. Figure 3 This is a diagram showing an example of HV voltage control and wafer charge amount adjustment according to one embodiment. Figure 3 (a) in FIG. 3 represents the charge amount of the wafer corresponding to the HV voltage supplied from the power supply 36. Figure 3 (b) in FIG. 1 represents the chip potential corresponding to the HV voltage.

[0076] When there is no residual charge on the electrostatic chuck 22, Figure 3 The chip charge amount shown in (a) is "0" to Figure 3 When the HV voltage is increased as shown in (1) below, Figure 3 The chip potential shown in (b) in FIG. 1 increases monotonically. Figure 3 At the moment shown in (2) in FIG. 1 , the chip potential reaches the discharge start voltage, and the chip potential stops rising when DC discharge starts. Figure 3 The discharge start voltage shown in (2) is denoted as V th .

[0077] DC discharge occurs, and the chip potential stabilizes at the discharge start voltage V th , discharge or power the chip according to the HV voltage. Figure 3 By controlling the HV voltage to an appropriate value as shown in (3) in FIG. Figure 3 As shown by the arrow in (a), the chip charge amount is continuously adjusted according to the HV voltage. In addition, when the chip charge amount has a negative value, the chip charge amount can also be continuously adjusted according to the HV voltage.

[0078] [Adjustment of wafer charge when residual charge exists]

[0079] Below, refer to Figure 4 , the adjustment of the chip charge amount when there is residual charge on the electrostatic chuck 22 is described. Figure 4 This is a diagram showing an example of the positive and negative charging (residual charge amount) of a chip and the adjustment of the chip charge amount according to one embodiment. Figure 4 (a) and (b) in FIG. 1 show the sheet charge amount and the chip potential corresponding to the HV voltage when the chip W is negatively charged (−5 μC) due to residual charge existing in the electrostatic chuck 22 . Figure 4 (c) and (d) in FIG. 1 represent the chip charge amount and chip potential corresponding to the HV voltage when the chip W is positively charged (5 μC) due to the presence of residual charge on the electrostatic chuck 22 .

[0080] When the chip W is negatively charged (-5μC), Figure 4 As shown by the arrow in (a), the HV voltage increases from the discharge start voltage V at which glow discharge starts. th When controlled in the positive direction, the charge neutralization point P is reached. In this specification, the "charge neutralization point" refers to the point where the chip charge becomes 0, that is, the chip charge is adjusted by controlling the HV voltage to discharge and / or supply power to the chip, thereby eliminating the residual charge of the electrostatic chuck 22.

[0081] When residual adsorption occurs on the wafer W, electric charge remains on the surface of the electrostatic chuck 22. As a result, the wafer W on the electrostatic chuck 22 has an electric charge opposite in sign to the residual electric charge on the electrostatic chuck 22. In the present embodiment, the HV voltage is controlled to adjust so that the amount of electric charge on the wafer becomes 0.

[0082] When the residual charge amount of the wafer W is negative, the HV voltage is controlled in the positive direction. Figure 4In (a), since the chip W is charged with -5μC, the HV voltage is controlled in the positive direction. In this way, electrons are supplied from the upper electrode to the chip W, and when the HV voltage of about 700V is applied to the adsorption electrode 23, the chip charge becomes 0, and the residual charge of the electrostatic chuck 22 is eliminated.

[0083] On the contrary, when the residual charge amount of the wafer W is positive, the HV voltage is controlled in the negative direction. Figure 4 In (c), since the chip W is charged with 5μC, the HV voltage is controlled in the negative direction. In this way, electrons are released from the chip W to the upper electrode, and when the HV voltage of about -700V is applied to the adsorption electrode 23, the chip charge becomes 0, and the residual charge of the electrostatic chuck 22 is eliminated.

[0084] As described above, when the HV voltage V is gradually increased or decreased, the charge neutralization point can be reached. By adjusting the charge amount of the wafer based on the control of the HV voltage, residual adsorption of the wafer W can be avoided. Figure 4 As an example, the electrostatic capacitance C0 of the space between the wafer W and the upper electrode is set to 100 [pF], the electrostatic capacitance C1 of the electrostatic chuck 22 is set to 10 [nF], and the discharge start voltage V th The simulation was performed with the voltage set to 500 [V].

[0085] An example of control that cyclically changes the HV voltage V by gradually increasing or decreasing is Figure 5 Indicated in. Figure 5 This is a diagram showing an example of the charge amount of the wafer when the HV voltage V is controlled to be gradually increased or decreased.

[0086] In (A), the HV voltage is controlled in the positive direction from the state where the chip charge amount is 0, so that the HV voltage increases.

[0087] In (B), the chip potential reaches the positive discharge start voltage V th Then, discharge starts, and negative charges (electrons) are supplied from the upper electrode to the wafer W, and the charge amount of the wafer (here, the negative charge amount) increases.

[0088] In (C), the HV voltage V is reduced. When the HV voltage V is reduced, the wafer potential is reduced, so discharge is not caused.

[0089] In (D), the chip potential reaches the negative discharge start voltage -V th Then, discharge starts, and negative charges (electrons) are released from the wafer W to the upper electrode.

[0090] In (E), the HV voltage V is increased. When the HV voltage V is increased, the wafer potential increases, thereby causing discharge.

[0091] In (F), the chip potential reaches the positive discharge start voltage V th Then, discharge starts, and negative charges (electrons) are supplied to the wafer W from the upper electrode.

[0092] [Discharge start voltage]

[0093] Below, refer to Figure 6 , the discharge start voltage V th Provide explanation. Figure 6 This is a diagram showing an example of a discharge voltage corresponding to the pressure in the processing container 10 according to one embodiment. Figure 6 Indicates that the "discharge start voltage V" used in the HV voltage control is obtained in advance. th An example of experimental results for the appropriate value of ”. Figure 6 The horizontal axis is the pressure in the processing container 10, and the vertical axis is the discharge voltage. Figure 6 The experimental results can be used to infer the actual flow rate of gas supplied to the processing container 10 and the pressure in the processing container 10 to control the discharge based on Paschen's law, that is, whether the discharge start voltage V can be reduced. th According to the experimental results, the discharge voltage is low on both the positive side and the negative side in the range of 200 to 800 mTorr. That is, it is known that the discharge start voltage V is low when the gas is supplied so that the pressure in the processing container 10 is in the range of 200 to 800 mTorr. th It becomes lower, making it easier to adjust the chip charge amount.

[0094] [Electrical removal process / de-staticization process]

[0095] The static elimination method of this embodiment includes the above-described release step of adjusting the charge amount of the wafer based on the control of the HV voltage. Figure 7 and Figure 8 The outline of the static elimination process and the separation process is described. Figure 7 This is a timing chart showing an example of a static elimination step and a release step according to an embodiment. Figure 8 This is a diagram showing an example of an execution cycle of a static elimination step and a release step after wafer processing according to an embodiment.

[0096] like Figure 7 As shown, the detachment process is performed after the de-staticization process after the wafer processing and before the lift pins 90 are raised in order to detach the wafer W from the electrostatic chuck 22. Figure 7As shown, in the destaticization process, the HV voltage is turned off to release the electrostatic adsorption of the electrostatic chuck 22 to the wafer W. In the destaticization process, after the HV voltage is turned off, an inactive gas may be supplied into the processing container 10 while an HV voltage of the same magnitude and opposite in sign to the HV voltage applied when the wafer W is processed is applied.

[0097] Then, when the desorption process starts, a predetermined gas (inert gas, etc.) is supplied into the processing container 10 so that the pressure in the processing container 10 becomes a preset value within the range of 200 to 800 mTorr. th becomes an appropriate value.

[0098] In the detachment process, the charge amount of the wafer is adjusted by controlling the HV voltage to avoid the residual adsorption state of the wafer W caused by the wafer W being positively or negatively charged due to the residual charge on the surface of the electrostatic chuck 22 even after the de-electrification process. When the HV voltage is set to V, the HV voltage controlled in the adjustment of the wafer charge amount is expressed by the following formula (d).

[0099] q=C1V-(C0+C1)V th ...(d)

[0100] From equation (d), equation (e) can be derived.

[0101]

[0102] like Figure 4 As shown, when the HV voltage is controlled in the positive direction when the wafer W is negatively charged, the charge neutralization point P is reached. When the HV voltage is controlled in the negative direction when the wafer W is positively charged, the charge neutralization point P is reached. At the charge neutralization point P, the residual charge on the surface of the electrostatic chuck 22 is eliminated and the charge amount of the wafer is 0. By controlling the HV voltage to the charge neutralization point P so that the charge amount of the wafer W is 0, it is possible to avoid damage to the wafer W when the wafer W is detached.

[0103] In addition, in the release process, the HV voltage is not limited to being controlled to the charge neutralization point P. The absolute value of the HV voltage may be gradually applied until a charge neutralization region is reached where the charge amount of the wafer W becomes 0 or close to 0 after the discharge starts. The charge neutralization region may be a region where the voltage relative to the charge neutralization point P is within a predetermined range.

[0104] For example, when the electrostatic capacitance C1 between the adsorption electrode 23 and the wafer W is 10 [nF], the HV voltage may be within ±25 [V] of the voltage of the target charge neutralization point as the charge neutralization area. In this way, when the wafer W is actually adsorbed, the residual charge of the electrostatic chuck 22 can be within 1 [%] of the wafer charge. Figure 7 During the separation process, the HV voltage can also be gradually controlled to the charge neutralization point P.

[0105] like Figure 8 As shown, in the processing cycle of processing the wafer W in the substrate processing device 1, first, the wafer W is introduced into the substrate processing device 1 (step S1). Then, the HV voltage is applied from the power supply 36 to the adsorption electrode 23, so that the electrostatic chuck 22 electrostatically adsorbs the wafer W (step S2). Then, the first high-frequency electric power and the second high-frequency electric power are applied to the mounting table 20, so that the processing gas supplied from the gas supply source 50 is plasma-formed, and the wafer W is subjected to plasma processing such as etching (step S3).

[0106] Next, the lifting pins 90 are moved up and down to vibrate the wafer W. At this time, the induced current i3(t) flowing in the adsorption electrode 23 is measured, and the residual charge Q of the wafer W is calculated based on the induced current i3(t). The HV voltage reaching the neutralization point is calculated based on the residual charge Q (step S4). Hereinafter, the HV voltage reaching the neutralization point calculated based on the residual charge Q is referred to as the "target HV voltage". The induced current i3(t) can be measured after the plasma treatment of the wafer W is completed and before the static elimination process is performed.

[0107] The measured value of the torque generated when the lift pins 90 are raised after the last wafer processing is a preset first threshold value T th1 In the following cases, the normal static elimination process is performed (step S5). On the other hand, the measured value of the moment generated when the lift pins 90 are raised after the previous wafer processing is greater than the first threshold value T th1 If the value is large, it is determined that the wafer W may be damaged in the normal static elimination step. Therefore, in this case, the static elimination step and the release step of this embodiment are performed (step S6).

[0108] In the normal de-staticizing process of step S5, the HV voltage is turned off to release the adsorption of the electrostatic chuck 22 on the wafer W. In the de-staticizing process, an HV voltage of the same magnitude and opposite to the HV voltage applied when processing the wafer W may be applied while supplying an inert gas into the processing container 10. For details of the de-staticizing process and de-staticizing process of this embodiment of step S6, refer to Fig. 9 Explained later.

[0109] Next, after the processing of step S5 or step S6, the lifting pins 90 are raised to separate the wafer W (step S7). At this time, the torque generated when the lifting pins 90 are raised is measured. The control unit 100 obtains the logarithmic information of the measured torque, monitors how its maximum value changes, and uses it in the next judgment processing of which processing of step S5 or step S6 is to be performed. Next, the wafer W is sent out (step S8), and the next wafer W is sent in (step S1).

[0110] Reference Fig. 9 The static elimination process and the release process (step S6) using the induced current i3(t) measured in each wafer W, which are performed through the above execution cycle, will be described in more detail. Fig. 9 The processing is mainly controlled by the control unit 100.

[0111] [Static removal method (static removal process and release process)]

[0112] Fig. 9 1 is a flowchart showing an example of a wafer processing including a static elimination method (static elimination process and release process) according to an embodiment. This process is controlled by the CPU 105 of the control unit 100. This process is performed when the measured value of the moment generated when the lifting pins 90 are raised is greater than the first threshold value T th1 However, this is not limited to this, and this process can also be performed on all wafers W when the wafer is de-electrified. In this case, all wafers are executed Figure 8 Step S6 is performed and step S5 is not performed.

[0113] First, the CPU 105 causes the wafer W to be carried into the substrate processing device 1 (step S11). Next, the CPU 105 causes the lift pins 90 to descend, and applies a predetermined HV voltage from the power supply 36 to the adsorption electrode 23 (turning on HV), so that the electrostatic chuck 22 electrostatically adsorbs the wafer W (step S11). Next, the CPU 105 causes the gas supply source 50 to supply the processing gas, and applies the first high-frequency electric power and the second high-frequency electric power to the mounting table 20 (turning on RF), and excites the gas to ignite plasma (step S12).

[0114] Next, the CPU 105 starts a plasma process such as etching on the wafer W (step S13), and ends the process after a predetermined plasma process is performed (step S14). Next, the CPU 105 stops applying the DC voltage HV to the adsorption electrode 23 (turns off HV) (step S15).

[0115] Next, the CPU 105 moves the lift pins 90 up and down by about 0.5 mm to vibrate the wafer W (step S16). As a result, an induced current i3(t) is generated in the adsorption electrode. Next, the CPU 105 inputs the induced current i3(t) into the phase detector 80, and the phase detector 80 outputs the induced current I3 (step S17).

[0116] Next, the CPU 105 calculates the residual charge amount Q of the wafer W from the induced current I3 using equation (17) described later (step S18). Next, the CPU 105 calculates the target HV voltage for reaching the charge neutralization point based on the calculated residual charge amount Q (step S19).

[0117] Next, CPU105 supplies a specified gas into the processing container 10, and adjusts the pressure in the processing container 10 to a predetermined pressure in the range of, for example, 200mTorr to 800mTorr, so that discharge occurs (step S20). Next, CPU105 applies the target HV voltage that reaches the charge neutralization region to the adsorption electrode 23, and adjusts the charge of the chip (step S21). However, when the residual charge amount Q is negative, the HV voltage may be gradually increased in the positive direction to the target HV voltage. In addition, when the residual charge amount Q is positive, the HV voltage may be gradually decreased in the negative direction to the target HV voltage. Thus, by controlling the HV voltage, it is possible to reach the charge neutralization point P where the residual charge of the chip W is eliminated.

[0118] Next, the CPU 105 raises the lift pins 90 to release the wafer W (step S22 ). Next, the CPU 105 carries the wafer W out of the processing container 10 (step S23 ), and the present process ends.

[0119] As described above, according to the static elimination method including the detachment process of this embodiment, by controlling the HV voltage in the charge neutralization region where the chip charge is 0 or close to 0, the residual charge of the electrostatic chuck 22 can be eliminated, allowing the chip W to be detached without damage.

[0120] [Method for measuring residual charge Q]

[0121] Finally, refer to Fig.10 and Fig.11 , an example of a method for measuring the residual charge amount Q is described. Fig.10 This is a diagram showing an example of an induced current generated by displacement of a wafer according to an embodiment. Fig.11 This is a diagram showing an example of a device model for calculating the residual charge amount according to one embodiment.

[0122] After the wafer W is subjected to plasma processing, when the wafer W is to be carried out, the residual charge on the surface of the electrostatic chuck 22 causes charge to be retained on the wafer W. In this embodiment, the lift pins 90 are moved up and down in this state. The signal for moving the lift pins 90 up and down (hereinafter referred to as the "reference signal") is controlled by the control unit 100 and input to the pin driver 82. The pin driver 82 is driven according to the input of the reference signal, thereby moving the lift pins 90.

[0123] As described later, the amplitude of the reference signal may be 1 mm or less when converted into distance, and preferably 0.5 mm or less when converted into distance. In addition, the frequency of the reference signal is preferably 1 Hz or more and 10 Hz or less.

[0124] When the lift pins 90 are moved and the wafer W is displaced, an induction current flows. Fig.10 In the figure, line B represents the moving speed of the lift pins 90, and line A represents the induced current flowing with the movement of the lift pins 90. When the lift pins 90 change their moving speed from 0 mm / sec to 5 mm / sec and start to push up the wafer W, an induced current corresponding to the displacement of the wafer W begins to flow, and the maximum induced current flows to about -1.0 [μA]. At this time, whether the negative induced current flows or the positive induced current flows depends on the positive or negative charge retained on the wafer W.

[0125] At this time, the induced current flows through all electrodes facing the wafer W. That is, the induced current flows through the adsorption electrode 23 , the upper electrode, and the inner wall of the processing container 10 . Fig.10 2 is a diagram showing a measurement of the induced current generated in the adsorption electrode 23. In the present embodiment, an ammeter 46 connected to the adsorption electrode 23 is provided, and the ammeter 46 is used to measure the induced current.

[0126] In addition, Fig.10 In the example of FIG. 1 , the moving distance of the lift pins 90 is about 0.5 mm. That is, the wafer W is displaced by about 0.5 mm by the up and down movement of the lift pins 90 . Fig.11 The left side of the model shows a state where the wafer W is placed on the mounting table 20, and the right side of the model shows a state where the wafer W is lifted about 0.5 mm from the mounting table 20 by the lift pins 90. The wafer W is pushed up by the lift pins 90 and slightly rises while the wafer W is not completely separated from the electrostatic chuck 22 and is partially adsorbed by the electrostatic chuck 22 due to residual adsorption.

[0127] [Phase detection method]

[0128] The induced current is out of phase by 90° compared to the leakage current. Therefore, the phase detector 80 outputs the DC current of the induced current separately from the leakage current. In the potential measurement of metal electrodes based on the Kelvin method, a system between electrodes of arbitrary potential (for example, two electrodes (bipolar) directly connected to a power supply like a capacitor) is the object. In contrast, in the substrate processing device 1 of the present embodiment, the chip W becomes a floating electrode and is in a state where the potential cannot be determined, and the condition for potential measurement becomes only the monopole of the adsorption electrode 23. Therefore, in the substrate processing device 1 of the present embodiment, the Kelvin method cannot be used to measure the potential of the adsorption electrode 23 (monopole). Therefore, in the present embodiment, the electrostatic capacitance C is calculated according to the physical structure of the chip W and the electrostatic suction cup 22, and it is necessary to associate the potential V of the chip W with the residual charge Q.

[0129] use Fig.11 The equivalent circuit of Fig.11 The upper electrode (gas showerhead 40) containing the wafer W and the substrate 24 and the adsorption electrode 23 (bipolar) can measure the voltage between the two electrodes. However, the Kelvin method cannot measure the state of the wafer W and the adsorption electrode 23 (monopole).

[0130] In the measurement method of the present embodiment, the state of the wafer W and the adsorption electrode 23 can be directly measured. The cracking or bouncing of the wafer W is mainly caused by the residual adsorption of the wafer W due to the change in the state of the surface of the electrostatic chuck 22. In order to prevent the cracking or bouncing of the wafer W, the measurement method of the present embodiment calculates the residual charge amount Q of the wafer W before the wafer is detached from the electrostatic chuck 22, and calculates the target HV voltage based on the calculated residual charge amount Q.

[0131] In the present embodiment, the residual charge amount Q is calculated based on the DC current of the induced current output from the phase detector 80, and the target HV voltage is calculated based on the calculated residual charge amount Q. Then, by applying the target HV voltage during the detachment process, the wafer W can be detached from the electrostatic chuck 22 without causing the wafer W to break or bounce.

[0132] [Method for measuring residual charge]

[0133] Next, the calculation method of the residual charge amount Q is described. Figure 2The charge q of the chip shown is the same. When the chip W is charged, an induced current flows in the upper electrode and the adsorption electrode 23 when the chip W moves. The induced current flowing in the adsorption electrode 23 is determined by the charge of the chip and the electrostatic capacitance between the chip and the ground potential. The electrostatic capacitance between the chip and the ground potential is determined by the structure of the electrostatic chuck 22 and the structure of the processing container 10. Therefore, when the structure of the electrostatic chuck 22 and the structure of the processing container 10 are determined, the electrostatic capacitance between the chip W and the ground potential can be calculated by calculation. Therefore, the charge of the chip W is proportional to the induced current by using a value corresponding to the electrostatic capacitance between the chip and the ground potential as a proportional constant.

[0134] exist Fig.11 In the model, when the wafer W moves, an induced current flows in the adsorption electrode 23. The amount of the current is measured by the ammeter 46. An equation is obtained in which the induced current i3(t) of the adsorption electrode 23 is proportional to the residual charge Q of the wafer W. In the following equations, the subscripts for the variables are "1" for variables related to the upper electrode, "2" for variables related to the wafer, and "3" for variables related to the electrostatic chuck.

[0135] First, when the vertical movement of the wafer W is represented by a time function, the lift distance h2(t) of the wafer W by the lift pins 90 is calculated by equation (1).

[0136]

[0137] Here, A1 is the amplitude of the reference signal in the spatial dimension when the pin is vibrated (amplitude of the up and down movement of the pin), A0 is the compensation of the amplitude of the reference signal (compensation: center value of the amplitude), and ω is the angular frequency.

[0138] The distance h1(t) between the wafer and the upper electrode is calculated by equation (2).

[0139]

[0140] Here, H gap is the distance between the upper electrode surface and the electrostatic chuck surface, H wafer is the thickness of the wafer, B0 is determined by H gap -H wafer express.

[0141] The residual charge Q of the wafer is constant when no discharge occurs. Therefore, according to Coulomb's law, the residual charge Q of the wafer is expressed by equation (3).

[0142] Q=c(t)v(t)=const……(3)

[0143] Here, c(t) is the electrostatic capacitance between the chip and the ground, and v(t) is the voltage between the chip and the ground.

[0144] The charge is only carried on the chip, so the voltage v(t) between the chip and the ground is calculated by equation (4).

[0145] v(t)=v1(t)=v3(t)……(4)

[0146] Here, v1(t) is the voltage between the wafer and the upper electrode, and v3(t) is the voltage between the wafer and the adsorption electrode.

[0147] The residual charge Q of the wafer is the sum of the charge q1(t) induced on the upper electrode side and the charge q3(t) induced on the adsorption electrode side. This relationship is expressed in equation (5).

[0148] Q=q1(t)+q3(t)=q2(t)……(5)

[0149] q2(t) represents the charge of the chip.

[0150] The electrostatic capacitance c(t) between the chip and the ground is calculated by equation (6).

[0151] c(t)=(c1(t)c2(t)+c2(t)C3+C3c1(t)) / (c2(t)+C3)……(6)

[0152] c1(t) is the electrostatic capacitance between the chip and the upper electrode, c2(t) is the electrostatic capacitance between the chip and the surface of the electrostatic chuck, and C3 is the electrostatic capacitance of the gap filled with dielectric between the surface of the electrostatic chuck and the adsorption electrode.

[0153] Based on equations (3) and (6), the voltage v(t) between the chip and the ground is calculated by equation (7).

[0154] v(t)=Q / c(t)=(c2(t)+C3)Q / (c1(t)c2(t)+c2(t)C3+C3c1(t))……(7)

[0155] Equation (8) is derived based on equations (5) and (7).

[0156] Q=q1(t)+q3(t)=v(t)(c1(t)c2(t)+c2(t)C3+C3c1(t)) / (c2(t)+C3)……(8)

[0157] The electrostatic capacitance between the components is expressed by equations (9) to (13).

[0158] c1(t)=ε0×S wafer / h1(t)……(9)

[0159] c1(t) is the electrostatic capacitance between the chip and the upper electrode, ε0 is the relative dielectric constant of vacuum, S wafer is the area of ​​the chip surface, and h1(t) is the distance between the chip and the upper electrode.

[0160] c2(t)=ε0×S wafer / h2(t)……(10)

[0161] c2(t) is the electrostatic capacitance between the chip and the surface of the electrostatic chuck, and h2(t) is the distance between the chip and the surface of the electrostatic chuck.

[0162] C3=ε ESC ×ε0×S wafer / h ESC ……(11)

[0163] C3 is the electrostatic capacitance of the gap filled by the dielectric layer between the electrostatic chuck surface and the adsorption electrode, ε ESC is the relative dielectric constant of the material of the electrostatic chuck, h ESC is the distance between the electrostatic chuck surface and the adsorption electrode.

[0164] c 23 (t) = ε ESC ×ε0×S wafer / (ε ESC ×h2(t)+h ESC )……(12)

[0165] c 23 (t) is the electrostatic capacitance between the chip and the adsorption electrode, and h2(t) is the push-up distance of the chip.

[0166] c(t)=ε0×S wafer / h1(t)+ε ESC ×ε0×S wafer / (ε ESC ×h2(t)+h ESC )……(13)

[0167] c(t) is the electrostatic capacitance between the chip and the ground.

[0168] By expanding equation (8) using equations (2), (7), (9), and (11), equation (14) for determining the charge q3(t) induced on the adsorption electrode side can be derived.

[0169]

[0170] Where, Q0 = Q(B0-A0) / (h ESC / ε ESC + B0), A = QA1 / (hESC / ε ESC +B0).

[0171] Using (14), the induced current i3(t) of the adsorption electrode can be calculated by differentiating the charge q3(t) induced on the adsorption electrode side according to the definition of current (15).

[0172]

[0173] As a result, the induced current I3 of the adsorption electrode is calculated by equation (16).

[0174] I3=Aω=QA1ω / (h ESC / ε ESC +B0)……(16)

[0175] The induced current i3(t) of the adsorption electrode is input to the phase detector 80. When the induced current I3 is output from the phase detector 80, the control unit 100 calculates the residual charge Q of the chip W based on the induced current I3 from the phase detector 80 using formula (17).

[0176] Q=[(h ESC / ε ESC +B0) / A1ω]×I3……(17)

[0177] The residual charge amount Q can be calculated by the above method.

[0178] However, the calculation method of the residual charge amount Q is not limited to this, and other methods may be used. In addition, the residual charge amount Q may not be used, and the CPU 105 may determine the positive and negative control direction of the HV voltage by trial and error in the separation process.

[0179] For example, the charge amount of the chip can be monitored, and the neutral point can be determined in the positive direction or the negative direction according to the relationship between the control direction of the HV voltage and the monitored value. For example, when the torque continues to rise when the HV voltage is controlled in the positive direction, the HV voltage can be controlled through repeated experiments to change the control to the negative direction.

[0180] In addition, there may be no Figure 2(b) The ammeter 44 shown. When the ammeter 44 is disposed between the upper electrode and the ground, when the electrostatic capacitance C1 of the electrostatic chuck 22 is measured, the slope of the measured value of the ammeter 44 corresponds to the electrostatic capacitance C1, so the electrostatic capacitance C1 can be measured more accurately based on the slope of the measured value of the ammeter 44. The electrostatic capacitance C1 does not change substantially during the control of the static elimination method including the separation process of the present embodiment, but even if the electrostatic capacitance C1 changes during the present control, the accurate electrostatic capacitance C can be grasped based on the measured value of the ammeter 44. Since the electrostatic capacitance C1 is measured more accurately, the residual charge amount Q and the like can be calculated more accurately.

[0181] As described above, according to the static elimination method of the present embodiment and the substrate processing apparatus 1 of the present embodiment, residual charges on the electrostatic chuck can be sufficiently eliminated.

[0182] The static elimination method and substrate processing device of one embodiment disclosed in this disclosure are illustrative in all aspects and should not be considered as limiting. The above-mentioned embodiment can be modified and improved in various ways without exceeding the scope and gist of the attached claims. The contents described in the above-mentioned various embodiments can also adopt other structures within the scope of non-contradiction, and can also be combined within the scope of non-contradiction.

[0183] For example, in adjusting the charge amount of a chip based on HV voltage, DC discharge is used, but this is not limited to this. High-frequency electric power may be used to excite gas to generate plasma discharge, and the charge amount of the chip may be adjusted using plasma discharge.

[0184] The substrate processing device of the present invention can also be applied to any type of device such as Atomic Layer Deposition (ALD: atomic layer deposition) device, Capacitively Coupled Plasma (CCP: capacitively coupled plasma), Inductively Coupled Plasma (ICP: inductively coupled plasma), Radial Line Slot Antenna (RLSA: radial line slot antenna), Electron Cyclotron Resonance Plasma (ECR: electron cyclotron resonance plasma), and Helicon Wave Plasma (HWP: helicon wave plasma).

[0185] In addition, a plasma processing apparatus has been described as an example of a substrate processing apparatus, but the substrate processing apparatus may be an apparatus that performs a predetermined process (eg, film forming process, etching process, etc.) on a substrate and is not limited to a plasma processing apparatus.

Claims

1. A static elimination method, characterized in that: have: Step (a), introducing gas into the processing container with the substrate mounted on the electrostatic chuck; Step (b), applying a DC voltage to the adsorption electrode of the electrostatic chuck while increasing the absolute value of the DC voltage until discharge based on the gas starts; Step (c), after the discharge based on the gas starts, applying the absolute value of the DC voltage so that the charge amount of the substrate reaches the charge neutralization region where it becomes zero; Step (d), applying the absolute value of the DC voltage until the charge neutralization region is reached, and then detaching the substrate from the electrostatic chuck; Step (e), calculating the residual charge of the substrate; and Step (f), based on the calculated residual charge amount, calculating the absolute value of the DC voltage that causes the charge amount of the substrate to reach the charge neutralization region, In step (c), applying the absolute value of the DC voltage calculated in step (f), In step (e), the substrate is vibrated by moving the lift pins for lifting the substrate in the up-down direction, and the residual charge amount is calculated based on the induced current flowing in the adsorption electrode at this time.

2. The static elimination method according to claim 1, wherein: When the calculated residual charge amount of the substrate is negative, the DC voltage is controlled in a positive direction. When the calculated residual charge amount of the substrate is positive, the DC voltage is controlled in a negative direction.

3. The static elimination method according to claim 1 or 2, characterized in that: Also features: Step (g), when the substrate is to be detached after the substrate is processed, measuring the torque of the lifting pins that push up the substrate; and Step (h), judging whether to execute the static elimination method based on the measured torque of the lifting pin.

4. The static elimination method according to claim 1, wherein: In step (c), the charge amount of the substrate is monitored, and the absolute value of the DC voltage is applied according to the relationship between the control direction of the DC voltage and the monitored value, so that the charge amount of the substrate reaches a charge neutralization region where it becomes zero.

5. The static elimination method according to claim 1 or 2, characterized in that: The gas is an inert gas.

6. The static elimination method according to claim 1 or 2, characterized in that: In step (a), the gas is introduced so that the pressure in the processing container becomes a preset value within the range of 200 to 800 mTorr.

7. A substrate processing method, characterized in that: include: The step of placing the substrate on the electrostatic chuck; A step of applying a DC voltage to the adsorption electrode to adsorb the substrate to the electrostatic chuck; a step of processing the substrate; The step of stopping applying the DC voltage to release the electrostatic chuck from adsorbing the substrate; and A step of executing the static elimination method according to any one of claims 1 to 6.

8. A substrate processing device, characterized in that: have: Handling containers; an electrostatic chuck disposed in the processing container; a control unit for controlling the processing of the substrate in the processing container; A lifting pin for lifting the substrate; and a pin driver for moving the lift pin up and down, The control unit performs a process comprising the following steps, namely: Step (a), introducing gas into the processing container with the substrate mounted on the electrostatic chuck; Step (b), applying a DC voltage to the adsorption electrode of the electrostatic chuck while increasing the absolute value of the DC voltage until discharge based on the gas starts; Step (c), after the discharge based on the gas starts, applying the absolute value of the DC voltage so that the charge amount of the substrate reaches the charge neutralization region where it becomes zero; Step (d), applying the absolute value of the DC voltage until the charge neutralization region is reached, and then detaching the substrate from the electrostatic chuck, Step (e), calculating the residual charge of the substrate; and Step (f), based on the calculated residual charge amount, calculating the absolute value of the DC voltage that causes the charge amount of the substrate to reach the charge neutralization region, In step (c), applying the absolute value of the DC voltage calculated in step (f), In step (e), the control unit further performs a process comprising the following steps, namely: Step (e1), inputting a reference signal for moving the lift pins up and down into a pin driver, so that the lift pins move in the up and down direction, thereby vibrating the substrate; Step (e2), measuring the induced current generated by the vibration of the substrate; and Step (e3), calculating the residual charge based on the induced current.

9. The substrate processing device according to claim 8, characterized in that: The amplitude of the reference signal is less than 1 mm after being converted into distance.

10. The substrate processing device according to claim 8 or 9, characterized in that: The frequency of the reference signal is greater than 1 kHz and less than 10 kHz.

11. The substrate processing device according to claim 8 or 9, characterized in that: The moving speed of the lifting pin varies from 0 mm / s to 5 mm / s.

12. The substrate processing device according to claim 8 or 9, characterized in that: It also has an ammeter connected to the adsorption electrode, The induced current can be measured by the ammeter.

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