Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, the method comprising: providing a substrate, the substrate comprising adjacent N-type transistor regions and P-type transistor regions; forming a work function layer on the substrate, the work function layer comprising: a P-type work function layer formed in the P-type transistor region and an N-type work function layer formed in the N-type transistor region; removing the work function layer at the junction of the N-type transistor region and the P-type transistor region to form an opening; after the opening is formed, forming a gate layer across the N-type transistor region and the P-type transistor region on the substrate, used to form a P-type gate structure with the remaining P-type work function layer, and also used to form an N-type gate structure with the remaining N-type work function layer. In an embodiment of the present invention, the opening is formed so that the N-type work function layer or the P-type work function layer is not easily located in different types of transistor regions, which expands the process window for forming the work function layer, so that the performance of the semiconductor structure is improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] In the current semiconductor industry, integrated circuit products can be mainly divided into three categories: logic, memory and analog circuits, among which memory devices account for a considerable proportion of integrated circuit products. With the development of semiconductor technology, memory devices are more widely used, and it is necessary to form the memory devices and other device areas on a chip at the same time to form an embedded semiconductor storage device. For example, if the memory device is embedded in a central processing unit, it is necessary to make the memory device compatible with the embedded central processing unit platform and maintain the original specifications and corresponding electrical performance of the memory device.

[0003] Generally, the memory device needs to be compatible with the embedded standard logic device. For embedded semiconductor devices, they are usually divided into a logic area and a storage area, the logic area usually includes a logic device, and the storage area includes a memory device. With the development of storage technology, various types of semiconductor memories have emerged, such as static random access memory (SRAM), dynamic random access memory (DRAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM) and flash memory (Flash). Since static random access memory has the advantages of low power consumption and faster operating speed, static random access memory and its formation method have received more and more attention.

[0004] However, the performance of the static random access memory in the semiconductor device formed by the prior art needs to be further improved, resulting in poor overall performance of the semiconductor device. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to optimize the electrical performance of the semiconductor structure.

[0006] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising adjacent N-type transistor regions and P-type transistor regions; forming a work function layer on the substrate, the work function layer comprising: a P-type work function layer formed in the P-type transistor region and an N-type work function layer formed in the N-type transistor region; removing the work function layer at the junction of the N-type transistor region and the P-type transistor region to form an opening; after forming the opening, forming a gate layer spanning the N-type transistor region and the P-type transistor region on the substrate, which is used to form a P-type gate structure with the remaining P-type work function layer, and is also used to form an N-type gate structure with the remaining N-type work function layer.

[0007] Correspondingly, an embodiment of the present invention also provides a semiconductor structure, including: a substrate, the substrate including adjacent N-type transistor regions and P-type transistor regions; a work function layer, located on the substrate, the work function layer including: a P-type work function layer formed on the P-type transistor region and an N-type work function layer formed on the N-type transistor region, and the P-type work function layer and the N-type work function layer are separated at the junction of the N-type transistor region and the P-type transistor region; a gate layer, located on the substrate, and the gate layer spans over the N-type transistor region and the P-type transistor region, and is used to form a P-type gate structure with the P-type work function layer, and is also used to form an N-type gate structure with the N-type work function layer.

[0008] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0009] In an embodiment of the present invention, a substrate is provided, the substrate comprising an adjacent N-type transistor region and a P-type transistor region; a work function layer is formed on the substrate, the work function layer comprising: a P-type work function layer formed on the P-type transistor region and an N-type work function layer formed on the N-type transistor region; the work function layer at the junction of the N-type transistor region and the P-type transistor region is removed to form an opening, after the opening is formed, a gate layer spanning the N-type transistor region and the P-type transistor region is formed, which is used to form a P-type gate structure with the remaining P-type work function layer, and is also used to form an N-type gate structure with the remaining N-type work function layer. In an embodiment of the present invention, the opening is formed so that the remaining N-type work function layer and the remaining P-type work function layer are spaced apart, and the opening is located at the junction of the N-type transistor region and the P-type transistor region, so that the N-type work function layer is not easy to be located in the P-type transistor region (the P-type work function layer is not easy to be located in the N-type transistor region), when the semiconductor structure is working, the semiconductor structure is not easy to have leakage problems, so that the performance of the semiconductor structure is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 to Figure 2 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0011] Figures 3 to 18 is a schematic structural diagram corresponding to each step in a first embodiment of a method for forming a semiconductor structure according to an embodiment of the present invention;

[0012] Figures 19 to 20 is a schematic structural diagram corresponding to each step in a second embodiment of a method for forming a semiconductor structure according to an embodiment of the present invention;

[0013] Fig.21 and Fig. 22 is a schematic structural diagram of a first embodiment of a semiconductor structure according to an embodiment of the present invention;

[0014] Fig.23 It is a structural schematic diagram of a second embodiment of a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0015] As can be seen from the background technology, the devices currently formed still have the problem of poor performance. The reasons for the poor performance of the devices are now analyzed in combination with a method for forming a semiconductor structure.

[0016] refer to Figure 1 and Figure 2 , showing a structural schematic diagram corresponding to each step in a method for forming a semiconductor structure.

[0017] refer to Figure 1 , providing a substrate, the substrate including adjacent N-type transistor region I and P-type transistor region II; the substrate including a substrate 10 and a fin 11 located on the substrate 10; forming an isolation material layer 12 on the substrate 10 where the fin 11 is exposed, the isolation material layer 12 covering a portion of the sidewall of the fin 11.

[0018] refer to Figure 2 , forming a dummy gate structure (not shown in the figure) spanning the fin 11, and the dummy gate structure covers part of the top wall and part of the side wall of the fin 11; after the dummy gate structure is formed, source-drain doping regions (not shown in the figure) are formed in the fin 11 on both sides of the dummy gate structure; after the source-drain doping regions are formed, a gate structure 13 is formed to replace the dummy gate structure, the gate structure 13 includes a work function layer 131 and a gate layer 132 located on the work function layer 131, and the work function layer 131 includes: a P-type work function layer 1311 formed on the P-type transistor region II and an N-type work function layer 1312 formed on the N-type transistor region I.

[0019] The work function layer 131 is used to adjust the threshold voltage of the semiconductor structure. The junction of the N-type transistor area I and the P-type transistor area II does not overlap with the junction of the N-type work function layer and the P-type work function layer. That is to say, the N-type work function layer 1312 is easily located in the P-type transistor area II, or the P-type work function layer 1311 is easily located in the N-type transistor area I. Therefore, when the semiconductor structure is working, it is easy to cause the threshold voltage of the semiconductor structure to deviate, and there are problems such as leakage, resulting in poor electrical performance of the semiconductor structure.

[0020] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising adjacent N-type transistor regions and P-type transistor regions; forming a work function layer on the substrate, the work function layer comprising: a P-type work function layer formed on the P-type transistor region and an N-type work function layer formed on the N-type transistor region; removing the work function layer at the junction of the N-type transistor region and the P-type transistor region to form an opening, after forming the opening, forming a gate layer spanning the N-type transistor region and the P-type transistor region, used to form a P-type gate structure with the remaining P-type work function layer, and also used to form an N-type gate structure with the remaining N-type work function layer. In the embodiment of the present invention, the opening is formed so that the remaining N-type work function layer and the remaining P-type work function layer are spaced apart, and the opening is located at the junction of the N-type transistor region I and the P-type transistor region II, so that the N-type work function layer is not easy to be located in the P-type transistor region (the P-type work function layer is not easy to be located in the N-type transistor region), when the semiconductor structure is working, the semiconductor structure is not easy to have leakage problems, so that the performance of the semiconductor structure is improved.

[0021] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and easy to understand, specific embodiments of the embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0022] Figures 3 to 18 It is a schematic structural diagram corresponding to each step in the first embodiment of the method for forming a semiconductor structure of the present invention.

[0023] refer to Figure 3 , providing a substrate, the substrate including adjacent N-type transistor region I and P-type transistor region II.

[0024] In this embodiment, the substrate is used to form an SRAM device, and the N-type transistor area I provides a process platform for the subsequent formation of a pull-down transistor (PD, Pull Down), and the pull-down transistor is an NMOS device; the P-type transistor area II provides a process platform for the subsequent formation of a pull-up transistor (PU, Pull Up), and the pull-up transistor is a PMOS device.

[0025] In this embodiment, the semiconductor structure formed is a fin field effect transistor (FinFET) as an example, and the substrate includes a substrate 100 and a fin 101 located on the substrate 100. In other embodiments, the semiconductor structure formed may also be a planar structure, and accordingly, the substrate is a planar substrate.

[0026] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be a silicon on insulator substrate or a germanium on insulator substrate.

[0027] In this embodiment, the material of the fin 101 is silicon. In other embodiments, the material of the fin may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0028] The base also includes: an isolation layer 102 formed on the substrate 100 where the fin 101 is exposed, and the isolation layer 102 covers a portion of the sidewall of the fin 101. The isolation layer 102 is used to electrically isolate adjacent fins 101, thereby optimizing the electrical performance of the semiconductor structure.

[0029] In this embodiment, the isolation layer 102 is made of insulating material.

[0030] refer to Figures 4 to 9 , a work function layer 106 (such as Fig. 9 As shown), the work function layer 106 includes: a P-type work function layer 1061 (as shown) formed in the P-type transistor region II Figure 8 ) and an N-type work function layer 1062 (as shown) formed in the N-type transistor region I Fig. 9 shown).

[0031] The work function layer 106 is used to adjust the threshold voltage of the semiconductor structure.

[0032] Specifically, the steps of forming the work function layer 106 include:

[0033] like Figure 6 and Figure 7 As shown, a P-type work function layer 1061 (such as Figure 7 ), which is used to adjust the threshold voltage of the PMOS device.

[0034] In this embodiment, the material of the P-type work function layer 1061 is TiN or TaN.

[0035] The step of forming the P-type work function layer 1061 includes: forming a P-type work function material layer 108 (such as Figure 6 ); forming a shielding layer 109 covering the P-type transistor region II (as shown); Figure 7The P-type work function material layer 108 on the N-type transistor region I is removed by etching using the blocking layer 109 as a mask, and the remaining P-type work function material layer 108 on the P-type transistor region II is used as the P-type work function layer 1061.

[0036] In this embodiment, an atomic layer deposition process (Atomic Layer Deposition, ALD) is used to form the P-type work function material layer 108. The atomic layer deposition process has good conformal coverage, which is conducive to ensuring that in the step of forming the P-type work function material layer 108, the P-type work function material layer 108 can conformally cover the fin 101 and the substrate 100 exposed by the fin 101, and by adopting the atomic layer deposition process, it is also conducive to improving the thickness uniformity of the P-type work function material layer 108. In other embodiments, the P-type work function material layer can also be formed by a physical vapor deposition process (Physical Vapor Deposition, PVD).

[0037] The shielding layer 109 protects the P-type work function material layer 108 on the P-type transistor region II from being mistakenly etched during the process of forming the P-type work function layer 1061 , thereby improving the formation quality of the P-type work function layer 1061 .

[0038] The shielding layer 109 is made of a material that is easy to remove, which reduces damage to the P-type work function layer 1061 when the shielding layer 109 is subsequently removed.

[0039] The material of the shielding layer 109 is an organic material, such as BARC (bottom anti-reflective coating) material, ODL (organic dielectric layer) material, photoresist, DARC (dielectric anti-reflective coating) material, DUO (Deep UV Light Absorbing Oxide) material or APF (Advanced Patterning Film) material. In this embodiment, the material of the shielding layer 109 is BARC.

[0040] In this embodiment, a dry etching process is used to etch the P-type work function material layer 108 exposed by the blocking layer 109 to form a P-type work function layer 1061 .

[0041] like Figure 8 As shown, after the P-type work function layer 1061 is formed, the shielding layer 109 is removed by an ashing process.

[0042] It should be noted that, in this embodiment, before forming the P-type work function material layer 108 , a gate dielectric layer 110 is further formed on the fin 101 and the substrate 100 where the fin 101 is exposed.

[0043] The material of the gate dielectric layer 110 is a gate dielectric material having a relative dielectric constant greater than that of silicon oxide. In this embodiment, the material of the gate dielectric layer 110 is HfO 2 .

[0044] like Fig. 9 As shown, an N-type work function layer 1062 is formed on the N-type transistor region I to adjust the threshold voltage of the NMOS device.

[0045] In this embodiment, the material of the N-type work function layer 1062 is one or more of TiAL, TaAlN, TiAlN, TiC, TaCN, AlN and TiAlC.

[0046] In this embodiment, an atomic layer deposition process (Atomic Layer Deposition, ALD) is used to form the N-type work function layer 1062. In other embodiments, the N-type work function layer can also be formed by a physical vapor deposition process (Physical Vapor Deposition, PVD).

[0047] It should be noted that, in the present embodiment, the N-type work function layer 1062 is also formed on the P-type work function layer 1061. When the semiconductor structure is working, the N-type work function layer 1062 on the P-type transistor region II is farther away from the channel than the P-type work function layer 1061, and is not easy to affect the threshold voltage of the PMOS device, and thus does not need to be removed.

[0048] like Figure 4 and Figure 5 As shown, Figure 5 for Figure 4 The method for forming the semiconductor structure further includes: before forming the work function layer 106 on the substrate, forming a dummy gate structure 103, source and drain doping regions 104 in the substrate on both sides of the dummy gate structure 103, and an interlayer dielectric layer 105 covering the source and drain doping regions 104 on the substrate, wherein the interlayer dielectric layer 105 covers the sidewalls of the dummy gate structure 103 and exposes the top of the dummy gate structure 103.

[0049] In this embodiment, the dummy gate structure 103 spans across the fin 101 , and covers a portion of the top wall and a portion of the side wall of the fin 101 . The source and drain doped regions 104 are located in the fin 101 on both sides of the gate structure 103 .

[0050] The dummy gate structure 103 provides a space for the subsequent formation of a gate structure.

[0051] In this embodiment, the dummy gate structure 103 is a stacked structure. Specifically, the dummy gate structure 103 includes a dummy gate oxide layer (not shown in the figure) and a dummy gate layer (not shown in the figure) located on the dummy gate oxide layer. In other embodiments, the dummy gate structure can also be a single-layer structure, that is, the dummy gate structure only includes a dummy gate layer.

[0052] In this embodiment, the material of the dummy gate oxide layer is silicon oxide, and the material of the dummy gate layer is polysilicon.

[0053] When the semiconductor structure is working, the source-drain doped regions 104 provide stress for the channel to increase the carrier migration rate.

[0054] Specifically, the source-drain doped regions 104 are formed in the fin 101 on both sides of the dummy gate structure 103 .

[0055] The interlayer dielectric layer 105 is used to achieve electrical isolation between adjacent semiconductor structures. Therefore, the material of the interlayer dielectric layer 105 is an insulating material.

[0056] The method for forming a semiconductor structure includes: after forming an interlayer dielectric layer 105, removing the dummy gate structure 103 (such as Figure 4 As shown), a groove 107 is formed (as shown Figure 6 The groove 107 provides a spatial location for subsequently forming a work function layer.

[0057] refer to Figures 10 to 13 , Fig.13 for Fig.12 The top view of the embodiment of the present invention is to remove the work function layer 106 at the junction of the N-type transistor region I and the P-type transistor region II to form an opening 112 (such as Fig.12 shown).

[0058] The opening 112 is formed so that the remaining N-type work function layer 1062 and the remaining P-type work function layer 1061 are separated, and the opening 112 is located at the junction of the N-type transistor area I and the P-type transistor area II, so that the N-type work function layer 1062 is not easy to be located in the P-type transistor area II (the P-type work function layer 1061 is not easy to be located in the N-type transistor area I), and when the semiconductor structure is working, the semiconductor structure is not easy to have leakage problems, so that the performance of the semiconductor structure is improved.

[0059] In addition, because the work function layer 106 at the junction of the N-type transistor region I and the P-type transistor region II is removed to form the opening 112 , the process window for forming the work function layer 106 is expanded.

[0060] It should be noted that the width of the opening 112 should not be too large or too small in the direction parallel to the substrate surface and perpendicular to the junction of the N-type transistor region I and the P-type transistor region II. If the width of the opening 112 is too large, that is, too much work function layer 106 is removed, it is easy to cause the remaining P-type work function layer 1061 to be unable to adjust the threshold voltage of the PMOS device at the junction well, or the remaining N-type work function layer 1062 to be unable to adjust the threshold voltage of the NMOS device at the junction well, resulting in poor electrical performance of the semiconductor structure. If the width of the opening 112 is too small, it is easy to cause the remaining P-type work function layer 1061 or the remaining N-type work function layer 1062 to be located in different types of transistor regions, thereby causing the semiconductor structure to be prone to leakage and other problems, thereby resulting in poor electrical performance of the semiconductor structure. In this embodiment, the width of the opening 112 in the direction parallel to the substrate surface and perpendicular to the junction of the N-type transistor region I and the P-type transistor region II is 20 nanometers to 30 nanometers.

[0061] The step of forming the opening 112 includes: forming a mask layer (not shown in the figure) on the gate structure material layer 111 ; and etching the work function layer 106 using the mask layer as a mask to form the opening 112 .

[0062] In this embodiment, a dry etching process is used to etch the work function layer 106 at the junction of the N-type transistor region I and the P-type transistor region II to form an opening 112 .

[0063] The process parameters for forming the opening 112 include: the etching gas includes BCl 3 , Cl 2 , CH 4 and H 2 One or more of; gas flow rate is 50sccm to 500sccm; chamber pressure is 5mToor to 50mToor.

[0064] It should be noted that the flow rate of the etching gas should not be too large or too small. If the flow rate of the etching gas is too large, it is easy to produce a high rate of etching, which will cause the opening 112 to be too large, and then the work function layer 106 on the fin 101 will be mistakenly etched, so that the work function layer 106 cannot adjust the threshold voltage of the PMOS device or the NMOS device well. If the flow rate of the etching gas is too small, the formation rate of the opening 113 is slow, which is not conducive to improving the formation efficiency of the semiconductor structure. In this embodiment, the flow rate of the etching gas is 50sccm to 500sccm.

[0065] It should be noted that in this embodiment, the semiconductor structure is an SRAM device, and the SRAM device includes six MOS transistors, wherein the pull-down transistor and the control switch (PG) of the bit line (bit line) used for reading and writing of the storage basic unit are usually NMOS, and the pull-up transistor is PMOS. A pair of pull-up transistors and the pull-down transistor are connected to form a CMOS inverter, and the control switch and the pull-up transistor are disconnected. In order to reduce the chip area occupied by the SRAM unit, the quantitative relationship of PU, PD and PG is usually PU:PD:PG=1:1:1.

[0066] Correspondingly, such as Fig.13 As shown, in the embodiment of the present invention, the number of fins 101 is four. From left to right, the first fin 101 is located in the N-type transistor area I, the second and third fins 101 are located in the P-type transistor area II, and the fourth fin 101 is located in the N-type transistor area I. The gate structure material layer 111 includes a gate structure material layer 111a and a gate structure material layer 111b. The gate structure material layer 111a forms a control switch at the junction with the first fin 101, forms a pull-up transistor at the junction with the third fin 101, and forms a pull-down transistor at the junction with the fourth fin 101; the gate structure material layer 111b forms a pull-down transistor at the junction with the first fin 101, forms a pull-up transistor at the junction with the second fin 101, and forms a control switch at the junction with the fourth fin 101. The control switch and the pull-up transistor on the same gate structure material layer 111 need to be disconnected.

[0067] Therefore, if Fig.10 and Fig.11 As shown, Fig.11 yes Fig.10 In the cross-sectional view in the EE direction, the method for forming the semiconductor structure further includes: after forming the work function layer 106 and before forming the opening 112, forming a gate structure material layer 111 on the work function layer 106, the gate structure material layer 111 is formed in the trench 107 (such as Figure 6 As shown in FIG. 1 , the gate structure material layer 111 spans across the fin 101 , and the gate structure material layer 111 covers a portion of the top wall and a portion of the side wall of the fin 101 .

[0068] In the step of forming the opening 112, the gate structure material layer 111 is etched to form a first through-groove 113, which is connected to the opening 112. The first through-groove 113 is prepared for the subsequent formation of an isolation structure for the isolation control switch and the pull-up transistor.

[0069] In the embodiment of the present invention, during the process of forming the opening 112 , the first through groove 113 is formed in the gate structure material layer 111 , thereby simplifying the method for forming the semiconductor structure and improving the process efficiency.

[0070] In this embodiment, the material of the gate structure material layer 111 includes magnesium tungsten alloy. In other embodiments, the material of the gate structure material layer includes one or more of W, Al, Cu, Ag, Au, Pt and Ti.

[0071] The step of forming the gate structure material layer 111 includes: filling the trench 107 with a conductive material, removing the conductive material outside the trench 107 , and using the conductive material in the trench 107 as the gate structure material layer 111 .

[0072] It should also be noted that the semiconductor structure is a SRAM device, and the pull-up transistor and the pull-down transistor in the same gate structure material layer 111 need to be connected.

[0073] refer to Fig.14 An isolation structure 114 is formed in the first through groove 113. The isolation structure 114 is used to isolate the control switch from the pull-up transistor.

[0074] In this embodiment, the isolation structure 114 is made of insulating material.

[0075] Specifically, the material of the isolation structure 114 includes one or more of silicon oxide, silicon nitride, silicon carbonitride, silicon carbon nitride oxide, silicon nitride oxide, boron nitride and boron carbonitride. In this embodiment, the material of the isolation structure 114 is silicon oxide.

[0076] The step of forming the isolation structure 114 includes: forming an isolation structure material layer (not shown in the figure) in the first through groove 113 ; removing the isolation structure material layer exposing the first through groove 113 , and the remaining isolation structure material layer in the first through groove 113 serves as the isolation structure 114 .

[0077] In this embodiment, the isolation structure material layer is formed by a flowable chemical vapor deposition (FCVD) process. The flowable chemical vapor deposition process has good filling ability and is suitable for filling structures with high aspect ratios, which is beneficial to reducing the probability of defects such as voids forming in the isolation structure material layer, and correspondingly helps to improve the film quality of the isolation structure 114.

[0078] It should be noted that, during the process of forming the isolation structure 114 , the isolation structure 114 is also formed in the opening 112 .

[0079] refer to Figures 15 to 18 After the opening 112 is formed, a gate layer 115 (eg, Fig.17 As shown), it is used to form a P-type gate structure with the remaining P-type work function layer 1061, and is also used to form an N-type gate structure with the remaining N-type work function layer 1062.

[0080] The P-type gate structure and the N-type gate structure also act on the fins 101 of the N-type transistor region I and the P-type transistor region II, respectively.

[0081] Specifically, the steps of forming the gate layer 115 include:

[0082] like Fig.15 As shown, a dielectric layer 116 is formed on the gate structure material layer 111 .

[0083] The dielectric layer 116 is used to electrically isolate a conductive connection layer to be formed subsequently.

[0084] In this embodiment, the material of the dielectric layer 116 is an insulating material.

[0085] Specifically, the material of the dielectric layer 116 includes one or more of silicon oxide, silicon nitride, silicon carbonitride, silicon carbon oxynitride, silicon oxynitride, boron nitride and boron carbonitride. In this embodiment, the material of the dielectric layer 116 is silicon oxide.

[0086] The step of forming the dielectric layer 116 includes: forming a dielectric material layer (not shown in the figure) on the isolation structure material layer 111 and the isolation structure 114 ; and performing a planarization process on the dielectric material layer to form the dielectric layer 116 .

[0087] like Fig.16 As shown, the dielectric layer 116 at the junction of the N-type transistor region I and the P-type transistor region II is removed to form a second through groove 118, which exposes the isolation structure 114 and the gate structure material layer 111 with a partial width of the N-type transistor region I and the P-type transistor region II.

[0088] The second through groove 118 provides a space for the subsequent formation of a conductive connection layer.

[0089] Specifically, in the step of forming the second through-groove 118 , the dielectric layer 116 on the pull-up transistor and the pull-down transistor in the SRAM device is removed to form the second through-groove 118 .

[0090] The step of forming the second through-groove 118 includes: forming a dielectric mask layer on the dielectric layer 116 ; and etching the dielectric layer 116 using the dielectric mask layer as a mask to form the second through-groove 118 .

[0091] In this embodiment, the dielectric layer 116 is etched by dry etching to form the second through groove 118. The dry etching process is an anisotropic etching process with good etching profile controllability, which is conducive to making the morphology of the second through groove 118 meet the process requirements and also helps to improve the removal efficiency of the dielectric layer 116.

[0092] like Fig.17 and Fig.18As shown, Fig.17 is a cross-sectional view perpendicular to the extending direction of the fin 101, Fig.18 yes Fig.17 In the top view, a conductive connection layer 117 is formed in the second through groove 118, and the conductive connection layer 117 and the gate structure material layer 111 in the N-type transistor region I and the P-type transistor region II together serve as the gate layer 115.

[0093] The conductive connection layer 117 is used to electrically connect the gate structure material layer 111 in the N-type transistor region I and the P-type transistor region II, so that the pull-down transistor and the pull-up transistor in the SRAM device are connected.

[0094] In this embodiment, the material of the conductive connection layer 117 includes magnesium tungsten alloy. In other embodiments, the material of the gate structure material layer includes one or more of W, Al, Cu, Ag, Au, Pt and Ti.

[0095] The step of forming the conductive connection layer 117 includes: forming a conductive material covering the second through-groove 119 , removing the conductive material exposing the second through-groove 119 , and using the conductive material in the second through-groove 119 as the conductive connection layer 117 .

[0096] It should be noted that, along the extension direction of the gate structure material layer 111, the width of the conductive connection layer 117 in contact with the gate structure material layer 111 in the N-type transistor region I and the P-type transistor region II should not be too large or too small. If the width is too large, it will lead to material waste and the capacitance of the semiconductor structure will be too large, which is not conducive to reducing the back-end RC delay; if the width is too small, it will easily lead to excessive contact resistance between the conductive connection layer 117 and the gate structure material layer 111. In this embodiment, along the extension direction of the gate structure material layer 111, the width of the conductive connection layer 117 in contact with the gate structure material layer 111 in the N-type transistor region I and the P-type transistor region II is 10 nanometers to 50 nanometers.

[0097] It should be noted that because the gate structure material layer 111 spans across the fin 101 and the gate layer 115 covers part of the top wall and part of the side wall of the fin 101 , correspondingly, the gate layer 115 spans across the fin 101 and covers part of the top wall and part of the side wall of the fin 101 .

[0098] Figures 19 to 20 It is a schematic structural diagram corresponding to each step in the second embodiment of the method for forming a semiconductor structure of the present invention.

[0099] The similarities between the embodiment of the present invention and the first embodiment are not repeated here. The difference is that no isolation structure is formed at the junction of the N-type transistor region I and the P-type transistor region II.

[0100] like Fig.19As shown, a work function layer 206 is formed on the substrate, and the work function layer 206 includes: a P-type work function layer 2061 formed in the P-type transistor region II and an N-type work function layer 2062 formed in the N-type transistor region I; the work function layer 206 at the junction of the N-type transistor region I and the P-type transistor region II is removed to form an opening 212.

[0101] The specific formation process and materials of the work function layer 206 refer to the first embodiment and will not be described in detail here.

[0102] The specific method of forming the opening 212 is similar to that of the first embodiment and will not be described in detail herein.

[0103] like Fig. 20 As shown, the step of forming a gate layer 211 spanning the N-type transistor region I and the P-type transistor region II includes: forming a conductive material covering the remaining N-type work function layer 2062 , the remaining P-type work function layer 2061 and the opening 212 , and etching the conductive material to form the gate layer 211 .

[0104] In this embodiment, etching the conductive material to form the gate layer 211 means removing the conductive material exposed in the trench, and the conductive material in the trench serves as the gate layer 211 .

[0105] In the embodiment of the present invention, the work function layer 206 is directly etched after being formed to form the opening 212, thereby simplifying the steps of forming the opening 212; and the formed gate layer 211 is an integrated structure, which is beneficial to reducing the resistivity between the NMOS device and the PMOS device and improving the electrical performance of the semiconductor structure.

[0106] The opening 212 separates the remaining N-type work function layer 2062 and the remaining P-type work function layer 2061, and the opening 212 is located at the junction of the N-type transistor area I and the P-type transistor area II, so that the N-type work function layer 2062 is not easy to be located in the P-type transistor area II (the P-type work function layer 2061 is not easy to be located in the N-type transistor area I). ​​When the semiconductor structure is working, the semiconductor structure is not easy to have leakage problems, thereby improving the electrical performance of the semiconductor structure.

[0107] Accordingly, an embodiment of the present invention further provides a semiconductor structure. Fig.21 and Fig. 22 , showing a schematic structural diagram of a first embodiment of a semiconductor structure of the present invention, Fig.21 is a cross-sectional view perpendicular to the extension direction of the fin, Fig. 22 yes Fig.21 Top view of the .

[0108] The semiconductor structure includes: a substrate, the substrate includes adjacent N-type transistor region I and P-type transistor region II; a work function layer 306, located on the substrate, the work function layer 306 includes: a P-type work function layer 3061 formed on the P-type transistor region II and an N-type work function layer 3062 formed on the N-type transistor region I, and the P-type work function layer 3061 is isolated from the N-type work function layer 3062 at the junction of the N-type transistor region I and the P-type transistor region II; a gate layer 315, located on the substrate, and the gate layer 315 spans the N-type transistor region I and the P-type transistor region II, and is used to form a P-type gate structure with the P-type work function layer 3061, and is also used to form an N-type gate structure with the N-type work function layer 3062.

[0109] In the embodiment of the present invention, the P-type work function layer 3061 and the N-type work function layer 3062 are spaced apart at the boundary between the N-type transistor region I and the P-type transistor region II, so that the N-type work function layer 3062 is not easily located in the P-type transistor region II (the P-type work function layer 3061 is not easily located in the N-type transistor region I), thereby improving the performance of the semiconductor structure.

[0110] In this embodiment, the semiconductor structure is an SRAM device, a pull-down transistor (PD, Pull Down) is formed in the N-type transistor area I, and the pull-down transistor is an NMOS device; a pull-up transistor (PU, PullUp) is formed in the P-type transistor area II to provide a process platform, and the pull-up transistor is a PMOS device.

[0111] In this embodiment, the semiconductor structure is a fin field effect transistor (FinFET) as an example, and the substrate includes a substrate 300 and a fin 301 located on the substrate 300. In other embodiments, the semiconductor structure may also be a planar structure, and accordingly, the substrate is a planar substrate.

[0112] In this embodiment, the material of the substrate 300 is silicon. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be a silicon on insulator substrate or a germanium on insulator substrate.

[0113] In this embodiment, the material of the fin 301 is silicon. In other embodiments, the material of the fin may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0114] The base also includes an isolation layer 302 located on the substrate 300 where the fin 301 is exposed, and the isolation layer 302 covers a portion of the sidewall of the fin 301 .

[0115] The isolation layer 302 is used to electrically isolate adjacent fins 301, thereby optimizing the electrical performance of the semiconductor structure. In this embodiment, the isolation layer 302 is made of an insulating material.

[0116] The P-type work function layer 3061 is used to adjust the threshold voltage of the PMOS device and is located on the fin 301 in the P-type transistor region II and on the substrate 300 where the fin 301 is exposed.

[0117] In this embodiment, the material of the P-type work function layer 3061 is TiN or TaN.

[0118] The N-type work function layer 3062 is used to adjust the threshold voltage of the NMOS device. The N-type work function layer 3062 is located on the fin 301 in the N-type transistor region I and on the substrate 300 where the fin 301 is exposed.

[0119] In this embodiment, the material of the N-type work function layer 3062 is one or more of TiAL, TaAlN, TiAlN, TiC, TaCN, AlN and TiAlC.

[0120] It should be noted that the spacing between the N-type work function layer 3062 and the P-type work function layer 3061 should not be too large or too small. If the spacing is too large, it is easy to cause the P-type work function layer 3061 to be unable to adjust the threshold voltage of the PMOS device at the junction well, or the N-type work function layer 3062 to be unable to adjust the threshold voltage of the NMOS device at the junction well, resulting in poor electrical performance of the semiconductor structure. If the spacing is too small, it is easy to cause the P-type work function layer 3061 or the N-type work function layer 3062 to be located in different types of transistor regions, resulting in problems such as leakage in the semiconductor structure, which in turn leads to poor electrical performance of the semiconductor structure. In this embodiment, the spacing between the N-type work function layer 3062 and the P-type work function layer 3061 is 20 nanometers to 30 nanometers.

[0121] It should be noted that the N-type work function layer 3062 is also located on the P-type work function layer 3061. When the semiconductor structure is working, the N-type work function layer 3062 on the P-type transistor region II is farther away from the channel than the P-type work function layer 3061, and is not easy to affect the threshold voltage of the PMOS device, and does not need to be removed.

[0122] The semiconductor structure further includes: a gate dielectric layer 310 located on the fin 301 and the isolation layer 302 exposed by the fin 301 .

[0123] The material of the gate dielectric layer 310 is a gate dielectric material having a relative dielectric constant greater than that of silicon oxide. 2 .

[0124] In the embodiment of the present invention, the semiconductor structure is an SRAM device, and the SRAM device includes six MOS transistors, wherein the pull-down transistor and the control switch (PG) of the bit line (bit line) used for reading and writing of the storage basic unit are usually NMOS, and the pull-up transistor is PMOS. A pair of pull-up transistors and the pull-down transistor are connected to form a CMOS inverter, and the control switch and the pull-up transistor are disconnected. In order to reduce the chip area occupied by the SRAM unit, the quantitative relationship of PU, PD and PG is usually PU:PD:PG=1:1:1.

[0125] Accordingly, in the embodiment of the present invention, the number of fins 301 is four. From left to right, the first fin 301 is located in the N-type transistor region I, the second and third fins 301 are located in the P-type transistor region II, and the fourth fin 301 is located in the N-type transistor region I. The gate structure material layer 311 includes a gate structure material layer 311a (such as Fig. 22 ) and the gate structure material layer 311b (as shown Fig. 22 As shown), the gate structure material layer 311a forms a control switch at the junction with the first fin 301, forms a pull-up transistor at the junction with the third fin 301, and forms a pull-down transistor at the junction with the fourth fin 301; the gate structure material layer 311b forms a pull-down transistor at the junction with the first fin 301, forms a pull-up transistor at the junction with the second fin 301, and forms a control switch at the junction with the fourth fin 301. The pull-up transistor and the pull-down transistor in the same gate layer 315 need to be connected.

[0126] Correspondingly, the gate layer 315 includes: a gate structure material layer 311 located in the N-type transistor region I and the P-type transistor region II; and a conductive connection layer 317 connecting the gate structure material layer 311 in the N-type transistor region I and the gate structure material layer 311 in the P-type transistor region II.

[0127] The gate structure material layer 311 in the P-type transistor region II is used to form a P-type gate structure with the P-type work function layer 3061 , and the gate structure material layer 311 in the N-type transistor region I is used to form an N-type gate structure with the N-type work function layer 3062 .

[0128] When the semiconductor structure is working, the N-type gate structure and the P-type gate structure are used to control the opening and closing of the channels in the N-type transistor region I and the P-type transistor region II, respectively.

[0129] In this embodiment, the material of the gate structure material layer 311 includes magnesium tungsten alloy. In other embodiments, the material of the gate structure material layer includes one or more of W, Al, Cu, Ag, Au, Pt and Ti.

[0130] In this embodiment, the semiconductor structure is a SRAM device; the conductive connection layer 317 is located between the pull-up transistor and the pull-down transistor in the SRAM device.

[0131] Accordingly, the conductive connection layer 317 electrically connects the gate structure material layer 311 in the N-type transistor region I and the P-type transistor region II.

[0132] In this embodiment, the material of the conductive connection layer 317 includes magnesium tungsten alloy. In other embodiments, the material of the gate structure material layer includes one or more of W, Al, Cu, Ag, Au, Pt and Ti.

[0133] It should be noted that the width of the conductive connection layer 317 in contact with the gate structure material layer 311 in the N-type transistor region I and the P-type transistor region II parallel to the extension direction of the gate structure material layer 311 should not be too large or too small. If the width is too large, it will lead to material waste and the capacitance of the semiconductor structure will be too large, which is not conducive to reducing the back-end RC delay; if the width is too small, it will easily lead to excessive contact resistance between the conductive connection layer 317 and the gate structure material layer 311. In this embodiment, parallel to the extension direction of the gate structure material layer 311, the width of the conductive connection layer 317 in contact with the gate structure material layer 311 in the N-type transistor region I and the P-type transistor region II is 10 nanometers to 50 nanometers.

[0134] It should be noted that, in this embodiment, the base includes a substrate 300 and a fin 301 located on the substrate 300 ; the gate layer 315 correspondingly spans the fin 301 , and the gate layer 315 covers a portion of the top wall and a portion of the side wall of the fin 301 .

[0135] It should be noted that, in this embodiment, the semiconductor structure is an SRAM device, and accordingly, the control switch and the pull-up transistor need to be disconnected.

[0136] The semiconductor structure further includes: an isolation structure 314 located between the gate structure material layer 311 in the N-type transistor region I and the gate structure material layer 311 in the P-type transistor region II; and a conductive connection layer 317 located on the isolation structure 314 .

[0137] The isolation structure 314 is used to isolate the control switch from the pull-up transistor.

[0138] In this embodiment, the material of the isolation structure 314 is an insulating material. Specifically, the material of the isolation structure 314 includes one or more of silicon oxide, silicon nitride, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride and boron carbonitride. In this embodiment, the material of the isolation structure 314 is silicon oxide.

[0139] The isolation structure 314 has a width that is equal to the distance between the N-type work function layer 3062 and the P-type work function layer 3061 in a direction perpendicular to the extension direction of the fin 301. Accordingly, the width of the isolation structure 314 is 20 nanometers to 30 nanometers.

[0140] In this embodiment, the semiconductor structure further includes a source-drain doping layer (not shown in the figure) located in the fin 301 on both sides of the gate layer 315 .

[0141] In this embodiment, the semiconductor structure further includes a dielectric layer 316 located on the gate structure material layer 311 ; and a conductive connection layer 317 is located in the dielectric layer 316 .

[0142] The dielectric layer 316 is used to electrically isolate the connected conductive connection layer 317. In this embodiment, the material of the dielectric layer 316 is an insulating material.

[0143] Specifically, the material of the dielectric layer 316 includes one or more of silicon oxide, silicon nitride, silicon carbonitride, silicon carbon oxynitride, silicon oxynitride, boron nitride and boron carbonitride. In this embodiment, the material of the dielectric layer 316 is silicon oxide.

[0144] refer to Fig.23 , showing a schematic structural diagram of a second embodiment of a semiconductor structure of the present invention.

[0145] The similarities between the embodiment of the present invention and the first embodiment are not repeated here. The difference is that no isolation structure is formed at the junction of the N-type transistor region I and the P-type transistor region II.

[0146] In this embodiment, the gate layer 411 is an integrated structure, and is located on the N-type work function layer 4062 , the P-type work function layer 4061 , and the substrate between the N-type work function layer 4062 and the P-type work function layer 4061 .

[0147] In the embodiment of the present invention, the gate layer 411 is an integrated structure, which is beneficial to reducing the resistivity between the NMOS device and the PMOS device and improving the electrical performance of the semiconductor structure.

[0148] The N-type work function layer 4062 and the P-type work function layer 4061 are separated at the junction of the N-type transistor region I and the P-type transistor region II, so that the N-type work function layer 4062 is not easy to be located in the P-type transistor region II (the P-type work function layer 4061 is not easy to be located in the N-type transistor region I). When the semiconductor structure is working, the semiconductor structure is not easy to have leakage problems, thereby improving the electrical performance of the semiconductor structure.

[0149] Although the embodiments of the present invention are disclosed above, the embodiments of the present invention are not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the embodiments of the present invention. Therefore, the protection scope of the embodiments of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising adjacent N-type transistor regions and P-type transistor regions; forming a work function layer on the substrate, the work function layer comprising: a P-type work function layer formed in the P-type transistor region and an N-type work function layer formed in the N-type transistor region; Removing the work function layer at the junction of the N-type transistor region and the P-type transistor region to form an opening; After forming the opening, forming a gate layer across the N-type transistor region and the P-type transistor region on the substrate, which is used to form a P-type gate structure with the remaining P-type work function layer, and is also used to form an N-type gate structure with the remaining N-type work function layer; The step of forming the gate layer includes: forming a dielectric layer on the gate structure material layer; removing the dielectric layer at the junction of the N-type transistor area and the P-type transistor area to form a second through groove; Wherein, the conductive connection layer is located in the second through groove, and the conductive connection layer is distributed diagonally.

2. The method for forming a semiconductor structure according to claim 1, wherein: In a direction parallel to the surface of the substrate and perpendicular to the boundary between the N-type transistor region and the P-type transistor region, the width of the opening is 20 nanometers to 30 nanometers.

3. The method for forming a semiconductor structure according to claim 1, wherein: The work function layer at the junction of the N-type transistor region and the P-type transistor region is etched by a dry etching process to form the opening.

4. The method for forming a semiconductor structure according to claim 1, wherein: The process parameters for forming the opening include: the etching gas includes one or more of BCl3, Cl2, CH4 and H2; The gas flow rate is 50 sccm to 500 sccm; the chamber pressure is 5 mToor to 50 mToor.

5. The method for forming a semiconductor structure according to claim 1, wherein: After forming the work function layer and before forming the opening, the method further includes: forming a gate structure material layer on the work function layer; in the step of forming the opening, the method further includes etching the gate structure material layer to form a first through groove, wherein the first through groove is connected to the opening.

6. The method for forming a semiconductor structure according to claim 5, wherein: After forming the opening and before forming the gate layer, the method further includes: forming an isolation structure in the first through groove.

7. The method for forming a semiconductor structure according to claim 6, wherein: The step of forming a gate layer also includes: the second through groove exposes the isolation structure and the gate structure material layer of a partial width of the N-type transistor area and the P-type transistor area; the conductive connection layer and the gate structure material layer in the N-type transistor area and the P-type transistor area together serve as the gate layer.

8. The method for forming a semiconductor structure according to claim 7, wherein: Along the extension direction of the gate structure material layer, the width of the conductive connection layer in contact with the gate structure material layer in the N-type transistor region and the P-type transistor region is 10 nanometers to 50 nanometers.

9. The method for forming a semiconductor structure according to claim 7, wherein: The semiconductor structure is a SRAM device; The step of forming the second through groove includes: removing the dielectric layer on the pull-up transistor and the pull-down transistor in the SRAM device to form the second through groove.

10. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming a gate layer spanning the N-type transistor region and the P-type transistor region includes: forming a conductive material covering the remaining N-type work function layer, the remaining P-type work function layer and the opening, and etching the conductive material to form the gate layer.

11. The method for forming a semiconductor structure according to claim 1, wherein: The base comprises a substrate and a fin located on the substrate; In the step of forming a work function layer on the substrate, the work function layer covers the fin and the substrate exposed by the fin; In the step of forming a gate layer on the work function layer, the gate layer spans across the fin, and the gate layer covers a portion of a top wall and a portion of a side wall of the fin.

12. A semiconductor structure, characterized in that: The semiconductor structure is formed by the method for forming a semiconductor structure according to any one of claims 1 to 11, comprising: A substrate, the substrate comprising adjacent N-type transistor regions and P-type transistor regions; A work function layer is located on the substrate, the work function layer comprising: a P-type work function layer formed on the P-type transistor region and an N-type work function layer formed on the N-type transistor region, and the P-type work function layer and the N-type work function layer are spaced apart at the boundary between the N-type transistor region and the P-type transistor region; A gate layer is located on the substrate, and the gate layer spans across the N-type transistor region and the P-type transistor region. on the transistor region, used to form a P-type gate structure with the P-type work function layer, and also used to form an N-type gate structure with the N-type work function layer; The conductive connection layer is distributed diagonally and is used to connect the gate structure material layer in the N-type transistor area and the gate structure material layer in the P-type transistor area.

13. The semiconductor structure according to claim 12, wherein: The distance between the N-type work function layer and the P-type work function layer is 20 nanometers to 30 nanometers.

14. The semiconductor structure according to claim 12, wherein: The gate layer includes: a gate structure material layer located in the N-type transistor region and in the P-type transistor region; The semiconductor structure further includes: an isolation structure located between the gate structure material layer in the N-type transistor region and the gate structure material layer in the P-type transistor region; The conductive connection layer is located on the isolation structure.

15. The semiconductor structure according to claim 14, wherein: Parallel to the extension direction of the gate structure material layer, the width of the conductive connection layer in contact with the gate structure material layer in the N-type transistor region and the P-type transistor region is 10 nanometers to 50 nanometers.

16. The semiconductor structure according to claim 14, wherein: The semiconductor structure is a SRAM device; The conductive connection layer is located between a pull-up transistor and a pull-down transistor in the SRAM device.

17. The semiconductor structure according to claim 14, wherein: The semiconductor structure further comprises a dielectric layer located on the gate structure material layer; the conductive connection layer is located in the dielectric layer.

18. The semiconductor structure according to claim 12, wherein: The gate layer is an integrated structure and is located on the N-type work function layer, on the P-type work function layer, and on the substrate between the N-type work function layer and the P-type work function layer.

19. The semiconductor structure according to claim 12, wherein: The base comprises a substrate and a fin located on the substrate; The gate layer spans across the fin portion, and the gate layer covers a portion of the top wall and a portion of the side wall of the fin portion.

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