Integrated chip and method for forming integrated chip

Abstract

In some embodiments, the disclosed embodiments relate to an integrated chip and a method of forming an integrated chip, the integrated chip comprising one or more lower interconnect layers within one or more stacked interlayer dielectric layers arranged above a substrate. A bottom electrode is disposed above the one or more interconnect layers, and a top electrode is disposed above the bottom electrode. A ferroelectric layer is disposed between a first surface of the bottom electrode and a second surface of the top electrode and contacts the first surface and the second surface. The ferroelectric layer comprises a protrusion extending over an outer surface of the top electrode and the bottom electrode along a first direction perpendicular to a second direction, the second direction being orthogonal to the first surface. The protrusion is defined between lines extending along the first and second surfaces.

Description

Technical Field

[0001] The present disclosure relates to an integrated chip and a method for forming the integrated chip. Background Art

[0002] Many modern electronic devices include non-volatile memory. Non-volatile memory is electronic memory that can store data when power is not available. Ferroelectric random access memory (FeRAM) is a promising candidate for the next generation of non-volatile memory. FeRAM has a relatively simple structure and is compatible with complementary metal-oxide-semiconductor (CMOS) logic manufacturing processes. Summary of the invention

[0003] According to one embodiment of the present disclosure, an integrated chip is provided, comprising: one or more lower interconnect layers arranged within one or more stacked interlayer dielectric (ILD) layers above a substrate; a bottom electrode disposed above the one or more lower interconnect layers; a top electrode disposed above the bottom electrode; and a ferroelectric layer disposed between a first surface of the bottom electrode and a second surface of the top electrode and contacting the first surface and the second surface, wherein the ferroelectric layer comprises protrusions extending over outer surfaces of the top electrode and the bottom electrode along a first direction perpendicular to a second direction, the second direction being orthogonal to the first surface, the protrusions being defined between lines extending along the first surface and the second surface.

[0004] According to one embodiment of the present disclosure, an integrated chip is provided, comprising: one or more lower interconnect layers arranged within one or more stacked interlayer dielectric (ILD) layers above a substrate; a bottom electrode disposed above the one or more lower interconnect layers; a top electrode disposed above the bottom electrode; and a ferroelectric layer disposed between the bottom electrode and the top electrode and extending over outer surfaces of the top electrode and the bottom electrode, wherein lines parallel to an interface between the bottom electrode and the ferroelectric layer and between the bottom electrode and the top electrode extend through an outermost surface of the ferroelectric layer.

[0005] According to one embodiment of the present disclosure, a method for forming an integrated chip is provided, comprising: depositing a ferroelectric layer above a bottom electrode layer; depositing a top electrode layer above the ferroelectric layer; performing a first removal step to remove the bottom electrode layer, the ferroelectric layer, and peripheral portions of the top electrode layer; and performing a second removal step to remove portions of the bottom electrode layer and the top electrode layer using a second etch selective to the bottom electrode layer and the top electrode layer, wherein after the second removal step, the ferroelectric layer has a surface that protrudes beyond the surfaces of the bottom electrode layer and the top electrode layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, the aspects of the disclosed embodiments will be well understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for the purpose of clarity of discussion.

[0007] Figure 1A to Figure 1B A cross-sectional view of some embodiments of an integrated wafer having a ferroelectric random access memory (FeRAM) cell including a ferroelectric layer between a top electrode and a bottom electrode, wherein the ferroelectric layer extends beyond outermost walls of the top electrode and the bottom electrode;

[0008] FIG. 2A to FIG. 2B A cross-sectional view of some embodiments of a ferroelectric random access memory cell is shown, the ferroelectric random access memory cell including a ferroelectric layer below first and second layers of a top electrode and above first and second layers of a bottom electrode, wherein the ferroelectric layer extends beyond outermost walls of the first layer of the top and bottom electrodes;

[0009] Figure 3 A cross-sectional view of some embodiments of a ferroelectric random access memory cell is shown, the ferroelectric random access memory cell including a ferroelectric layer between a top electrode and a bottom electrode, wherein a topmost surface of the ferroelectric layer is above a topmost surface of the top electrode and the bottom electrode;

[0010] Figure 4 A cross-sectional view of some embodiments of a ferroelectric random access memory cell is shown, the ferroelectric random access memory cell including a ferroelectric layer between a bottom electrode and a top electrode, the top electrode including an additional layer of the top electrode, wherein a topmost surface of the ferroelectric layer is above a topmost surface of the top electrode and the bottom electrode;

[0011] FIG. 5A to FIG. 5B shows a cross-sectional view of some embodiments of an integrated wafer having a ferroelectric random access memory cell coupled to an access transistor;

[0012] Figures 6 to 13 Cross-sectional views showing some embodiments of methods of patterning a ferroelectric layer between a top electrode and a bottom electrode in a ferroelectric random access memory cell;

[0013] Fig.14 Shows Figures 6 to 13 Flowcharts of some embodiments of the method.

[0014]

Explanation of symbols

[0015] 100A: Cross-section

[0016] 100B: Cross-section

[0017] 101: Ferroelectric Random Access Memory Cell

[0018] 102:Substrate

[0019] 104: Access transistor

[0020] 104a: drain region

[0021] 104b: Source region

[0022] 104c: gate electrode

[0023] 104d: gate dielectric layer

[0024] 106: Dielectric structure

[0025] 108: Interconnection through hole

[0026] 108b: Bottom electrode through hole

[0027] 108t: Top electrode through hole

[0028] 109: Lower interconnect layer

[0029] 110: Interconnection wiring

[0030] 112: Bottom electrode

[0031] 112c: Center top surface

[0032] 112p: Outer protrusion

[0033] 112s: Outermost wall

[0034] 112t: Top surface

[0035] 112u: First surface

[0036] 114: Ferroelectric layer

[0037] 114c: Center

[0038] 114d: Damaged area

[0039] 114p: protrusion

[0040] 114s: Outermost wall

[0041] 114t: Top surface

[0042] 116: Top electrode

[0043] 116b: Second surface

[0044] 116s: Outermost wall

[0045] 116t: Top surface

[0046] 130: Line

[0047] 200A: Cross-section

[0048] 200B: Cross-section

[0049] 202: The first layer of the bottom electrode

[0050] 202s: the outermost wall of the first layer of the bottom electrode

[0051] 204: First layer of top electrode

[0052] 204s: the outermost wall of the first layer of the top electrode

[0053] 212: Second layer of bottom electrode

[0054] 212s: The outermost wall of the second layer of the bottom electrode

[0055] 216: Second layer of top electrode

[0056] 216s: the outermost wall of the second layer of the top electrode

[0057] 300: Cross-section

[0058] 302: Interface

[0059] 304: Front Line

[0060] 400: Cross-section

[0061] 402: Additional layer of top electrode

[0062] 402t: Topmost surface of the additional layer of the top electrode

[0063] 500A: Cross-section

[0064] 500B: Cross-section

[0065] 502: ferroelectric gate layer

[0066] 502d: Damaged gate area

[0067] 600: Cross-section

[0068] 602: Etching stop layer

[0069] 700: Cross-section

[0070] 800A: Cross-section

[0071] 800B: Cross-section

[0072] 800C: Cross-section

[0073] 800D: Cross-section

[0074] 802: First mask

[0075] 804: First Etching

[0076] 806: Second Etching

[0077] 812: bottom electrode layer

[0078] 814: Ferroelectric Materials

[0079] 816: Top electrode layer

[0080] 822: Patterned bottom electrode

[0081] 822i: Middle outer side wall of patterned bottom electrode

[0082] 826: Patterned top electrode

[0083] 826i: Middle outer side wall of patterned top electrode

[0084] 900A: Cross-section

[0085] 900B: Cross-section

[0086] 900C: Cross-section

[0087] 900D: Cross-section

[0088] 902: First material of bottom electrode layer

[0089] 904: First material of top electrode layer

[0090] 912: Second material of bottom electrode layer

[0091] 914: Ferroelectric Materials

[0092] 916: Second material of top electrode layer

[0093] 924: Patterned first layer of top electrode

[0094] 926: Patterned second layer of top electrode

[0095] 930: Patterned first layer of bottom electrode

[0096] 932: Patterned second layer of bottom electrode

[0097] 1000A: Cross-section

[0098] 1000B: Cross-section

[0099] 1000C: Cross-section

[0100] 1000D: Cross-section

[0101] 1000E: Cross-section

[0102] 1002: Upper dielectric layer

[0103] 1002s: Inner wall

[0104] 1004: Cavity

[0105] 1006:Remove step

[0106] 1008: The third etching

[0107] 1012: Conformal bottom electrode layer

[0108] 1014: Conformal ferroelectric layer

[0109] 1016: Conformal top electrode layer

[0110] 1022: Conformal top electrode portion

[0111] 1026: Conformal bottom electrode portion

[0112] 1100A: Cross-section

[0113] 1100B: Cross-section

[0114] 1100C: Cross-section

[0115] 1100D: Cross-section

[0116] 1100E: Cross-section

[0117] 1102: Additional conformal top electrode layer

[0118] 1200: Cross-section

[0119] 1300: Cross-section

[0120] 1400: Method

[0121] 1402: Action

[0122] 1404: Action

[0123] 1406: Action

[0124] 1408: Action

[0125] 1410: Action

[0126] 1412: Action

[0127] 1414: Action

[0128] 1416: Action

[0129] d1: first distance

[0130] d2: second distance

[0131] d3: third distance

[0132] t1: first thickness

[0133] t2: second thickness

[0134] t3: third thickness

[0135] t4: fourth thickness

[0136] w1: first width

[0137] w2: second width

[0138] w3: third width

[0139] w4: fourth width

[0140] w5: fifth width

[0141] BL: Bit Line

[0142] SL: Source Line

[0143] WL: Word Line DETAILED DESCRIPTION

[0144] The following disclosure provides many different embodiments or examples to implement the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are only examples and are not intended to be limiting. For example, the following description may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the disclosed embodiments may repeat element symbols and / or letters in each example. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0145] Additionally, for ease of description, embodiments herein may use spatially relative terms, such as "below," "under," "lower," "above," "upper," and the like, to describe the relationship of one element or feature to another element (or elements) or feature (or features) illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used in embodiments herein may be similarly interpreted accordingly.

[0146] A ferroelectric random access memory (FeRAM) device having a metal / ferroelectric layer / metal (MFM) structure includes a ferroelectric layer disposed between a top electrode and a bottom electrode. Because the crystal structure of the ferroelectric layer can change in the presence of an electric field, the ferroelectric random access memory device is configured to store data values ​​based on a reversible switching process between polarization states. For example, in a ferroelectric random access memory cell, a negative voltage bias applied to the ferroelectric layer can induce atoms to shift to a first crystal structure orientation having a first resistance indicating a first data value (e.g., a logical "1"), while a positive voltage bias applied to the ferroelectric layer can induce atoms to shift to a second crystal structure orientation having a second resistance indicating a second data value (e.g., a logical "0").

[0147] For example, a method for forming a ferroelectric random access memory cell may include depositing a bottom electrode over one or more interconnect layers coupled to an access transistor. A first mask may be used to pattern the bottom electrode. A ferroelectric layer may be deposited over and extending over the patterned bottom electrode, and a top electrode may be deposited over the ferroelectric layer. A second mask may be used to pattern the top electrode. The top electrode may be patterned using plasma etching.

[0148] For example, another method for forming a ferroelectric random access memory cell may include depositing a bottom electrode over one or more interconnect layers coupled to an access transistor. Subsequently, a top electrode over the ferroelectric layer may be deposited over the bottom electrode. A first mask and plasma etch may be used to pattern the bottom electrode, the ferroelectric layer, and the top electrode.

[0149] However, in both methods, plasma etching may damage the crystal structure of the ferroelectric layer between the top electrode and the bottom electrode. Examples of damage to the crystal structure due to plasma etching may include a crystal structure that favors one of the crystal structure orientations, a crystal structure that no longer exhibits ferroelectric properties, and crystal structure defects (e.g., dislocations, vacancies, dangling bonds) that cause device failure and / or have a shorter lifetime. Therefore, damage to the crystal structure of the ferroelectric layer adversely affects the reversible switching between polarization states of the ferroelectric random access memory device, thereby reducing device reliability.

[0150] In order to prevent the ferroelectric random access memory device from having a damaged ferroelectric layer, an undamaged portion of the ferroelectric layer can be arranged between the top electrode and the bottom electrode, while the damaged portion of the ferroelectric layer is limited to a position outside the top electrode and the bottom electrode. Therefore, an electric field for changing the crystallization state of the ferroelectric layer is applied to the undamaged portion of the ferroelectric layer, so that the damaged portion of the ferroelectric layer does not affect the device reliability of the ferroelectric random access memory.

[0151] Various embodiments of the present disclosure provide a method for manufacturing a ferroelectric random access memory cell having a top electrode above a bottom electrode separated by an undamaged ferroelectric layer to produce a reliable ferroelectric random access memory device. In some embodiments, the method includes depositing a ferroelectric layer above the bottom electrode layer and depositing a top electrode layer above the ferroelectric layer. A first removal step is performed to remove the bottom electrode layer, the ferroelectric layer, and the peripheral portion of the top electrode layer. The first removal step may use a first mask. A second removal step is then performed using a second etch that is selective to the bottom electrode layer and the top electrode layer, and the mask is not used. The second etch causes the ferroelectric layer to protrude outward from between the bottom electrode layer and the top electrode layer, thereby causing the relevant portion of the ferroelectric layer that may have been damaged by plasma to be outside the bottom electrode layer and the top electrode layer.

[0152] Therefore, one embodiment of the present disclosure provides a fabrication method that prevents damaged portions of a ferroelectric layer from being used to operate an FRAM device, thereby producing a reliable FRAM device.

[0153] Figure 1A A cross-sectional view 100A of some embodiments of an integrated wafer including a ferroelectric random access memory cell is shown.

[0154] The integrated chip in the cross-sectional view 100A includes a ferroelectric random access memory cell 101 arranged above a substrate 102. In some embodiments, the ferroelectric random access memory cell 101 includes a ferroelectric layer 114 between a bottom electrode 112 and a top electrode 116. The ferroelectric layer 114, the bottom electrode 112, and the top electrode 116 are vertically stacked layers extending laterally. In some embodiments, the ferroelectric layer 114 directly contacts a first surface 112u of the bottom electrode 112 and a second surface 116b of the top electrode 116. The bottom electrode 112 is separated from the substrate 102 by one or more lower interconnect layers 109 embedded in a dielectric structure 106. The dielectric structure 106 may include one or more stacked interlayer dielectric (ILD) layers. In some embodiments, the one or more lower interconnect layers 109 include interconnect vias 108 and interconnect wiring 110. The bottom electrode via 108b couples the bottom electrode 112 to the access transistor 104 disposed in the substrate 102, and the top electrode 116 is coupled to the top electrode via 108t.

[0155] In some embodiments, the ferroelectric layer 114 extends laterally across the bottom electrode 112 and the top electrode 116 such that the ferroelectric layer 114 has an outermost wall 114s that is laterally separated from the outermost wall 112s of the bottom electrode 112 and from the outermost wall 116s of the top electrode 116. In other words, a vertically extending axis along the outermost wall 114s of the ferroelectric layer 114 will not intersect the bottom electrode 112 or the top electrode 116, wherein the vertically extending axis is substantially orthogonal to the top surface of the ferroelectric layer 114. The outermost wall 114s of the ferroelectric layer 114 is laterally separated from the outermost wall 112s of the bottom electrode and the outermost wall 116s of the top electrode 116 by a first distance d1. In some embodiments, the first distance d1 is in a range between approximately 5 nanometers and approximately 10 nanometers.

[0156] In some embodiments, during the formation of the ferroelectric random access memory cell 101, the outermost wall 114s of the ferroelectric layer 114 may be damaged due to the plasma etching action. The plasma damage causes the ferroelectric layer 114 to have a damaged region 114d along the outermost wall 114s. Therefore, the first distance d1 may be greater than or equal to the depth of the damaged region 114d of the ferroelectric layer 114 at its outermost wall 114s to prevent the damaged region 114d of the ferroelectric layer 114 from being used to store data in the ferroelectric random access memory cell 101. Alternatively, the undamaged portion of the ferroelectric layer 114 is arranged between the top electrode 116 and the bottom electrode 112 for reliably storing data in the ferroelectric random access memory cell 101.

[0157] Figure 1B A cross-sectional view 100B of some embodiments of a ferroelectric random access memory cell having a ferroelectric layer with damaged outer sidewalls is shown.

[0158] The cross-sectional view 100B shows a Figure 1A The ferroelectric random access memory cell 101 is provided with a ferroelectric layer 114 having a protruding portion 114p surrounding a central portion 114c. In some embodiments, the protruding portion 114p is defined between lines 130 extending along a first surface 112u of the bottom electrode 112 and a second surface 116b of the top electrode 116. In some embodiments, the central portion 114c is also defined between the lines 130. The central portion 114c is in direct contact with the bottom electrode 112 and the top electrode 116, so that the ferroelectric random access memory cell is operated by using the central portion 114c of the ferroelectric layer 114 instead of the protruding portion 114p of the ferroelectric layer 114. The protruding portion 114p of the ferroelectric layer 114 extends laterally in a first direction over the outermost wall 112s of the bottom electrode 112 and the outermost wall 116s of the top electrode 116. In some embodiments, the first direction is perpendicular to a second direction, which is orthogonal to the first surface 112u of the bottom electrode 112. The protruding portion 114 p includes the outermost wall 114 s of the ferroelectric layer 114 .

[0159] In some embodiments, during the formation of the ferroelectric random access memory cell 101, the outermost wall 114s of the ferroelectric layer 114 is damaged due to the action of plasma etching. In some embodiments, the plasma damage causes the ferroelectric layer 114 to have a damaged region 114d along the outermost wall 114s. The damaged region 114d may have a larger surface roughness at the outermost wall 114s than the top surface or the bottom surface of the ferroelectric layer 114, thereby indicating etching damage on the outermost wall 114s of the ferroelectric layer 114. In other embodiments, the surface roughness of the outermost wall 114s and the surface roughness of the top surface or the bottom surface of the ferroelectric layer 114 may be comparable, and thus, damage to the ferroelectric layer 114 (although present) may not be indicated via surface roughness measurement. For example, damage to the ferroelectric layer 114 in the damaged region 114d may include dislocations, dangling bonds, and / or vacancies, thereby disturbing the crystal structure and, therefore, the ferroelectric properties of the ferroelectric layer 114. Nevertheless, in Figure 1B In the cross-sectional view 100B, damage to the outermost wall 114s of the ferroelectric layer 114 is shown by the high surface roughness.

[0160] The damaged region 114d of the ferroelectric layer 114 may extend from the outermost sidewall 114s into the ferroelectric layer 114 by a second distance d2. In some embodiments, the second distance d2 is less than the first distance d1. In other embodiments, the second distance d2 is substantially equal to the first distance d1. Therefore, in some embodiments, the protruding portion 114p of the ferroelectric layer 114 includes the damaged region 114d of the ferroelectric layer 114, while the central portion 114c of the ferroelectric layer 114 includes an undamaged portion of the ferroelectric layer 114 to reliably store data.

[0161] In some embodiments, the ferroelectric layer 114 may have an upper surface laterally outside the bottom electrode 112 and the top electrode 116 that is recessed directly below the upper surface of the ferroelectric layer 114 between the bottom electrode 112 and the top electrode 116. In such embodiments, the thickness of the ferroelectric layer 114 below the top electrode 116 may have a greater thickness than laterally outside the top electrode 116. In some additional embodiments, the ferroelectric layer 114 may have a lower surface laterally outside the bottom electrode 112 and the top electrode 116 that is directly above the lower surface of the ferroelectric layer 114 between the bottom electrode 112 and the top electrode 116.

[0162] In some embodiments, the top electrode 116 and the bottom electrode 112 include the same material. In other embodiments, the top electrode 116 may include a different material than the bottom electrode 112. In some embodiments, the top electrode 116 and / or the bottom electrode 112 may include multiple layers of conductive materials.

[0163] Figure 2A A cross-sectional view 200A of some embodiments of a ferroelectric random access memory cell including top and bottom electrodes each including a variety of materials is shown.

[0164] The ferroelectric random access memory cell of cross-sectional view 200A includes a bottom electrode having a second layer 212 disposed above a first layer 202. The first layer 202 of the bottom electrode is coupled to and directly contacts the bottom electrode via 108b. The ferroelectric layer 114 is above the second layer 212 of the bottom electrode. In some embodiments, the top surface of the second layer 212 of the bottom electrode directly contacts the bottom surface of the ferroelectric layer 114. Above the ferroelectric layer 114 is a top electrode having a first layer 204 disposed above a second layer 216. In some embodiments, the bottom surface of the second layer 216 of the top electrode directly contacts the top surface of the ferroelectric layer 114. The first layer 204 of the top electrode is between the second layer 216 of the top electrode and the top electrode via 108t. In some embodiments, the ferroelectric layer 114 extends laterally across the second layer 212 of the bottom electrode and the second layer 216 of the top electrode, such that a damaged region 114d of the ferroelectric layer 114 is not reliable for data storage. In some embodiments, the ferroelectric layer 114 extends laterally beyond the outermost wall 216s of the second layer 216 of the top electrode and extends laterally beyond the outermost wall 212s of the second layer 212 of the bottom electrode by a first distance d1.

[0165] In some embodiments, the outermost wall 114s of the ferroelectric layer 114 may be substantially laterally aligned with the outermost wall 204s of the first layer 204 of the top electrode and the outermost wall 202s of the first layer 202 of the bottom electrode (i.e., aligned along a vertical line perpendicular to the bottom surface of the dielectric structure 106). In other embodiments (not shown), the outermost wall 114s of the ferroelectric layer 114 may be laterally between the outermost wall 204s of the first layer 204 of the top electrode and / or the outermost wall 202s of the first layer 202 of the bottom electrode.

[0166] In some embodiments, the first layer 204 of the top electrode and the first layer 202 of the bottom electrode include a first material, and the second layer 216 of the top electrode and the second layer 212 of the bottom electrode include a second material different from the first material. In other embodiments, the first layer 202 of the bottom electrode, the first layer 204 of the top electrode, the second layer 212 of the bottom electrode, and the second layer 216 of the top electrode may each include a different material from each other.

[0167] Figure 2B A cross-sectional view 200B of an additional embodiment of a FRAM cell including multiple top and bottom electrodes is shown.

[0168] Figure 2B The cross-sectional view 200B includes Figure 2AIn some embodiments, the outermost wall 202s of the first layer 202 of the bottom electrode and the outermost wall 204s of the first layer 204 of the top electrode may extend laterally beyond the outermost wall 114s of the ferroelectric layer 114 by a third distance d3, and the third distance d3 is greater than the first distance d1. In the cross-sectional views 200A and 200B, the outermost wall 202s of the first layer 202 of the bottom electrode and the outermost wall 204s of the first layer 204 of the top electrode are substantially vertically aligned. In other embodiments, due to etching effects, the outermost wall 202s of the first layer 202 of the bottom electrode and the outermost wall 204s of the first layer 204 of the top electrode may be slightly misaligned vertically.

[0169] Figure 3 A cross-sectional diagram 300 of some embodiments of a ferroelectric random access memory cell including a ferroelectric layer having a topmost surface above topmost surfaces of a top electrode and a bottom electrode is shown.

[0170] The ferroelectric random access memory cell shown in the cross-sectional view 300 includes a bottom electrode 112 having an outer protrusion 112p. The outer protrusion 112p extends from a central top surface 112c of the bottom electrode 112 to a topmost surface 112t of the bottom electrode 112, wherein the topmost surface 112t is above the central top surface 112c. The ferroelectric layer 114 is disposed along an inner surface of the outer protrusion 112p of the bottom electrode 112 and along the central top surface 112c of the bottom electrode 112. The top electrode 116 is within the inner surface of the ferroelectric layer 114. In some embodiments, the ferroelectric layer 114 extends over the topmost surface 112t of the bottom electrode 112, such that the topmost surface 114t of the ferroelectric layer 114 is above the topmost surface 112t of the bottom electrode 112. In some embodiments, the top electrode 116 directly contacts the ferroelectric layer 114 and has a topmost surface 116t that is below the topmost surface 114t of the ferroelectric layer 114. In some embodiments, a portion of the ferroelectric layer 114 and a portion of the bottom electrode 112 meet at an interface 302. A first line 304 parallel to the interface 302 may be between the bottom electrode 112 and the top electrode 116, and may also extend through the topmost surface 114t of the ferroelectric layer 114. In some embodiments, the topmost surface 114t of the ferroelectric layer 114 may also be the topmost surface of the ferroelectric layer 114. In some embodiments, the topmost surface 114t of the ferroelectric layer 114 is above the topmost surface 116t of the top electrode 116 and / or the topmost surface 112t of the bottom electrode 112 by a distance d1. In some embodiments, the distance d1 is in a range between approximately 5 nanometers and approximately 10 nanometers. In some embodiments, the topmost surface 114t of the ferroelectric layer 114 may be damaged due to etching effects during patterning, thereby defining a damaged region 114d of the ferroelectric layer, and thus, the damaged region 114d is not in contact with the bottom electrode 112 and the top electrode 116. Alternatively, the undamaged portion of the ferroelectric layer 114 is surrounded by the bottom electrode 112 and the top electrode 116 to reliably store data in the ferroelectric random access memory cell.

[0171] Figure 4 A cross-sectional diagram 400 of some embodiments of a ferroelectric random access memory cell including a top electrode having additional layers is shown.

[0172] Figure 4 The cross-sectional view 400 includes Figure 3106 and has an additional layer 402 of a top electrode. In some embodiments, the additional layer 402 of a top electrode is arranged above the top electrode 116 so that the sidewalls and the bottom surface of the additional layer 402 of a top electrode contact the top electrode 116. In some embodiments, the topmost surface 402t of the additional layer 402 of a top electrode is substantially aligned with the topmost surface 114t of the ferroelectric layer 114. In other embodiments, the topmost surface 402t of the additional layer 402 of a top electrode may be substantially aligned with the topmost surface 116t of the top electrode 116. The additional layer 402 of a top electrode is separated from the ferroelectric layer 114 by the dielectric structure 106 and the top electrode 116. In some embodiments, the additional layer 402 of a top electrode includes a different material from the top electrode 116. In some embodiments, the additional layer 402 of a top electrode also includes a different material from the bottom electrode 112.

[0173] Figure 5A A cross-sectional view 500A of some embodiments of an integrated wafer having a ferroelectric random access memory cell is shown.

[0174] Figure 5A The cross-sectional view 500A includes a ferroelectric random access memory cell 101 coupled to an access transistor 104. The access transistor 104 includes a drain region 104a and a source region 104b within a substrate 102. A gate electrode 104c is between the drain region 104a and the source region 104b and above the substrate 102. A gate dielectric layer 104d separates the gate electrode 104c from the substrate 102. A dielectric structure 106 is disposed above the substrate 102 and surrounds an interconnect via 108 and an interconnect wire 110. In some embodiments, the source region 104b is coupled to a source line SL, and the gate electrode 104c is coupled to a word line WL. In some embodiments, a top electrode 116 of the ferroelectric random access memory cell 101 may be coupled to a bit line BL, and a bottom electrode 112 of the ferroelectric random access memory cell 101 may be coupled to the drain region 104a. When the FRAM cell 101 is accessed via the bit line BL, the word line WL, and the source line SL, the first or second data state can be written into or read from the FRAM cell 101 via the ferroelectric layer 114. The ferroelectric layer 114 has a damaged region 114d, which may have a damaged crystal structure and therefore does not contact the bottom electrode 112 or the top electrode 116, so that the FRAM cell 101 stores data on the undamaged portion of the ferroelectric layer 114.

[0175] Figure 5B A cross-sectional view 500B of another embodiment of an integrated wafer having a ferroelectric gate layer is shown.

[0176] Figure 5B 500B includes another embodiment of an access transistor 104 having a ferroelectric gate layer 502 disposed above a substrate 102. The access transistor 104 also includes a drain region 104a and a source region 104b, which are adjacent to the ferroelectric gate layer 502 and disposed within the substrate 102. A dielectric structure 106 is disposed above the substrate 102 and surrounds an interconnect via 108 and an interconnect wire 110. In some embodiments, the drain region 104a is coupled to a bit line BL and the source region 104b is coupled to a source line SL. When the access transistor 104 is accessed via the bit line BL, the word line WL, and the source line SL, a first or second data state can be written to or read from the ferroelectric gate layer 502. The ferroelectric gate layer 502 has a topmost sidewall that is laterally separated from an outermost sidewall of the word line WL. The outermost sidewall of the ferroelectric gate layer 502 may have a damaged crystal structure, thereby defining a damaged gate region 502d, and in some embodiments, the damaged gate region 502d of the ferroelectric gate layer 502 does not contact the word line WL, thus facilitating data storage.

[0177] Figures 6 to 13 Cross-sectional views 600-1300 of some embodiments of methods of forming an integrated wafer having a ferroelectric random access memory cell are shown. Figures 6 to 13 The description is about the method, it should be understood that Figures 6 to 13 The structures disclosed in are not limited to this method, but can stand alone as structures independent of this method.

[0178] like Figure 6 As shown in the cross-sectional view 600 of FIG. 60 , a substrate 102 is provided. In various embodiments, the substrate 102 may include any type of semiconductor body (e.g., silicon / CMOS bulk, SiGe, SOI, etc.), such as a semiconductor wafer or one or more dies on a wafer, as well as any other type of semiconductor and / or epitaxial layer formed thereon and / or other semiconductors associated therewith. An access transistor 104 may be formed over the substrate 102 and may include a drain region 104a, a source region 104b, a gate electrode 104c, and a gate dielectric layer 104d. One or more lower interconnect layers 109 are formed within a dielectric structure 106 disposed over the substrate 102 and are coupled to the access transistor 104. In some embodiments, one or more of the one or more lower interconnect layers 109 may be formed using a damascene process (e.g., a single damascene process or a dual damascene process). The one or more lower interconnect layers 109 may include an interconnect via 108 and an interconnect wire 110. In some embodiments, the one or more lower interconnect layers 109 may include tungsten, copper, and / or aluminum, and / or the like.

[0179] In some embodiments, for example, the dielectric structure 106 may include a nitride (e.g., silicon nitride, silicon oxynitride), a carbide (e.g., silicon carbide), an oxide (e.g., silicon oxide), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), a low dielectric constant oxide (e.g., carbon-doped oxide, SiCOH), or the like. In some embodiments, an etch stop layer 602 is formed over the dielectric structure 106 and one of the interconnect wires 110. In some embodiments, the etch stop layer 602 may include a different material than the dielectric structure 106. In other embodiments, the etch stop layer 602 may include the same material as the dielectric structure 106. For example, the etch stop layer 602 may include an oxide (e.g., a silicon-rich oxide), a nitride (e.g., silicon nitride, silicon oxynitride), a carbide (e.g., silicon carbide), or the like. In some embodiments, the dielectric structure 106 and the etch stop layer 602 may be deposited by a physical vapor deposition technique (e.g., PVD, CVD, PE-CVD, ALD, etc.).

[0180] like Figure 7 As shown in the cross-sectional view 700 of FIG. 7 , the etch stop layer 602 is patterned, and the bottom electrode via 108 b is formed in the etch stop layer 602. In some embodiments, the bottom electrode via 108 b may be formed using a damascene process (e.g., a single damascene process or a dual damascene process). The damascene process is performed by etching the etch stop layer 602 to form a via hole and / or a metal trench, and filling the via hole and / or the metal trench with the bottom electrode via 108 b. In some embodiments, the bottom electrode via 108 b including a conductive material may be formed using a deposition process and / or a plating process (e.g., electroplating, electroless plating, etc.). In some embodiments, the bottom electrode via 108 b is part of one or more lower interconnect layers 109, and thus may include tungsten, copper, and / or aluminum, and / or the like.

[0181] FIG. 8A to FIG. 8D Shows the formation Figure 1A and Figure 1B Cross-sectional views 800A-800D of some embodiments of a method of fabricating a ferroelectric random access memory cell 101 are shown.

[0182] like Fig. 8AAs shown in cross-sectional view 800A of , a bottom electrode layer 812 is formed over the etch stop layer 602 and the bottom electrode via 108b. In some embodiments, the bottom electrode layer 812 may be formed using a deposition process and / or a plating process (e.g., electroplating, electroless plating, etc.). A ferroelectric material 814 is then formed over the bottom electrode layer 812. In some embodiments, the ferroelectric material 814 includes a ferroelectric material such as, for example, strontium bismuth tantalate, lead zirconium titanate, hafnium zirconium oxide, doped hafnium oxide, or the like. In some embodiments, the ferroelectric material 814 may have a thickness ranging between about 10 angstroms and about 200 angstroms. In some embodiments, the ferroelectric material 814 may be formed by an atomic layer deposition process. A top electrode layer 816 is then deposited over the ferroelectric material 814. In some embodiments, the top electrode layer 816 may be formed using a deposition process and / or a plating process (e.g., electroplating, electroless plating, etc.). In some embodiments, the bottom electrode layer 812 and the top electrode layer 816 may each include, for example, titanium nitride, tantalum nitride, tungsten, ruthenium, iridium, or the like. In some embodiments, the top electrode layer 816 and the bottom electrode layer 812 may include the same material, while in other embodiments, the top electrode layer 816 and the bottom electrode layer 812 may include different materials. In some embodiments, the bottom electrode layer 812 and the top electrode layer 816 may each have a thickness ranging between approximately 50 nanometers and approximately 300 nanometers.

[0183] like Figure 8B As shown in the cross-sectional view 800B of FIG. 800B , a first mask 802 is formed over the top electrode layer 816. In some embodiments, the first mask 802 is substantially centered over the bottom electrode through hole 108b. In some embodiments, the first mask 802 may include a photosensitive material (e.g., a photoresist) formed by a spin coating process and then selectively exposed to electromagnetic radiation according to the photomask. The electromagnetic radiation modifies the solubility of the exposed areas within the photosensitive material to define dissolved areas. The photosensitive material is then developed to remove the dissolved areas, thereby forming the first mask 802 in the cross-sectional view 800B. In other embodiments, the first mask 802 may include a silicon nitride layer, a silicon carbide layer, or the like.

[0184] like Figure 8C As shown in the cross-sectional view 800C of FIG. 800A , a first etching 804 is performed according to the first mask 802, thereby removing the first mask ( Figure 8C802 in the embodiment of the present invention, and forms a patterned bottom electrode 822, a ferroelectric layer 114, and a patterned top electrode 826. The patterned bottom electrode 822 has an intermediate outer surface 822i, and the patterned top electrode 826 has an intermediate outer surface 826i defined by the first etch 804. After the first etch 804, the patterned top electrode 826 may have a first thickness t1. The first thickness t1 may be in a range between about 50 nanometers and about 300 nanometers. In some embodiments, the first etch 804 may be a dry plasma etch (e.g., an RF plasma-based etch). In other embodiments, the first etch 804 may be a wet etch. The first etch 804 is selective to the materials of the patterned bottom electrode 822, the ferroelectric layer 114, and the patterned top electrode 826. In some embodiments, the first etch 804 causes the ferroelectric layer 114 to have a damaged area 114d along its outermost sidewall 114s. In other words, the first etch 804 may cause damage to any exposed areas of the ferroelectric layer 114 .

[0185] Because the crystal structure of the ferroelectric layer 114 contributes to the final ferroelectric random access memory cell ( Figure 1A 101), the damage to the crystal structure of the damaged region 114d of the ferroelectric layer 114 by the first etch 804 will cause the ferroelectric random access memory device to be unreliable. In some embodiments, the damage to the crystal structure at the damaged region 114d by the first etch 804 (e.g., plasma etching) may include, for example, loss of ferroelectric transistor structure, biased crystal structure orientation, dislocation, vacancy, dangling bond, or the like. The damaged region 114d may extend from the outermost sidewall 114s of the ferroelectric layer 114 to a second distance d2. In some embodiments, the second distance d2 may be in a range between about 5 nanometers and about 10 nanometers.

[0186] like Fig.8D As shown in the cross-sectional view 800D, the first mask ( Figure 8C 802), and a second etch 806 is performed to define the bottom electrode 112 and the top electrode 116. The second etch 806 has an effect on the patterned bottom electrode ( Figure 8C 822) and patterned top electrode ( Figure 8C 826) has a high selectivity, thereby removing a larger amount of the patterned bottom electrode ( Figure 8C 822) and patterned top electrode ( Figure 8C 826). In some embodiments, because the patterned bottom electrode ( Figure 8C 822) and patterned top electrode ( Figure 8C826) includes the same material, which is different from the material of the ferroelectric layer 114. Compared with the ferroelectric layer 114, the second etch 806 has a greater effect on the patterned bottom electrode ( Figure 8C 822) and patterned top electrode ( Figure 8C Therefore, in some embodiments, the ferroelectric layer 114 is substantially unaffected during the second etch 806. The etch stop layer 602 is also substantially unaffected by the second etch 806 and thus protects the bottom electrode via 108b during the second etch 806.

[0187] In some embodiments, the second etch 806 may be a wet etch, such as, for example, an organic solvent (e.g., methanol) or an aqueous solution of ammonium hydroxide and hydrogen peroxide. In other embodiments, the second etch 806 may be a dry etch, such as, for example, sputtering, chemical etching, ion-enhanced etching, RF plasma-based etching. In some embodiments, when the second etch 806 is a chemical etch, the second etch 806 is isotropic and has a wide angle of arrival distribution due to the flux from the chemical. In other words, the second etch 806 effectively targets and laterally removes the patterned bottom electrode ( Figure 8C 822), including the patterned bottom electrode ( Figure 8C The middle outer wall of 822) Figure 8C 822i) to form the bottom electrode 112. The second etch 806 also effectively targets and laterally removes the patterned top electrode ( Figure 8C 826), including a patterned top electrode ( Figure 8C The middle outer wall of 826) Figure 8C 826i) to form the top electrode 116. In some embodiments, the second etch 806 also removes the patterned top electrode ( Figure 8C 826), so that the top electrode 116 has a second thickness t2 less than the first thickness t1. In some embodiments, the second thickness t2 is about 5 nanometers to about 10 nanometers less than the first thickness t1.

[0188] After the second etch 806, the bottom electrode 112 has a first width w1, which is measured as the maximum distance between the outermost walls of the bottom electrode 112. The top electrode 116 has a second width w2, which is measured as the maximum distance between the outermost walls of the top electrode 116. The ferroelectric layer 114 has a third width w3, which is measured as the maximum distance between the outermost walls of the ferroelectric layer 114. In some embodiments, after the second etch, the third width w3 is greater than the first width w1 and the second width w2. In some embodiments, the third width w3 may be greater than a measurement of the first width w1 in the range between approximately 5 nanometers and approximately 10 nanometers. In some embodiments, the third width w3 may be greater than a measurement of the second width w2 in the range between approximately 5 nanometers and approximately 10 nanometers. Therefore, in some embodiments, the second etch 806 removes at least the patterned bottom electrode ( Figure 8C 822) external and patterned top electrode ( Figure 8C 826), which vertically surrounds the damaged region 114d of the ferroelectric layer 114 from the first etch 804. Therefore, in some embodiments, the difference between the third width w3 and the second width w2 and / or the difference between the third width w3 and the first width w1 is at least equal to the second distance ( Figure 8C In some embodiments, the outermost walls of the top electrode 116 and the bottom electrode 112 are substantially aligned, while in other embodiments, the outermost walls of the top electrode 116 and the bottom electrode 112 may not be aligned due to the uneven etching rate of the second etching 806. For example, in some embodiments, the first width w1 may be greater than the second width w2. After the second etching 806, the damaged region 114d of the ferroelectric layer 114 does not contact the top electrode 116 and the bottom electrode 112.

[0189] 9A to 9D Shows the formation Figure 2A Some embodiments of a ferroelectric random access memory cell method are cross-sectional views 900A-900D. Fig. 9A from Figure 7 Continue (skip FIG. 8A to FIG. 8D action).

[0190] like Fig. 9AAs shown in cross-sectional view 900A of , the first material 902 of the bottom electrode layer is deposited over the etch stop layer 602 and the bottom electrode via 108b. The second material 912 of the bottom electrode layer is deposited over the first material 902 of the bottom electrode layer. A ferroelectric material 914 is then deposited over the second material 912 of the bottom electrode layer. In some embodiments, the ferroelectric material 914 includes a ferroelectric material such as, for example, strontium bismuth tantalate, lead zirconium titanate, hafnium zirconium oxide, doped hafnium oxide, or the like. In some embodiments, the ferroelectric material 914 may have a thickness in a range between about 10 angstroms and about 200 angstroms. In some embodiments, the ferroelectric material 914 may be formed by an atomic layer deposition process. In some embodiments, the first material 904 of the top electrode layer over the second material 916 of the top electrode layer may be deposited over the ferroelectric material 914. In some embodiments, the first material 902 and the second material 912 of the bottom electrode layer and the first material 904 and the second material 916 of the top electrode layer may be formed using a deposition process and / or a plating process (e.g., electroplating, electroless plating, etc.). In some embodiments, the first material 902 and the second material 912 of the bottom electrode layer and the first material 904 and the second material 916 of the top electrode layer may each include, for example, titanium nitride, tantalum nitride, tungsten, ruthenium, iridium, or the like. In some embodiments, the first material 904 of the top electrode layer and the first material 902 of the bottom electrode layer may include a first material, while the second material 916 of the top electrode layer and the second material 912 of the bottom electrode layer may include a second material different from the first material. In other embodiments, the first material 902 of the bottom electrode layer, the second material 912 of the bottom electrode layer, the first material 904 of the top electrode layer, and the second material 916 of the top electrode layer may each include different materials, the same material, or a combination thereof. In some embodiments, the first material 902 of the bottom electrode layer and the first material 904 of the top electrode layer may each have a thickness in the range of about 100 nanometers and about 300 nanometers. In some embodiments, the second material 912 of the bottom electrode layer and the second material 916 of the top electrode layer may each have a thickness in the range of about 50 nanometers and about 300 nanometers.

[0191] like Fig. 9B As shown in the cross-sectional view 900B, the first mask 802 is formed above the first material 904 of the top electrode layer. In some embodiments, the first mask 802 in the cross-sectional view 900B presents Figure 8B The cross-sectional view 800B has the same characteristics as the first mask 802.

[0192] like Fig. 9C As shown in the cross-sectional view 900C, the first etching 804 is performed according to the second mask 920, thereby removing the Fig. 9BThe first etch 804 in the cross-sectional view 900C at least shows the first material 904 and the second material 916 of the top electrode layer, the ferroelectric material 914, and the first material 902 and the second material 912 of the bottom electrode layer, and forms the patterned first layer 924 of the top electrode, the patterned second layer 926 of the top electrode, the ferroelectric layer 114, the patterned first layer 930 of the bottom electrode, and the patterned second layer 932 of the bottom electrode. Figure 8C In some embodiments, the first etch 804 may have similar characteristics to the first etch 804 in the cross-sectional view 800C of FIG. In addition, the first etch 804 in the cross-sectional view 900C is selective to the patterned first layer 930 and the second layer 932 of the bottom electrode, the patterned first layer 924 and the second layer 926 of the top electrode, and the ferroelectric layer 114. After the first etch 804, the patterned second layer 926 of the top electrode may have a third thickness t3. In some embodiments, the first etch 804 causes the ferroelectric layer 114 to have a damaged region 114d at its outermost sidewall 114s. The damage to the crystal structure of the damaged region 114d may extend from the outermost sidewall 114s of the ferroelectric layer 114 to a second distance d2. In some embodiments, the second distance d2 may be in a range between approximately 5 nanometers and approximately 10 nanometers.

[0193] like Fig.9D As shown in the cross-sectional view 900D, the first mask ( Fig. 9C 802), and a second etch 806 is performed. The second etch 806 in the cross-sectional view 900D presents Fig.8D The second etch 806 in the cross-sectional view 800D has similar characteristics. In some embodiments, the second etch 806 in the cross-sectional view 900D has similar characteristics to the second layer ( Fig. 9C The material of the patterned second layer (932, 926) of the bottom electrode and the top electrode is highly selective, thereby forming the second layer 212 of the bottom electrode and the second layer 216 of the top electrode. In some embodiments, the patterned second layer ( Fig. 9C In other words, the second etching 906 (such as Fig.8D ) for selectively targeting and laterally removing the patterned second layer ( Fig. 9C 932) and the patterned second layer of the top electrode ( Fig. 9C 926) to form the second layer 212 of the bottom electrode and the second layer 216 of the top electrode. In addition, in some embodiments, the second etch 806 can remove the patterned first layer ( Fig. 9C930, 924), thereby forming the first layer 202 of the bottom electrode and the first layer 204 of the top electrode. For example, after the second etch 806, the first layer 204 of the top electrode may have a fourth thickness t4. In some embodiments, due to the vertical residual etching effect of the second etch 806, the fourth thickness t4 may be less than the third thickness ( Fig. 9C In such an embodiment, the difference between the fourth thickness t4 and the third thickness (t3) may be in a range between about 5 nanometers and about 10 nanometers. In other embodiments, the patterned first layer ( Fig. 9C 930, 924) may be substantially unaffected by the second etch 806.

[0194] After the second etch 806, the second layer 212 of the bottom electrode has a first width w1, which is measured as the maximum distance between the outermost walls of the second layer 212 of the bottom electrode. The second layer 216 of the top electrode has a second width w2, which is measured as the maximum distance between the outermost walls of the second layer 216 of the top electrode. The ferroelectric layer 114 has a third width w3, which is measured as the maximum distance between the outermost walls of the ferroelectric layer 114. In some embodiments, after the second etch, the third width w3 is greater than the first width w1 and the second width w2. In some embodiments, the third width w3 may be greater than a measurement of the first width w1 in the range between approximately 5 nanometers and approximately 10 nanometers. In some embodiments, the third width w3 may be greater than a measurement of the second width w2 in the range between approximately 5 nanometers and approximately 10 nanometers. Therefore, in some embodiments, the second etch 806 removes at least the patterned second layer ( Fig. 9C The second layer of the patterned outer and top electrodes (932) Fig. 9C 926), which vertically surrounds the damaged region 114d of the ferroelectric layer 114 from the first etch 804. Therefore, in some embodiments, the difference between the third width w3 and the second width w2 and / or the difference between the third width w3 and the first width w1 is at least equal to the second distance ( Fig. 9C In some embodiments, the outermost walls of the second layer 216 of the top electrode and the second layer 212 of the bottom electrode are substantially aligned, while in other embodiments, the outermost walls of the second layer 216 of the top electrode and the second layer 212 of the bottom electrode may not be aligned due to the uneven etching rate of the second etching 806. For example, in some embodiments, the first width w1 may be greater than the second width w2. After the second etching 806, the damaged region 114d of the ferroelectric layer 114 does not contact the second layers 216, 212 of the top electrode and the bottom electrode.

[0195] In addition, in some embodiments, after the second etch 806, the first layer 202 of the bottom electrode has a fourth width w4, which is measured as the maximum distance between the outermost walls of the first layer 202 of the bottom electrode. The first layer 204 of the top electrode has a fifth width w5, which is measured as the maximum distance between the outermost walls of the first layer 204 of the top electrode. In some embodiments, after the second etch 806, the fourth width w4 is greater than the first width w1 and the second width w2. Similarly, in some embodiments, the fifth width w5 is greater than the first width w1 and the second width w2. In some embodiments, the fourth width w4 is equal to the fifth width w5, and the third width w3 is less than the fourth width w4 and the fifth width w5. In such embodiments, the difference between the fifth width w5 and the third width w3 and the difference between the fourth width w4 and the third width w3 may be in the range between about 0 nanometers and about 10 nanometers. In other embodiments, the third width w3, the fourth width w4, and the fifth width w5 may be approximately equal to each other. Nevertheless, the damaged region 114d of the ferroelectric layer 114 is not in contact with the second layer 216 of the top electrode and the second layer 212 of the bottom electrode, and therefore, has a Fig.9D The resulting FRAM device of the structure in the cross-sectional view 900D will not rely on the damaged region 114 d of the ferroelectric layer 114 for data storage.

[0196] FIG. 10A to FIG. 10E Shows the formation Figure 3 Some embodiments of a ferroelectric random access memory cell method are shown in cross-sectional views 1000A-1000E. Fig. 10A from Figure 7 Continue (skip FIG. 8A to FIG. 8D as well as 9A to 9D action).

[0197] like Fig. 10A As shown in the cross-sectional view 1000A of , the upper dielectric layer 1002 is deposited over the etch stop layer 602 and the bottom electrode via 108b. In some embodiments, the upper dielectric layer 1002 comprises the same material as the dielectric structure 106. Similarly, the upper dielectric layer 1002 can be deposited by physical vapor deposition techniques (e.g., PVD, CVD, PE-CVD, ALD, etc.).

[0198] like Fig. 10B As shown in the cross-sectional view 1000B of FIG. 1 , the upper dielectric layer 1002 is patterned to define a cavity 1004 in the upper dielectric layer 1002. The upper dielectric layer 1002 may be patterned using photolithography and etching techniques. The upper dielectric layer 1002 has inner sidewalls 1002s defining the cavity 1004. The bottom surface of the cavity 1004 exposes the bottom electrode via 108b.

[0199] like Fig. 10C As shown in the cross-sectional view 1000C of FIG. 1000 , the conformal bottom electrode layer 1012 is above the upper dielectric layer 1002 and in the cavity ( Fig. 10B 1004). In some embodiments, the conformal bottom electrode layer 1012 has a thickness in a range between about 100 nanometers and about 1 micron. The conformal ferroelectric layer 1014 is deposited over the conformal bottom electrode layer 1012. In some embodiments, the conformal ferroelectric layer 1014 has a thickness in a range between about 10 angstroms and about 200 angstroms. The conformal top electrode layer 1016 is deposited over the conformal ferroelectric layer 1014. In some embodiments, the conformal top electrode layer 1016 has a thickness in a range between about 200 nanometers and about 2 microns. In some embodiments, the conformal top electrode layer 1016 can be formed to have a substantially flat top surface. In some embodiments, the conformal top electrode 1016 and the conformal bottom electrode 1012 can be formed using a deposition process and / or a plating process (e.g., electroplating, electroless plating, etc.). In some embodiments, the conformal bottom electrode layer 1012 and the conformal top electrode layer 1016 may each include, for example, titanium nitride, tantalum nitride, tungsten, ruthenium, iridium, or the like. In some embodiments, the conformal top electrode layer 1016 and the conformal bottom electrode layer 1012 may include the same material, while in other embodiments, the conformal top electrode layer 1016 and the conformal bottom electrode layer 1012 may include different materials.

[0200] As shown in cross-sectional view 1000D, a removal step 1006 is performed to remove the conformal bottom electrode layer ( Fig. 10C 1012), conformal ferroelectric layer ( Fig. 10C 1014), and a conformal top electrode layer ( Fig. 10C 1016). After the removal step 1006, the conformal top electrode 1026, the ferroelectric layer 114, the conformal bottom electrode 1022, and the upper dielectric layer 1002 have substantially coplanar top surfaces. In some embodiments, the removal step 1006 can be a planarization process (e.g., chemical mechanical planarization) or a vertical etch (e.g., wet etching, dry etching). In some embodiments, the removal step 1006 causes the ferroelectric layer 114 to have a damaged region 114d at its topmost surface 114t. The damaged region 114d of the ferroelectric layer 114 has damage to its crystal structure, resulting in unreliable ferroelectric properties of the damaged region 114d. The damaged region 114d of the ferroelectric layer 114 may extend from the topmost surface 114t of the ferroelectric layer 114 to a second distance d2. In some embodiments, the second distance d2 may be in a range between approximately 5 nanometers and approximately 10 nanometers.

[0201] As shown in cross-sectional view 1000E, a third etch 1008 is performed, which is selective to the material of the conformal top electrode (1026 of cross-sectional view 1000D) and the material of the conformal bottom electrode (1022 of cross-sectional view 1000D). The third etch 1008 does not remove a portion of the ferroelectric layer 114. In some embodiments, the third etch 1008 can be a wet etch, such as, for example, an organic solvent (e.g., methanol) or an aqueous solution of ammonium hydroxide and hydrogen peroxide. In other embodiments, the third etch 1008 can be a dry etch, such as, for example, sputter etching, chemical etching, ion enhanced etching, RF plasma-based etching. After the third etch 1008, the top electrode 116 and the bottom electrode 112 have a topmost surface that is a first distance d1 below the topmost surface 114t of the ferroelectric layer 114. The first distance d1 is at least equal to the second distance d2, so that in some embodiments, the third etch 1008 removes a portion of the conformal top electrode (1026 of the cross-sectional view 1000D) and a portion of the conformal bottom electrode (1022 of the cross-sectional view 1000D) such that the damaged region 114d of the ferroelectric layer 114 is not in contact with the top electrode 116 and the bottom electrode 112. Therefore, the damaged region 114d of the ferroelectric layer 114 from the removal step 1006 is not included in the data storage of the final ferroelectric random access memory device.

[0202] FIG. 11A to FIG. 11E Shows the formation Figure 4 Some embodiments of a ferroelectric random access memory cell method are shown in cross-sectional views 1100A-1100E. Fig.11A from Figure 7 Continue (skip FIG. 8A to FIG. 8D , 9A to 9D ,as well as FIG. 10A to FIG. 10E action).

[0203] like Fig.11A As shown in the cross-sectional view 1100A of FIG. 1100A , the upper dielectric layer 1002 is deposited over the etch stop layer 602 and the bottom electrode via 108 b. The upper dielectric layer 1002 in the cross-sectional view 1100A is shown as Fig. 10A The upper dielectric layer 1002 has similar characteristics as in the cross-sectional view 1000A.

[0204] like Fig. 11B As shown in the cross-sectional view 1100B of FIG. 1 , the upper dielectric layer 1002 is patterned to define a cavity 1004 in the upper dielectric layer 1002. The upper dielectric layer 1002 may be patterned using photolithography and etching techniques. Fig. 10BThe upper dielectric layer 1002 in the cross-sectional view 1000B of FIG. 100B has inner sidewalls 1002s defining a cavity 1004. The bottom surface of the cavity 1004 exposes the bottom electrode through-hole 108b.

[0205] like Fig. 11C As shown in the cross-sectional view 1100C, then Fig. 10C 1000C, where an additional conformal top electrode layer 1102 is additionally deposited over the conformal top electrode layer 1016. Thus, in the cross-sectional view 1100C, the conformal bottom electrode layer 1012, the conformal ferroelectric layer 1014, and the conformal top electrode layer 1016 are deposited onto the surface of the substrate. Fig. 10C The cavity described in the description of Fig. 11B 1004). Subsequently, an additional conformal top electrode layer 1102 is deposited over the conformal top electrode layer 1016. In some embodiments, the additional conformal top electrode layer 1102 has a substantially flat top surface. In some embodiments, the conformal bottom electrode layer 1012 has a thickness in a range between about 100 nanometers and about 1 micron. In some embodiments, the conformal ferroelectric layer 1014 has a thickness in a range between about 10 angstroms and about 200 angstroms. In some embodiments, the conformal top electrode layer 1016 has a thickness in a range between about 100 nanometers and about 1 micron. In some embodiments, the additional conformal top electrode layer 1102 has a thickness in a range between about 200 nanometers and about 2 microns. In some embodiments, similar to the conformal top electrode 1016 and the conformal bottom electrode 1012, the additional conformal top electrode layer 1102 can be formed using a deposition process and / or a plating process (e.g., electroplating, electroless plating, etc.).

[0206] In some embodiments, the conformal bottom electrode layer 1012 and the conformal top electrode layer 1016 may each include, for example, titanium nitride, tantalum nitride, tungsten, ruthenium, iridium, or the like. In some embodiments, the conformal top electrode layer 1016 and the conformal bottom electrode layer 1012 may include the same material, while in other embodiments, the conformal top electrode layer 1016 and the conformal bottom electrode layer 1012 may include different materials. In some embodiments, the additional conformal top electrode layer 1102 may include a different material than the conformal top electrode layer 1016 and the conformal bottom electrode layer 1012. In some embodiments, the additional conformal top electrode layer 1102 may include, for example, titanium nitride, tantalum nitride, tungsten, ruthenium, iridium, or the like.

[0207] like Fig.11D As shown in the cross-sectional view 1100D of FIG. 1100 , the removal step 1006 is performed. Fig.11D The removal step 1006 in the cross-sectional view 1100D includes Fig. 10D The same features as those of the removal step 1006 in the cross-sectional view 1000D of FIG. 1100D are also removed in the removal step 1006 of the cross-sectional view 1100D. Fig. 11C 1102), so that after the removal step 1006, the conformal bottom electrode 1022, the ferroelectric layer 114, the conformal top electrode 1026, the upper dielectric layer 1002, and the additional layer 402 of the top electrode have substantially coplanar top surfaces. In some embodiments, the removal step 1006 may cause the ferroelectric layer 114 to have a damaged region 114d at its topmost surface 114t. The damaged region 114d has damage to its crystal structure, thereby causing the ferroelectric properties of the damaged region 114d to be unreliable. The damage to the crystal structure of the damaged region 114d may extend from the topmost surface 114t of the ferroelectric layer 114 to a second distance d2. In some embodiments, the second distance d2 may be in a range between approximately 5 nanometers and approximately 10 nanometers.

[0208] like Fig.11E As shown in cross-sectional view 1100E of FIG. 1100A , a third etch 1008 is performed that is selective to the material of the conformal top electrode ( 1026 of cross-sectional view 1100D ) and the material of the conformal bottom electrode ( 1022 of cross-sectional view 1100D ). The third etch 1008 in cross-sectional view 1100E includes the same characteristics as the third etch 1008 in cross-sectional view 1000E . In addition, in some embodiments, Fig.11E The third etch 1008 in the cross-sectional view 1100E of FIG. 100A does not remove a portion of the additional layer of top electrode 402. In other embodiments, a small portion of the top surface of the additional layer of top electrode 402 may be removed due to residual effects from the third etch 1008. In some embodiments, the topmost surface of the additional layer of top electrode 402 is above the topmost surface of the top electrode 116. In some embodiments, the top electrode 116 and the ferroelectric layer 114 have topmost surfaces that are substantially aligned. In other embodiments (not shown), the topmost surface of the additional layer of top electrode 402 may be substantially coplanar with the topmost surface of the top electrode 116.

[0209] After the third etch 1008, the bottom electrode 112 and the top electrode 116 have topmost surfaces below the topmost surface 114t of the ferroelectric layer 114 by a first distance d1. The first distance d1 is at least equal to the second distance d2, such that in some embodiments, the third etch 1008 removes a portion of the conformal top electrode (1026 of the cross-sectional view 1100D) and a portion of the conformal bottom electrode (1022 of the cross-sectional view 1100D), such that a damaged region 114d of the ferroelectric layer 114 extending from the topmost surface 114t of the ferroelectric layer 114 is not in direct contact with the top electrode 116 and the bottom electrode 112. Therefore, the damaged region 114d of the ferroelectric layer 114 from the removal step 1006 is not included in the data storage of the final ferroelectric random access memory device, such that the final ferroelectric random access memory device is more reliable due to the third etch 1008.

[0210] Figure 12 to Figure 13 Shown in Figure 1A Cross-sectional views 1200 - 1300 of some embodiments of methods for forming a dielectric structure and a top electrode via above a ferroelectric random access memory cell 101 are shown. Fig.12 from Fig.8D Continue (skip 9A to 9D , FIG. 10A to FIG. 10E ,as well as FIG. 11A to FIG. 11E action). You will understand that Figure 12 to Figure 13 The steps in Fig.8D and can also be applied to Fig.9D , Fig.10E ,and Fig.11E The embodiments are used to form a top electrode via and a dielectric structure above a ferroelectric random access memory cell.

[0211] like Fig.12 As shown in the cross-sectional view 1200 of , the dielectric structure 106 is deposited over the top electrode 116 such that the dielectric structure 106 surrounds the bottom electrode 112, the ferroelectric layer 114, and the top electrode 116. In some embodiments, for example, the dielectric structure 106 may include a nitride (e.g., silicon nitride, silicon oxynitride), a carbide (e.g., silicon carbide), an oxide (e.g., silicon oxide), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), a low dielectric constant oxide (e.g., carbon-doped oxide, SiCOH), or the like. In some embodiments, the dielectric structure 106 may be deposited by a physical vapor deposition technique (e.g., PVD, CVD, PE-CVD, ALD, etc.).

[0212] like Fig.13As shown in the cross-sectional view 1300 of FIG. 1300 , the dielectric structure 106 is patterned and a conductive material is deposited to form a top electrode via 108t coupled to the top electrode 116. Similar to the formation of the bottom electrode via 108b, in some embodiments, the top electrode via 108t may be formed using a damascene process (e.g., a single damascene process or a dual damascene process). The dielectric structure 106 is etched to form a via and / or a metal trench, and the via and / or the metal trench is filled with the top electrode via 108t. In some embodiments, the top electrode via 108t including the conductive material may be formed using a deposition process and / or a plating process (e.g., electroplating, electroless plating, etc.). In some embodiments, the top electrode via 108t is part of one or more lower interconnect layers 109, and thus may include tungsten, copper, or aluminum copper, or the like.

[0213] Fig.14 It shows that the formation of Figures 6 to 13 A flow chart of some embodiments of a method 1400 for integrating a ferroelectric random access memory cell into a wafer is shown.

[0214] Although method 1400 is shown and described as a series of actions or events in the following text, it should be understood that the order of the actions or events shown should not be interpreted as a limitation of the disclosed embodiments. For example, some actions can occur in different orders and / or occur simultaneously with other actions or events other than those shown and / or described in an embodiment of this invention. In addition, all the actions shown are not necessary for implementing one or more aspects or embodiments described herein. In addition, one or more actions in the actions described in an embodiment of this invention can be performed in one or more independent actions and / or stages.

[0215] At 1402, a first access transistor is formed in a substrate.

[0216] At 1404, one or more interconnect layers are formed within a dielectric structure over a substrate. Figure 6 and Figure 7 Cross-sectional views 600 and 700 are shown that may correspond to some embodiments of acts 1402 and 1404 .

[0217] At 1406, a bottom electrode layer is deposited over the dielectric structure. The bottom electrode layer is coupled to the first access transistor through one or more interconnect layers.

[0218] At 1408, a ferroelectric layer is deposited over the bottom electrode layer.

[0219] At 1410, a top electrode layer is deposited over the ferroelectric layer. Fig. 8A , Fig. 9A , Fig. 10A ,and Fig.11ACross-sectional views 800A, 900A, 1000A, and 1100A are shown that may correspond to various embodiments of acts 1406, 1408, and 1410, respectively.

[0220] At 1412, the bottom electrode layer, the top electrode layer, and the ferroelectric layer are patterned using a first etch to remove peripheral portions of the bottom electrode layer, the top electrode layer, and the ferroelectric layer. Figure 8C , Fig. 9C , Fig. 10C ,and Fig. 11C Cross-sectional views 800C, 900C, 1000C, and 1100C are shown, respectively, that may correspond to various embodiments of act 1412 .

[0221] At 1414, a second etch selective to the bottom electrode layer and the top electrode layer is performed to remove portions of the bottom electrode layer and the top electrode layer. The ferroelectric layer has a surface that protrudes beyond a surface of the bottom electrode layer and a surface of the top electrode layer, wherein the surface of the bottom electrode layer and the surface of the top electrode layer are formed by the second etch. Fig.8D , Fig.9D , Fig. 10D ,and Fig.11D Cross-sectional views 800D, 900D, 1000D, and 1100D are shown, respectively, which may correspond to various embodiments of act 1414 .

[0222] An additional interconnect layer is formed within the additional layer of the dielectric structure at 1416. The additional interconnect layer is above and coupled to the top electrode layer. Fig.12 and Fig.13 Cross-sectional views 1200 and 1300 are shown, which may correspond to act 1416 .

[0223] Thus, one embodiment of the present disclosure is related to a method of manufacturing a ferroelectric random access memory cell so that a damaged region of the ferroelectric layer does not directly contact the top electrode and the bottom electrode to prevent the damaged region of the ferroelectric layer from unreliably storing data in the ferroelectric random access memory cell.

[0224] Thus, in some embodiments, an embodiment of the present disclosure relates to an integrated chip, comprising: one or more lower interconnect layers arranged within one or more stacked interlayer dielectric (ILD) layers above a substrate; a bottom electrode disposed above the one or more lower interconnect layers; a top electrode disposed above the bottom electrode; and a ferroelectric layer disposed between a first surface of the bottom electrode and a second surface of the top electrode and contacting the first surface and the second surface, wherein the ferroelectric layer comprises protrusions extending over outer surfaces of the top electrode and the bottom electrode along a first direction perpendicular to a second direction, the second direction being orthogonal to the first surface, the protrusions being defined between lines extending along the first surface and the second surface.

[0225] In some embodiments, the protrusion of the ferroelectric layer includes a damaged area separated from the outer surfaces of the top electrode and the bottom electrode. In some embodiments, the protrusion of the ferroelectric layer has a first surface connecting the second and third surfaces of the protrusion, wherein the first surface has a surface roughness greater than the second and third surfaces of the protrusion. In some embodiments, the protrusion has a thickness measured in the second direction, the thickness is less than the distance between the first surface of the bottom electrode and the second surface of the top electrode measured in the second direction. In some embodiments, the outer surfaces of the top electrode and the bottom electrode are the topmost surfaces of the top electrode and the bottom electrode. In some embodiments, the bottom electrode has a first width, the first width is the maximum distance of the bottom electrode in the second direction, the top electrode has a second width, the second width is the maximum distance of the top electrode in the second direction, and the ferroelectric layer has a third width, the third width is the maximum distance of the ferroelectric layer in the second direction, wherein the third width is greater than the first width and the second width. In some embodiments, the integrated wafer further comprises: an additional layer of a top electrode disposed above the top electrode; and an additional layer of a bottom electrode disposed below the bottom electrode, wherein the additional layer of the top electrode has a fourth width, the fourth width being a maximum distance between a plurality of outermost walls of the additional layer of the top electrode, wherein the additional layer of the bottom electrode has a fifth width, the fifth width being a maximum distance between a plurality of outermost walls of the additional layer of the bottom electrode, and wherein the third width is less than or equal to the fourth width and the fifth width. In some embodiments, the bottom electrode and the top electrode comprise a first material, and wherein the additional layer of the top electrode and the additional layer of the bottom electrode comprise a second material different from the first material.

[0226] In other embodiments, an embodiment of the present disclosure is directed to an integrated chip comprising: one or more lower interconnect layers arranged within one or more stacked interlayer dielectric (ILD) layers above a substrate; a bottom electrode disposed above the one or more lower interconnect layers; a top electrode disposed above the bottom electrode; and a ferroelectric layer disposed between the bottom electrode and the top electrode and extending over outer surfaces of the top electrode and the bottom electrode, wherein lines parallel to an interface between the bottom electrode and the ferroelectric layer and between the bottom electrode and the top electrode extend through an outermost surface of the ferroelectric layer.

[0227] In some embodiments, the wire is below the bottommost surface of the top electrode and above the topmost surface of the bottom electrode. In some embodiments, the wire is perpendicular to the topmost surfaces of the top electrode and the bottom electrode. In some embodiments, the outermost surface of the ferroelectric layer has a higher surface roughness than other surfaces of the ferroelectric layer. In some embodiments, the integrated wafer further includes an additional layer of the top electrode, arranged above the top electrode, wherein the lower portion of the additional layer of the top electrode is surrounded by the top electrode, wherein the upper portion of the additional layer of the top electrode extends beyond the outer surface of the top electrode. In some embodiments, the ferroelectric layer is spaced apart from the upper portion of the additional layer of the top electrode by one or more stacked interlayer dielectric layers.

[0228] In some other embodiments, an embodiment of the present disclosure is related to a method of forming an integrated chip, comprising: depositing a ferroelectric layer above a bottom electrode layer; depositing a top electrode layer above the ferroelectric layer; performing a first removal step to remove the bottom electrode layer, the ferroelectric layer, and peripheral portions of the top electrode layer; and performing a second removal step to remove portions of the bottom electrode layer and the top electrode layer using a second etch that is selective to the bottom electrode layer and the top electrode layer, wherein after the second removal step, the ferroelectric layer has a surface that protrudes beyond the surfaces of the bottom electrode layer and the top electrode layer.

[0229] In some embodiments, after the first removal step and before the second removal step, the bottom electrode layer and the top electrode layer each have an intermediate outer surface defined by the first removal step, and wherein the portions of the bottom electrode layer and the top electrode layer removed by the second removal step include the intermediate outer surfaces of the bottom electrode layer and the top electrode layer. In some embodiments, after the first removal step and before the second removal step, the top electrode layer has a first thickness, and wherein after the second removal step, the top electrode layer has a second thickness less than the first thickness. In some embodiments, after the first removal step and before the second removal step, the ferroelectric layer has a plurality of surfaces exposed to the first removal step, the surfaces having a surface roughness greater than surfaces of the ferroelectric layer not exposed to the first removal step. In some embodiments, before performing the first removal step and after depositing the top electrode layer, the method further includes depositing an additional layer of the top electrode layer above the top electrode layer. In some embodiments, the first removal step removes a peripheral portion of the additional layer of the top electrode layer, and wherein the second etch is not selective to the additional layer of the top electrode layer.

[0230] The features of several embodiments are summarized above so that those skilled in the art can better understand the aspects of an embodiment of the present disclosure. Those skilled in the art should understand that an embodiment of the present disclosure can be easily used as a basis for designing or modifying other processes and structures to implement the same purpose and / or achieve the same advantages of the embodiment introduced in an embodiment of the present disclosure. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of an embodiment of the present disclosure, and various changes, substitutions and modifications of an embodiment of the present disclosure can be made without departing from the spirit and scope of an embodiment of the present disclosure.

Claims

1. An integrated chip, characterized in that: Include: one or more lower interconnect layers disposed within one or more stacked interlayer dielectric layers over a substrate; a first bottom electrode disposed above the one or more lower interconnect layers; a second bottom electrode disposed above the first bottom electrode; a first top electrode disposed above the second bottom electrode; a second top electrode disposed between the first top electrode and the second bottom electrode; as well as A ferroelectric layer is arranged between a first surface of the second bottom electrode and a second surface of the second top electrode and contacts the first surface and the second surface, wherein the ferroelectric layer includes a protrusion extending over the outer surface of the second top electrode and the second bottom electrode along a first direction perpendicular to a second direction, the second direction is orthogonal to the first surface, and the protrusion is confined between lines extending along the first surface and the second surface, wherein the width of the ferroelectric layer is greater than the width of the second bottom electrode, the width of the ferroelectric layer is greater than the width of the second top electrode, the width of the first bottom electrode is greater than the width of the ferroelectric layer, and the width of the first top electrode is greater than the width of the ferroelectric layer.

2. The integrated chip according to claim 1, characterized in that: The protrusion of the ferroelectric layer has a first surface connecting a second surface and a third surface of the protrusion, wherein a surface roughness of the first surface is greater than a surface roughness of the second surface and the third surface of the protrusion.

3. The integrated chip according to claim 1, characterized in that: The protrusion has a thickness measured in the second direction, and the thickness is smaller than a distance between the first surface of the second bottom electrode and the second surface of the second top electrode measured in the second direction.

4. The integrated chip according to claim 1, characterized in that: The first bottom electrode and the first top electrode include a first material, and the second top electrode and the second bottom electrode include a second material different from the first material.

5. An integrated chip, characterized in that: Include: one or more lower interconnect layers disposed within one or more stacked interlayer dielectric layers over a substrate; a bottom electrode disposed above the one or more lower interconnect layers; a top electrode disposed above the bottom electrode; as well as A ferroelectric layer is disposed between a first surface of the bottom electrode and a second surface of the top electrode and contacts the first surface and the second surface, the ferroelectric layer comprising a protrusion extending over the outer surfaces of the top electrode and the bottom electrode along a first direction perpendicular to a second direction, the second direction being orthogonal to the first surface, the protrusion being defined between lines extending along the first surface and the second surface, wherein the protrusion has a thickness measured in the second direction, the thickness being less than a distance between the first surface of the bottom electrode and the second surface of the top electrode measured in the second direction, wherein a bottommost surface of the protrusion is above the first surface of the bottom electrode, and a topmost surface of the protrusion is below the second surface of the top electrode.

6. The integrated chip according to claim 5, characterized in that: The protrusion of the ferroelectric layer has an outermost surface with a surface roughness higher than that of other surfaces of the ferroelectric layer.

7. The integrated chip according to claim 5, characterized in that: Further including: An additional layer of the top electrode is disposed above the top electrode, wherein a width of the additional layer of the top electrode is greater than a width of the top electrode.

8. The integrated chip according to claim 7, characterized in that: The ferroelectric layer and the additional layer of the top electrode are separated from the top electrode by the one or more stacked interlayer dielectric layers.

9. A method for forming an integrated chip, characterized in that: Include: depositing a second bottom electrode layer over a first bottom electrode layer; depositing a ferroelectric layer over the second bottom electrode layer; depositing a second top electrode layer over the ferroelectric layer; depositing a first top electrode layer above the second top electrode layer; performing a first removal step to remove peripheral portions of the first bottom electrode layer, the second bottom electrode layer, the ferroelectric layer, the first top electrode layer, and the second top electrode layer; and A second removal step is performed using a second etch that is selective to the first bottom electrode layer and the second bottom electrode layer and the first top electrode layer and the second top electrode layer to remove portions of the second bottom electrode layer and the second top electrode layer, wherein after the second removal step, the ferroelectric layer has a surface that protrudes beyond an outer surface of the second bottom electrode layer and the second top electrode layer, wherein after the second removal step, the width of the ferroelectric layer is greater than the width of the second bottom electrode, the width of the ferroelectric layer is greater than the width of the second top electrode, the width of the first bottom electrode is greater than the width of the ferroelectric layer, and the width of the first top electrode is greater than the width of the ferroelectric layer.

10. The method according to claim 9, characterized in that Wherein after the first removing step and before the second removing step, the first top electrode layer has a first thickness, and wherein after the second removing step, the first top electrode layer has a second thickness less than the first thickness.

11. The method according to claim 9, characterized in that Wherein after the first removal step and before the second removal step, the ferroelectric layer has multiple surfaces exposed to the first removal step, and a surface roughness of the multiple surfaces is greater than a surface roughness of a surface of the ferroelectric layer not exposed to the first removal step.

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