Semiconductor memory devices

Abstract

A semiconductor memory device includes: a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer between the first semiconductor layer and the second semiconductor layer; a gate electrode arranged on the second semiconductor layer and spaced apart from each other in a first direction perpendicular to an upper surface of the second semiconductor layer; and a channel structure surrounded by the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the gate electrode, each corresponding channel structure in the channel structure includes a gate insulating film, a channel layer, and a buried insulating film, the gate insulating film includes a tunnel insulating film adjacent to the channel layer, a charge blocking film adjacent to the gate electrode, and a charge storage film between the tunnel insulating film and the charge blocking film, the charge storage film including an upper cover protruding toward the outside of the corresponding channel structure.

Description

Technical Field

[0001] Some example embodiments relate to semiconductor memory devices. More particularly, some example embodiments relate to semiconductor memory devices having improved integration. Background Art

[0002] Recently, due to the multifunctionalization of information communication equipment, there is a demand for large-capacity and highly integrated semiconductor memory devices. As the integration of semiconductor memory devices increases, the impact of process distribution on the performance of semiconductor memory devices also increases. Therefore, various methods of controlling process distribution to improve the reliability of semiconductor memory devices will be needed. Summary of the invention

[0003] Some example embodiments provide a semiconductor memory device having improved reliability and a method of manufacturing the same.

[0004] Some example embodiments are not limited to the above-mentioned tasks, and other tasks not mentioned may be clearly understood by those skilled in the art from the following description.

[0005] According to some example embodiments, a semiconductor memory device is provided, comprising: a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer between the first semiconductor layer and the second semiconductor layer; a plurality of gate electrodes arranged on the second semiconductor layer and spaced apart from each other in a first direction perpendicular to an upper surface of the second semiconductor layer; and a plurality of channel structures surrounded by the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer and the plurality of gate electrodes, each corresponding channel structure of the plurality of channel structures comprising a gate insulating film, a channel layer, and a buried insulating film, the gate insulating film comprising a tunnel insulating film adjacent to the channel layer, a charge blocking film adjacent to the plurality of gate electrodes, and a charge storage film between the tunnel insulating film and the charge blocking film, the charge storage film comprising an upper cover protruding toward the outside of the corresponding channel structure.

[0006] According to some example embodiments, a semiconductor memory device is provided, comprising: a first semiconductor layer and a second semiconductor layer arranged on the first semiconductor layer; a plurality of gate electrodes arranged on the second semiconductor layer and spaced apart from each other in a first direction perpendicular to an upper surface of the second semiconductor layer; and a plurality of channel structures penetrating the first semiconductor layer and the second semiconductor layer and the plurality of gate electrodes in the first direction, each of the plurality of channel structures comprising a gate insulating film, a channel layer and a buried insulating film, the channel layer being connected to the first semiconductor layer, the gate insulating film comprising an upper charge storage film in contact with a side surface of the second semiconductor layer.

[0007] According to some example embodiments, there is provided a semiconductor memory device, comprising: a first semiconductor layer, a second semiconductor layer on the first semiconductor layer, and a third semiconductor layer between the first and second semiconductor layers; a plurality of gate electrodes spaced apart from each other in a first direction perpendicular to an upper surface of the second semiconductor layer, the plurality of gate electrodes forming a word line cut portion in the first direction, the word line cut portion separating the plurality of gate electrodes in a second direction perpendicular to the first direction; and a plurality of channel structures penetrating the second and third semiconductor layers and the plurality of gate electrodes in the first direction, each corresponding channel structure of the plurality of channel structures comprising a gate insulating film, a channel layer, and a buried insulating film, the third semiconductor layer comprising an opening partially exposing an upper surface of the first semiconductor layer, the second semiconductor layer comprising a supporting connection structure contacting the first semiconductor layer at the opening, the gate insulating film comprising an upper tunnel insulating film, an upper charge blocking film, and an upper charge storage film between the upper tunnel insulating film and the upper charge blocking film, the upper charge storage film comprising an upper cap protruding toward the outside of the corresponding channel structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Some example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1A is a cross-sectional view for explaining a semiconductor memory device according to some example embodiments;

[0010] Figure 1B yes Figure 1A an enlarged partial cross-sectional view of a portion of;

[0011] Figure 2 and Figure 3 is a flowchart for explaining a method of manufacturing a semiconductor memory device according to some example embodiments; and

[0012] Figures 4 to 13 is a cross-sectional view for explaining a method of manufacturing a semiconductor memory device according to some example embodiments. DETAILED DESCRIPTION

[0013] Figure 1A is a cross-sectional view for explaining a semiconductor memory device 10 according to some example embodiments, Figure 1B yes Figure 1A An enlarged partial cross-sectional view of region E1.

[0014] Reference Figure 1A and Figure 1B, the semiconductor memory device 10 may include a conductive flat plate 200, a semiconductor layer 201 disposed on the conductive flat plate 200, and / or an insulating film 230 and a gate electrode 240 alternately stacked on the semiconductor layer 201. The semiconductor memory device 10 may include a first upper insulating film 261, a second upper insulating film 263, and / or a third upper insulating film 265 disposed on a structure in which the insulating film 230 and the gate electrode 240 are alternately stacked (e.g., a structure consisting of the alternately stacked insulating film 230 and the gate electrode 240). According to some example embodiments, the semiconductor memory device 10 may further include a channel structure 250 penetrating the insulating film 230 and the gate electrode 240, and a first bit line contact path 271 and / or a second bit line contact path 273, an upper conductive pattern 281 (e.g., a conductive structure and / or region), and / or a bit line BL with which the channel structure 250 may operate as a memory cell array. According to some example embodiments, the gate electrodes 240 include uppermost and second uppermost gate electrodes 240 (SE), a lowermost gate electrode 240 (GE), and several gate electrodes 240 (WE) between the second uppermost gate electrode 240 (SE) and the lowermost gate electrode 240 (GE).

[0015] According to some example embodiments, the conductive plate 200 may be in the form of a plate. According to some example embodiments, the conductive plate 200 may include tungsten (W) or a tungsten (W) compound. The peripheral circuit may be formed below the conductive plate 200 and / or formed horizontally with the common source line (e.g., at a position such as Figure 1A According to some example embodiments, the peripheral circuit may include a circuit for controlling the operation of the semiconductor memory device 10, for example, a control logic, a row decoder, a page buffer, and / or the like. The conductive plate 200 may be formed on a semiconductor substrate such as a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, and / or may be formed on an epitaxial thin film obtained by performing selective epitaxial growth (SEG).

[0016] According to some example embodiments, the semiconductor layer 201 may support the insulating film 230 and the gate electrode 240. According to some example embodiments, the semiconductor layer 201 may include, but is not limited to, a plurality of layers. For example, the semiconductor layer may also include and / or constitute a single layer.

[0017] According to some example embodiments, the semiconductor layer 201 may include a first semiconductor layer 201a disposed on the conductive plate 200, a second semiconductor layer 201b disposed on the first semiconductor layer 201a, and a third semiconductor layer 201c disposed between the first semiconductor layer 201a and the second semiconductor layer 201b. According to some example embodiments, the conductive plate 200 may be in contact with the first semiconductor layer 201a. According to some example embodiments, the first semiconductor layer 201a may be in contact with the third semiconductor layer 201c. According to some example embodiments, the third semiconductor layer 201c may be in contact with the second semiconductor layer 201b. According to some example embodiments, the third semiconductor layer 201c may include an opening 201op exposing a portion of an upper surface of the first semiconductor layer 201a. According to some example embodiments, the second semiconductor layer 201b may include a support connection structure 201bl in contact with the first semiconductor layer 201a through the opening 201op. According to some example embodiments, the first to third semiconductor layers 201a, 201b, and 201c may include polycrystalline silicon. According to some example embodiments, the first to third semiconductor layers 201a, 201b, and 201c may include doped polysilicon. According to some example embodiments, the first to third semiconductor layers 201a, 201b, and 201c may be doped at the same or substantially the same concentration, but some example embodiments are not limited thereto. According to some example embodiments, when the first to third semiconductor layers 201a, 201b, and 201c are doped at the same or substantially the same concentration, the first to third semiconductor layers 201a, 201b, and 201c may be integrated into a single layer, but some example embodiments are not limited thereto. Even when the first to third semiconductor layers 201a, 201b, and 201c have the same concentration or substantially the same concentration, the first to third semiconductor layers 201a, 201b, and 201c may be distinguished from each other. According to some example embodiments, the first to third semiconductor layers 201a, 201b, and 201c may be separate layers doped at different concentrations.

[0018] Here, the direction perpendicular or substantially perpendicular to the upper surface of the semiconductor layer 201 is referred to as the first direction (Z direction), and the two directions parallel or substantially parallel to the upper surface of the semiconductor layer 201 are referred to as the second direction and the third direction (X direction and Y direction). The second direction and the third direction (X direction and Y direction) may be perpendicular or substantially perpendicular to each other. Here, the term "vertical direction" may refer to a direction parallel or substantially parallel to the first direction (Z direction), and the term "vertical level" may refer to the height from a reference plane (e.g., the upper surface of the semiconductor layer 201) in the first direction (Z direction). In addition, the term "horizontal direction" may refer to the second direction (X direction) or the third direction (Y direction), or may refer to a direction perpendicular or substantially perpendicular to the first direction (Z direction) and inclined relative to the second direction (X direction) and the third direction (Y direction). According to some example embodiments, the X direction, the Y direction and / or the Z direction may also include directions opposite thereto. Unless otherwise specified in all the drawings, the definition of the directions is the same as in Figure 1A Same as in.

[0019] According to some example embodiments, the gate electrodes 240 and the insulating film 230 may be alternately arranged in the first direction (Z direction). According to some example embodiments, the gate electrodes 240 may be insulated from each other by the insulating film 230 arranged therebetween. According to some example embodiments, the gate electrodes 240 located at the same vertical level or similar vertical levels may be separated by a word line cutting portion (WLC) and / or a string selection line cutting portion (SLC). According to some example embodiments, the gate electrode 240 may extend in the second direction (X direction).

[0020] According to some example embodiments, the gate electrode 240 may include a conductive material. According to some example embodiments, the gate electrode 240 may include, but is not limited to, tungsten, tantalum, cobalt, nickel, tungsten silicide, tantalum silicide, cobalt silicide, and / or nickel silicide. According to some example embodiments, the gate electrode 240 may also include polysilicon.

[0021] According to some example embodiments, the gate electrodes 240 may each include a plurality of layers. According to some example embodiments, the gate electrodes 240 may each include a first barrier layer 241, a second barrier layer 242, and / or a gate conductive layer 243. According to some example embodiments, the first barrier layer 241, the second barrier layer 242, and the gate conductive layer 243 may each include different materials. According to some example embodiments, the first barrier layer 241 and the second barrier layer 242 may have a constant thickness. According to some example embodiments, the first barrier layer 241 and the second barrier layer 242 may have the same thickness as each other or a thickness similar to each other. According to some example embodiments, the first barrier layer 241 may include, but is not limited to, a metal oxide (e.g., aluminum oxide), a metal nitride, and / or a metal oxynitride. According to some example embodiments, the second barrier layer 242 may include, but is not limited to, titanium nitride. According to some example embodiments, the gate conductive layer 243 may include, but is not limited to, tungsten.

[0022] According to some example embodiments, the first and second bit line contact vias 271 and 273, the upper conductive pattern 281, and the bit line BL to be described below may include any one or more of the above-mentioned materials of the gate electrode 240 (e.g., tungsten, tantalum, cobalt, nickel, tungsten silicide, tantalum silicide, cobalt silicide, and / or nickel silicide).

[0023] According to some example embodiments, first to third upper insulating films 261, 263, and 265 may be disposed on the uppermost gate electrode 240 (SE). The first to third upper insulating films 261, 263, and 265 may include an insulating material (eg, silicon oxide and / or the like).

[0024] According to some example embodiments, a plurality of channel structures 250 may penetrate the first upper insulating film 261, the gate electrode 240, the insulating film 230, and / or the second semiconductor layer 201b and the third semiconductor layer 201c in the first direction (Z direction). According to some example embodiments, a plurality of channel structures 250 may be surrounded or partially surrounded by the first upper insulating film 261, the gate electrode 240, the insulating film 230, and / or the second semiconductor layer 201b and the third semiconductor layer 201c. According to some example embodiments, the bottom of the channel structure 250 may be surrounded or partially surrounded by the first semiconductor layer 201a. Therefore, the upper surface of the channel structure 250 may be coplanar or substantially coplanar with the first upper insulating film 261 (e.g., with the upper surface of the first upper insulating film 261), and the lower surface of the channel structure 250 may be located at a lower level than the upper surface of the first semiconductor layer 201a. Adjacent channel structures 250 may be spaced apart from each other at predetermined or determined intervals in the second and third directions (X and Y directions).

[0025] According to some example embodiments, the channel structure 250 may have a high aspect ratio. According to some example embodiments, the channel structure 250 may have a circular horizontal cross-sectional shape or a nearly circular horizontal cross-sectional shape, but is not limited thereto. According to some example embodiments, the channel structure 250 may include a tapered structure. Here, the channel structure 250 having a tapered structure means that the width of the upper portion of the channel structure 250 is greater than the width of the lower portion thereof.

[0026] According to some example embodiments, each of the channel structures 250 may include a plurality of layers According to some example embodiments, the channel structures 250 may each include a gate insulating film 251 , a channel layer 253 , and / or a buried insulating film 255 .

[0027] According to some example embodiments, the gate insulating film 251 may constitute a bottom surface and / or an outer side surface of each of the channel structures 250. According to some example embodiments, the gate insulating film 251 may insulate the channel layer 253 from the gate electrode 240.

[0028] According to some example embodiments, the gate insulating film 251 may include a plurality of layers. According to some example embodiments, the gate insulating film 251 may include an upper gate insulating film 251u and a lower gate insulating film 251d. According to some example embodiments, the upper gate insulating film 251u and the lower gate insulating film 251d may be spaced apart from each other with the third semiconductor layer 201c therebetween. According to some example embodiments, the upper gate insulating film 251u may include an upper tunnel insulating film 251au, an upper charge storage film 251bu, and / or an upper charge blocking film 251cu. According to some example embodiments, the lower gate insulating film 251d may include a lower tunnel insulating film 251ad, a lower charge storage film 251bd, and / or a lower charge blocking film 251cd.

[0029] According to some example embodiments, the upper tunnel insulating film 251au and the lower tunnel insulating film 251ad may include silicon oxide, hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, and / or the like. According to some example embodiments, the upper tunnel insulating film 251au and the lower tunnel insulating film 251ad may be formed by forming the tunnel insulating film 251a (see Figure 7B ) are separated and formed.

[0030] According to some example embodiments, the upper tunnel insulating film 251au may be in contact with the third semiconductor layer 201c. According to some example embodiments, a lower surface of the upper tunnel insulating film 251au may be in contact with the third semiconductor layer 201c. According to some example embodiments, a side surface of the upper tunnel insulating film 251au may be in contact with the channel layer 253 and / or the upper charge storage film 251bu. According to some example embodiments, a first side surface of the upper tunnel insulating film 251au may be in contact with the channel layer 253, and a second side surface of the upper tunnel insulating film 251au may be in contact with the upper charge storage film 251bu.

[0031] According to some example embodiments, the lower tunnel insulating film 251ad may be in contact with the third semiconductor layer 201c. According to some example embodiments, an upper surface of the lower tunnel insulating film 251ad may be in contact with the third semiconductor layer 201c. According to some example embodiments, a side surface of the lower tunnel insulating film 251ad may be in contact with the channel layer 253 and / or the lower charge storage film 251bd. According to some example embodiments, a first side surface of the lower tunnel insulating film 251ad may be in contact with the channel layer 253, and a second side surface of the lower tunnel insulating film 251ad may be in contact with the lower charge storage film 251bd.

[0032] According to some example embodiments, the upper charge storage film 251bu and the lower charge storage film 251bd may include silicon nitride, boron nitride, silicon boron nitride, and / or polysilicon doped with impurities. According to some example embodiments, the upper charge storage film 251bu and the lower charge storage film 251bd may each include a material having a high etching selectivity with respect to each of the upper tunnel insulating film 251au and the lower tunnel insulating film 251ad. For example, when the upper tunnel insulating film 251au and the lower tunnel insulating film 251ad include silicon oxide, the upper charge storage film 251bu and the lower charge storage film 251bd may include silicon nitride, but are not limited thereto.

[0033] According to some example embodiments, the upper charge storage film 251bu may be a region in which electrons tunneling from the channel layer 253 through the upper tunnel insulating film 251au are stored. According to some example embodiments, since the upper charge storage film 251bu may be disposed at the same vertical level as the gate electrode 240 or at a similar vertical level, charges for data storage may be stored by applying a voltage to the gate electrode 240. Since the lower charge storage film 251bd is disposed below the gate electrode 240, charges for data storage may not be stored. According to some example embodiments, the upper charge storage film 251bu and the lower charge storage film 251bd may be formed by forming the charge storage film 251b (see Figure 7B) are separated and formed.

[0034] According to some example embodiments, the upper charge storage film 251bu may be between the upper tunnel insulating film 251au and the upper charge blocking film 251cu. According to some example embodiments, the upper charge storage film 251bu may be in contact with the upper tunnel insulating film 251au and the upper charge blocking film 251cu. According to some example embodiments, the upper charge storage film 251bu may be in contact with the second semiconductor layer 201b and the third semiconductor layer 201c. According to some example embodiments, a lower surface of the upper charge storage film 251bu may be in contact with the third semiconductor layer 201c. According to some example embodiments, among the lower surface of the upper tunnel insulating film 251au, the lower surface of the upper charge storage film 251bu, and the lower surface of the upper charge blocking film 251cu, the lower surface of the upper charge storage film 251bu is closest to the first semiconductor layer 201a.

[0035] According to some example embodiments, the upper charge storage film 251bu may include an upper cap 251buc that protrudes horizontally toward the second semiconductor layer 201b at the same level (eg, vertical level) or a similar level as the second semiconductor layer 201b. The upper cap 251buc may be formed by Figure 1B The dashed lines shown are distinguished. According to some example embodiments, the upper cover 251buc may be a portion of the upper charge storage film 251bu arranged below the upper charge blocking film 251cu. According to some example embodiments, the upper cover 251buc may be in contact with the side surface of the second semiconductor layer 201b. According to some example embodiments, the upper cover 251buc may be between the upper surface and the lower surface of the second semiconductor layer 201b (e.g., at a vertical level between the upper surface and the lower surface of the second semiconductor layer 201b). According to some example embodiments, the upper cover 251buc may cover the lower surface of the upper charge blocking film 251cu. According to some example embodiments, the upper cover 251buc may be in contact with the lower surface of the upper charge blocking film 251cu. According to some example embodiments, the level of the lower surface of the upper charge blocking film 251cu may be between the level of the upper surface of the second semiconductor layer 201b and the level of the lower surface of the second semiconductor layer 201b.

[0036] According to some example embodiments, in a top view, the upper cap 251buc may protrude outward from the center of each of the channel structures 250 to have substantially circular symmetry. According to some example embodiments, the upper charge storage film 251bu may have a maximum or highest horizontal thickness (e.g., width) at a level (e.g., a vertical level) at which the upper cap 251buc is formed. According to some example embodiments, a portion of each of the upper tunnel insulating film 251au, the upper charge storage film 251bu, and the upper charge blocking film 251cu that is farther from the first semiconductor layer 201a than the upper cap 251buc may have a constant or substantially constant thickness along the first direction (Z direction) (e.g., relative to each other).

[0037] As described in detail later with respect to the method for manufacturing the semiconductor memory device 10, the process profile of the upper charge blocking film 251cu can be controlled by the formation of the upper cap 251buc. Therefore, the formation of a parasitic transistor that may cut off the current path through the channel layer 253 can be prevented or reduced, and thus the reliability of the semiconductor memory device 10 can be improved.

[0038] According to some example embodiments, the lower charge storage film 251bd may be between the lower tunnel insulating film 251ad and the lower charge blocking film 251cd. According to some example embodiments, the lower charge storage film 251bd may be in contact with the lower tunnel insulating film 251ad and the lower charge blocking film 251cd. According to some example embodiments, the lower charge storage film 251bd may be in contact with the first semiconductor layer 201a and the third semiconductor layer 201c. According to some example embodiments, the upper surface of the lower charge storage film 251bd may be in contact with the third semiconductor layer 201c (e.g., the lower surface of the third semiconductor layer 201c).

[0039] According to some example embodiments, the lower charge storage film 251bd may include a lower cap 251bdc that protrudes horizontally toward the first semiconductor layer 201a at the same level (eg, vertical level) or a similar level as the first semiconductor layer 201a. The lower cap 251bdc may be formed by Figure 1BThe dashed lines shown are distinguished. According to some example embodiments, the lower cover 251bdc may be a portion of the lower charge storage film 251bd arranged on the lower charge blocking film 251cd. According to some example embodiments, the lower cover 251bdc may be in contact with the side surface of the first semiconductor layer 201a. According to some example embodiments, the lower cover 251bdc may be located below the upper surface of the first semiconductor layer 201a (e.g., located at a vertical level below the upper surface of the first semiconductor layer 201a). According to some example embodiments, the lower cover 251bdc may cover the upper surface of the lower charge blocking film 251cd. According to some example embodiments, the lower cover 251bdc may be in contact with the upper surface of the lower charge blocking film 251cd.

[0040] According to some example embodiments, in a top view, the lower cap 251bdc may protrude outward from the center of each of the channel structures 250 to have substantially circular symmetry. In addition, the lower charge storage film 251bd may have a maximum or highest horizontal thickness (e.g., width) at a level (e.g., a vertical level) at which the lower cap 251bdc is formed. According to some example embodiments, a portion of each of the lower tunnel insulating film 251ad, the lower charge storage film 251bd, and the lower charge blocking film 251cd that is farther from the second semiconductor layer 201b than the lower cap 251bdc may have a constant or substantially constant thickness along the first direction (Z direction) (e.g., relative to each other).

[0041] According to some example embodiments, the upper charge blocking film 251cu and the lower charge blocking film 251cd may include a single layer or a multilayer film of silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide and / or the like. However, they are not limited thereto, and the upper charge blocking film 251cu and the lower charge blocking film 251cd may include a dielectric material having a high dielectric constant. According to some example embodiments, the upper charge blocking film 251cu and the lower charge blocking film 251cd may include a material having a high etching selectivity relative to the upper charge storage film 251bu and the lower charge storage film 251bd. For example, when the upper charge storage film 251bu and the lower charge storage film 251bd include silicon nitride, the upper charge blocking film 251cu and the lower charge blocking film 251cd may include silicon oxide. According to some example embodiments, the upper charge blocking film 251cu and the lower charge blocking film 251cd may be formed by forming the charge blocking film 251c (see Figure 7B ) are separated and formed.

[0042] According to some example embodiments, the upper charge blocking film 251cu and the lower charge blocking film 251cd may define an outer boundary of the channel structure 250. According to some example embodiments, the upper charge blocking film 251cu may contact the insulating film 230 and the gate electrode 240. In some cases, the insulating film 230 and the upper charge blocking film 251cu may include the same or substantially the same material, and thus the insulating film 230 and the upper charge blocking film 251cu may be integrated to form a continuous structure. However, they are not limited thereto, and the insulating film 230 and the upper charge blocking film 251cu may include different materials, and thus the insulating film 230 and the upper charge blocking film 251cu may be independent of each other.

[0043] According to some example embodiments, the inner side surface of the upper charge blocking film 251cu may be in contact with the upper charge storage film 251bu. According to some example embodiments, the outer side surface of the upper charge blocking film 251cu may be in contact with the second semiconductor layer 201b. Here, the inner side surface of the upper charge blocking film 251cu may mean the side surface closest to the channel layer 253, and the outer side surface of the upper charge blocking film 251cu may mean the side surface closest to the gate electrode 240. According to some example embodiments, the upper charge blocking film 251cu may be in contact with the side wall of the second semiconductor layer 201b. According to some example embodiments, the upper charge blocking film 251cu may be in contact with only the second semiconductor layer 201b (e.g., among the first to third semiconductor layers 201a, 201b, and 201c). According to some example embodiments, the upper charge blocking film 251cu may not be in contact with the third semiconductor layer 201c. According to some example embodiments, the upper charge blocking film 251cu may be spaced apart from the third semiconductor layer 201c with the upper charge storage film 251bu (more specifically, the upper cap 251buc) therebetween.

[0044] According to some example embodiments, the lower charge blocking film 251cd may be in contact with the first semiconductor layer 201a. According to some example embodiments, the lower charge blocking film 251cd may be in contact with the sidewall of the first semiconductor layer 201a. According to some example embodiments, the lower charge blocking film 251cd may be in contact with only the first semiconductor layer 201a (e.g., among the first to third semiconductor layers 201a, 201b, and 201c). According to some example embodiments, the lower charge blocking film 251cd may not contact the third semiconductor layer 201c. According to some example embodiments, the lower charge blocking film 251cd may be spaced apart from the third semiconductor layer 201c with the lower charge storage film 251bd (more specifically, the lower cover 251bdc) therebetween.

[0045] According to some example embodiments, the lower surface profile of each of the upper tunnel insulating film 251au, the upper charge storage film 251bu, and the upper charge blocking film 251cu may include a circular shape. However, it is not limited thereto, and a portion of the lower surface profile of the upper tunnel insulating film 251au, the upper charge storage film 251bu, and the upper charge blocking film 251cu may include a linear shape or a polygonal shape. According to some example embodiments, the upper surface profile of each of the lower tunnel insulating film 251ad, the lower charge storage film 251bd, and the lower charge blocking film 251cd may include a circular shape. However, it is not limited thereto, and a portion of the upper surface profile of the lower tunnel insulating film 251ad, the lower charge storage film 251bd, and the lower charge blocking film 251cd may include a linear shape or a polygonal shape.

[0046] According to some example embodiments, the third semiconductor layer 201c may be in contact with the channel layer 253. According to some example embodiments, a portion of the third semiconductor layer 201c in contact with the upper tunnel insulating film 251au, the upper charge storage film 251bu, the lower tunnel insulating film 251ad, and the lower charge storage film 251bd may include a circular profile, but is not limited thereto. As described later, the third semiconductor layer 201c may be formed by removing a portion of the gate insulating film 251 and the sacrificial semiconductor layer 202 (see Figure 5 ) and growing a semiconductor material (e.g., polysilicon) at the portion of the gate insulating film 251 and the region where the sacrificial semiconductor layer 202 is removed. Therefore, the lower surface profile of the upper tunnel insulating film 251au and the upper charge storage film 251bu and the upper surface profile of the lower tunnel insulating film 251ad and the lower charge storage film 251bd can be transferred to the third semiconductor layer 201c. Therefore, the third semiconductor layer 201c can include any complementary profile corresponding to the lower surface profile of the upper tunnel insulating film 251au and the upper charge storage film 251bu and the upper surface profile of the lower tunnel insulating film 251ad and the lower charge storage film 251bd.

[0047] According to some example embodiments, since the third semiconductor layer 201c may contact the upper tunnel insulating film 251au and the lower tunnel insulating film 251ad and the upper charge storage film 251bu and the lower charge storage film 251bd, but the third semiconductor layer 201c may not contact the upper charge blocking film 251cu and the lower charge blocking film 251cd, the third semiconductor layer 201c may include two discontinuous positions on the lower surface profile and the upper surface profile. According to some example embodiments, the profile of the third semiconductor layer 201c may be discontinuously changed at the following positions: i) a boundary between the upper tunnel insulating film 251au and the upper charge storage film 251bu, ii) a boundary between the upper charge storage film 251bu and the second semiconductor layer 201b, iii) a boundary between the lower tunnel insulating film 251ad and the lower charge storage film 251bd, and iv) a boundary between the lower charge storage film 251bd and the first semiconductor layer 201a.

[0048] According to some example embodiments, the channel layer 253 may fill a portion of the inner space defined by the gate insulating film 251. The channel layer 253 formed on the inner wall of the gate insulating film 251 may have a constant or substantially constant thickness. According to some example embodiments, the buried insulating film 255 may fill in the space defined by the channel layer 253. The upper surface of the buried insulating film 255 may be covered by the upper portion of the channel layer 253. According to some example embodiments, the upper portion of the channel layer 253 may have a greater thickness than the sidewall of the channel layer 253 to form a contact with the first bit line contact path 271. According to some example embodiments, the upper surface of the channel layer 253 may be used as a contact pad for the first bit line contact path 271.

[0049] According to some example embodiments, the word line cut portion (WLC) may penetrate the first upper insulating film 261 and the second upper insulating film 263, the gate electrode 240 and / or the insulating film 230 in the first direction (Z direction). The word line cut portion (WLC) may extend in the second direction (X direction). The length of the word line cut portion (WLC) in the second direction (X direction) may be greater than the length of the gate electrode 240 in the second direction (X direction). According to some example embodiments, the word line cut portion (WLC) may extend in the second direction (X direction) so that the gate electrode 240 is separated in the horizontal direction (e.g., the third direction (Y direction)). Therefore, the gate electrodes 240 spaced apart horizontally from each other may serve as gates of different transistors.

[0050] According to some example embodiments, the word line cut portion (WLC) may penetrate the second semiconductor layer 201b and the third semiconductor layer 201c. According to some example embodiments, the word line cut portion (WLC) may extend to an upper portion of the first semiconductor layer 201a. According to some example embodiments, some of the word line cut portions (WLC) may extend in the first direction (Z direction) to penetrate the opening 201op formed in the third semiconductor layer 201c. Therefore, some of the word line cut portions (WLC) may be covered by the support connection structure 201bl and thus may be spaced apart from the third semiconductor layer 201c. Here, some of the word line cut portions (WLC) may be spaced apart from the third semiconductor layer 201c may mean that some of the word line cut portions (WLC) may penetrate the support connection structure 201bl without contacting the third semiconductor layer 201c. Alternatively, the fact that some of the word line cuts (WLCs) may be spaced apart from the third semiconductor layer 201c may mean that the third upper insulating film 265 filling some of the word line cuts (WLCs) may not contact the third semiconductor layer 201c with the second semiconductor layer 201b therebetween.

[0051] The string selection line cut portion (SLC) may extend in a first direction (Z direction). According to some example embodiments, the string selection line cut portion (SLC) may penetrate the topmost and second topmost gate electrodes 240 (SE) in the first direction (Z direction). The length of the string selection line cut portion (SLC) in the second direction (X direction) may be greater than the length of the topmost and second topmost gate electrodes 240 (SE) in the second direction (X direction). Therefore, the string selection line cut portion (SLC) may separate the topmost and second topmost gate electrodes 240 (SE) horizontally. According to some example embodiments, the first upper insulating film 261 may fill the space defined by the string selection line cut portion (SLC). The first upper insulating film 261 may insulate the topmost and second topmost gate electrodes 240 (SE) spaced apart from each other in the third direction (Y direction) at the same level (e.g., vertical level) or similar levels. Therefore, the topmost and second topmost gate electrodes 240 (SE) spaced apart from each other horizontally may serve as gates of different transistors.

[0052] The third upper insulating film 265 may be disposed on the second upper insulating film 263. The third upper insulating film 265 may include an insulating material. According to some example embodiments, the inside of the word line cutting portion (WLC) may be filled with the third upper insulating film 265. Therefore, different gate electrodes 240 arranged at the same vertical level or similar vertical levels may be insulated from each other by the third upper insulating film 265. According to some example embodiments, the first bit line contact path 271 and the second bit line contact path 273 may be covered by the third upper insulating film 265.

[0053] According to some example embodiments, the first bit line contact path 271 and the second bit line contact path 273 may extend in the first direction (Z direction). According to some example embodiments, the first bit line contact path 271 may further penetrate the second upper insulating film 263. According to some example embodiments, the first bit line contact path 271 may contact the channel layer 253.

[0054] According to some example embodiments, the upper conductive pattern 281 may be disposed between the first bit line contact path 271 and the second bit line contact path 273. According to some example embodiments, the upper conductive pattern 281 may extend in a horizontal direction (e.g., the second direction (X direction) and / or the third direction (Y direction)). According to some example embodiments, the upper conductive pattern 281 may contact the first bit line contact path 271 and the second bit line contact path 273. According to some example embodiments, the bit line BL may contact the second bit line contact path 273.

[0055] According to some example embodiments, the channel structure 250 may be connected to the bit line BL via the first bit line contact via 271 , the upper conductive pattern 281 , and / or the second bit line contact via 273 .

[0056] Figure 2 and Figure 3 is a flowchart for explaining a method of manufacturing a semiconductor memory device according to some example embodiments.

[0057] Figures 4 to 13 is a cross-sectional view for illustrating a method of manufacturing a semiconductor memory device according to some example embodiments. Figures 4 to 13 In the discussion of, the term "providing" may mean providing, obtaining, and / or forming.

[0058] Reference Figure 2 and Figure 4 , a first semiconductor layer 201 a , a sacrificial semiconductor layer 202 , and a second semiconductor layer 201 b may be formed at P110 .

[0059] After providing the conductive plate 200, the first semiconductor layer 201a may be provided. The conductive plate 200 and / or the first semiconductor layer 201a may be formed by a chemical vapor deposition process, an atomic layer deposition process, a physical vapor deposition process, and / or the like.

[0060] The sacrificial semiconductor layer 202 may be provided on the first semiconductor layer 201a, and then a portion of the sacrificial semiconductor layer 202 may be patterned to form an opening 201op for partially exposing the upper surface of the first semiconductor layer 201a. According to some example embodiments, the opening 201op may extend in the second direction (X direction), but is not limited thereto. Then, the second semiconductor layer 201b may be provided conformally throughout the first semiconductor layer 201a and the sacrificial semiconductor layer 202. The second semiconductor layer 201b may include a supporting connection structure 201bl in contact with the first semiconductor layer 201a at the opening 201op. According to some example embodiments, the first semiconductor layer 201a and the second semiconductor layer 201b may include doped polysilicon.

[0061] According to some example embodiments, the sacrificial semiconductor layer 202 may include an insulating material. According to some example embodiments, the sacrificial semiconductor layer 202 may include any one of silicon oxide, silicon nitride, and silicon oxynitride. According to some example embodiments, the sacrificial semiconductor layer 202 may be opposite to the insulating film 230 described below (see Figure 5 ) has high etching selectivity.

[0062] Reference Figure 2 and Figure 5 , an insulating film 230 and a sacrificial film 220 may be provided at P120.

[0063] According to some example embodiments, the sacrificial film 220 and the insulating film 230 may be alternately stacked on the second semiconductor layer 201b. According to some example embodiments, the insulating film 230 and the sacrificial film 220 may include different materials. According to some example embodiments, the insulating film 230 and the sacrificial film 220 may each have a high etching selectivity relative to each other. For example, when the sacrificial film 220 includes silicon oxide, the insulating film 230 may include silicon nitride. As another example, when the sacrificial film 220 includes silicon nitride, the insulating film 230 may include silicon oxide. As another example, when the sacrificial film 220 includes undoped polysilicon, the insulating film 230 may include silicon nitride or silicon oxide.

[0064] Reference Figure 2 and Figure 6 , a first upper insulating film 261 may be provided at P130.

[0065] Providing the first upper insulating film 261 may include forming a string selection line cut portion (SLC), providing an insulating material, and then planarizing the insulating material. According to some example embodiments, the string selection line cut portion (SLC) may be formed by a dry etching process so that the two sacrificial films 220 farthest from the second semiconductor layer 201b are horizontally separated from each other. Subsequently, after the insulating material is sufficiently provided to fill the string selection line cut portion (SLC), the provided insulating material may be planarized to form the first upper insulating film 261.

[0066] Reference Figure 2 , Fig. 7A and Figure 7B , a channel structure 250 may be formed at P140. Here, Figure 7B yes Fig. 7A In order to form the channel structure 250, after providing a photoresist material layer on the alternately stacked insulating film 230 and the sacrificial film 220, an exposure and development process and an etching process may be sequentially performed to form a channel hole penetrating the first upper insulating film 261, the stacked structure of the sacrificial film 220 and the insulating film 230, the second semiconductor layer 201b, the sacrificial semiconductor layer 202 and / or the upper portion of the first semiconductor layer 201a.

[0067] Then, a gate insulating material film, a channel material film and / or a buried insulating material film, each of which fills at least a portion of the channel hole, may be provided sequentially and conformally. According to some example embodiments, the gate insulating material film may include a charge blocking material film, a charge storage material film and a tunnel insulating material film provided sequentially. Then, by performing an etch-back process, the upper surface of the first upper insulating film 261 may be exposed. Next, after further removing the upper portion of the buried insulating material film in the channel hole, a material that is the same as or similar to the channel material film may be deposited to cover the upper portion of the buried insulating film 255. Thus, a first line contact path 271 (see Figure 1A ) of the contact can be formed.

[0068] Thus, a channel structure 250 including a gate insulating film 251, a channel layer 253, and a buried insulating film 255 may be formed. The gate insulating film 251 may include a tunnel insulating film 251a, a charge storage film 251b, and a charge blocking film 251c.

[0069] Reference Figure 2 and Figure 8 , a word line cutting portion (WLC) may be formed at P150. According to some example embodiments, a second upper insulating film 263 covering an upper surface of the channel structure 250 and an upper surface of the first upper insulating film 261, and a hard mask pattern may be formed at Fig. 7Aare sequentially provided on the product, and then the second upper insulating film 263 and the first upper insulating film 261, the sacrificial film 220 and the insulating film 230, the second semiconductor layer 201b, the sacrificial semiconductor layer 202 and / or the first semiconductor layer 201a can be etched by using the hard mask pattern as an etching mask.

[0070] After forming the word line cut portion (WLC), the hard mask pattern may be removed. According to some example embodiments, the word line cut portion (WLC) may include a tapered shape in the first direction (Z direction). According to some example embodiments, the length of the word line cut portion (WLC) in the second direction (X direction) may be longer than the length of each of the sacrificial films 220 in the second direction (X direction). Therefore, the word line cut portion (WLC) may separate the sacrificial films 220 horizontally from each other.

[0071] According to some example embodiments, some of the word line cut portions (WLC) may overlap vertically with the opening 201op. According to some example embodiments, some of the word line cut portions (WLC) may extend through the opening 201op in the first direction (Z direction). Therefore, according to some example embodiments, some of the word line cut portions (WLC) may penetrate the support connection structure 201b1 and may not contact the sacrificial semiconductor layer 202.

[0072] Reference Figure 2 , Figure 8 , Fig. 9A and Fig. 9B , the sacrificial semiconductor layer 202 can be removed at P160. Here, Fig. 9B yes Fig. 9A A partial enlarged cross-sectional view of area E3.

[0073] According to some example embodiments, after a word line cutting pad material layer is provided on a structure in which a word line cutting portion (WLC) is formed, a portion of the word line cutting pad material layer may be removed to expose at least a portion of the sacrificial semiconductor layer 202 located at a lower portion of the word line cutting portion (WLC), thereby forming a word line cutting pad (WLCL). The word line cutting pad (WLCL) may include a material having a high etching selectivity with respect to the sacrificial semiconductor layer 202. The word line cutting pad (WLCL) may expose the sacrificial semiconductor layer 202 while covering the sacrificial film 220. The word line cutting pad (WLCL) may serve as a layer for protecting the sacrificial film 220 in a process of removing the sacrificial semiconductor layer 202.

[0074] Since the first semiconductor layer 201a can be connected to the second semiconductor layer 201b via the supporting connection structure 201b1, even when the sacrificial semiconductor layer 202 can be removed, the insulating film 230 and the sacrificial film 220 can be prevented from collapsing, or the occurrence of the collapse can be reduced.

[0075] The space formed by removing the sacrificial semiconductor layer 202 may be referred to as a side opening (LO). After removing the sacrificial semiconductor layer 202, the word line cutting pad (WLCL) may be removed.

[0076] Reference Figure 2 , Figure 3 and FIG. 10A to FIG. 11B , a third semiconductor layer may be formed at P170. Here, FIG. 10A to FIG. 10D is with Fig. 9A A local cross-sectional view corresponding to area E3 in FIG.

[0077] The formation of the third semiconductor layer at P170 may include the following operations: at P171, etching the charge blocking film 251c (see Fig. 9B ); at P173, deposit (e.g., form) a cover material film 251bc; at P175, etch the cover material film 251bc and the charge storage film 251b; at P177, etch the tunnel insulating film 251a; and then at P179, provide a third semiconductor layer 201c.

[0078] More specifically, refer to Figure 3 and Fig. 10A , the charge blocking film 251c can be etched at P171 (see Fig. 9B ).

[0079] According to some example embodiments, the charge blocking film 251c (see Fig. 9B ) may be wet etched. According to some example embodiments, the charge blocking film 251c (see Fig. 9B ) may be partially etched by an etchant having a low etching rate relative to the charge storage film 251b and relative to the charge blocking film 251c (see Fig. 9B ) has a high etching rate. Therefore, the charge blocking film 251c (see Fig. 9B ) may be separated to form an upper charge blocking film 251cu and a lower charge blocking film 251cd. The side opening LO (see Fig. 9A ) can be achieved by etching the charge blocking film 251c (see Fig. 9B) is enlarged to form the first side opening LOa. The upper charge blocking film 251cu and the lower charge blocking film 251cd may be formed by a wet etching process and thus may have a circular profile on each of the lower surface of the upper charge blocking film 251cu and the upper surface of the lower charge blocking film 251cd, but is not limited thereto.

[0080] Reference Figure 3 and Fig. 10B , a cover material film 251bc may be provided at P173. According to some example embodiments, the cover material film 251bc may include, but is not limited to, the same material as or a similar material to the charge storage film 251b. According to some example embodiments, when the cover material film 251bc and the charge storage film 251b include the same material or a similar material, the cover material film 251bc may be integrated with the charge storage film 251b so that the charge storage film 251b and the cover material film 251bc constitute a continuous structure. According to some example embodiments, the cover material film 251bc may cover the upper charge blocking film 251cu and the lower charge blocking film 251cd. According to some example embodiments, the cover material film 251bc may be provided by various methods such as a chemical vapor deposition method, an atomic layer deposition method, and the like. According to some example embodiments, by providing the cover material film 251bc, Fig. 10A The first side opening LOa in can be reduced to form a second side opening LOb.

[0081] Reference Figure 3 , Fig. 10B and Fig. 10C , portions of the cap material film 251bc and the charge storage film 251b may be etched at P175.

[0082] According to some example embodiments, the cover material film 251bc and the charge storage film 251b may be etched by a wet etching process. According to some example embodiments, the cover material film 251bc and the charge storage film 251b may be partially removed by using an etchant having a low etching rate relative to the tunnel insulating film 251a and a high etching rate relative to the cover material film 251bc and the charge storage film 251b. Thus, an upper charge storage film 251bu including an upper cover 251buc and a lower charge storage film 251bd including a lower cover 251bdc may be formed. According to some example embodiments, by etching the charge storage film 251b, the second side opening LOb may be expanded to form a third side opening LOc.

[0083] Reference Figure 3 , Fig. 10C and Fig. 10D , the tunnel insulating film 251a can be etched at P177.

[0084] According to some example embodiments, the tunnel insulating film 251a may be wet etched. According to some example embodiments, the tunnel insulating film 251a may be partially removed by using an etchant having a low etching rate relative to the upper charge storage film 251bu and the lower charge storage film 251bd and having a high etching rate relative to the tunnel insulating film 251a. Therefore, the tunnel insulating film 251a may be separated to form an upper tunnel insulating film 251au and a lower tunnel insulating film 251ad. According to some example embodiments, by etching the tunnel insulating film 251a, the third side opening LOc may be expanded to form a fourth side opening LOd.

[0085] In the conventional technology, the charge blocking film is doubly etched in the etching process of the charge blocking film and the etching process of the tunnel insulating film, resulting in excessive process distribution. In particular, according to the process distribution in the process of etching the upper charge blocking film and the lower charge blocking film, the upper charge storage film and the lower charge storage film, and the upper tunnel insulating film and the lower tunnel insulating film, a parasitic transistor may be generated and may act as a switching device that blocks the current path between the third semiconductor layer and the channel layer, resulting in a semiconductor device with reduced reliability.

[0086] According to some example embodiments, since the upper cap 251buc and the lower cap 251bdc covering the upper charge blocking film 251cu and the lower charge blocking film 251cd may be formed before etching the tunnel insulating film 251a, the upper charge blocking film 251cu and the lower charge blocking film 251cd may be prevented from being double-etched, or the degree or situation of the upper charge blocking film 251cu and the lower charge blocking film 251cd being double-etched may be reduced. Therefore, according to some example embodiments, the process distribution in the etching process of the plurality of layers constituting the gate insulating film 251 may be controlled, and thus the semiconductor memory device 10 (see Figure 1A ) reliability.

[0087] Reference Figure 3 , Fig.11A and Fig. 11B , a third semiconductor layer 201c may be provided at P179. Here, Fig. 11B is with Fig.11A A local cross-sectional view corresponding to area E4 in FIG.

[0088] The third semiconductor layer 201c may be formed by selectively removing the sacrificial semiconductor layer 202 (see Fig. 7A) is provided in a space formed by the first semiconductor layer 201a and the second semiconductor layer 201b. According to some example embodiments, the third semiconductor layer 201c may include polycrystalline silicon doped with the same or substantially the same concentration as the first semiconductor layer 201a and the second semiconductor layer 201b. According to some example embodiments, the third semiconductor layer 201c may include polycrystalline silicon doped with a concentration different from that of the first semiconductor layer 201a and the second semiconductor layer 201b, or include undoped polycrystalline silicon. According to some example embodiments, the third semiconductor layer 201c may include the same or substantially the same concentration as the first semiconductor layer 201a and the second semiconductor layer 201b by diffusion of dopants contained in the first semiconductor layer 201a and the second semiconductor layer 201b via a subsequent heat treatment process, but is not limited thereto. The newly formed third semiconductor layer 201c and the channel layer 253 may contact each other. Therefore, a charge transfer path may be formed to allow the channel structure 250 to operate as a memory cell.

[0089] According to some example embodiments, since the third semiconductor layer 201c may be filled by removing the sacrificial semiconductor layer 202 (see Fig. 7A ), so the opening 201op partially exposing the upper surface of the first semiconductor layer 201a can also be maintained.

[0090] Reference Figure 2 , Fig. 12A and Fig. 12B , a gate electrode material layer (EML) may be provided at P180. Here, the sacrificial film 220 may be removed before providing the gate electrode material layer EML. Here, Fig. 12B is with Fig. 12A A local cross-sectional view corresponding to area E5 in FIG.

[0091] The gate electrode material layer EML may include a first barrier layer 241 (see Figure 1B ) corresponding to the first barrier material layer 241L and the second barrier layer 242 (see Figure 1B ) and the second barrier material layer 242L corresponding to the gate conductive layer 243 (see Figure 1B ) The first barrier material layer 241L may include aluminum oxide, the second barrier material layer 242L may include titanium nitride, and the gate conductive material layer 243L may include tungsten, but are not limited thereto.

[0092] Reference Figure 2 , Fig. 12A and Fig.13 , a third upper insulating film 265 may be provided after performing a node isolation process at P190.

[0093] The node isolation process may be a process of removing a portion of the exposed gate electrode material layer EML by a wet etching process. Thus, the gate electrode material layer EML formed on different layers may be separated to form a plurality of gate electrodes 240. Then, a third upper insulating film 265 filling the word line cutting portion WLC and covering the upper surface of the second upper insulating film 263 may be provided. The gate electrodes 240 horizontally separated from each other at the same vertical level or similar vertical levels may be insulated from each other by the third upper insulating film 265.

[0094] Then, refer to Figure 1A By further performing some wiring processes, the upper conductive pattern 281, the first and second bit line contact vias 271 and 273, and the bit line BL may be further formed. Thus, the semiconductor memory device 10 may be provided.

[0095] For ease of description, spatial relation terms such as "below", "under", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or feature to another element(s) or feature(s) as shown in the figures. For example, as used herein, the terms "upper", "higher", "on", and / or "top" may refer to a relative position (such as above) to another element or feature. Figure 1A In the embodiment of the present invention, the term "bottom" and / or "under" may refer to an element or feature that is farther in the Z direction (as depicted in the figure) relative to another element or feature in the direction opposite to the Z direction. It will be understood that, in addition to the orientation depicted in the figure, the spatial relationship terms are intended to also cover different orientations of the device in use or operation. For example, if the device in the figure is turned over, the element described as "under" or "below" another element or feature will be oriented "above" the other element or feature. Therefore, the term "under" can cover both the upper and lower directions. The device can be oriented separately (rotated 90 degrees or in another direction), and the spatial relationship descriptors used here are interpreted accordingly. Similarly, the term "covering" can describe the relationship between a first element or feature on or below a second element or feature.

[0096] It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intervening elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Also, as used herein, the term "fill" may describe partially or completely filling, and the term "cover" may describe partially or completely covering.

[0097] Some example embodiments are described herein with reference to cross-sectional illustrations, which are schematic representations of idealized examples. As such, variations from the shapes illustrated as a result of, for example, manufacturing techniques and / or tolerances, are to be expected. Thus, some example embodiments should not be construed as limited to the particular shapes of regions shown herein, but are to include deviations in shapes that result, for example, from manufacturing.

[0098] While certain example embodiments have been particularly shown and described, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.

[0099] This application claims the benefit of Korean Patent Application No. 10-2019-0050984 filed on April 30, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor memory device, comprising: A first semiconductor layer, a second semiconductor layer, and a third semiconductor layer between the first semiconductor layer and the second semiconductor layer; a plurality of gate electrodes on the second semiconductor layer and spaced apart from each other in a first direction perpendicular to an upper surface of the second semiconductor layer; as well as a plurality of channel structures, surrounded by the first semiconductor layer, the second semiconductor layer, the third semiconductor layer and the plurality of gate electrodes, each corresponding channel structure in the plurality of channel structures comprising a gate insulating film, a channel layer and a buried insulating film, the gate insulating film comprising a tunnel insulating film adjacent to the channel layer, a charge blocking film adjacent to the plurality of gate electrodes, and a charge storage film between the tunnel insulating film and the charge blocking film, the charge storage film comprising an upper cover protruding toward the outside of a corresponding channel structure in the plurality of channel structures, The charge storage film is closer to the center of the third semiconductor layer than the tunnel insulating film.

2. The semiconductor memory device according to claim 1, The lower portion of the charge blocking film is spaced apart from the third semiconductor layer and the upper portion covers therebetween.

3. The semiconductor memory device according to claim 1, The lower surface of the charge blocking film is covered by the upper cover.

4. The semiconductor memory device according to claim 1, The level of the lower surface of the charge blocking film is between the level of the upper surface of the second semiconductor layer and the level of the lower surface of the second semiconductor layer.

5. The semiconductor memory device according to claim 1, The upper cover is in contact with a side surface of the second semiconductor layer.

6. The semiconductor memory device according to claim 1, further comprising: A conductive plate is below the first semiconductor layer and in contact with the first semiconductor layer.

7. The semiconductor memory device according to claim 6, The conductive plate includes one of tungsten and a tungsten compound.

8. A semiconductor memory device comprising: a first semiconductor layer and a second semiconductor layer on the first semiconductor layer; a plurality of gate electrodes on the second semiconductor layer and spaced apart from each other in a first direction perpendicular to an upper surface of the second semiconductor layer; as well as A plurality of channel structures penetrate the first semiconductor layer and the second semiconductor layer and the plurality of gate electrodes in the first direction, each of the plurality of channel structures comprises a gate insulating film, a channel layer and a buried insulating film, the channel layer is connected to the first semiconductor layer, the gate insulating film comprises an upper charge storage film, wherein the channel layer extends along the first direction and the upper charge storage film contacts a side surface of the second semiconductor layer.

9. The semiconductor memory device according to claim 8, The first semiconductor layer and the second semiconductor layer are in contact with each other.

10. The semiconductor memory device according to claim 8, further comprising: An upper charge blocking film is between the upper charge storage film and the second semiconductor layer.

11. The semiconductor memory device according to claim 10, The upper charge storage film includes an upper cap covering a lower surface of the upper charge blocking film.

12. The semiconductor memory device according to claim 10, wherein a width of the upper charge storage film at a first level is greater than a width of the upper charge storage film at a second level higher than the first level, the first level being below a level of the upper charge blocking film.

13. The semiconductor memory device according to claim 10, wherein the width of the upper charge storage film is highest at the same level as that of the second semiconductor layer.

14. The semiconductor memory device according to claim 8, The gate insulating film includes a lower charge storage film, and the lower charge storage film contacts a lower surface of the first semiconductor layer.

15. The semiconductor memory device according to claim 14, wherein the gate insulating film includes a lower charge blocking film spaced apart from the first semiconductor layer with the lower charge storage film therebetween.

16. A semiconductor memory device comprising: a first semiconductor layer, a second semiconductor layer on the first semiconductor layer, and a third semiconductor layer between the first semiconductor layer and the second semiconductor layer; a plurality of gate electrodes spaced apart from each other in a first direction perpendicular to an upper surface of the second semiconductor layer, the plurality of gate electrodes forming a word line cut portion in the first direction, the word line cut portion separating the plurality of gate electrodes in a second direction perpendicular to the first direction; as well as A plurality of channel structures penetrate the second semiconductor layer and the third semiconductor layer and the plurality of gate electrodes in the first direction, each corresponding channel structure in the plurality of channel structures comprises a gate insulating film, a channel layer and a buried insulating film, the third semiconductor layer comprises an opening partially exposing the upper surface of the first semiconductor layer, the second semiconductor layer comprises a supporting connection structure contacting the first semiconductor layer at the opening, the gate insulating film comprises an upper tunnel insulating film, an upper charge blocking film, and an upper charge storage film between the upper tunnel insulating film and the upper charge blocking film, the upper charge storage film comprises an upper cover protruding toward the outside of the corresponding channel structure in the plurality of channel structures.

17. The semiconductor memory device according to claim 16, further comprising: An upper insulating film filling the word line cut portion, the upper insulating film not contacting the third semiconductor layer.

18. The semiconductor memory device according to claim 16, Among the lower surface of the upper charge storage film, the lower surface of the upper tunnel insulating film, and the lower surface of the upper charge blocking film, the lower surface of the upper charge storage film is closest to the first semiconductor layer.

19. The semiconductor memory device according to claim 16, The third semiconductor layer has a discontinuous profile at a boundary between the upper charge storage film and the second semiconductor layer.

20. The semiconductor memory device according to claim 19, wherein the third semiconductor layer has a discontinuous profile at a boundary between the upper tunnel insulating film and the upper charge storage film.

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