Power semiconductor module device

Abstract

A power semiconductor module device includes: first and second switch elements (S1, S2), each having a control terminal (10, 14) and a controllable load path between two load terminals, the load paths of the first and second switch elements (S1, S2) are operably coupled in series and between a first power supply node configured to be operably coupled to a first potential (DC+) and a second power supply node configured to be operably coupled to a second potential (DC‑), wherein the first switch element (S1) and the second switch element (S2) are connected to each other via a first common node. The power semiconductor module device (300) also includes an output node configured to be coupled to an output potential (AC). The output node is coupled to the first common node. The first power supply node is formed by a plurality of first terminals (1, 2, 9), the second power supply node is formed by a plurality of second terminals (6, 7, 8), and the output node is formed by a plurality of third terminals (3, 4, 5).

Description

Technical Field

[0001] The present disclosure relates to a power semiconductor module arrangement. Background Art

[0002] The power semiconductor module device often includes at least one semiconductor substrate arranged in a housing. A semiconductor device including a plurality of controllable semiconductor elements (e.g., two IGBTs in a half-bridge configuration) is arranged on each of the at least one substrate. Each substrate typically includes a substrate layer (e.g., a ceramic layer), a first metallization layer deposited on a first side of the substrate layer, and a second metallization layer deposited on a second side of the substrate layer. For example, the controllable semiconductor element is mounted on the first metallization layer. The second metallization layer can be optionally attached to a substrate. The controllable semiconductor device is typically mounted to the semiconductor substrate by welding or sintering techniques.

[0003] The wires or electrical connections are used to interconnect different semiconductor devices of the power semiconductor device. In addition, terminal elements are provided to contact the semiconductor device from outside the housing. Such terminal elements are usually electrically coupled to the first metallization layer with a first end. The second end of the terminal element protrudes outside the housing. The layout of the power semiconductor module device, in particular the positioning of the second end or the terminal element, may have an influence on the switching characteristics of the semiconductor device.

[0004] There is a need for a power semiconductor module arrangement with improved switching characteristics, in which requirements regarding creepage distances are met. Summary of the invention

[0005] A power semiconductor module device includes a first switch element and a second switch element, each of which has a control terminal and a controllable load path between two load terminals, the load paths of the first switch element and the second switch element are operably coupled in series and between a first power supply node configured to be operably coupled to a first potential and a second power supply node configured to be operably coupled to a second potential, wherein the first switch element and the second switch element are connected to each other via a first common node. The power semiconductor module device also includes an output node configured to be coupled to an output potential. The output node is coupled to the first common node. The first power supply node is formed by a plurality of first terminals, the second power supply node is formed by a plurality of second terminals, and the output node is formed by a plurality of third terminals. The first auxiliary emitter terminal of the first switch element is electrically coupled to the control terminal of the first switch element, and the second auxiliary emitter terminal of the second switch element is electrically coupled to the control terminal of the second switch element. The first switch element and the second switch element are arranged inside a housing, which includes a first longitudinal side, a second longitudinal side, a first narrow side, and a second narrow side. The first terminal is at least partially arranged in a first section of the housing adjacent to the first narrow side, the third terminal, the first control terminal, the first emitter terminal and the first auxiliary emitter terminal are arranged in a third section of the housing adjacent to the second narrow side, and the second terminal, the second control terminal, the second emitter terminal and the second auxiliary emitter terminal are arranged in a second section of the housing, wherein the second section is arranged between the first section and the third section.

[0006] The present invention can be better understood with reference to the following drawings and descriptions. The components in the drawings are not necessarily drawn to scale, but rather emphasis is placed on illustrating the principles of the present invention. In addition, in the drawings, similar reference numerals designate corresponding parts throughout the different views. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a cross-sectional view of a power semiconductor module device.

[0008] Figure 2 A circuit arrangement according to an example is schematically shown.

[0009] Figure 3 A top view of a power semiconductor module arrangement according to an example is schematically shown.

[0010] Figure 4 A top view of a power semiconductor module arrangement according to another example is schematically shown.

[0011] Figure 5 A three-dimensional diagram of a power semiconductor module arrangement according to an example is schematically shown. DETAILED DESCRIPTION

[0012] Reference will be made to the accompanying drawings in the following detailed description. The accompanying drawings show specific examples in which the present invention can be practiced. It should be understood that the features and principles described in connection with the various examples can be combined with each other unless otherwise specifically stated. In the specification and claims, the designation of certain elements as "first element", "second element", "third element", etc. should not be understood as being used as an enumeration. On the contrary, such designation is only for the purpose of referring to different "elements". That is, for example, the presence of a "third element" does not require the presence of a "first element" and a "second element". The wires or electrical connections described herein may be a single conductive element or may include at least two individual conductive elements connected in series and / or in parallel. The wires and electrical connections may include metal and / or semiconductor materials and may be permanently conductive (i.e., non-switchable). The semiconductor body as described herein may be made of (doped) semiconductor material and may be a semiconductor chip or may be included in a semiconductor chip. The semiconductor body has an electrical connection pad and includes at least one semiconductor element having an electrode.

[0013] refer to Figure 1 , schematically shows a cross-sectional view of a power semiconductor module device 300. The power semiconductor module device 300 includes a housing 37 and a semiconductor substrate 310. The semiconductor substrate 310 includes a dielectric insulating layer 311, a (structured) first metallization layer 3111 attached to the dielectric insulating layer 311, and a (structured) second metallization layer 3112 attached to the dielectric insulating layer 311. The dielectric insulating layer 311 is arranged between the first metallization layer 3111 and the second metallization layer 3112.

[0014] Each of the first metallization layer 3111 and the second metallization layer 3112 may be composed of or include one of the following materials: copper; copper alloy; aluminum; aluminum alloy; any other metal or alloy that remains solid during operation of the power semiconductor module device. The semiconductor substrate 310 may be a ceramic substrate, i.e., a substrate in which the dielectric insulating layer 311 is a ceramic (e.g., a thin ceramic layer). The ceramic may be composed of or include one of the following materials: aluminum oxide; aluminum nitride; zirconium oxide; silicon nitride; boron nitride; or any other dielectric ceramic. For example, the dielectric insulating layer 11 may be composed of or include one of the following materials: Al2O3, AlN, SiC, BeO, or Si3N4. For example, the substrate 310 may be, for example, a direct copper bonding (DCB) substrate, a direct aluminum bonding (DAB) substrate, or an active metal brazing (AMB) substrate. In addition, the substrate 310 may be an insulated metal substrate (IMS). For example, the insulated metal substrate generally includes a dielectric insulating layer 311 containing a (filling) material such as epoxy resin or polyimide. For example, the material of the dielectric insulating layer 311 can be filled with ceramic particles. Such particles can include (for example) Si2O, Al2O3, AlN or BrN, and can have a diameter between about 1 μm and about 50 μm. The substrate 310 can also be a conventional printed circuit board (PCB) with a non-ceramic dielectric insulating layer 311. For example, the non-ceramic dielectric insulating layer 311 can be composed of a cured resin or can include a cured resin.

[0015] The semiconductor substrate 310 is arranged in the housing 37. Figure 1 In the example shown in , the semiconductor substrate 310 forms the bottom surface of the housing 37, and the housing 37 itself only includes side walls and a cover. However, this is only an example. It is also possible that the housing 37 also includes a bottom surface, and the semiconductor substrate 310 can be arranged inside the housing 37. According to another example, the semiconductor substrate 310 can be mounted on a substrate (not shown). In some power semiconductor module devices 300, more than one semiconductor substrate 310 is arranged on the bottom surface of the housing 37 or on a single substrate (not shown). For example, the substrate can form the bottom surface of the housing 37.

[0016] One or more semiconductor bodies 320 may be arranged on at least one semiconductor substrate 310. Each of the semiconductor bodies 320 arranged on at least one semiconductor substrate 310 may include a diode, an IGBT (insulated gate bipolar transistor), a MOSFET (metal oxide semiconductor field effect transistor), a JFET (junction field effect transistor), a HEMT (high electron mobility transistor), or any other suitable semiconductor element.

[0017] One or more semiconductor bodies 320 may form a semiconductor device on the semiconductor substrate 310. Figure 1 In FIG. 3 , only two semiconductor bodies 320 are shown by way of example. Figure 1 The second metallization layer 3112 of the semiconductor substrate 310 is a continuous layer. Figure 1 In the example shown, the first metallization layer 3111 is a structured layer. By "structured layer" is meant that the first metallization layer 3111 is not a continuous layer, but includes recesses between different sections of the layer. Figure 1 Such a recess is schematically shown in . The first metallization layer 3111 in this example includes three different sections. However, this is just an example. Any other number of sections is possible. Different semiconductor bodies 320 can be mounted to the same section or different sections of the first metallization layer 3111. The different sections of the first metallization layer may not have any electrical connections, or may be electrically connected to one or more other sections using (for example) bonding wires 33. For example, just to name a few examples, the electrical connection 33 may also include a connecting plate or a conductor track. One or more semiconductor bodies 320 can be electrically and mechanically connected to the semiconductor substrate 310 via a conductive connection layer 330. Such a conductive connection layer can be a solder layer, a conductive adhesive layer, or a sintered metal powder (for example, a sintered silver powder) layer.

[0018] According to other examples, the second metallization layer 3112 may also be a structured layer. It is also possible to completely omit the second metallization layer 3112. For example, the first metallization layer 3111 may also be a continuous layer.

[0019] Figure 1 The power semiconductor module device 300 shown in also includes a terminal element 34. The terminal element 34 is electrically connected to the first metallization layer 3111 and provides an electrical connection between the interior and the exterior of the housing 37. The terminal element 34 can be electrically connected to the first metallization layer 3111 at a first end, while the second end 341 of the terminal element 34 extends out of the housing 37. The terminal element 34 can be electrically contacted from the outside at the second end 341 of the terminal element 34. The first part of the terminal element 34 can extend through the interior of the housing 37 in a vertical direction y. The vertical direction y is a direction perpendicular to the top surface of the semiconductor substrate 310, wherein the top surface of the semiconductor substrate 310 is the surface on which at least one semiconductor body 320 is mounted. The second ends 341 of the terminal elements 34 can be bent so that they extend in a first horizontal direction x parallel to the top surface of the semiconductor substrate 310. In this way, for some applications, it can be easier to make electrical contact with the second end 341. However, Figure 1The terminal elements 34 shown are only examples. The terminal elements 34 can be implemented in any other way, and the terminal elements 34 can be arranged at any position in the housing 37. For example, one or more terminal elements 34 can be arranged to be close to the side wall of the housing 37 or adjacent to the side wall of the housing 37. The terminal elements 34 can also extend through the side wall of the housing 37 instead of through the cover. The second end 341 is also likely to extend completely in the vertical direction y, rather than being bent to the first horizontal direction x. Any other suitable embodiment is possible.

[0020] The semiconductor body 320 may include a chip pad metallization (not specifically shown), for example, a source, a drain, an anode, a cathode or a gate metallization. The chip pad metallization generally provides a contact surface for electrically connecting the semiconductor body 320. For example, the chip pad metallization may be in electrical contact with the connection layer 330, the terminal element 34 or the electrical connection 33. The chip pad metallization may be made of a metal such as aluminum, copper, gold or silver or may include a metal such as aluminum, copper, gold or silver. The electrical connection 33 and the terminal element 34 may also be made of a metal such as copper, aluminum, gold or silver or may include a metal such as copper, aluminum, gold or silver.

[0021] Reference now Figure 2 , and as mentioned above, at least two semiconductor bodies 320 may be arranged in a half-bridge configuration. Figure 2 is a circuit diagram of an exemplary half-bridge arrangement.

[0022] The half-bridge device is configured to convert a DC voltage provided at the input DC+, DC- of the half-bridge device into an AC voltage. The AC voltage can be provided to a load (not shown) coupled to the output AC of the half-bridge device, for example. The half-bridge device is coupled between a first power supply node 1, 2, 9 configured to be operably coupled to a first potential DC+ and a second power supply node 6, 7, 8 configured to be operably coupled to a second potential DC-. The first potential DC+ may be a positive potential and the second potential DC- may be a negative potential, thereby supplying a DC voltage via the first and second power supply nodes 1, 2, 9, 6, 7, 8. The first and second power supply nodes 1, 2, 9, 6, 7, 8 form the input of the half-bridge device.

[0023] The half-bridge device may include a high-side switch S1 (first switch) and a low-side switch S2 (second switch) coupled in series between the first power supply node 1, 2, 9 and the second power supply node 6, 7, 8. The half-bridge device can be configured to drive a load (not specifically shown) at the output node 3, 4, 5 of the half-bridge device. For example, the load can be an inductive load. The output nodes 3, 4, 5 are electrically connected to a common node between the high-side switch S1 and the low-side switch S2.

[0024] exist Figure 2 In the circuit arrangement of the invention, each switch S1, S2 of the half-bridge device is implemented as an IGBT (insulated gate bipolar transistor). However, this is only an example. For example, the switches S1, S2 may also be implemented as a MOSFET (metal oxide semiconductor field effect transistor), a JFET (junction field effect transistor), a HEMT (high electron mobility transistor), a BJT (bipolar junction transistor) or any other kind of transistor. Each of the switches S1, S2 may include an internal or external freewheeling diode. According to another example, each of the switches S1, S2 includes two or more separate switching elements (not shown) electrically coupled in parallel to each other.

[0025] Each of the first and second switches S1, S2 comprises a control electrode 10, 14 and a controllable load path between the first and second load electrodes. The load paths of the first and second switches S1, S2 are coupled in series between the first and second supply nodes 1, 2, 9 and 6, 7, 8.

[0026] according to Figure 2 According to an example, several different connection terminals may be provided to facilitate electrical contact with the half-bridge device. According to an example, three different first terminals 1, 2, 9 may be provided to form a first power supply node, and three different second terminals 6, 7, 8 may be provided to form a second power supply node. A third terminal 10 may be provided to form a control electrode of a first switch S1, and a fourth terminal 14 may be provided to form a control electrode of a second switch S2. A fifth terminal 3, 4, 5 may be provided to form an output node of the half-bridge device.

[0027] Furthermore, each of the first switch S1 and the second switch S2 may be provided with an emitter terminal 12, 13 and a so-called auxiliary emitter terminal 11, 15. For example, the auxiliary emitter terminal 11, 15 may be provided in order to minimize potential negative feedback effects on the gate-emitter voltage (gate-emitter voltage = voltage between the control electrode 10, 14 of the switch S1, S2 and the corresponding emitter terminal 12, 13). According to another example, the auxiliary emitter terminal 11, 15 may be provided in order to detect an internal voltage drop (e.g., a voltage drop between the terminals 11 and 12 or a voltage drop between the terminals 13 and 15) between the emitter terminal 12, 13 and a corresponding one of the auxiliary emitter terminals 11, 15. For example, a voltage drop may occur due to stray inductance at the moment of opening or closing the corresponding first or second switch S1, S2. For example, the detected voltage drop may be used for error detection.

[0028] In this way, a total of (for example) fifteen terminals can be provided for electrical contact with a single half-bridge device. In the power semiconductor module device 300, each of the individual terminals 1-15 can be implemented as a terminal element 34, as described above in connection with Figure 1 Described. One or more terminals 1-15 can be electrically coupled to the same segment of the first metallization layer 311. For example, each first terminal 1, 2, 9 can be electrically coupled to the same segment of the first metallization layer 311, and each second terminal 6, 7, 8 can be electrically coupled to a different one of the segments of the first metallization layer 311. For example, two or more terminals electrically coupled to the same potential can be electrically coupled to the same segment of the first metallization layer 311. However, this is just an example. Two or more terminals electrically coupled to the same potential may also be electrically coupled to two or more different segments of the first metallization layer 311. However, such segments can be electrically coupled to each other by (for example) bonding wires, connecting plates or conductor tracks.

[0029] Reference now Figure 1 and Figure 2 The layout of the power semiconductor module arrangement and in particular the position of the terminal elements 34 in the housing 37 can have an influence on the switching behavior of the semiconductor arrangement. Therefore, the position of the individual terminal elements 34 in the housing 37 can be selected to meet the requirements regarding creepage distances and to improve the switching behavior of the half-bridge arrangement.

[0030] like Figure 2 and Figure 3 As schematically shown in FIG. 1 , the terminals can be grouped according to their potentials. That is, the first terminals 1, 2, 9 electrically connected to the first potential DC+ can form a first group ( Figure 2 and Figure 3 The second terminals 6, 7, 8 electrically connected to the second potential DC- and the second emitter terminal and the second auxiliary emitter terminal 13, 15 can form a second group ( Figure 2 and Figure 3 The output terminals 3, 4, 5 electrically connected to the output potential AC and the first emitter terminal and the first auxiliary emitter terminal 12, 11 can form a third group ( Figure 2 and Figure 3 For example, the control terminal 10 of the first switch S1 may be included in the third group AC, and the control terminal 14 of the second switch S2 may be included in the second group DC-.

[0031] The terminals of a certain group may be arranged adjacent to each other or at least close to each other, with no or as few other terminals of another group arranged therebetween. For example, the power semiconductor module device 300, in particular the semiconductor substrate 310 and the housing 37, may have a rectangular shape. That is, the power semiconductor module device 300 may include a first longitudinal side L1, a second longitudinal side L2, a first narrow side B1, and a second narrow side B2. Figure 3 It is schematically shown in the top view that the terminals 3, 4, 5, 10, 11, 12 of the third group AC can be arranged in the third section of the power semiconductor module device 300, wherein the third section is arranged along the second narrow side B2. The terminals 1, 2, 9 of the first group DC+ can be at least partially arranged in the first section of the power semiconductor module device 300, wherein the first section is arranged along the first narrow side B1. Figure 3 In the example shown in , only two of the first group of DC+ terminals are arranged in the first section along the first narrow side B1. The second group of DC- terminals 6, 7, 8, 13, 14, 15 can be arranged in the second section of the power semiconductor module device 300, wherein the second section is arranged between the first section and the third section. The second section is adjacent to the first longitudinal side L1 and the second longitudinal side L2, but not adjacent to the first narrow side B1 and the second narrow side B2. That is, in the first horizontal direction x, one side of the second section is bounded by the first section, and the opposite side is bounded by the third section.

[0032] The first emitter terminal 12 is arranged closer to the third terminals 3, 4, 5 than to the second control terminal 14, the second emitter terminal 13 and the second auxiliary emitter terminal 15. The distance between the first control terminal 10 and the first terminal 9 arranged in the fourth section is substantially equal to the distance between the first terminal 9 arranged in the fourth section and the third second terminal 8 of the second terminals arranged adjacent to the second longitudinal side L2.

[0033] like Figure 3 As schematically shown in , it may not be possible to arrange all the terminals 1, 2, 9 of the first group in the same section. Therefore, at least one terminal 9 of the first group may be arranged separately in the fourth section. For example, the fourth section may be adjacent to the second longitudinal side L2 and may be arranged between the second section and the third section in the first horizontal direction x. However, the fourth section may not be adjacent to the first longitudinal side L1. In the second horizontal direction z, part of the second section may be arranged between the fourth section and the first longitudinal side L1.

[0034] In this way, the terminals 1-15 are grouped according to the potential to which they are electrically connected. This allows the power semiconductor module device 30 to be contacted and controlled as symmetrically as possible. In addition, any requirements regarding creepage distances can be met. Due to the reason that the terminals are grouped according to the potential of the terminals, the surface area of ​​the semiconductor substrate 310 can be better utilized. The conductor tracks (sections of the first metallization layer 311) can be kept as short as possible because all terminals in contact with a certain conductor track are arranged within a certain range relative to each other, and terminals of other potentials are not arranged in between.

[0035] The voltage drop between terminals electrically connected to the same potential (e.g., terminals 5 and 12, both electrically connected to the third potential AC) can be significantly smaller (e.g., several volts smaller) than the voltage drop (e.g., tens of volts) between terminals electrically connected to different potentials (e.g., terminal 12 electrically connected to the third potential AC and terminal 13 electrically connected to the second potential DC-). Therefore, arranging terminals connected to the same potential adjacent to each other provides several advantages over arranging multiple terminals electrically connected to different potentials adjacent to each other.

[0036] For example, both terminals 11 and 12 are electrically connected to the third potential AC, and both terminals 8 and 15 are electrically connected to the second potential DC-. The internal dispersion of these terminal pairs results in different routing of conductor traces on the semiconductor substrate 310. Different routing of conductor traces can result in different internal inductances. For example, any inductance differences can be compensated by routing of the conductor traces in a meandering shape.

[0037] In each of the first, second and third sections, the corresponding terminals can be arranged on the periphery along the side of the corresponding section. That is, in the first section DC+, the terminals 1 and 2 can be arranged along the first narrow side B1, wherein one terminal 1 is arranged adjacent to the first longitudinal side L1 (significantly closer to the first longitudinal side L1 than to the second longitudinal side L2), and the other terminal 2 is arranged adjacent to the second longitudinal side L2 (significantly closer to the second longitudinal side L2 than to the first longitudinal side L1). In the second section DC-, the first subgroup of the terminals 13, 14, and 15 is arranged along the first longitudinal side L1 (significantly closer to the first longitudinal side L1 than to the second longitudinal side L2), the second subgroup of the terminal 8 is arranged along the second longitudinal side L2 (significantly closer to the second longitudinal side L2 than to the first longitudinal side L1), and the third subgroup of the terminals 6 and 7 is arranged along the boundary of the second section DC- toward the first section DC+. In the third subgroup, one terminal 6 is arranged adjacent to the first subgroup and the first longitudinal side L1 (significantly closer to the first longitudinal side L1 than to the second longitudinal side L2), and another terminal 7 is arranged adjacent to the second subgroup and the second longitudinal side L2 (significantly closer to the second longitudinal side L2 than to the first longitudinal side L1). No terminal may be arranged in the central part of the second section. In the third section AC, the terminals 3, 4, 5 of the fourth subgroup may be arranged along the second narrow side B2 (closer to the second narrow side B2 than to the first narrow side B1), the fifth subgroup of terminals 10, 11 may be arranged along the second longitudinal side L2 (closer to the second longitudinal side L2 than to the first longitudinal side L1), and the sixth subgroup of terminals 12 may be arranged along the first longitudinal side L1 (closer to the first longitudinal side L1 than to the second longitudinal side L2). No terminal may be arranged in the central part of the third section. Each subgroup may include at least one terminal.

[0038] Figure 5 A three-dimensional view of a power semiconductor module arrangement 300 including a housing 37 is schematically shown, wherein the terminal elements 34 (terminals 1-15) are accumulated in three main groups, as already described above in connection with Figure 3 Because any components arranged inside the housing 37 cannot be seen through the side walls and the top cover of the housing 37, the semiconductor substrate 310 and the semiconductor body 320 mounted thereon are Figure 5 is not visible in the 3D image.

[0039] For reasons of space, for example, it is almost never necessary to connect a Figure 3 Terminal 9 in the figure) or a plurality of terminals (not shown) are arranged away from other terminals connected to the same potential. However, for many applications, it is not necessary to arrange most of the terminals in three main groups according to their potential (see Figure 3In the group DC+, DC-, AC), then this approach may be acceptable.

[0040] As already contacted above Figure 3 As described, arranging the terminals in at least three main groups will provide an optimized layout for the parallel connection of two or more power semiconductor module arrangements 300. Figure 4 In the example shown in Figure 4 In the top view shown in FIG. 2 , two power semiconductor module arrangements 300 are connected in parallel with each other. It can be seen that, as has already been mentioned above, the terminals are arranged in at least three main groups. Figure 3 As described, all terminals 3, 4, 5, 10, 11, 12 electrically connected to the third potential AC may be arranged along one side of the parallel connection. All terminals 1, 2 electrically connected to the first potential DC+ may be arranged at least partially along the opposite side of the parallel connection of the power semiconductor module device 300. All terminals 6, 7, 8, 13, 14, 15 electrically connected to the second potential DC- may be arranged centrally between the first side and the second side. The remaining terminals 9 electrically connected to the first potential DC+ may form a fourth group, and the remaining terminals 9 electrically connected to the first potential DC+ may be arranged centrally between the first side and the second side.

[0041] As already contacted above Figure 1 As described, the terminal element 34 may include a second end 341 extending outside the housing 37. Each of the second ends 341 may form a connection plate outside the housing 37. In the drawings, for example, some of the terminals 1, 2, 3, 4, 5, 6, 7 are shown as including a connection plate. The connection plate may be arranged substantially parallel to the top surface of the semiconductor substrate 310 arranged inside the housing 37. Such a connection plate may include a threaded hole, for example (in Figures 3 to 5 1, 2, 3, 4, 5, 6, 7). For example, the terminal element 34 can be electrically contacted by means of a conductive bolt (bolt not shown in the figure). Such a conductive bolt can be inserted into the threaded hole. Any external element (not shown) can be mechanically and electrically coupled to the terminal element 34 by means of such a bolt.

[0042] In the drawings, the other terminals 8, 9, 10, 11, 12, 13, 14, 15 are shown as including contact pins extending vertically from the inside of the housing 37 to the outside of the housing 37. For example, the contact pins may include threaded holes, such as (in Figures 3 to 5The terminal element 34 may be electrically connected to the terminal element 34 by means of a conductive bolt (bolt not shown in the figure). Such a conductive bolt may be inserted into the threaded hole. Any external element (not shown) may be mechanically and electrically coupled to the terminal element 34 by means of a bolt. For example, the external element may include at least one of a connecting plate, a circuit board, and a connecting wire.

Claims

1. A power semiconductor module device (300), comprising: a first switching element (S1) and a second switching element (S2), each of the first switching element (S1) and the second switching element (S2) having a control terminal (10, 14) and a controllable load path between two load terminals, the load paths of the first switching element (S1) and the second switching element (S2) being operably coupled in series and between a first power supply node configured to be operably coupled to a first potential (DC+) and a second power supply node configured to be operably coupled to a second potential (DC-), wherein the first switching element (S1) and the second switching element (S2) are connected to each other via a first common node; and an output node configured to be coupled to an output potential (AC), wherein the output node is coupled to the first common node, wherein The first power supply node is formed by a plurality of first terminals (1, 2, 9), The second power supply node is formed by a plurality of second terminals (6, 7, 8), The output node is formed by a plurality of third terminals (3, 4, 5), The first switch element (S1) and the second switch element (S2) are arranged inside a housing (37), the housing (37) comprising a first longitudinal side (L1), a second longitudinal side (L2), a first narrow side (B1) and a second narrow side (B2), The first terminal (1, 2) is at least partially arranged in a first section of the housing (37) adjacent to the first narrow side (B1), The third terminal (3, 4, 5), the first control terminal (10) of the first switching element (S1), the first emitter terminal (12) and the first auxiliary emitter terminal (11) are arranged in a third section of the housing (37) adjacent to the second narrow side (B2), and The second terminal (6, 7, 8), the second control terminal (14) of the second switching element (S2), the second emitter terminal (13) and the second auxiliary emitter terminal (15) are arranged in a second section of the housing (37), wherein the second section is arranged between the first section and the third section.

2. The power semiconductor module device (300) according to claim 1, wherein: One of the first terminals (9) is arranged in a fourth section remote from the first section.

3. The power semiconductor module device (300) according to claim 2, wherein: The fourth section is arranged adjacent to the second longitudinal side (L2) and adjacent to the second section and the third section, and wherein the second section is arranged between the first section and the fourth section.

4. The power semiconductor module arrangement (300) according to any one of claims 1 to 3, wherein: The third terminals (3, 4, 5) are arranged in a row along the second narrow side (B2), The first control terminal (10) and the first auxiliary emitter terminal (11) are arranged in a row along the second longitudinal side (L2), The first emitter terminal (12) is arranged adjacent to the first longitudinal side (L1), and The central portion of the third section does not include any terminals.

5. The power semiconductor module arrangement (300) according to any one of claims 1 to 3, wherein: The second control terminal (14), the second emitter terminal (13) and the second auxiliary emitter terminal (15) are arranged in a row along the first longitudinal side (L1), Two of the second terminals (6, 7) are arranged in a row perpendicular to the first longitudinal side (L1) and the second longitudinal side (L2) and adjacent to the first section, A third one of the second terminals (8) is arranged adjacent to the second longitudinal side (L2).

6. The power semiconductor module arrangement (300) according to any one of claims 1 to 3, wherein: A voltage drop between a third of the second terminals (8) and the second auxiliary emitter terminal (15) indicates an error state of the power semiconductor module arrangement (300).

7. The power semiconductor module arrangement (300) according to any one of claims 1 to 3, wherein: A voltage drop between the first emitter terminal (12) and the first auxiliary emitter terminal (11) indicates an error state of the power semiconductor module arrangement (300).

8. The power semiconductor module arrangement (300) according to any one of claims 1 to 3, wherein: The first emitter terminal (12) is arranged closer to the third terminal (3, 4, 5) than to the second control terminal (14), the second emitter terminal (13) and the second auxiliary emitter terminal (15).

9. The power semiconductor module arrangement (300) according to any one of claims 1 to 3, wherein: The distance between the first control terminal (10) and the first terminal (9) arranged in the fourth section is substantially equal to the distance between the first terminal (9) arranged in the fourth section and a third second terminal (8) among the second terminals.

10. The power semiconductor module arrangement (300) according to any one of claims 1 to 3, wherein: The first switching element (S1) includes at least one IGBT, at least one MOSFET, at least one JFET or at least one HEMT.

11. The power semiconductor module arrangement (300) according to any one of claims 1 to 3, wherein: The second switching element (S2) includes at least one IGBT, at least one MOSFET, at least one JFET or at least one HEMT.

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