A programmable self-calibrating single-integration type analog-to-digital conversion circuit

Abstract

The present invention relates to a programmable self - calibration single - integration type analog - to - digital conversion circuit, which includes a sawtooth wave generating circuit, a counter, and three third comparators. The sawtooth wave generating circuit includes an integrator, a rising - edge locking circuit, and an unlocking circuit; the integrator includes a controllable constant - current source and a capacitor connected in series; the controllable constant - current source is connected to a programming terminal; a discharge switch is connected in parallel across the capacitor; the rising - edge locking circuit is used to achieve reliable discharge of the integrator; the unlocking circuit is used to unlock the integrator to trigger an integration action when the rising edge of the clock signal arrives; the output end of the integrator is connected to an input end of one of the three third comparators, and the output ends of the three third comparators are respectively connected to three registers. The present invention can reduce the circuit complexity while improving the measurement accuracy.

Description

Technical Field

[0001] The present invention relates to an integrating analog-to-digital conversion circuit, and more particularly to a programmable self-calibrating single-integrating analog-to-digital conversion circuit. Background Art

[0002] The integrating ADC (analog-to-digital conversion) is an indirect measurement method that converts an electrical signal into time for measurement. It has the advantages of simple circuit and high measurement accuracy. The disadvantage is that the measurement speed is not high, and it is generally applied to devices such as multimeters.

[0003] The performance of the single-integrating ADC is related to the accuracy of the integrating resistor and capacitor and the reference voltage. Limited by the process level, it is difficult to meet the requirements for the accuracy of component parameters, especially the capacitor accuracy. There are also problems such as parameter drift, resulting in the single-integrating ADC not reaching practical value.

[0004] In the dual-integrating ADC, the integrating elements (such as integrating resistors and integrating capacitors) used in the two integration processes can cancel each other out, thus eliminating the problems of parameter accuracy and drift. However, there is a switch delay in the two integration conversion processes of the dual-integrating circuit. The comparator used in the circuit is non-ideal and has an offset voltage problem. The starting moment of the counting clock is random, and the measurement time required for different measured voltages (Vin) is different. The improved multi-integrating ADC circuit has a slight improvement in speed, but increases the circuit complexity. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a programmable self-calibrating single-integrating analog-to-digital conversion circuit, which can improve the measurement accuracy while reducing the circuit complexity.

[0006] The technical solution adopted by the present invention to solve its technical problems is: to provide a programmable self-calibrating single-integrating analog-to-digital conversion circuit, including a sawtooth wave generating circuit, a counter, and three third comparators. The output end of the counter is respectively connected to three registers. The sawtooth wave generating circuit includes an integrator, a rising edge locking circuit, and an unlocking circuit. The integrator includes a controllable constant current source and a capacitor connected in series. The controllable constant current source is connected to the programming terminal. A discharge switch is connected in parallel across the capacitor. The rising edge locking circuit is used to realize reliable discharge of the integrator. The unlocking circuit is used to unlock the integrator to trigger the integration action when the rising edge of the clock signal arrives. The output end of the integrator is connected to one input end of the three third comparators. The other input end of one of the three third comparators is connected to the VIN input terminal, and the other input ends of the other two third comparators are respectively connected to the positive reference voltage terminal and the negative reference voltage terminal. The output ends of the three third comparators are respectively connected to the three registers.

[0007] The rising edge locking circuit includes a first comparator. One input terminal of the first comparator is connected to the output terminal of the integrator, another input terminal is connected to a first reference voltage, and the output terminal is connected to one input terminal of an OR gate. The output terminal of the OR gate is respectively connected to the discharge switch and the counter.

[0008] The unlocking circuit includes a second comparator and a D flip-flop. One input terminal of the second comparator is connected to the output terminal of the integrator, another input terminal is connected to a second reference voltage, and the output terminal is connected to one input terminal of an AND gate through the D flip-flop. Another input terminal of the AND gate is connected to the output terminal of the OR gate, and the output terminal of the AND gate is connected to the other input terminal of the OR gate.

[0009] The D flip-flop is a rising edge flip-flop.

[0010] Beneficial effects

[0011] Due to the adoption of the above technical solution, compared with the prior art, the present invention has the following advantages and positive effects: The integrator of the present invention is composed of a controllable constant current source and a capacitor, and the sawtooth wave function is realized through a discharge switch. By changing the control signal of the controllable constant current source, the period of the sawtooth wave is changed, and different precision (number of digits) measurements are realized under the condition of a certain counting clock frequency, that is, the programmable function is realized. The rising edge locking circuit composed of the first comparator, the AND gate and the OR gate is used to realize the reliable discharge of the integrator. The unlocking circuit is composed of the second comparator and the D flip-flop, and the integration action is unlocked and triggered only when the rising edge of the clock signal arrives, which is used to solve the problem of random phase of the counting clock. In addition, by using three comparators with consistent characteristics, the offset voltage is eliminated through subtraction operation during the self-calibration counting process, thereby improving the measurement accuracy. Description of the drawings

[0012] Figure 1 is the circuit diagram of the present invention;

[0013] Figure 2 is the schematic diagram of the present invention;

[0014] Figure 3 is the verification schematic diagram of the clock initial phase random problem in the embodiment of the present invention;

[0015] Figure 4 is the comparison diagram of the results after direct conversion and self-calibration after injecting perturbations. Specific embodiments

[0016] The present invention will be further described below in conjunction with specific embodiments. It should be understood that these embodiments are only used to illustrate the present invention and not to limit the scope of the present invention. In addition, it should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms also fall within the scope defined by the appended claims of this application.

[0017] An embodiment of the present invention relates to a programmable self-calibrating single-integration type analog-to-digital conversion circuit. As Figure 1 shown, it includes a sawtooth wave generating circuit, a counter, and three third comparators C. The output terminals of the counter are respectively connected to three registers. The counter and the registers in this embodiment can be replaced by a single-chip microcomputer or an FPGA, etc. The sawtooth wave generating circuit includes an integrator, a rising edge locking circuit, and an unlocking circuit.

[0018] In this embodiment, the integrator includes a controllable constant current source 1 and a capacitor 2 connected in series; the controllable constant current source 1 is connected to the programming terminal; a discharge switch 3 is connected in parallel across both ends of the capacitor 2. The output terminal of the integrator is connected to one input terminal of the three third comparators C. Another input terminal of one of the three third comparators C is connected to the VIN input terminal, and the other input terminals of the other two third comparators C are respectively connected to the positive reference voltage terminal and the negative reference voltage terminal; the output terminals of the three third comparators C are respectively connected to the three registers.

[0019] It can be seen that the integrator is composed of a controllable constant current source and a capacitor plus a discharge switch to realize the sawtooth wave function. By changing the control signal of the controllable constant current source, the period of the sawtooth wave can be changed, and different precision (number of bits) measurements can be realized under the condition of a certain counting clock frequency, that is, the programmable function is realized. Through three third comparators with consistent characteristics, the offset voltage can be eliminated through subtraction operations during the self-calibration counting process.

[0020] The rising edge locking circuit is used to realize reliable discharge of the integrator. The rising edge locking circuit includes a first comparator A. One input terminal of the first comparator A is connected to the output terminal of the integrator, the other input terminal is connected to the first reference voltage 4, and the output terminal is connected to one input terminal of an OR gate 5; the output terminal of the OR gate 5 is respectively connected to the discharge switch 3 and the counter.

[0021] The unlocking circuit is used to unlock the integrator to trigger the integration action when the rising edge of the clock signal arrives. The unlocking circuit includes a second comparator B and a D flip-flop 6. One input terminal of the second comparator B is connected to the output terminal of the integrator, the other input terminal is connected to a second reference voltage, and the output terminal is connected to one input terminal of an AND gate 7 through the D flip-flop 6; the other input terminal of the AND gate 7 is connected to the output terminal of the OR gate 5, and the output terminal of the AND gate 7 is connected to the other input terminal of the OR gate 5. The second comparator B and the D flip-flop 6 form an unlocking circuit and only unlock and trigger the integration action when and only when the rising edge of the clock signal arrives, which is used to solve the problem of random phase of the counting clock.

[0022] The principle of the programmable self-calibration single-integration type analog-to-digital conversion circuit in this embodiment is described as follows Figure 2 shown in the figure. Among them, the slope of the integration curve is determined by the controlled constant current source, and the integration period is changed by changing the voltage to obtain different sampling accuracies and speeds (the faster the speed, the lower the sampling accuracy). At the circled part in the figure, due to the characteristic of the D flip-flop, the integrator is only triggered at the rising edge of the clock CKL, which ensures the consistency of the clock phase during the measurement process. The shaded area in the figure is the effective measurement area, and this area avoids the start and end stages of the integrator to avoid errors such as switch delay. The triangular proportional relationship is satisfied within the effective measurement area, and this relationship is used to realize the parameter self-calibration function with the help of the reference voltage Vref to eliminate the problems of the accuracy and parameters of devices such as resistors and capacitors being far from the normal values. The measurement times T0, T1, and T2 are obtained by triggering three third comparators. When the offset voltages of the three third comparators are the same, the offset voltage band can be eliminated through the self-calibration formula in the figure.

[0023] The following is a further description through simulation verification. Figure 3 This is the verification of the random problem of the initial phase of the clock. Figure 3 In the upper part of the figure, the D flip-flop is not added, and the lower part is the situation after adding the D flip-flop. The two are compared. Among them, the time T2 is represented by the numbers q2_0 to q2_7 (the simulation is in eight bits as an example), and the time T1 is represented by the numbers q1_0 to q1_7. It can be seen from the comparison that there is random fluctuation at the least significant bit without adding the D flip-flop at the circled part in the figure, while there is no random fluctuation problem after adding the D flip-flop.

[0024] The characteristics of the self-calibration ADC are verified by adding a DAC circuit. A perturbation signal (the effect is equivalent to parameter drift) is added at the programming end (Cycle), and the digital signals of the times T0, T1, and T2 (corresponding to the q0, q1, and q2 terminals) are obtained respectively. The latter stage is connected to a DAC circuit (AD558t), and the direct DAC conversion result is compared with the result after self-calibration operation, as shown in Figure 4 .

[0025] Comparing with the above figure, Vin is the input standard sine wave signal, n_1639 is the direct DAC conversion result, and Vout is the result of using the self-calibration algorithm. From the simulation results, it can be seen that after using the self-calibration algorithm, the perturbation of the integration parameters can be basically ignored, and the same effect as that of the dual-slope ADC can be achieved.

[0026] It is not difficult to find that the programmable self-calibration ADC of the present invention is extremely simple in circuit, and all factors affecting the measurement accuracy are avoided as much as possible in the design. The measurement error is eliminated theoretically, and because of the programmable function of the measurement accuracy, a low-cost, high-precision, and multi-application field ADC solution can be realized.

Claims

1. A programmable self - calibrating single - integration type analog - to - digital conversion circuit, comprising a sawtooth wave generating circuit, a counter, and three third comparators. The output end of the counter is respectively connected to three registers. Characterized in that, The sawtooth wave generating circuit includes an integrator, a rising - edge locking circuit, and an unlocking circuit; the integrator includes a controllable constant - current source and a capacitor connected in series; the controllable constant - current source is connected to the programming terminal; a discharge switch is connected in parallel across the two ends of the capacitor. The rising - edge locking circuit is used to achieve reliable discharge of the integrator; the unlocking circuit is used to unlock the integrator to trigger the integration action when the rising edge of the clock signal arrives; the output end of the integrator is connected to one input end of the three third comparators, the other input end of one of the three third comparators is connected to the VIN input terminal, and the other input ends of the other two third comparators are respectively connected to the positive reference voltage terminal and the negative reference voltage terminal; the output ends of the three third comparators are respectively connected to the three registers.

2. The programmable self - calibrating single - integration type analog - to - digital conversion circuit according to claim 1, Characterized in that, The rising - edge locking circuit includes a first comparator. One input end of the first comparator is connected to the output end of the integrator, the other input end is connected to a first reference voltage, and the output end is connected to one input end of an OR gate; the output end of the OR gate is respectively connected to the discharge switch and the counter.

3. The programmable self - calibrating single - integration type analog - to - digital conversion circuit according to claim 2, Characterized in that, The unlocking circuit includes a second comparator and a D - type flip - flop. One input end of the second comparator is connected to the output end of the integrator, the other input end is connected to a second reference voltage, and the output end is connected to one input end of an AND gate through the D - type flip - flop; the other input end of the AND gate is connected to the output end of the OR gate, and the output end of the AND gate is connected to the other input end of the OR gate.

4. The programmable self - calibrating single - integration type analog - to - digital conversion circuit according to claim 3, Characterized in that, The D - type flip - flop is a rising - edge flip - flop.

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