Semiconductor memory device and multiplier accumulator

Abstract

[Problem] To provide a semiconductor memory device and a multiplier accumulator that can apply a sufficient voltage to a ferroelectric capacitor and is suitable for high integration. [Solution] The semiconductor memory device is provided with: a transistor; and a ferroelectric capacitor formed by sandwiching a ferroelectric member between a pair of conductive members, one of the pair of conductive members being electrically connected to a gate electrode of the transistor, wherein a channel of the transistor is three-dimensionally formed involving a plurality of surfaces.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor memory device and a multiplier-accumulator. Background Art

[0002] In recent years, ferroelectric random access memory (FeRAM) has attracted attention as a next-generation memory. FeRAM is a semiconductor memory device that stores information by using the remanent polarization direction of ferroelectrics.

[0003] As an example of the structure of FeRAM, a structure is known in which a ferroelectric capacitor is formed by sequentially stacking a lower electrode, a ferroelectric film, and an upper electrode on a gate electrode of a metal-insulator-semiconductor (MIS) field effect transistor that has been formed on a semiconductor substrate. This structure is also called a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) structure.

[0004] In FeRAM having an MFMIS structure, a voltage is applied between a semiconductor substrate and an upper electrode, and thus the applied voltage is distributed to the gate insulating film of the MIS field effect transistor and the ferroelectric film of the ferroelectric capacitor. Therefore, in some cases, depending on the ratio of the gate capacitance of the MIS field effect transistor to the capacitance of the ferroelectric capacitor, a voltage sufficient to reverse the polarization of the ferroelectric film cannot be applied to the ferroelectric film.

[0005] For example, patent document 1 described below discloses a technology for increasing the distributed voltage of a ferroelectric capacitor in a FeRAM having an MFMIS structure by further setting a paraelectric capacitor, one end of which is connected between the gate electrode of the MIS field effect transistor and the lower electrode of the ferroelectric capacitor, and the other end is connected to the source of the MIS field effect transistor.

[0006] Citation List

[0007] Patent Literature

[0008] Patent Document 1: Japanese Patent Application Laid-Open No. 2004-22944 Summary of the invention

[0009] Problems to be solved by the present invention

[0010] However, in the technique disclosed in Patent Document 1, a region for forming a paraelectric capacitor needs to be further provided on the semiconductor substrate, so the area per unit cell of FeRAM increases. Therefore, it is difficult to highly integrate the FeRAM disclosed in Patent Document 1.

[0011] Therefore, the present disclosure proposes a novel and improved semiconductor memory device and a multiplier-accumulator capable of applying a sufficient voltage to a ferroelectric capacitor and having a structure suitable for high integration.

[0012] Solution to the problem

[0013] According to the present disclosure, a semiconductor storage device is provided, which includes: a transistor; and a ferroelectric capacitor, wherein the ferroelectric capacitor is formed by sandwiching a ferroelectric material between a pair of conductive materials, one of the pair of conductive materials is electrically connected to the gate electrode of the transistor, wherein the channel of the transistor is formed three-dimensionally across multiple surfaces.

[0014] In addition, according to the present disclosure, a multiplier accumulator is provided, which includes: a transistor; and a ferroelectric capacitor, which is formed by sandwiching a ferroelectric material between a pair of conductive materials, one of the pair of conductive materials is electrically connected to the gate electrode of the transistor, wherein the channel of the transistor is formed three-dimensionally across multiple surfaces.

[0015] In addition, according to the present disclosure, a semiconductor storage device is provided, which includes: a transistor; and a ferroelectric capacitor, wherein the ferroelectric capacitor is formed by sandwiching a ferroelectric material between a pair of conductive materials, one of the pair of conductive materials is electrically connected to the gate electrode of the transistor, wherein the pair of conductive materials and the ferroelectric material are stacked parallel to the upper surface of the gate electrode to set the ferroelectric capacitor on the gate electrode, and the planar area of ​​the ferroelectric capacitor is smaller than the planar area of ​​the upper surface of the gate electrode.

[0016] In addition, according to the present disclosure, a multiplication accumulator is provided, which includes: a transistor; and a ferroelectric capacitor, wherein the ferroelectric capacitor is formed by sandwiching a ferroelectric material between a pair of conductive materials, one of the pair of conductive materials is electrically connected to the gate electrode of the transistor, wherein the pair of conductive materials and the ferroelectric material are stacked parallel to the upper surface of the gate electrode to set the ferroelectric capacitor on the gate electrode, and the planar area of ​​the ferroelectric capacitor is smaller than the planar area of ​​the upper surface of the gate electrode.

[0017] According to the present disclosure, the semiconductor memory device can further increase the distributed voltage to be applied to the ferroelectric film of the ferroelectric capacitor by increasing the gate capacitance of the field effect transistor without increasing the size of the unit cell.

[0018] Effects of the Invention

[0019] As described above, according to the present disclosure, a semiconductor memory device and a multiplier-accumulator capable of applying a sufficient voltage to a ferroelectric capacitor and having a structure suitable for high integration can be provided.

[0020] Note that the above-described effects are not necessarily limitative, and any effects described in the specification or other effects that can be understood from the specification may be exhibited in addition to or instead of the above-described effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a longitudinal cross-sectional view schematically showing a structural example of a semiconductor memory device according to a first embodiment of the present disclosure.

[0022] Figure 2A is a longitudinal cross-sectional view schematically showing a structure of a modified example of a semiconductor memory device.

[0023] Figure 2B is a longitudinal cross-sectional view schematically showing a structure of a modified example of a semiconductor memory device.

[0024] Figure 3 It is limited Figure 1 A longitudinal cross-sectional view showing the dimensions of each structure of the semiconductor memory device shown in FIG.

[0025] Figure 4A is a graph showing a range in which the semiconductor memory device according to the same embodiment has satisfactory characteristics.

[0026] Figure 4B is a graph showing a range in which the semiconductor memory device according to the same embodiment has satisfactory characteristics.

[0027] Figure 4C is a graph showing a range in which the semiconductor memory device according to the same embodiment has satisfactory characteristics.

[0028] Figure 5A is a schematic longitudinal cross-sectional view showing one process of the method for manufacturing the semiconductor memory device according to the same embodiment.

[0029] Figure 5B is a schematic longitudinal cross-sectional view showing one process of the method for manufacturing the semiconductor memory device according to the same embodiment.

[0030] Figure 5C is a schematic longitudinal cross-sectional view showing one process of the method for manufacturing the semiconductor memory device according to the same embodiment.

[0031] Figure 5D is a schematic longitudinal cross-sectional view showing one process of the method for manufacturing the semiconductor memory device according to the same embodiment.

[0032] Figure 5E is a schematic longitudinal cross-sectional view showing one process of the method for manufacturing the semiconductor memory device according to the same embodiment.

[0033] Fig. 5F is a schematic longitudinal cross-sectional view showing one process of the method for manufacturing the semiconductor memory device according to the same embodiment.

[0034] Figure 5G is a schematic longitudinal cross-sectional view showing one process of the method for manufacturing the semiconductor memory device according to the same embodiment.

[0035] Figure 6 is a plan view schematically showing a planar configuration of a semiconductor device in which a plurality of semiconductor memory devices according to the same embodiment are arranged in a matrix shape.

[0036] Figure 7 is schematically shown along Figure 6 1 is a longitudinal sectional view of a section taken along line A-AA of the semiconductor device shown in FIG.

[0037] Figure 8 yes Figure 6 and Figure 7 Equivalent circuit diagram of the semiconductor device shown in .

[0038] Fig. 9 It is a longitudinal cross-sectional view schematically showing a cross-sectional structure in a modification of the semiconductor device.

[0039] Fig.10 is a perspective view schematically showing a structural example of a semiconductor memory device according to a second embodiment of the present disclosure.

[0040] Fig.11A is a longitudinal cross-sectional view schematically showing a structure of a modified example of a semiconductor memory device.

[0041] Fig. 11B is a longitudinal cross-sectional view schematically showing a structure of a modified example of a semiconductor memory device.

[0042] Fig. 11C is a longitudinal cross-sectional view schematically showing a structure of a modified example of a semiconductor memory device.

[0043] Fig.11D is a longitudinal cross-sectional view schematically showing a structure of a modified example of a semiconductor memory device.

[0044] Fig.12 It is limited Fig.10 A perspective view showing the dimensions of each structure of the semiconductor memory device shown in FIG.

[0045] Fig.13 is a plan view schematically showing a planar configuration of a semiconductor device in which a plurality of semiconductor memory devices according to the same embodiment are arranged in a matrix shape.

[0046] Fig.14 is a longitudinal cross-sectional view schematically showing a structural example of a semiconductor memory device according to the same embodiment.

[0047] Fig.15 It is limited Fig.14 A longitudinal cross-sectional view showing the dimensions of each structure of the semiconductor memory device shown in FIG.

[0048] Fig.16A is a schematic longitudinal cross-sectional view showing one process of the method for manufacturing the semiconductor memory device according to the same embodiment.

[0049] Fig. 16B is a schematic longitudinal cross-sectional view showing one process of the method for manufacturing the semiconductor memory device according to the same embodiment.

[0050] Fig. 16C is a schematic longitudinal cross-sectional view showing one process of the method for manufacturing the semiconductor memory device according to the same embodiment.

[0051] Fig.16D is a schematic longitudinal cross-sectional view showing one process of the method for manufacturing the semiconductor memory device according to the same embodiment.

[0052] Fig.16E is a schematic longitudinal cross-sectional view showing one process of the method for manufacturing the semiconductor memory device according to the same embodiment.

[0053] Fig.17 is a longitudinal cross-sectional view schematically showing a structure of a modified example of a semiconductor memory device.

[0054] Fig.18 is a longitudinal cross-sectional view schematically showing a structure of a modified example of a semiconductor memory device.

[0055] Fig.19 is a longitudinal cross-sectional view schematically showing a structure of a modified example of a semiconductor memory device. DETAILED DESCRIPTION

[0056] Preferred embodiments of the present disclosure are described in detail below with reference to the accompanying drawings. Note that in the specification and the drawings, components having substantially the same functional configuration are denoted by the same reference symbols, and thus repeated descriptions are omitted.

[0057] In each of the drawings mentioned in the following specification, in some cases, for the convenience of description, the size of some constituent members is emphasized and shown. Therefore, the relative size of the constituent members shown in each drawing does not always accurately indicate the actual size relationship between the constituent members. In addition, in the following description, in some cases, the direction of stacking substrates or layers is described as an upward direction.

[0058] Note that the description is provided in the order described below.

[0059] 1. First Embodiment

[0060] 1.1. Structure example

[0061] 1.2. Design Example

[0062] 1.3. Manufacturing method

[0063] 1.4. Application Examples

[0064] 2. Second Embodiment

[0065] 2.1. Example of structure

[0066] 2.2. Design Example

[0067] 2.3 Application Examples

[0068] 3. Third embodiment

[0069] 3.1. Example of structure

[0070] 3.2. Design Example

[0071] 3.3. Manufacturing method

[0072] 3.4. Modifications

[0073] <1. First Embodiment>

[0074] (1.1. Structure example)

[0075] First, refer to Figure 1 A structural example of a semiconductor memory device according to a first embodiment of the present disclosure is described. Figure 1 is a longitudinal cross-sectional view schematically showing a structural example of the semiconductor memory device according to the present embodiment.

[0076] like Figure 1 As shown in , the semiconductor memory device 100 includes a semiconductor substrate 110 , a source or drain region 111 , a gate insulating film 121 , a lower electrode 120 , a ferroelectric film 131 , an upper electrode 130 , and a conductor electrode 140 .

[0077] The semiconductor memory device 100 is a FeRAM having an MFMIS structure, in which a ferroelectric capacitor is connected in series to a gate electrode of a field effect transistor. Specifically, the field effect transistor includes a semiconductor substrate 110, a source or drain region 111, a gate insulating film 121, and a lower electrode 120, and the ferroelectric capacitor includes a lower electrode 120, a ferroelectric film 131, and an upper electrode 130. The ferroelectric capacitor is connected in series to the gate of the field effect transistor through the lower electrode 120.

[0078] The semiconductor substrate 110 is a substrate constructed by using a semiconductor material. In the region where the semiconductor memory device 100 is formed, an impurity of a first conductivity type (e.g., a p-type impurity such as boron or aluminum) is introduced into the semiconductor substrate 110. The semiconductor substrate 110 may be a silicon substrate, or may be a silicon-on-insulator (SOI) substrate in which an insulating film of SiO2 or the like is maintained in the silicon substrate. Alternatively, the semiconductor substrate 110 may be a substrate including another element semiconductor such as germanium, or may be a substrate including a compound semiconductor such as gallium arsenide (GaAs), gallium nitride (GaN), or silicon carbide (SiC). In addition, the semiconductor substrate 110 may be a substrate in which a semiconductor layer is stacked on a substrate including quartz, sapphire, resin, metal, etc.

[0079] The source or drain region 111 is a region of the second conductivity type (e.g., an n-type region) formed in the semiconductor substrate 110. Specifically, the source or drain region 111 is provided by introducing an impurity of the second conductivity type (e.g., an n-type impurity such as phosphorus or arsenic) into a region on both sides of an opening provided in the semiconductor substrate 110. Within the opening provided in the semiconductor substrate 110, a field effect transistor and a ferroelectric capacitor are formed. Note that if the source or drain regions 111 are separated from each other, it is not always necessary to provide the source or drain regions 111 on both sides of the opening provided in the semiconductor substrate 110.

[0080] Note that, in the source or drain regions 111 formed on both sides of the opening provided in the semiconductor substrate 110, either one may be used as a source region, and either one may be used as a drain region. The source region and the drain region may be arbitrarily changed according to the wiring connected to the corresponding source or drain region 111.

[0081] The gate insulating film 121 is constructed by using an insulating material, and is provided along the inner shape of the opening formed in the semiconductor substrate 110. Specifically, the opening formed in the semiconductor substrate 110 is provided up to a region deeper than the source or drain region 111 in the semiconductor substrate 110, and the gate insulating film 121 is provided along the bottom surface and the side surface of the opening. The gate insulating film 121 may be formed by using an insulating material known as a gate insulating film of a field effect transistor. For example, the gate insulating film 121 may be formed by using silicon oxide (SiO x ), Silicon Nitride (SiN x ) or an insulating nitride oxide such as silicon oxynitride (SiON) to form the gate insulating film 121.

[0082] The lower electrode 120 is configured by using a conductive material, and is provided on the gate insulating film 121 to fill the opening formed in the semiconductor substrate 110. For example, the lower electrode 120 may be formed by using polysilicon or the like, or may be formed by using a metal, an alloy, or a metal compound. Note that the lower electrode 120 is not electrically connected to another wiring, and is provided in an independent potential state (referred to as a floating state).

[0083] The ferroelectric film 131 is constructed by using a ferroelectric material, and is provided along the inner shape of the opening provided in the lower electrode 120. Specifically, the opening provided in the lower electrode 120 is provided inside the lower electrode 120, and the ferroelectric film 131 is provided along the bottom surface and the side surface of the opening. Note that the opening provided in the lower electrode 120 may be provided to expose the gate insulating film 121.

[0084] The ferroelectric film 131 is formed by using a ferroelectric material that is automatically polarized and has a residual polarization direction that can be controlled by an external electric field. Specifically, the ferroelectric film 131 is formed by using a ferroelectric material including hafnium (Hf), zirconium (Zr), silicon (Si), or oxygen (O). For example, the ferroelectric film 131 can be formed by using a ferroelectric material having a perovskite structure such as lead zirconate titanate (Pb(Zr, Ti)O3: PZT) or strontium bismuth tantalate (SrBi2Ta2O9: SBT). In addition, the ferroelectric film 131 can be formed by treating a ferroelectric material including HfO x 、ZrO x or HfZrO x The ferroelectric film 131 may be a ferroelectric film obtained by performing heat treatment or the like on a film of a high dielectric material such as HfO to modify the film, or may be a ferroelectric film obtained by introducing atoms such as lanthanum (La), silicon (Si), or gadolinium (Gd) into a film including the above high dielectric material to modify the film. In addition, the ferroelectric film 131 may be formed to have a single layer, or may be formed to have a multilayer. For example, the ferroelectric film 131 may be a film including HfO xA single layer of ferroelectric material such as .

[0085] The upper electrode 130 is configured by using a conductive material, and is disposed on the ferroelectric film 131 to fill the opening formed in the lower electrode 120. For example, the upper electrode 130 may be formed by using a metal such as titanium (Ti) or tungsten (W), or a metal compound such as titanium nitride (TiN) or tantalum nitride (TaN).

[0086] The conductor electrode 140 is constructed by using a conductive material, and is provided on the upper electrode 130. However, the size of the conductor electrode 140 is set so as not to contact the lower electrode 120 so that the lower electrode 120 is in a floating state. The conductor electrode 140 serves as a connection terminal of the semiconductor memory device 100, for example, by being electrically connected to another wiring in a layer above the semiconductor substrate 110. The conductor electrode 140 can be formed, for example, by using a metal material such as copper (Cu) or aluminum (Al).

[0087] Note that the semiconductor memory device 100 may have Figure 2A or Figure 2B The structure shown in . Figure 2A and Figure 2B Each of the longitudinal cross-sectional views schematically shows a structure in a modification of the semiconductor memory device 100 .

[0088] like Figure 2A As shown in , the conductor electrode 141 may be provided on the upper electrode 130 to fill the opening provided in the lower electrode 120. In other words, the conductor electrode 141 may be provided in such a manner that a portion of the conductor electrode 141 is embedded in the semiconductor substrate 110, rather than being provided on the surface of the semiconductor substrate 110. The material and the like configuring the conductor electrode 141 are substantially similar to those of the conductor electrode 140, and the description thereof is omitted here.

[0089] In addition, if Figure 2B As shown in , in the semiconductor memory device 100, the opening provided in the lower electrode 120 may be provided to expose the gate insulating film 121, and the ferroelectric film 131 may be provided to contact the gate insulating film 121. For example, the opening provided in the lower electrode 120 may make the lower electrode 120 recessed from the surface of the semiconductor substrate 110, and the ferroelectric film 131 and the upper electrode 130 may be formed in the recessed region of the lower electrode 120. Figure 2B In the semiconductor memory device 100 shown in FIG. 1 , the lower electrode 120 in a floating state is not exposed on the surface of the semiconductor substrate 110. Therefore, the conductor electrode 141 can be formed to have an arbitrary size without considering the possibility of contact with the lower electrode 120.

[0090] In the semiconductor memory device 100 according to the present embodiment, a voltage is applied to the ferroelectric film 131 of the ferroelectric capacitor and the gate insulating film 121 of the field effect transistor by applying a voltage V between the upper electrode 130 and the source or drain region 111. At this time, voltages inversely proportional to the ratio of the capacitance Cf of the ferroelectric capacitor and the gate capacitance Ci of the field effect transistor are applied to the ferroelectric film 131 and the gate insulating film 121, respectively. Specifically, a distributed voltage Vf (=V(Ci / (Ci+Cf)) is applied to the ferroelectric film 131, and a distributed voltage Vi (=V(Cf / (Ci+Cf)) is applied to the gate insulating film 121.

[0091] Here, the distributed voltage Vf applied to the ferroelectric film 131 depends on the coupling ratio (Ci / (Ci+Cf)) of the capacitance Cf of the ferroelectric capacitor and the gate capacitance Ci of the field effect transistor.

[0092] However, generally, the dielectric constant of the ferroelectric film 131 formed by using a ferroelectric material is higher than the dielectric constant of the gate insulating film 121 formed by using an insulating material. Therefore, in the case where the area of ​​the ferroelectric film 131 is the same as the area of ​​the gate insulating film 121, the capacitance Cf of the ferroelectric capacitor is greater than the gate capacitance Ci of the field effect transistor. In this case, most of the voltage V applied between the upper electrode 130 and the source or drain region 111 is distributed to the gate insulating film 121 of the field effect transistor.

[0093] In the semiconductor memory device 100 according to the present embodiment, the field effect transistor and the ferroelectric capacitor are arranged in the opening provided in the semiconductor substrate 110, and the ferroelectric capacitor is arranged on the field effect transistor. In this case, in the field effect transistor, the channel is formed three-dimensionally across multiple surfaces. By doing so, in the field effect transistor, compared with a planar field effect transistor (a field effect transistor in which a gate insulating film and a gate electrode are stacked in parallel on a semiconductor substrate) having the same area formed on a semiconductor substrate, the effective length of the channel can be increased, and thus the gate capacitance Ci can be increased.

[0094] Therefore, the semiconductor memory device 100 according to the present embodiment can increase the gate capacitance Ci of the field effect transistor without increasing the size of the unit cell, and can increase the distributed voltage to be applied to the ferroelectric film 131. Therefore, the semiconductor memory device 100 can apply a sufficient voltage to the ferroelectric film 131, and thus the stability of the operation of writing and erasing information can be improved.

[0095] (1.2. Design example)

[0096] Next, refer to Figures 3 to 4C A specific design example of the semiconductor memory device 100 according to the present embodiment is described. Figure 3It is limited Figure 1 A longitudinal cross-sectional view showing the dimensions of each structure of the semiconductor memory device 100 shown in FIG. FIG. 4A to FIG. 4C is a graph showing a range in which the semiconductor memory device 100 according to the present embodiment has satisfactory characteristics.

[0097] like Figure 3 As shown in , it is assumed that the depth of the opening formed in the semiconductor substrate 110 is hi, the depth of the opening formed in the lower electrode 120 is hf, the film thickness of the gate insulating film 121 is di, and the film thickness of the ferroelectric film 131 is df. In addition, it is assumed that the relative dielectric constant of the gate insulating film 121 is εi, and the relative dielectric constant of the ferroelectric film 131 is εf. In this case, by controlling the dimensions of each structure to meet the following conditions, the characteristics of the semiconductor memory device 100 can be made more satisfactory.

[0098] Specifically, in the case where the voltage Vprg is applied to the upper electrode 130 , the voltage Vf applied to the ferroelectric film 131 and the voltage Vi applied to the gate insulating film 121 are expressed by the formulas described below.

[0099] Vf=Vprg / (1+Cf / Ci)

[0100] =Vprg / (1+(εf·hf·di) / (εi·hi·df))

[0101] Vi=Vprg-Vf

[0102] Therefore, the electric field Ef generated in the ferroelectric film 131 and the electric field Ei generated in the gate insulating film 121 are expressed by the formulas described below.

[0103] Ef=Vprg / df·(1+(εf·hf·di) / (εi·hi·df))

[0104] Ei=di·(Vprg-Vf)

[0105] Here, in order to obtain sufficient residual polarization in the ferroelectric film 131, Ef>2MV / cm is desirable. In addition, in order not to generate dielectric breakdown in the gate insulating film 121, Ei<10MV / cm is desirable.

[0106] Specifically, in the case where the ferroelectric film 131 is formed by using a ferroelectric material including Hf, the amount of residual polarization of the ferroelectric film 131 with respect to an electric field is, for example, Figure 4A as shown in the curve graph. Figure 4A The ferroelectric film 131 has an area of ​​7500 μm. 2The film thickness of the ferroelectric film 131 is 12 nm and the ferroelectric film 131 is formed by using HfOx to form a ferroelectric capacitor. Figure 4A From the graph shown in , it is clear that in order to sufficiently saturate the polarization hysteresis loop of the ferroelectric film 131 and obtain a sufficiently large remanent polarization, it is preferred that the electric field generated in the ferroelectric film 131 is greater than 2 MV / cm.

[0107] In addition, in the case where the gate insulating film 121 includes a silicon oxide film, the lifetime length of the gate insulating film 121 with respect to the electric field is as follows: Figure 4B as shown in the curve graph. Figure 4B The measurement is shown in which the area of ​​the gate insulating film 121 is 5000 μm 2 , the result of dielectric breakdown of a field effect transistor in which the film thickness of the gate insulating film 121 is 12 μm and the gate insulating film 121 includes a silicon oxide film. Figure 4B From the graph shown in , it is clear that in order to achieve a lifetime of 1.00E+05 or more (actually, a sufficient lifetime) of the gate insulating film 121, the electric field generated in the gate insulating film 121 is preferably less than 10 MV / cm.

[0108] Therefore, by appropriately designing hf, hi, df, and di in such a manner that Ef and Ei described above satisfy the preferred ranges, the characteristics of the semiconductor memory device 100 can be made satisfactory.

[0109] For example, in the case where the ferroelectric film 131 is formed by using a ferroelectric material including Hf, εf is about 20, and in the case where the gate insulating film 121 is formed by using a silicon oxide film, εi is about 3.9. Here, assuming that the film thickness of the gate insulating film 121 is 1 nm and Vprg is 3.5 V, the appropriate ratio of hf and hi and the appropriate film thickness df of the ferroelectric film 131 fall within Figure 4C within the range shown in . Figure 4C is a graph showing the combination of the ratio of hf / hi and the film thickness df of the ferroelectric film 131. Figure 4C By adjusting the ratio of hf to hi in the black region and the film thickness df of the ferroelectric film 131 , the semiconductor memory device 100 can have more suitable characteristics.

[0110] (1.3. Manufacturing method)

[0111] Next, refer to FIG. 5A to FIG. 5G A method of manufacturing the semiconductor memory device 100 according to the present embodiment is described. FIG. 5A to FIG. 5G 1 and 2 are schematic longitudinal cross-sectional views each showing one process of the method for manufacturing the semiconductor memory device 100 according to the present embodiment.

[0112] First, if Figure 5A As shown in FIG. 1 , in order to form an opening 120A in a semiconductor substrate 110, patterning is performed on the semiconductor substrate 110 formed by using silicon to form a mask 151. For example, the mask 151 may be a simple photoresist substance, or may also be a stack of a hard mask such as an oxide film or a nitride film and a photoresist.

[0113] Next, if Figure 5B As shown in FIG, by etching the semiconductor substrate 110 using the mask 151, an opening 120A corresponding to the pattern of the mask 151 is formed in the semiconductor substrate 110. Note that ion implantation may be performed so that a channel implant of a first conductivity type (e.g., p-type) that adjusts the threshold voltage of the field effect transistor is formed in the semiconductor substrate 110, and then the opening 120A is formed.

[0114] Next, if Figure 5C As shown in , a gate insulating film 121, a lower electrode 120, a ferroelectric film 131, and an upper electrode 130 are sequentially formed on a semiconductor substrate 110. Specifically, the gate insulating film 121, the lower electrode 120, the ferroelectric film 131, and the upper electrode 130 are sequentially formed on the semiconductor substrate 110 along the outer shape of the semiconductor substrate 110 provided with the opening 120A, so that the opening 120A provided in the semiconductor substrate 110 is filled. The film thickness of each of the gate insulating film 121, the lower electrode 120, the ferroelectric film 131, and the upper electrode 130 can be adjusted to have a value within the above range that allows the semiconductor memory device 100 to have satisfactory characteristics. As materials for configuring the gate insulating film 121, the lower electrode 120, the ferroelectric film 131, and the upper electrode 130, the above materials can be appropriately used.

[0115] Next, if Figure 5D As shown in , chemical mechanical polishing (CMP) or the like is performed to polish the surface side of the semiconductor substrate 110 where the opening 120A is formed until the surface of the semiconductor substrate 110 is exposed. Note that polishing such as CMP may also be continued after the surface of the semiconductor substrate 110 has been exposed. Figure 5D In the embodiment, the surface height of the semiconductor substrate 110 after polishing matches the surface heights of the gate insulating film 121, the lower electrode 120, the ferroelectric film 131, and the upper electrode 130. However, for example, the center of the upper electrode 130 may be recessed.

[0116] Next, if Figure 5EAs shown in , ion implantation is performed to introduce impurities of the second conductivity type (e.g., n-type impurities) into the semiconductor substrate 110 on both sides of the opening 120A, and thus form the source or drain region 111. Note that the impurities of the second conductivity type may be introduced into the semiconductor substrate 110 via a resist mask or the like, or may not be introduced via a resist mask or the like. Note that the process of forming the source or drain region 111 may be performed immediately before or after the opening 120A is formed in the semiconductor substrate 110.

[0117] Next, if Fig. 5F As shown in FIG. 1 , after the conductor electrode layer 140A is formed on the semiconductor substrate 110 by using sputtering or the like, a mask 152 is provided on the conductor electrode layer 140A. As a material configuring the conductor electrode layer 140A, the above-described materials can be appropriately used.

[0118] Afterwards, if Figure 5G As shown in , patterning is performed on the conductor electrode layer 140A by using a mask 152 , thereby forming a conductor electrode 140 on the upper electrode 130 , and the size of the conductor electrode 140 is designed not to contact the lower electrode 120 .

[0119] By performing the above-described processes, the semiconductor memory device 100 according to the present embodiment can be manufactured.

[0120] (1.4. Application examples)

[0121] Next, refer to Figures 6 to 9 An application example of the semiconductor memory device 100 according to the present embodiment is described. Figure 6 is a plan view schematically showing a planar configuration of a semiconductor device 1 in which a plurality of semiconductor memory devices 100 according to the present embodiment are arranged in a matrix shape, and Figure 7 is schematically shown along Figure 6 1 is a longitudinal sectional view of a section taken along line A-AA of the semiconductor device 1 shown in FIG.

[0122] like Figure 6 and Figure 7 As shown in , the semiconductor device 1 is a storage device that can store a large amount of information in a plurality of semiconductor storage devices 100 arranged in a matrix shape. In addition, by using the plurality of semiconductor storage devices 100 arranged in a matrix shape as synapses and using the resistance value of the channel of the semiconductor storage device 100 as the weight of the synapse, the semiconductor device 1 can also be used as a multiplication accumulator that can perform a multiplication accumulation operation.

[0123] In the semiconductor device 1, in a first direction (for example, facing Figure 6The wiring 21 extending in the left and right directions (in the left and right directions) is electrically connected to one of the source or drain regions 111 of the semiconductor memory device 100 via the contact 31. The conductor electrode 140 is arranged in a second direction orthogonal to the first direction (for example, facing Figure 6 In addition, the wiring 23 is electrically connected to the other of the source or drain regions 111 of the semiconductor memory device 100 via the contact 32. In addition, the semiconductor memory device 100 is provided in the semiconductor substrate 110 at each intersection of the wiring 21 and the conductor electrode 140 that are orthogonal to each other. Note that the semiconductor memory devices 100 adjacent in the second direction are electrically insulated from each other by the element isolation layer 10 having an insulating property.

[0124] Here, further reference Figure 8 An operation of writing or reading information in the semiconductor device 1 is described. Figure 8 yes Figure 6 and Figure 7 An equivalent circuit diagram of the semiconductor device 1 is shown in FIG.

[0125] like Figure 8 As shown in , for example, in the case of writing information, the semiconductor device 1 provides a potential difference between a predetermined wiring 21 and a predetermined conductor electrode 140 to selectively apply the potential difference to the semiconductor memory device 100, which exists at the intersection of the predetermined wiring 21 and the predetermined conductor electrode 140. By doing so, the semiconductor device 1 can selectively reverse the remanent polarization of the ferroelectric film 131 of the semiconductor memory device 100 existing at the intersection of the wiring 21 and the conductor electrode 140, and information can be written to the semiconductor memory device 100.

[0126] On the other hand, in the case of reading information, for example, the semiconductor device 1 applies a voltage to the conductor electrode 140 to put the field effect transistor of the semiconductor memory device 100 into an on state, and then measures the current flowing between the wiring 21 and the wiring 23 (that is, the current flowing between the source and the drain of the semiconductor memory device 100). By doing so, the semiconductor device 1 can obtain the current value corresponding to the residual polarization direction of the ferroelectric film 131 from each semiconductor memory device 100, and therefore, the semiconductor device 1 can read information from each semiconductor memory device 100.

[0127] Notice, Figure 7 The cross-sectional structure of the semiconductor device 1 shown in FIG. 1 may be Fig. 9 The cross-sectional structure shown in . Fig. 9 1 is a longitudinal cross-sectional view schematically showing a cross-sectional structure of a modified example of the semiconductor device 1. Fig. 9 As shown in , the conductor electrode 140 may be electrically connected to the upper electrode 130 via a contact 33 .

[0128] The semiconductor memory device 100 according to the first embodiment of the present disclosure has been described above in detail.

[0129] <2. Second Embodiment>

[0130] (2.1. Structure example)

[0131] Next, refer to Fig.10 A structural example of a semiconductor memory device according to a second embodiment of the present disclosure is described. Fig.10 is a perspective view schematically showing a structural example of the semiconductor memory device according to the present embodiment.

[0132] like Fig.10 As shown in , the semiconductor memory device 200 includes a semiconductor substrate 210, an insulating layer 212, a semiconductor layer 211, a source or drain region 215, a gate insulating film 214, a gate electrode 213, a lower electrode 217, a ferroelectric film 220, an upper electrode 221 and a conductor electrode 222.

[0133] The semiconductor memory device 200 is a FeRAM having an MFMIS structure, in which a ferroelectric capacitor is connected in series to a gate electrode of a field effect transistor. Specifically, the field effect transistor is a fin-type field effect transistor including a semiconductor layer 211, a source or drain region 215, a gate insulating film 214, and a gate electrode 213. The ferroelectric capacitor includes a lower electrode 217, a ferroelectric film 220, and an upper electrode 221. The lower electrode 120 is electrically connected to the gate electrode 213 of the field effect transistor, so the ferroelectric capacitor is connected in series to the gate of the field effect transistor.

[0134] The semiconductor substrate 210 is a substrate constructed by using a semiconductor material. The semiconductor substrate 210 may be a silicon substrate, or may be a silicon-on-insulator (SOI) substrate in which an insulating film of SiO2 or the like is maintained in the silicon substrate. Alternatively, the semiconductor substrate 210 may be a substrate including another element semiconductor such as germanium, or may be a substrate including a compound semiconductor such as gallium arsenide (GaAs), gallium nitride (GaN), or silicon carbide (SiC). In addition, the semiconductor substrate 210 may be a substrate in which a semiconductor layer is stacked on a substrate including quartz, sapphire, resin, metal, or the like.

[0135] The insulating layer 212 is constructed by using an insulating material and is provided on the semiconductor substrate 210. The insulating layer 212 electrically insulates various structures such as the gate electrode 213 and the lower electrode 217 provided on the semiconductor substrate 210 from the semiconductor substrate 210. In addition, in the case where a plurality of semiconductor layers 211 are provided, the insulating layer 212 electrically insulates the semiconductor layers 211 protrudingly provided on the semiconductor substrate 210 from each other. The insulating layer 212 can be made of, for example, silicon oxide (SiO x ), Silicon Nitride (SiN x ) or an insulating nitride oxide such as silicon oxynitride (SiON).

[0136] The semiconductor layer 211 is constructed by using a semiconductor material, and is protrudingly provided on the semiconductor substrate 210 to pierce the insulating layer 212. Specifically, the semiconductor layer 211 may be protrudingly provided on the semiconductor substrate 210 to have a rectangular parallelepiped shape extending in one direction. For example, the semiconductor layer 211 may have a flat plate shape, and may be protrudingly provided on the semiconductor substrate 210 in such a manner that the main surface (the surface having the largest area) of the flat plate shape is perpendicular to the semiconductor substrate 210. In addition, in the case where a plurality of semiconductor layers 211 are provided, each of the plurality of semiconductor layers 211 may be protrudingly provided on the semiconductor substrate 210 in such a manner that the extending directions are parallel to each other. For example, the semiconductor layer 211 may be formed by using silicon, may be formed by using another element semiconductor such as germanium, or may be formed by using a compound semiconductor such as gallium arsenide (GaAs), gallium nitride (GaN), or silicon carbide (SiC).

[0137] The gate insulating film 214 is constructed by using an insulating material and is provided to cover the upper surface and the side surface of the semiconductor layer 211 across a direction orthogonal to the extension direction of the semiconductor layer 211. The gate insulating film 214 may be provided to be sandwiched between the gate electrode 213 and the semiconductor layer 211, wherein the gate electrode 213 is provided to span the semiconductor layer 211 across a direction orthogonal to the extension direction of the semiconductor layer 211. The gate insulating film 214 may be formed by using an insulating material known as a gate insulating film of a field effect transistor. For example, the gate insulating film 214 may be formed by using silicon oxide (SiO x ), Silicon Nitride (SiN x ) or an insulating nitride oxide such as silicon oxynitride (SiON) to form the gate insulating film 214.

[0138] The gate electrode 213 is constructed by using a conductive material, and is arranged to span the semiconductor layer 211 across the gate insulating film 214 in a direction orthogonal to the extension direction of the semiconductor layer 211. For example, the gate electrode 213 may be provided on the semiconductor layer 211 to extend in a direction orthogonal to the extension direction of the semiconductor layer 211 and intersect with the semiconductor layer 211. In addition, in the case where a plurality of semiconductor layers 211 are provided, the gate electrode 213 may be provided on a plurality of semiconductor layers 211 provided to extend in parallel to each other to extend in a direction orthogonal to the extension direction of the semiconductor layer 211, and thus the gate electrode 213 may be continuously provided to span the plurality of semiconductor layers 211. For example, the gate electrode 213 may be formed by using polycrystalline silicon or the like, or may be formed by using a metal, an alloy, or a metal compound.

[0139] Note that the gate insulating film 214 and the gate electrode 213 are provided approximately in the center of the semiconductor layer 211 in such a manner that the semiconductor layer 211 protrudes from both sides of the gate electrode 213. By doing so, a source or drain region 215 described later can be formed in the semiconductor layer 211 protruding from both sides of the gate electrode 213.

[0140] The source or drain region 215 is a region of the second conductivity type (e.g., an n-type region) formed in the semiconductor layer 211. Specifically, the source or drain region 215 is provided in a region protruding on both sides of the gate electrode 213 in the semiconductor layer 211. For example, the source or drain region 215 may be provided by introducing an impurity of the second conductivity type (e.g., an n-type impurity such as phosphorus or arsenic) into a region protruding from both sides of the gate electrode 213 of the semiconductor layer 211.

[0141] Note that any one of the source or drain regions 215 provided in the semiconductor layer 211 can be used as a source region and any one can be used as a drain region. The source region and the drain region can be arbitrarily changed according to wiring connected to the corresponding source or drain region 215.

[0142] The lower electrode 217 is constructed by using a conductive material, and is provided on the insulating layer 212 to be electrically connected to the gate electrode 213. Specifically, the lower electrode 217 may be provided to be electrically connected to the gate electrode 213 and to extend in a direction orthogonal to the extension direction of the semiconductor layer 211. For example, the lower electrode 217 may be formed by using polysilicon or the like, or may be formed by using a metal, an alloy, or a metal compound. Note that if the lower electrode 217 is electrically connected to the gate electrode 213 and is in an independent potential state (referred to as a floating state), the position where the lower electrode 217 is formed is not particularly limited.

[0143] The ferroelectric film 220 is configured by using a ferroelectric material, and is disposed on the lower electrode 217. Specifically, the ferroelectric film 220 is disposed on the lower electrode 217, and the lower electrode 217 extends on the insulating layer 212.

[0144] The ferroelectric film 220 is formed by using a ferroelectric material that is automatically polarized and has a residual polarization direction that can be controlled by an external electric field. The ferroelectric film 220 is formed by using a ferroelectric material including hafnium (Hf), zirconium (Zr), silicon (Si), or oxygen (O). For example, the ferroelectric film 220 can be formed by using a ferroelectric material having a perovskite structure such as lead zirconate titanate (Pb(Zr, Ti)O3: PZT) or strontium bismuth tantalate (SrBi2Ta2O9: SBT). In addition, the ferroelectric film 220 can be formed by treating a ferroelectric material including HfO x 、ZrO x or HfZrO x The ferroelectric film 220 may be a ferroelectric film obtained by performing heat treatment or the like on a film of a high dielectric material such as HfO to modify the film, or may be a ferroelectric film obtained by introducing atoms such as lanthanum (La), silicon (Si), or gadolinium (Gd) into a film including the above high dielectric material to modify the film. In addition, the ferroelectric film 220 may be formed to have a single layer, or may be formed to have a multilayer. For example, the ferroelectric film 220 may be a film including HfO x A single layer of ferroelectric material such as .

[0145] The upper electrode 221 is configured by using a conductive material and is disposed on the ferroelectric film 220. For example, the upper electrode 221 may be formed by using a metal such as titanium (Ti) or tungsten (W) or a metal compound such as titanium nitride (TiN) or tantalum nitride (TaN).

[0146] The conductor electrode 222 is constructed by using a conductive material, and is provided on the upper electrode 221. Specifically, the conductor electrode 222 may be provided on the upper electrode 221 to extend in the extension direction of the semiconductor layer 211. In other words, the conductor electrode 222 and the lower electrode 217 may be provided to be orthogonal to each other, and the ferroelectric film 220 and the upper electrode 221 may be provided to be sandwiched between the conductor electrode 222 and the lower electrode 217 at the intersection of the conductor electrode 222 and the lower electrode 217. For example, the conductor electrode 222 may be formed by using a metal material such as copper (Cu) or aluminum (Al), for example.

[0147] Note that the semiconductor memory device 200 may have FIG. 11A to FIG. 11D The structure shown in . FIG. 11A to FIG. 11D Each of the longitudinal cross-sectional views schematically shows a structure in a modification of the semiconductor memory device 200 .

[0148] like Fig.11A As shown in , a plurality of semiconductor layers 211 may be provided. Note that the upper limit of the number of semiconductor layers 211 is not particularly limited. In this case, each of the plurality of semiconductor layers 211 may be provided protrudingly on the semiconductor substrate 210 in such a manner that the extension directions are parallel to each other. In addition, the gate electrode 213 may be provided on the plurality of semiconductor layers 211 provided to extend in parallel to each other so as to extend in a direction orthogonal to the extension direction of the semiconductor layers 211, and thus the gate electrode 213 may be provided continuously to span the plurality of semiconductor layers 211. The gate insulating film 214 may be provided to be sandwiched between the semiconductor layer 211 and the gate electrode 213.

[0149] In addition, if Fig. 11B As shown in , the upper electrode 221 may also be provided in a wiring shape extending in the extending direction of the semiconductor layer 211 similarly to the conductor electrode 222. In this case, the upper electrode 221 may be formed in the same shape as that of the conductor electrode 222, and wiring may be formed by the conductor electrode 222 and the upper electrode 221.

[0150] In addition, if Fig. 11C and Fig.11D As shown in FIG. 2 , the ferroelectric film 220 and the upper electrode 221 may be arranged to be sequentially stacked on the gate electrode 216. Fig. 11C As shown in FIG. 1 , the region where the ferroelectric film 220 and the upper electrode 221 are stacked may be the entire upper surface of the gate electrode 216, or as shown in FIG. Fig.11D As shown in , it may be a part of the upper surface of the gate electrode 216. In addition, the conductor electrode 222 not shown may be stacked on the upper electrode 221. In this case, the semiconductor memory device 200 can further reduce the plane area per unit cell. Note that in Fig. 11C and Fig.11D In the semiconductor memory device 200 shown in FIG. 1 , the ferroelectric film 220 is directly stacked on the gate electrode 216 , and thus the lower electrode 217 can be omitted.

[0151] In the semiconductor memory device 200 according to the present embodiment, the field effect transistor is set as a so-called fin-type transistor. In this case, in the field effect transistor, a channel is three-dimensionally formed across multiple surfaces, side surfaces, and upper surfaces of the semiconductor layer 211. By doing so, in the field effect transistor, compared with a planar field effect transistor having the same area formed on a semiconductor substrate (a field effect transistor in which a gate insulating film and a gate electrode are stacked in parallel on a semiconductor substrate), the area of ​​the channel can be increased, and thus the gate capacitance Ci can be increased.

[0152] Therefore, the semiconductor memory device 200 according to the present disclosure can increase the gate capacitance Ci of the field effect transistor without increasing the size of the unit cell, and can increase the distributed voltage to be applied to the ferroelectric film 220. Therefore, the semiconductor memory device 200 can apply a sufficient voltage to the ferroelectric film 220, and thus can improve the stability of the operation of writing and erasing information.

[0153] (2.2. Design example)

[0154] Next, refer to Fig.12 A specific design example of the semiconductor memory device 200 according to the present embodiment is described. Fig.12 It is limited Fig.10 2 is a perspective view showing the dimensions of each structure of the semiconductor memory device 200 shown in FIG.

[0155] like Fig.12 As shown in , it is assumed that the width in the direction orthogonal to the extension direction of the semiconductor layer 211 is px, the height of the semiconductor layer 211 from the surface of the insulating layer 212 is py, and the number of semiconductor layers 211 is N. It is assumed that the width of the conductor electrode 222 in the direction orthogonal to the extension direction of the semiconductor layer 211 is qx, and the gate electrode 213 and the lower electrode 217 have the same width in the extension direction of the semiconductor layer 211. It is assumed that the film thickness of the gate insulating film 214 is di, the film thickness of the ferroelectric film 220 is df, the relative dielectric constant of the gate insulating film 214 is εi, and the relative dielectric constant of the ferroelectric film 220 is εf. In this case, by controlling the dimensions of each structure to meet the following conditions, the characteristics of the semiconductor memory device 200 can be made more satisfactory.

[0156] Specifically, in the case where the voltage Vprg is applied to the conductor electrode 222, the electric field Ef generated in the ferroelectric film 220 and the electric field Ei generated in the gate insulating film 214 are expressed by the formulas described below.

[0157] Ef=Vprg / df·(1+(εf·qx·di) / (εi·(px+2py)·N·df))

[0158] Ei=di·(Vprg-Vf)

[0159] Here, as described above, in order to obtain sufficient residual polarization in the ferroelectric film 220, Ef>2MV / cm is desirable. In addition, in order not to cause dielectric breakdown in the gate insulating film 214, Ei<10MV / cm is desirable.

[0160] Therefore, by appropriately designing px, py, N, qx, df, and di in such a manner that the above-mentioned Ef and Ei satisfy the preferred ranges, the characteristics of the semiconductor memory device 200 can be made satisfactory.

[0161] (2.3. Application examples)

[0162] Next, refer to Fig.13 An application example of the semiconductor memory device 200 according to the present embodiment is described. Fig.13 2 is a plan view schematically showing a plan configuration of the semiconductor device 2 in which a plurality of semiconductor memory devices 200 according to the present embodiment are arranged in a matrix shape.

[0163] like Fig.13 As shown in , the semiconductor device 2 is a storage device that can store a large amount of information in a plurality of semiconductor storage devices 200 arranged in a matrix shape. In addition, by using the plurality of semiconductor storage devices 200 arranged in a matrix shape as synapses and using the resistance value of the channel of the semiconductor storage device 200 as the weight of the synapse, the semiconductor device 2 can also be used as a multiplication accumulator that can perform multiplication and accumulation operations.

[0164] In the semiconductor device 2, in a first direction (for example, facing Fig.13 The wiring 251 extending in the left and right directions (in the direction of the left and right directions) is electrically connected to one of the source or drain regions 215 of the semiconductor memory device 200 via the contact 255. In a second direction orthogonal to the first direction (for example, facing Fig.13 The wiring 252 extending in the upward and downward directions (in the upward and downward directions) is electrically connected to the other of the source or drain regions 111 of the semiconductor memory device 200 via the contact 256. In addition, the conductor electrode 222 is arranged in a second direction (for example, facing the first direction) orthogonal to the first direction. Fig.13 In addition, the ferroelectric capacitor is provided at the intersection of the conductor electrode 222 and the gate electrode 213 and the lower electrode 217 which are orthogonal to each other.

[0165] Here, an operation of writing or reading information in the semiconductor device 2 is described.

[0166] For example, in the case of writing information, the semiconductor device 2 provides a potential difference between a predetermined wiring 251 and a predetermined conductor electrode 222 to selectively apply the potential difference to a ferroelectric capacitor provided at an intersection of the conductor electrode 222 and the gate electrode 213 and the lower electrode 217. By doing so, the semiconductor device 2 can selectively reverse the residual polarization of the ferroelectric film 220 of the predetermined ferroelectric capacitor, and information can be written to the semiconductor memory device 200.

[0167] On the other hand, in the case of reading information, for example, the semiconductor device 2 applies a voltage to the conductor electrode 222 to put the field effect transistor of the semiconductor memory device 200 into an on state, and then measures the current flowing between the wiring 251 and the wiring 252 (that is, the current flowing between the source and the drain of the semiconductor memory device 200). By doing so, the semiconductor device 2 can obtain the current value corresponding to the residual polarization direction of the ferroelectric film 220 from each semiconductor memory device 200, and thus the semiconductor device 2 can read information from each semiconductor memory device 200.

[0168] The semiconductor memory device 200 according to the second embodiment of the present disclosure has been described above in detail.

[0169] <3. Third embodiment>

[0170] (3.1. Structure example)

[0171] Next, refer to Fig.14 A structural example of a semiconductor memory device according to a third embodiment of the present disclosure is described. Fig.14 is a longitudinal cross-sectional view schematically showing a structural example of the semiconductor memory device according to the present embodiment.

[0172] like Fig.14 As shown in the figure, the semiconductor storage device 300 includes a semiconductor substrate 320, an element isolation layer 321, a source or drain region 301, an LDD region 301A, a gate insulating film 302, a gate electrode 303, a first side wall 311, a lower electrode 304, a ferroelectric film 305, an upper electrode 306, a second side wall 312 and a conductor electrode 307.

[0173] The semiconductor memory device 300 is a FeRAM having an MFMIS structure, in which a ferroelectric capacitor is connected in series to a gate electrode of a field effect transistor. Specifically, the field effect transistor includes a semiconductor substrate 320, a source or drain region 301, an LDD region 301A, a gate insulating film 302, and a gate electrode 303, and the ferroelectric capacitor includes a lower electrode 304, a ferroelectric film 305, and an upper electrode 306. The ferroelectric capacitor is connected in series to the gate of the field effect transistor through the lower electrode 304.

[0174] The semiconductor substrate 320 is a substrate constructed by using a semiconductor material. In the region where the semiconductor memory device 300 is formed, an impurity of the first conductivity type (for example, a p-type impurity such as boron or aluminum) is introduced into the semiconductor substrate 320. The semiconductor substrate 320 may be a silicon substrate, or may be a silicon-on-insulator (SOI) substrate in which an insulating film of SiO2 or the like is maintained in the silicon substrate. Alternatively, the semiconductor substrate 320 may be a substrate including another element semiconductor such as germanium, or may be a substrate including a compound semiconductor such as gallium arsenide (GaAs), gallium nitride (GaN) or silicon carbide (SiC). In addition, the semiconductor substrate 320 may be a substrate in which a semiconductor layer is stacked on a substrate including quartz, sapphire, resin, metal, etc.

[0175] The element isolation layer 321 is constructed by using an insulating material, and electrically insulates the semiconductor memory devices 300 provided in the semiconductor substrate 320 from each other. For example, the element isolation layer 321 may be formed by using silicon oxide (SiO x ), Silicon Nitride (SiN x ) or an insulating nitride oxide such as silicon oxynitride (SiON) to form the element isolation layer 321.

[0176] Specifically, a portion of the semiconductor substrate 320 in a predetermined region may be removed by performing etching or the like using shallow trench isolation (STI) and replacing the semiconductor substrate 320 with silicon oxide (SiO x ) is used to fill the opening formed by etching or the like to form the element isolation layer 321. In addition, the element isolation layer 321 can be formed by performing thermal oxidation on the semiconductor substrate 320 in a predetermined region by using local oxidation of silicon (LOCOS).

[0177] The source or drain region 301 is a region of the second conductivity type (e.g., an n-type region) formed in the semiconductor substrate 320. Specifically, the source or drain region 301 is provided by introducing impurities of the second conductivity type (e.g., n-type impurities such as phosphorus or arsenic) into the semiconductor substrate 320 on both sides of the gate electrode 213.

[0178] Note that a lightly doped drain (LDD) region 301A may be formed in the semiconductor substrate 320 between the source or drain region 301 and the gate electrode 303, wherein the LDD region 301A is of a second conductive type (e.g., n-type) that is the same type as that of the source or drain region 301 and has a concentration of impurities of the conductive type that is lower than the concentration of the source or drain region 301.

[0179] Note that either of the source or drain regions 301 provided on both sides of the gate electrode 303 may be used as a source region and either may be used as a drain region. The source region and the drain region may be arbitrarily changed depending on wiring connected to the corresponding source or drain region 301.

[0180] The gate insulating film 302 is configured by using an insulating material and is provided on the semiconductor substrate 320. The gate insulating film 302 can be formed by using an insulating material known as a gate insulating film of a field effect transistor. For example, the gate insulating film 302 can be formed by using silicon oxide (SiO x ), Silicon Nitride (SiN x ) or an insulating nitride oxide such as silicon oxynitride (SiON) to form the gate insulating film 302.

[0181] The gate electrode 303 is configured by using a conductive material, and is provided on the gate insulating film 302. For example, the gate electrode 303 may be provided on the semiconductor layer 211 to extend in a direction orthogonal to the extension direction of the semiconductor layer 211 and to intersect with the semiconductor layer 211. For example, the gate electrode 303 may be formed by using polycrystalline silicon or the like, or may be formed by using a metal, an alloy, or a metal compound.

[0182] The first side wall 311 is configured by using an insulating material and is provided as a side wall on the side surface of the gate electrode 303. Specifically, the first side wall 311 can be formed by uniformly forming an insulating film in a region including the gate electrode 303 and performing vertical anisotropic etching on the insulating film. For example, the first side wall 311 can be formed by using silicon oxide (SiO x ), Silicon Nitride (SiN x ) or an insulating nitride oxide such as silicon oxynitride (SiON) to be formed to have a single layer or a multilayer.

[0183] When the second conductive type impurities are introduced into the semiconductor substrate 320, the first sidewall 311 shields the second conductive type impurities and controls the positional relationship between the gate electrode 303 and the source or drain region 301 in a self-aligned manner. By using the first sidewall 311, the introduction of the second conductive type impurities into the semiconductor substrate 320 can be gradually controlled, and thus, the LDD region 301A can be formed between the source or drain region 301 and the gate electrode 303 in a self-aligned manner.

[0184] The lower electrode 304 is configured by using a conductive material, and is provided on the gate electrode 303. For example, the lower electrode 304 may be formed by using polysilicon or the like, or may be formed by using a metal, an alloy, or a metal compound.

[0185] The ferroelectric film 305 is constructed by using a ferroelectric material and is disposed on the lower electrode 304. The ferroelectric film 305 is formed by using a ferroelectric material that is automatically polarized and has a residual polarization direction that can be controlled by an external electric field. Specifically, the ferroelectric film 305 is formed by using a ferroelectric material including hafnium (Hf), zirconium (Zr), silicon (Si), or oxygen (O). For example, the ferroelectric film 305 can be formed by using a ferroelectric material having a perovskite structure such as lead zirconate titanate (Pb(Zr, Ti)O3: PZT) or strontium bismuth tantalate (SrBi2Ta2O9: SBT). In addition, the ferroelectric film 305 can be formed by treating a ferroelectric material including HfO x 、ZrO x or HfZrO x The ferroelectric film 305 may be a ferroelectric film obtained by performing heat treatment or the like on a film of a high dielectric material such as HfO to modify the film, or may be a ferroelectric film obtained by introducing atoms such as lanthanum (La), silicon (Si), or gadolinium (Gd) into a film including the above high dielectric material to modify the film. In addition, the ferroelectric film 305 may be formed to have a single layer, or may be formed to have a multilayer. For example, the ferroelectric film 305 may be a film including HfO x A single layer of ferroelectric material such as .

[0186] The upper electrode 306 is configured by using a conductive material, and is provided on the ferroelectric film 305. For example, the upper electrode 306 can be formed by using a metal such as titanium (Ti) or tungsten (W), or a metal compound such as titanium nitride (TiN) or tantalum nitride (TaN).

[0187] Here, the lower electrode 304 , the ferroelectric film 305 , and the upper electrode 306 are arranged in the same planar shape, and the second side wall 312 is provided on the side surface of the stack of the lower electrode 304 , the ferroelectric film 305 , and the upper electrode 306 .

[0188] The second side wall 312 is configured by using an insulating material and is provided as a side wall on the side surface of the stack of the lower electrode 304, the ferroelectric film 305, and the upper electrode 306. Specifically, the second side wall 312 can be formed by uniformly forming an insulating film on the stack of the lower electrode 304, the ferroelectric film 305, and the upper electrode 306 and performing vertical anisotropic etching on the insulating film. For example, the second side wall 312 can be formed by using silicon oxide (SiO x ), Silicon Nitride (SiN x ) or an insulating nitride oxide such as silicon oxynitride (SiON) to be formed to have a single layer or a multilayer.

[0189] Here, the plane area occupied by the stack of the lower electrode 304, the ferroelectric film 305, and the upper electrode 306, and the second side wall 312 may be substantially equal to the plane area of ​​the upper surface of the gate electrode 303. As described later, in the semiconductor memory device 300, first, etching is performed to form the stack of the lower electrode 304, the ferroelectric film 305, and the upper electrode 306, and the second side wall 312, and then etching is performed by using the stack and the second side wall 312 as a mask, thereby forming the gate electrode 303. By doing so, in the semiconductor memory device 300, the stack of the lower electrode 304, the ferroelectric film 305, and the upper electrode 306, the second side wall 312, the gate electrode 303, and the first side wall 311 can be formed in a self-aligned manner.

[0190] The conductor electrode 307 is configured by using a conductive material, and is provided on the upper electrode 306. The conductor electrode 307 serves as a connection terminal of the semiconductor memory device 300, for example, by being electrically connected to another wiring not shown. The conductor electrode 307 can be formed, for example, by using a metal material such as titanium (Ti), tungsten (W), copper (Cu), or aluminum (Al).

[0191] In the semiconductor memory device 300 according to the present embodiment, the field effect transistor is set as a planar transistor, and the ferroelectric capacitor is set on the gate electrode of the field effect transistor together with the second side wall 312. In this case, the area of ​​the ferroelectric film 305 of the ferroelectric capacitor is slightly smaller than the area of ​​the gate insulating film 302 of the field effect transistor by the width of the second side wall 312. By doing so, in the semiconductor memory device 300, the gate capacitance Ci of the field effect transistor can be greater than the capacitance Cf of the ferroelectric capacitor.

[0192] Therefore, the semiconductor memory device 300 according to the present embodiment can increase the gate capacitance Ci of the field effect transistor without increasing the size of the unit cell, and can increase the distributed voltage to be applied to the ferroelectric film 305. Therefore, the semiconductor memory device 300 can apply a sufficient voltage to the ferroelectric film 305, and thus can improve the stability of the operation of writing and erasing information.

[0193] (3.2. Design example)

[0194] Next, refer to Fig.15 A specific design example of the semiconductor memory device 300 according to the present embodiment is described. Fig.15 It is limited Fig.14 A longitudinal cross-sectional view showing the dimensions of each structure of the semiconductor memory device 300 shown in FIG.

[0195] like Fig.15As shown in , it is assumed that the width of the gate electrode 303 in the direction in which the source or drain region 301 is set (also referred to as the channel direction) is Px, and the length of the gate electrode 303 in the direction orthogonal to the channel direction is Py. It is assumed that the length of the source or drain region 301 in the direction orthogonal to the channel direction is Qy, and the width of the second side wall 312 is X. In addition, it is assumed that the film thickness of the gate insulating film 302 is di, the film thickness of the ferroelectric film 305 is df, the relative dielectric constant of the gate insulating film 302 is εi, and the relative dielectric constant of the ferroelectric film 305 is εf. In this case, by controlling the dimensions of each structure to meet the following conditions, the characteristics of the semiconductor memory device 300 can be made more satisfactory.

[0196] Specifically, in the case where a voltage Vprg is applied to the conductor electrode 307, an electric field Ef generated in the ferroelectric film 305 and an electric field Ei generated in the gate insulating film 302 are expressed by the formulas described below.

[0197] Ef=Vprg / df·(1+(εf·di) / (εi·df)·(Px-2X)·(Qy-2X) / (Px·Py))

[0198] Ei=di·(Vprg-Vf)

[0199] Here, as described above, in order to obtain sufficient residual polarization in the ferroelectric film 305, Ef>2MV / cm is desirable. In addition, in order not to cause dielectric breakdown in the gate insulating film 302, Ei<10MV / cm is desirable.

[0200] Therefore, by appropriately designing Px, Py, Qy, X, df, and di in such a manner that the above-mentioned Ef and Ei satisfy the preferred ranges, the characteristics of the semiconductor memory device 300 can be made satisfactory.

[0201] (3.3. Manufacturing method)

[0202] Next, refer to FIG. 16A to FIG. 16E A method of manufacturing the semiconductor memory device 300 according to the present embodiment is described. FIG. 16A to FIG. 16E 2 are schematic longitudinal cross-sectional views each showing one process of the method for manufacturing the semiconductor memory device 300 according to the present embodiment.

[0203] First, if Fig.16AAs shown in FIG. 3 , a gate insulating film 302, a gate electrode 303, a lower electrode 304, a ferroelectric film 305, and an upper electrode 306 are uniformly formed on a semiconductor substrate 320 in which an element isolation layer 321 is formed. In addition, patterning is performed to form a mask 331 on the upper electrode 306 for forming a ferroelectric capacitor. For example, the mask 331 may be a simple photoresist substance, or may be a stack of a hard mask such as an oxide film or a nitride film and a photoresist.

[0204] Next, if Fig. 16B As shown in the figure, the lower electrode 304, the ferroelectric film 305 and the upper electrode 306 are simultaneously etched by using a mask 331, thereby forming a ferroelectric capacitor (i.e., a stack of the lower electrode 304, the ferroelectric film 305 and the upper electrode 306) having a size corresponding to the pattern of the mask 331.

[0205] Next, if Fig. 16C As shown in FIG. 3 , an insulating film is uniformly formed on the stack of the lower electrode 304, the ferroelectric film 305, and the upper electrode 306, and then etching back is performed on the entire surface. Thus, the second side wall 312 is formed.

[0206] Next, if Fig.16D As shown in FIG, the gate electrode 303 is etched by using the stack of the lower electrode 304, the ferroelectric film 305 and the upper electrode 306 and the second side wall 312 as a mask. By doing so, there is no need to separately set a mask for performing patterning to form the gate electrode 303, so the manufacturing cost of the semiconductor memory device 300 can be reduced.

[0207] Afterwards, if Fig.16E As shown in , ion implantation is performed to introduce impurities of the second conductivity type (eg, n-type impurities) into the semiconductor substrate 320, thereby forming a source or drain region 301. Note that Fig.16E As shown in FIG. 1 , by forming the first sidewall 311 , the LDD region 301A can be formed between the gate electrode 303 and the source or drain region 301 in a self-aligned manner.

[0208] By performing the above-described processes, the semiconductor memory device 300 according to the present embodiment can be manufactured.

[0209] (3.4. Modification)

[0210] In addition, reference Figures 17 to 19 A modification example of the semiconductor memory device 300 according to the present embodiment is described. Figures 17 to 19 Each of the longitudinal cross-sectional views schematically shows a structure in a modification of the semiconductor memory device 300 .

[0211] like Fig.17As shown in FIG, a ferroelectric capacitor including a lower electrode 304, a ferroelectric film 305, and an upper electrode 306 can be connected in series to a gate electrode 303 of a field effect transistor via a conductor electrode 323. Similar to the above-mentioned conductor electrode 307, the conductor electrode 323 can be formed, for example, by using a metal material such as titanium (Ti), tungsten (W), copper (Cu), or aluminum (Al).

[0212] exist Fig.17 In the structure of the semiconductor memory device 300 shown in , by controlling the dimensions of each structure to satisfy the following conditions, the characteristics of the semiconductor memory device 300 can be made more satisfactory.

[0213] Specifically, it is assumed that the width of the gate electrode 303 in the direction in which the source or drain region 301 is set (also referred to as the channel direction) is Px, and the length of the source or drain region 301 is Py. It is assumed that the width of the ferroelectric capacitor (i.e., the stack of the lower electrode 304, the ferroelectric film 305, and the upper electrode 306) in the channel direction is Qx, and the length of the ferroelectric capacitor in the direction orthogonal to the channel direction is Qy. In addition, it is assumed that the film thickness of the gate insulating film 302 is di, the film thickness of the ferroelectric film 305 is df, the relative dielectric constant of the gate insulating film 302 is εi, and the relative dielectric constant of the ferroelectric film 305 is εf.

[0214] In this case and in the case where the voltage Vprg is applied to the upper electrode 306, the electric field Ef generated in the ferroelectric film 305 and the electric field Ei generated in the gate insulating film 302 are expressed by the formulas described below.

[0215] Ef=Vprg / df·(1+(εf·di) / (εi·df)·(Qx·Qy) / (Px·Py))

[0216] Ei=di·(Vprg-Vf)

[0217] Here, as described above, in order to obtain sufficient residual polarization in the ferroelectric film 305, Ef>2MV / cm is desirable. In addition, in order not to cause dielectric breakdown in the gate insulating film 302, Ei<10MV / cm is desirable.

[0218] Therefore, by appropriately designing Px, Py, Qy, Qx, df, and di in such a manner that the above-mentioned Ef and Ei satisfy the preferred ranges, the characteristics of the semiconductor memory device 300 can be made satisfactory.

[0219] In addition, if Fig.18 As shown in , the ferroelectric capacitor may have a structure in which the ferroelectric film 305 and the upper electrode 306 are embedded in the lower electrode 304 by using a damascene process, rather than a stack of the lower electrode 304, the ferroelectric film 305, and the upper electrode 306. Fig.18 The structure of the semiconductor memory device 300 shown in FIG. Fig.17 The structure of the semiconductor memory device 300 shown in FIG. 1 is different in the structure of the ferroelectric capacitor.

[0220] exist Fig.18 In the structure of the semiconductor memory device 300 shown in , by controlling the dimensions of each structure to satisfy the following conditions, the characteristics of the semiconductor memory device 300 can be made more satisfactory.

[0221] Specifically, it is assumed that the width of the gate electrode 303 in the direction in which the source or drain region 301 is set (also referred to as the channel direction) is Px, and the length of the source or drain region 301 is Py. It is assumed that the width of the ferroelectric capacitor in the channel direction is Qx, and the length of the ferroelectric capacitor in the direction orthogonal to the channel direction is Qy. In addition, it is assumed that the film thickness of the gate insulating film 302 is di, the film thickness of the ferroelectric film 305 is df, the relative dielectric constant of the gate insulating film 302 is εi, and the relative dielectric constant of the ferroelectric film 305 is εf. In addition, it is assumed that the height of the lower electrode 304 (i.e., the height of the ferroelectric capacitor) is hf, and the thickness of the lower electrode 304 is Tf.

[0222] In this case and in the case where the voltage Vprg is applied to the upper electrode 306, the electric field Ef generated in the ferroelectric film 305 and the electric field Ei generated in the gate insulating film 302 are expressed by the formulas described below.

[0223] Ef=Vprg / df·(1+(εf·di) / (εi·df)·Sf / Si)

[0224] Ei=di·(Vprg-Vf)

[0225] in

[0226] Sf=2(hf-Tf-df)·(Qx+Qy-2Tf-2df)+(Qx-2df-2hf)·(Qy-2df-2hf)

[0227] Si=Px·Py

[0228] Here, as described above, in order to obtain sufficient residual polarization in the ferroelectric film 305, Ef>2MV / cm is desirable. In addition, in order not to cause dielectric breakdown in the gate insulating film 302, Ei<10MV / cm is desirable.

[0229] Therefore, by appropriately designing Px, Py, Qy, Qx, Tf, hf, df, and di in such a manner that the above-mentioned Ef and Ei satisfy the preferred ranges, the characteristics of the semiconductor memory device 300 can be made satisfactory.

[0230] In addition, if Fig.19 As shown in , the lower electrode 304 can be omitted from the semiconductor memory device 300 . Fig.19 The structure of the semiconductor memory device 300 shown in FIG. Fig.18 The structure of the semiconductor memory device 300 shown in FIG. 1 is different in that the ferroelectric capacitor includes a conductor electrode 323 , a ferroelectric film 305 , and an upper electrode 306 .

[0231] exist Fig.19 In the structure of the semiconductor memory device 300 shown in , by controlling the dimensions of each structure to satisfy the following conditions, the characteristics of the semiconductor memory device 300 can be made more satisfactory.

[0232] Specifically, it is assumed that the width of the gate electrode 303 in the direction in which the source or drain region 301 is set (also referred to as the channel direction) is Px, and the length of the source or drain region 301 is Py. It is assumed that the width of the ferroelectric capacitor in the channel direction is Qx, and the length of the ferroelectric capacitor in the direction orthogonal to the channel direction is Qy. In addition, it is assumed that the film thickness of the gate insulating film 302 is di, the film thickness of the ferroelectric film 305 is df, the relative dielectric constant of the gate insulating film 302 is εi, and the relative dielectric constant of the ferroelectric film 305 is εf. In addition, it is assumed that the height of the ferroelectric film 305 (i.e., the height of the ferroelectric capacitor) is hf, and the width of the conductor electrode 323 is Cx.

[0233] In this case and in the case where the voltage Vprg is applied to the upper electrode 306, the electric field Ef generated in the ferroelectric film 305 and the electric field Ei generated in the gate insulating film 302 are expressed by the formulas described below.

[0234] Ef=Vprg / df·(1+(εf·di) / (εi·df)·Sf / Si)

[0235] Ei=di·(Vprg-Vf)

[0236] in

[0237] Sf=2(hf-df)·(Qx+Qy-2df)+Cx·Cx

[0238] Si=Px·Py

[0239] Here, as described above, in order to obtain sufficient residual polarization in the ferroelectric film 305, Ef>2MV / cm is desirable. In addition, in order not to cause dielectric breakdown in the gate insulating film 302, Ei<10MV / cm is desirable.

[0240] Therefore, by appropriately designing Px, Py, Qy, Qx, hf, Cx, df, and di in such a manner that the above-mentioned Ef and Ei satisfy the preferred ranges, the characteristics of the semiconductor memory device 300 can be made satisfactory.

[0241] Note that Figures 17 to 19 In the figure, the plane shape of the conductor electrode 323 is approximately a square, but the plane shape of the conductor electrode 323 may be any one of a rectangle, a circle, or an ellipse.

[0242] The semiconductor memory device 300 according to the third embodiment of the present disclosure has been described in detail above. Similar to the semiconductor memory devices 100 and 200, the semiconductor memory device 300 according to the third embodiment of the present disclosure can be applied to a memory device that can store a large amount of information by arranging the semiconductor memory device 300 in a matrix shape. In addition, by using the semiconductor memory device 300 as a synapse, the semiconductor memory device 300 can be applied to a multiplication accumulator that can perform a multiplication-accumulation operation.

[0243] The preferred embodiments of the present disclosure have been described in detail above with reference to the accompanying drawings, but the technical scope of the present disclosure is not limited to the above examples. It is clear that a person of ordinary skill in the technical field of the present disclosure may think of various variations or modifications without departing from the technical ideas described in the claims, and it should be understood that these variations or modifications fall within the technical scope of the present disclosure.

[0244] In addition, the effects described herein are only exemplary or illustrative, not restrictive. In other words, in addition to or instead of the above effects, the technology according to the present disclosure may exhibit other effects that are clear to those skilled in the art according to the description provided herein.

[0245] Note that the configurations described below also fall within the technical scope of the present disclosure.

[0246] (1) A semiconductor storage device comprising:

[0247] transistors; and

[0248] a ferroelectric capacitor formed by sandwiching a ferroelectric material between a pair of conductive materials, one of the pair of conductive materials being electrically connected to a gate electrode of the transistor,

[0249] The channel of the transistor is formed three-dimensionally across multiple surfaces.

[0250] (2) The semiconductor memory device according to (1) above, wherein an electric field applied to the ferroelectric material of the ferroelectric capacitor is greater than 2 MV / cm.

[0251] (3) The semiconductor memory device according to (1) or (2) above, wherein an electric field applied to a gate insulating film of the transistor is less than 10 MV / m.

[0252] (4) The semiconductor memory device according to any one of (1) to (3) above, wherein the transistor includes a semiconductor substrate, a gate insulating film, and the gate electrode, the gate insulating film being provided along an inner shape of an opening formed in the semiconductor substrate, the gate electrode being provided on the gate insulating film so as to fill the opening of the semiconductor substrate, and

[0253] The ferroelectric capacitor includes a ferroelectric film, the ferroelectric film being disposed along an inner shape of an opening formed in the gate electrode, and an upper electrode being disposed on the gate electrode to fill the opening of the gate electrode.

[0254] (5) The semiconductor memory device according to (4) above, wherein the semiconductor substrate is of the first conductivity type, and

[0255] A source or drain region of a second conductivity type is provided on one side of a surface of the semiconductor substrate provided with the opening, the second conductivity type being different from the first conductivity type.

[0256] (6) The semiconductor memory device according to (5) above, wherein the opening of the semiconductor substrate is provided to a region deeper than the source or drain region.

[0257] (7) A semiconductor storage device according to any one of (1) to (3) above, wherein the transistor includes a semiconductor layer, a gate insulating film and the gate electrode, the semiconductor layer is protrudingly arranged on the substrate to extend in one direction, the gate insulating film is arranged to span the semiconductor layer in a direction orthogonal to the extension direction of the semiconductor layer to cover the upper surface and side surface of the semiconductor layer, and the gate electrode is arranged to span the semiconductor layer through the gate insulating film.

[0258] (8) A semiconductor storage device according to (7) above, wherein the ferroelectric capacitor includes one of the pair of conductive materials stacked on the gate electrode, the ferroelectric material stacked on the one of the pair of conductive materials, and the other of the pair of conductive materials stacked on the ferroelectric material.

[0259] (9) The semiconductor memory device according to (8) above, wherein the plurality of semiconductor layers are arranged in parallel with each other, and

[0260] The gate electrode is continuously disposed across the plurality of semiconductor layers.

[0261] (10) A multiplication accumulator, comprising:

[0262] transistors; and

[0263] a ferroelectric capacitor formed by sandwiching a ferroelectric material between a pair of conductive materials, one of the pair of conductive materials being electrically connected to a gate electrode of the transistor,

[0264] The channel of the transistor is formed three-dimensionally across multiple surfaces.

[0265] (11) A semiconductor storage device comprising:

[0266] transistors; and

[0267] a ferroelectric capacitor formed by sandwiching a ferroelectric material between a pair of conductive materials, one of the pair of conductive materials being electrically connected to a gate electrode of the transistor,

[0268] wherein the pair of conductive materials and the ferroelectric material are stacked parallel to the upper surface of the gate electrode to provide the ferroelectric capacitor on the gate electrode, and

[0269] A planar area of ​​the ferroelectric capacitor is smaller than a planar area of ​​an upper surface of the gate electrode.

[0270] (12) The semiconductor memory device according to (11) above, wherein an electric field applied to the ferroelectric material of the ferroelectric capacitor is greater than 2 MV / cm.

[0271] (13) The semiconductor memory device according to (11) or (12) above, wherein an electric field applied to a gate insulating film of the transistor is less than 10 MV / m.

[0272] (14) A semiconductor memory device according to any one of (11) to (13) above or later, wherein a side wall insulating film is provided on a side surface of the ferroelectric capacitor, and

[0273] The planar area occupied by the ferroelectric capacitor and the sidewall insulating film is substantially equal to the planar area of ​​the upper surface of the gate electrode.

[0274] (15) The semiconductor memory device according to any one of (11) to (13) above, wherein a contact electrode is provided between the ferroelectric capacitor and the gate electrode.

[0275] (16) A semiconductor storage device according to the above (15), wherein the ferroelectric capacitor includes the contact electrode or one of the pair of conductive materials stacked on the contact electrode, the ferroelectric material stacked on the one of the pair of conductive materials, and the other of the pair of conductive materials filling an opening formed in the ferroelectric material.

[0276] (17) A multiplication accumulator, comprising:

[0277] transistors; and

[0278] a ferroelectric capacitor formed by sandwiching a ferroelectric material between a pair of conductive materials, one of the pair of conductive materials being electrically connected to a gate electrode of the transistor,

[0279] wherein the pair of conductive materials and the ferroelectric material are stacked parallel to the upper surface of the gate electrode to provide the ferroelectric capacitor on the gate electrode, and

[0280] A planar area of ​​the ferroelectric capacitor is smaller than a planar area of ​​an upper surface of the gate electrode.

[0281] Reference Symbols List

[0282] 1 Semiconductor devices

[0283] 10 Component isolation layer

[0284] 21, 23 Wiring

[0285] 31, 32, 33 Contacts

[0286] 100 Semiconductor storage device

[0287] 110 Semiconductor substrate

[0288] 111 Source or drain region

[0289] 120 Lower electrode

[0290] 121 Gate insulating film

[0291] 130 Upper electrode

[0292] 131 Ferroelectric film

[0293] 140 Conductor Electrode

Claims

1. A semiconductor storage device, comprising: A transistor comprising a semiconductor substrate, a gate insulating film having a film thickness of di, and a lower electrode, wherein the gate insulating film is arranged along an inner shape of an opening having a depth of hi formed in the semiconductor substrate, and the lower electrode is arranged on the gate insulating film to fill the opening of the semiconductor substrate; and A ferroelectric capacitor comprising a ferroelectric film having a film thickness of df and the lower electrode, the ferroelectric film being arranged along the inner shape of an opening having a depth of hf formed in the lower electrode, the ferroelectric capacitor being formed by sandwiching the ferroelectric film between an upper electrode and the lower electrode, wherein The channel of the transistor is formed three-dimensionally across a plurality of surfaces, and By appropriately designing hf, hi, df and di, the electric field applied to the ferroelectric film of the ferroelectric capacitor is set to be greater than 2MV / cm taking into account the polarization-electric field measurement results of the ferroelectric capacitor, and the electric field applied to the gate insulating film of the transistor is set to be less than 10MV / m taking into account the life of the gate insulating film.

2. The semiconductor memory device according to claim 1, wherein: The semiconductor substrate is of a first conductivity type, and A source or drain region of a second conductivity type is provided on one side of a surface of the semiconductor substrate provided with the opening, the second conductivity type being different from the first conductivity type.

3. The semiconductor memory device according to claim 2, wherein: The opening of the semiconductor substrate is provided to a region deeper than the source or drain region.

4. A multiplication accumulator, comprising: A transistor comprising a semiconductor substrate, a gate insulating film having a film thickness of di, and a lower electrode, wherein the gate insulating film is arranged along an inner shape of an opening having a depth of hi formed in the semiconductor substrate, and the lower electrode is arranged on the gate insulating film to fill the opening of the semiconductor substrate; and A ferroelectric capacitor comprising a ferroelectric film having a film thickness of df and the lower electrode, the ferroelectric film being arranged along the inner shape of an opening having a depth of hf formed in the lower electrode, the ferroelectric capacitor being formed by sandwiching the ferroelectric film between an upper electrode and the lower electrode, wherein The channel of the transistor is formed three-dimensionally across a plurality of surfaces, and By appropriately designing hf, hi, df and di, the electric field applied to the ferroelectric film of the ferroelectric capacitor is set to be greater than 2MV / cm taking into account the polarization-electric field measurement results of the ferroelectric capacitor, and the electric field applied to the gate insulating film of the transistor is set to be less than 10MV / m taking into account the life of the gate insulating film.

5. A semiconductor storage device, comprising: A transistor, comprising a gate electrode, a gate insulating film with a film thickness of di, and a source or drain region, wherein the width of the gate electrode in a first direction in which the source or drain region is set is Px and the length of the gate electrode in a second direction orthogonal to the first direction is Py, and the length of the source or drain region in the second direction orthogonal to the first direction is Qy; and A ferroelectric capacitor, the ferroelectric capacitor comprising a ferroelectric film having a film thickness of df, the ferroelectric capacitor being formed by sandwiching the ferroelectric film between an upper electrode and a lower electrode, the lower electrode being electrically connected to a gate electrode of the transistor, wherein an insulating sidewall is provided on a side surface of the ferroelectric capacitor, and the width of the insulating sidewall is X, wherein The upper and lower electrodes and the ferroelectric film are stacked in parallel to an upper surface of the gate electrode to provide the ferroelectric capacitor on the gate electrode, The planar area of ​​the ferroelectric capacitor is smaller than the planar area of ​​the upper surface of the gate electrode, and By appropriately designing Px, Py, Qy, X, df and di, the electric field applied to the ferroelectric film of the ferroelectric capacitor is set to be greater than 2MV / cm in consideration of the polarization-electric field measurement results of the ferroelectric capacitor, and the electric field applied to the gate insulating film of the transistor is set to be less than 10MV / m in consideration of the life of the gate insulating film.

6. The semiconductor memory device according to claim 5, wherein: A planar area occupied by the ferroelectric capacitor and the insulating sidewall is substantially equal to a planar area of ​​an upper surface of the gate electrode.

7. The semiconductor memory device according to claim 5, wherein: A contact electrode is disposed between the ferroelectric capacitor and the gate electrode.

8. The semiconductor memory device according to claim 7, wherein: The ferroelectric capacitor includes the contact electrode or the lower electrode stacked on the contact electrode, the ferroelectric film stacked on the lower electrode, and the upper electrode filling an opening formed in the ferroelectric film.

9. A multiplication accumulator, comprising: A transistor, comprising a gate electrode, a gate insulating film with a film thickness of di, and a source or drain region, wherein the width of the gate electrode in a first direction in which the source or drain region is set is Px and the length of the gate electrode in a second direction orthogonal to the first direction is Py, and the length of the source or drain region in the second direction orthogonal to the first direction is Qy; and A ferroelectric capacitor, the ferroelectric capacitor comprising a ferroelectric film having a film thickness of df, the ferroelectric capacitor being formed by sandwiching the ferroelectric film between an upper electrode and a lower electrode, the lower electrode being electrically connected to a gate electrode of the transistor, wherein an insulating sidewall is provided on a side surface of the ferroelectric capacitor and has a width of X, wherein The upper and lower electrodes and the ferroelectric film are stacked in parallel to an upper surface of the gate electrode to provide the ferroelectric capacitor on the gate electrode, The planar area of ​​the ferroelectric capacitor is smaller than the planar area of ​​the upper surface of the gate electrode, and By appropriately designing Px, Py, Qy, X, df and di, the electric field applied to the ferroelectric film of the ferroelectric capacitor is set to be greater than 2MV / cm in consideration of the polarization-electric field measurement results of the ferroelectric capacitor, and the electric field applied to the gate insulating film of the transistor is set to be less than 10MV / m in consideration of the life of the gate insulating film.

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