Field effect transistor pair testing device and method

Abstract

The present application provides a field effect transistor pair test device and method, the device comprising: a field effect transistor pair selection circuit, connected to the field effect transistor pair; a detection circuit, connected to the field effect transistor pair selection circuit; a controller, respectively connected to the field effect transistor pair selection circuit and the detection circuit, for controlling the field effect transistor pair selection circuit and one of the field effect transistors in the field effect transistor pair to be turned on, and also for controlling the detection circuit to detect the turned-on field effect transistor. The test device provided by the present application is used to perform parameter testing on the field effect transistor pair, so that the test conditions of the two field effect transistors in the field effect transistor pair are the same, avoiding deviations caused by different test conditions and improving the accuracy of the test. At the same time, the user only needs to set the test conditions in advance to fully automatically perform parameter testing on the field effect transistor pair, effectively improving the test speed.

Description

Technical Field

[0001] The present application relates to the field of electronic component testing, and in particular to a field effect transistor pair testing device and method. Background Art

[0002] When designing the amplification of weak differential voltage signals, it is necessary to select two junction field-effect transistors with consistent characteristics as the input devices of the differential amplifier to effectively reduce nonlinear distortion and improve the common-mode rejection ratio.

[0003] During the mass production of field-effect transistor pairs, manufacturers can typically reduce their matching deviation to less than 10%. However, for higher amplifier design requirements, the two junction field-effect transistors must have a higher degree of matching. In this case, parameter testing of large quantities of junction field-effect transistor pairs is necessary to screen out devices with higher matching. The parameter testing process of junction field-effect transistor pairs requires testing dozens of operating points, and existing test equipment has a poor degree of automation, making the parameter testing process of junction field-effect transistor pairs extremely time-consuming. Summary of the Invention

[0004] The purpose of the embodiments of the present application is to provide a field effect transistor pair testing device and method to solve the problem that parameter testing of a junction field effect transistor pair takes a long time.

[0005] In a first aspect, an embodiment of the present invention provides a field effect transistor pair test device, comprising: a field effect transistor pair selection circuit connected to a field effect transistor pair; a detection circuit connected to the field effect transistor pair selection circuit; and a controller connected to the field effect transistor pair selection circuit and the detection circuit, respectively, for controlling the field effect transistor pair selection circuit and one of the field effect transistors in the field effect transistor pair to be turned on, and further for controlling the detection circuit to detect the turned-on field effect transistor.

[0006] In an optional embodiment, the field effect transistor pair selection circuit includes: a first relay, a second relay and a relay driver; one end of the relay driver is connected to the controller, and the other end is connected to the first relay and the second relay respectively; the first relay is respectively connected to the drains of the two field effect transistors of the field effect transistor pair; the second relay is respectively connected to the gates of the two field effect transistors of the field effect transistor pair.

[0007] In an optional embodiment, the detection circuit includes: a sampling resistor, an instrumentation amplifier, an analog-to-digital converter, a digital-to-analog converter and a programmable power supply module; one end of the sampling resistor is connected to the drains of the two field-effect transistors of the field-effect transistor pair via the first relay, and the other end is connected to the programmable power supply module; one end of the programmable power supply module is connected to the sampling resistor, and the other end is connected to the controller; the input end of the instrumentation amplifier is connected to both ends of the sampling resistor for detecting the voltage across the sampling resistor; the output end of the instrumentation amplifier is connected to the controller via the analog-to-digital converter; and the digital-to-analog converter is connected between the controller and the second relay.

[0008] In an optional embodiment, the device further includes: a host computer connected to the controller.

[0009] In an optional embodiment, the field effect transistor pair includes two junction field effect transistors, and both of the two junction field effect transistors are N-channel junction field effect transistors or P-channel junction field effect transistors.

[0010] By using the field-effect transistor pair testing device provided in this application to perform parameter testing on a field-effect transistor pair, the test conditions for both field-effect transistors in the field-effect transistor pair are identical, avoiding deviations caused by different test conditions and improving test accuracy. Furthermore, users only need to pre-set the test conditions to fully automatically perform parameter testing on the field-effect transistor pair, effectively increasing test speed.

[0011] In a second aspect, an embodiment of the present invention provides a field effect transistor pair testing method, which is applied to a controller of a field effect transistor pair testing device, wherein the controller is respectively connected to a field effect transistor pair selection circuit and a detection circuit. The method includes: controlling the field effect transistor pair selection circuit to sequentially turn on one field effect transistor in the field effect transistor pair and disconnect it from the other field effect transistor; and controlling the detection circuit to detect the turned-on field effect transistor.

[0012] In an optional embodiment, after controlling the detection circuit to detect the turned-on field effect transistor, the method includes: determining the matching degree of the field effect transistor pair according to the detection result.

[0013] In an optional embodiment, the field effect transistor pair selection circuit includes: a first relay, a second relay and a relay driver; one end of the relay driver is connected to the controller, and the other end is respectively connected to the first relay and the second relay; the first relay is respectively connected to the drains of the two field effect transistors of the field effect transistor pair; the second relay is respectively connected to the gates of the two field effect transistors of the field effect transistor pair; controlling the field effect transistor pair selection circuit to be turned on with one field effect transistor in the field effect transistor pair in turn and disconnected from the other field effect transistor, includes: controlling the relay driver to drive the first relay to be turned on with the drain of one field effect transistor in turn and disconnected from the drain of the other field effect transistor in turn, and driving the second relay to be turned on with the gate of the field effect transistor with the drain turned on in turn and disconnected from the gate of the other field effect transistor in turn.

[0014] In an optional embodiment, the detection circuit includes: a programmable power supply module, a digital-to-analog converter, a sampling resistor and an instrumentation amplifier. The controller is respectively connected to the programmable power supply module, the digital-to-analog converter and the instrumentation amplifier. The instrumentation amplifier is connected to both sides of the sampling resistor. The programmable power supply module is connected to the first relay through the sampling resistor, and the digital-to-analog converter is connected to the second relay. Controlling the detection circuit to detect the turned-on field effect transistor includes: controlling the programmable power supply module to input a fixed drain-source voltage to the drain of the turned-on field effect transistor; controlling the digital-to-analog converter to input a variable gate-source voltage to the gate of the turned-on field effect transistor; controlling the instrumentation amplifier to detect the voltage on both sides of the sampling resistor under different gate-source voltages; and determining the drain-source current of the turned-on field effect transistor based on the voltage on both sides of the sampling resistor.

[0015] In an optional embodiment, the detection circuit includes: a programmable power supply module, a digital-to-analog converter, a sampling resistor and an instrumentation amplifier, the controller is respectively connected to the programmable power supply module, the digital-to-analog converter and the instrumentation amplifier, the instrumentation amplifier is connected on both sides of the sampling resistor, the programmable power supply module is connected to the first relay through the sampling resistor, and the digital-to-analog converter is connected to the second relay, and the control of the detection circuit to detect the turned-on field effect transistor includes: controlling the digital-to-analog converter to input a fixed gate-source voltage to the gate of the turned-on field effect transistor; controlling the programmable power supply module to input a variable drain-source voltage to the drain of the turned-on field effect transistor; controlling the instrumentation amplifier to detect the voltage on both sides of the sampling resistor under different drain-source voltages; and determining the drain-source current of the turned-on field effect transistor based on the voltage on both sides of the sampling resistor.

[0016] By using the field-effect transistor pair testing method provided in this application to perform parameter testing on a field-effect transistor pair, the test conditions for both field-effect transistors in the field-effect transistor pair are identical, avoiding deviations caused by different test conditions and improving test accuracy. Furthermore, users only need to pre-set the test conditions to fully automatically perform parameter testing on the field-effect transistor pair, effectively increasing test speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 A structural block diagram of a field effect transistor pair testing device provided in an embodiment of the present application;

[0019] Figure 2 A structural block diagram of another field effect transistor pair testing device provided in an embodiment of the present application;

[0020] Figure 3 A flow chart of a field effect transistor pair testing method provided in an embodiment of the present application;

[0021] Figure 4 A schematic diagram of test results of a field effect transistor provided in an embodiment of the present application;

[0022] Figure 5 A schematic diagram of the transfer characteristic curve of a field effect transistor pair provided in an embodiment of the present application.

[0023] Icons: 100-field effect transistor pair test device; 101-field effect transistor pair selection circuit; 102-detection circuit; 103-controller; 1011-first relay; 1012-second relay; 1013-relay driver; 1021-sampling resistor; 1022-instrumentation amplifier; 1023-analog-to-digital converter; 1024-digital-to-analog converter; 1025-programmable power supply module; 104-host computer. DETAILED DESCRIPTION

[0024] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0025] When designing the amplification of weak differential voltage signals, it is necessary to select two junction field-effect transistors with consistent characteristics to form a junction field-effect transistor pair as the input device of the differential amplifier to effectively reduce nonlinear distortion and improve the common-mode rejection ratio.

[0026] In mass production of JFET pairs, manufacturers can typically reduce their matching deviation to less than 10%. However, for more demanding amplifier designs, even higher matching between the two JFETs is required. In this case, parameter testing of large batches of JFET pairs is necessary to select devices with higher matching.

[0027] Traditional JFET parameter testing methods are only suitable for testing the parameters of a single JFET and are not suitable for testing the parameters of a JFET pair. Furthermore, the JFET parameter testing process requires testing dozens of operating points, and existing test equipment has a low degree of automation, making the JFET parameter testing process extremely time-consuming. For JFET pairs, since both JFETs need to be measured, the required testing time also increases accordingly.

[0028] Based on this, an embodiment of the present application provides a field effect transistor pair testing device and testing method to solve the above problems.

[0029] See also Figure 1 , which is a block diagram of a field-effect transistor pair test device provided in an embodiment of the present application, includes a field-effect transistor pair test device 100, which may include a field-effect transistor pair selection circuit 101, a detection circuit 102, and a controller 103. The field-effect transistor pair selection circuit 101 is connected to the field-effect transistor pair. The detection circuit 102 is connected to the field-effect transistor pair selection circuit 101. The controller 103 is connected to the field-effect transistor pair selection circuit 101 and the detection circuit 102, respectively. The field-effect transistor pair test device 100 can perform parameter tests on the field-effect transistor pair.

[0030] The field-effect transistor pair consists of two field-effect transistors integrated in a single package. The two field-effect transistors are not connected to each other. The field-effect transistor pair provides six pins, corresponding to the drain, gate, and source of the two field-effect transistors. Field-effect transistors are divided into junction field-effect transistors and metal-oxide semiconductor field-effect transistors. Junction field-effect transistors can also be divided into N-channel junction field-effect transistors and P-channel junction field-effect transistors. This application does not limit the type of field-effect transistors in the field-effect transistor pair.

[0031] The controller 103 is connected to the field effect transistor pair selection circuit 101 and the detection circuit 102 respectively, and is used to control the field effect transistor pair selection circuit and one of the field effect transistors in the field effect transistor pair to be turned on, and is also used to control the detection circuit to detect the turned-on field effect transistor.

[0032] It should be noted that the controller 103 may be a single-chip microcomputer, integrated circuit chip, etc., having signal processing and control capabilities. For example, the processor may be a general-purpose processor, such as a central processing unit (CPU); it may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0033] Specifically, the FET pair selection circuit 101 can be connected to the FET pair. Based on a control signal from the controller 103, the FET pair selection circuit 101 selects one of the FETs in the FET pair and disconnects the other FET in the FET pair. That is, when testing the FET pair, only one of the two FETs in the FET pair is connected to the FET pair selection circuit 101 and is then connected to the detection circuit 102 for parameter testing; the other FET is disconnected from the FET pair selection circuit 101 and is not connected to the detection circuit 102.

[0034] As an optional implementation, see Figure 2 The field-effect transistor pair selection circuit 101 may include a first relay 1011, a second relay 1012, and a relay driver 1013. One end of the relay driver 1013 is connected to the controller 103, and the other end is connected to the first relay 1011 and the second relay 1012, respectively. The first relay 1011 is connected to the drains of the two field-effect transistors in the field-effect transistor pair. The second relay 1012 is connected to the gates of the two field-effect transistors in the field-effect transistor pair.

[0035] Specifically, for ease of explanation, the two field-effect transistors in the field-effect transistor pair are referred to as the first field-effect transistor and the second field-effect transistor. When testing the field-effect transistor pair, the first field-effect transistor is first parameter-tested. At this point, the controller 103 sends a control instruction to the relay driver 1013 to control the first relay 1011 to be conductive with the drain of the first field-effect transistor and disconnected from the drain of the second field-effect transistor; and to control the second relay 1012 to be conductive with the gate of the first field-effect transistor and disconnected from the gate of the second field-effect transistor. At this point, the first field-effect transistor is conductive with the detection circuit 102, and the detection circuit 102 performs a parameter test on the first field-effect transistor. After completing the test on the first field-effect transistor, the controller 103 sends a control instruction to the relay driver 1013 to similarly connect the second field-effect transistor to the detection circuit 102, disconnect the first field-effect transistor from the detection circuit 102, and perform a parameter test on the second field-effect transistor.

[0036] It should be noted that the structure of the field-effect transistor pair selection circuit 101 described above is only one embodiment, and the present application is not limited thereto. The field-effect transistor pair selection circuit 101 may also have other structures. For example, the field-effect transistor pair selection circuit 101 may only include a first relay and a second relay, and the controller may be directly connected to the first relay and the second relay to implement switching between the first field-effect transistor and the second field-effect transistor. Alternatively, switching circuits may be provided at the drain and gate of the first field-effect transistor and the second field-effect transistor, respectively, and the controller may control the switching circuits to switch different field-effect transistors on to implement testing of different field-effect transistors.

[0037] As an optional implementation, please continue to refer to Figure 2 The detection circuit 102 may include a sampling resistor 1021 , an instrumentation amplifier 1022 , an analog-to-digital converter 1023 , a digital-to-analog converter 1024 and a programmable power supply module 1025 .

[0038] One end of the sampling resistor 1021 is connected to the drains of the two field-effect transistors of the field-effect transistor pair via the first relay 1011, and the other end is connected to the programmable power supply module 1025. The programmable power supply module 1025 is connected to the sampling resistor 1021 at one end and to the controller 103 at the other end. The input of the instrumentation amplifier 1022 is connected to both ends of the sampling resistor 1021 for detecting the voltage across the sampling resistor 1021. The output of the instrumentation amplifier 1022 is connected to the controller 103. A digital-to-analog converter 1024 is connected between the controller 103 and the second relay 1012.

[0039] When performing parameter testing on a field effect transistor, the transfer characteristics of the field effect transistor can be obtained by changing the gate-source voltage while keeping the drain-source voltage fixed, measuring the drain-source current corresponding to different gate-source voltages; or by changing the drain-source voltage while keeping the gate-source voltage fixed, measuring the drain-source current corresponding to different drain-source voltages, and obtaining the output characteristics of the field effect transistor.

[0040] When testing a pair of field-effect transistors, controller 103 controls the output voltage of programmable power module 1025, which is then input to the drain of the field-effect transistor under test (i.e., the field-effect transistor that is conductive with detection circuit 102) via first relay 1011, serving as the drain-source voltage of the field-effect transistor under test. It is understood that programmable power module 1025 may alternatively be another power module, as long as it can adjust the desired drain-source voltage according to control signals from controller 103, and this application is not limited thereto.

[0041] Controller 103 transmits the digital code of the voltage signal to DAC 1024. DAC 1024 converts the digital signal into an analog signal as an output voltage. This output voltage, after selection by second relay 1012, is input to the gate of the field-effect transistor under test as the gate-source voltage of the field-effect transistor under test. It is understood that DAC 1024 can be any model, as long as it can output the required drain-source voltage in response to the control signal from controller 103, and this application is not limited thereto.

[0042] Instrumentation amplifier 1022 is connected across sampling resistor 1021 and is used to detect the voltage across sampling resistor 1021. Instrumentation amplifier 1022 converts the collected voltage signal into a digital signal via analog-to-digital converter 1023 and inputs it into controller 103. The resistance of sampling resistor 1021 is a known quantity. Based on the relationship between voltage and resistance, controller 103 can calculate the current flowing through sampling resistor 1021, which is the drain-source current of the field-effect transistor under test. It should be noted that in order to accurately measure the drain-source current, instrumentation amplifier 1022 must have high common-mode voltage rejection.

[0043] As an optional embodiment, the instrumentation amplifier 1022 may be an AD620 chip. It is understood that the instrumentation amplifier 1022 may also be replaced by other electronic devices such as a voltmeter that can measure the voltage across the sampling resistor, and this application does not impose any limitation on this.

[0044] It can be understood that when performing parameter testing of a pair of field-effect transistors, the controller 103 stores a program such as a preset gate voltage value, source-drain voltage value, test time, and relay switching. The controller 103 controls the analog-to-digital converter 1023 and the programmable power supply module 1025 to output a preset drain-source voltage and gate-source voltage, receives the voltage value collected by the instrumentation amplifier 1022, and calculates the corresponding drain-source current, thereby completing the parameter test of the pair of field-effect transistors. The user only needs to pre-set the test conditions (gate voltage value, source-drain voltage value, test time, and relay switching), and the field-effect transistor pair test device provided in the embodiment of the present application can automatically complete the parameter test of the pair of field-effect transistors.

[0045] The field effect transistor pair testing device 100 may further include an isolator, which may be provided between the controller 103 and any electronic device directly connected to the controller 103 .

[0046] As an optional embodiment, an isolator can be provided between the controller 103 and the detection circuit 102 to reduce interference from the digital circuits in the controller 103 on the detection circuit 102. When the controller 103 is in operation, the internal digital circuits may generate electromagnetic signals. If these electromagnetic signals are input into the detection circuit 102, they will cause electrical interference to the detection circuit 102, thereby affecting the test results of the field-effect transistor. Therefore, providing an isolator between the controller 103 and the detection circuit 102 can effectively reduce interference from the digital circuits in the controller 103 on the detection circuit 102.

[0047] Furthermore, when the detection circuit 102 includes a sampling resistor 1021, an instrumentation amplifier 1022, an analog-to-digital converter 1023, a digital-to-analog converter 1024, and a programmable power supply module 1025, an isolator can be respectively arranged between the controller 103 and the instrumentation amplifier 1022, the analog-to-digital converter 1023, the digital-to-analog converter 1024, and the programmable power supply module 1025 to reduce the interference of the digital circuit in the controller 103 on the above-mentioned electronic devices.

[0048] As an optional implementation, an isolator may also be provided between the controller 103 and the field effect transistor pair selection circuit 101 to reduce interference of the digital circuit in the controller 103 on the field effect transistor pair selection circuit 101 .

[0049] Furthermore, when the field effect transistor pair selection circuit 101 includes a first relay 1011 , a second relay 1012 and a relay driver 1013 , an isolator can be provided between the controller 103 and the relay driver 1013 to reduce interference of the digital circuit in the controller 103 on the relay driver 1013 .

[0050] As an optional embodiment, the isolator can be a HCPL-0661 chip. It is understood that the isolator can also be replaced by other electronic devices that can isolate electromagnetic interference, and this application does not limit this.

[0051] By using the field-effect transistor pair testing device provided in this application to perform parameter testing on a field-effect transistor pair, the test conditions for both field-effect transistors in the pair are identical, avoiding deviations caused by different test conditions and improving test accuracy. Furthermore, users only need to pre-set the test conditions to fully automatically perform parameter testing on the field-effect transistor pair, significantly accelerating testing speed.

[0052] As an optional embodiment, the field-effect transistor pair testing apparatus 100 further includes a host computer 104. The controller 103 transmits the drain-source voltage, gate-source voltage, and drain-source current to the host computer. Based on this data, the host computer plots the transfer characteristic curves and output characteristic curves of the first and second field-effect transistors in the field-effect transistor pair. By comparing the transfer characteristic curves and the output characteristic curves, the host computer selects field-effect transistor pairs with a high degree of matching.

[0053] By comparing the transfer characteristic curves or output characteristic curves of the two field effect transistors in a field effect transistor pair, the matching degree of the field effect transistor pair can be quickly determined, greatly improving the test efficiency.

[0054] Based on the same inventive concept, the present application also provides a field effect transistor pair test method. Figure 3 , Figure 3 This is a flow chart of a field effect transistor pair testing method provided in an embodiment of the present application. The field effect transistor pair testing method provided in an embodiment of the present application can be implemented using the field effect transistor pair testing device 100 described above. The field effect transistor pair testing method may include the following steps:

[0055] Step S201: Control the field effect transistor pair selection circuit to sequentially turn on one field effect transistor in the field effect transistor pair and disconnect the other field effect transistor.

[0056] Step S202: controlling the detection circuit to detect the turned-on field effect transistor.

[0057] The above process will be described in detail below with reference to examples.

[0058] Step S201: Control the field effect transistor pair selection circuit to sequentially turn on one field effect transistor in the field effect transistor pair and disconnect the other field effect transistor.

[0059] In the embodiment of the present application, the controller 103 controls the field effect transistor pair selection circuit 101 to switch the two field effect transistors in the field effect transistor pair. Specifically, this can be achieved through the following steps:

[0060] The control relay driver 1013 drives the first relay 1011 to be connected to the drain of one field effect transistor and disconnected from the drain of another field effect transistor in sequence, and drives the second relay 1012 to be connected to the gate of the field effect transistor with the drain connected and disconnected from the gate of the other field effect transistor in sequence.

[0061] To sequentially test the parameters of the first and second field-effect transistors in the field-effect transistor pair, controller 103 sends control instructions to relay driver 1013, controlling first relay 1011 to connect to the drain of the first field-effect transistor and disconnect it from the drain of the second field-effect transistor; and controlling second relay 1012 to connect to the gate of the first field-effect transistor and disconnect it from the gate of the second field-effect transistor. At this point, the first field-effect transistor is connected to detection circuit 102, and detection circuit 102 performs parameter testing on the first field-effect transistor.

[0062] After completing the test of the first field effect transistor, the controller 103 sends a control instruction to the relay driver 1013 to connect the second field effect transistor to the detection circuit 102 in the same way, and disconnect the connection between the first field effect transistor and the detection circuit 102 to perform parameter testing on the second field effect transistor.

[0063] Step S202: controlling the detection circuit to detect the turned-on field effect transistor.

[0064] In the embodiment of the present application, in order to detect the transfer characteristics and output characteristics of the field effect transistor, step S202 can be implemented in two ways.

[0065] As an optional implementation, step S202 may include the following steps:

[0066] In the first step, the programmable power supply module is controlled to input a fixed drain-source voltage to the drain of the conductive field effect transistor.

[0067] In the second step, the digital-to-analog converter is controlled to input a variable gate-source voltage to the gate of the conductive field effect transistor.

[0068] The third step is to control the instrumentation amplifier to detect the voltage on both sides of the sampling resistor at different gate-source voltages.

[0069] In the fourth step, the drain-source current of the turned-on field effect transistor is determined according to the voltage across the sampling resistor.

[0070] In the embodiment of the present application, by outputting a fixed drain-source voltage U DS , change different gate-source voltage U GS , collect the field effect transistor drain-source current I under different gate-source voltages DS , the transfer characteristics of the field effect transistor can be measured. For example, the drain-source voltage U DS Fixed at 9V, gate-source voltage U GS The gate-source voltage U is continuously changed from -1.1V to -0.1V at intervals of 0.1V, and each different gate-source voltage U is measured. GS Lower drain-source current I DS The value of drain-source voltage U DS Fixed to 7V, 5V, 3V, 1V, 0.8V, 0.6V, repeat the above steps to draw the drain-source voltage U DS The transfer characteristic curves of the field effect transistor are shown in Figure 1 for 7V, 5V, 3V, 1V, 0.8V, and 0.6V. Figure 4 , Figure 4 This is a schematic diagram of the test results of the field effect transistor provided in the embodiment of the present application. Figure 4 The left side is the transfer characteristic curve of the field effect transistor.

[0071] It should be noted that the above test condition is only one test condition provided in the embodiment of the present application. Different test conditions can be selected according to different test requirements, and the present application is not limited to this.

[0072] It can be understood that the specific method of controlling the programmable power supply module 1025, the digital-to-analog converter 1024 and the instrumentation amplifier 1022 corresponds to the contents of the aforementioned introduction to the programmable power supply module 1025, the digital-to-analog converter 1024 and the instrumentation amplifier 1022, so as to make the specification concise. The same or similar parts can be referenced to each other and will not be repeated here.

[0073] As another optional implementation, step S202 may include the following steps:

[0074] The first step is to control the digital-to-analog converter to input a fixed gate-source voltage to the gate of the conductive field effect transistor;

[0075] The second step is to control the programmable power supply module to input a variable drain-source voltage to the drain of the conductive field effect transistor;

[0076] The third step is to control the instrumentation amplifier to detect the voltage on both sides of the sampling resistor at different drain-source voltages;

[0077] In the fourth step, the drain-source current of the turned-on field effect transistor is determined according to the voltage across the sampling resistor.

[0078] In the embodiment of the present application, by outputting a fixed gate-source voltage UGS , change the drain-source voltage U DS , collect the field effect transistor drain-source current I under different gate-source voltages DS , the output characteristics of the field effect transistor can be measured. For example, the gate-source voltage U GS Fixed at -0.1V, drain-source voltage U DS Take 9V, 7V, 5V, 3V, 1V, 0.8V, and 0.6V respectively, and measure the voltage at each different drain-source voltage U DS Under this condition, the drain-source current I DS Then, the output characteristic curve is drawn. Then the gate-source voltage U GS The voltages are fixed at -1.1V to -0.1V and then changed continuously at intervals of 0.1V. Repeat the above steps to plot the voltage at a fixed drain-source voltage U. DS Output characteristic curve of field effect transistor under the condition of Figure 4 , Figure 4 This is a schematic diagram of the test results of the field effect transistor provided in the embodiment of the present application. Figure 4 The middle right side is the output characteristic curve of the field effect transistor.

[0079] It should be noted that the above test condition is only one test condition provided in the embodiment of the present application. Different test conditions can be selected according to different test requirements, and the present application is not limited to this.

[0080] It can be understood that the specific method of controlling the programmable power supply module 1025, the digital-to-analog converter 1024 and the instrumentation amplifier 1022 corresponds to the contents of the aforementioned introduction to the programmable power supply module 1025, the digital-to-analog converter 1024 and the instrumentation amplifier 1022, so as to make the specification concise. The same or similar parts can be referenced to each other and will not be repeated here.

[0081] It can be understood that the above two implementations are both testing methods for one field effect transistor in a field effect transistor pair. After completing the above test on one of the field effect transistors, the test is switched to the other field effect transistor in the field effect transistor pair and the above test method is repeated to obtain the transfer characteristic curves and output characteristic curves of the two field effect transistors in the field effect transistor pair.

[0082] By employing the field-effect transistor pair testing method provided in this application to perform parameter testing on a field-effect transistor pair, the test conditions for both field-effect transistors in the pair are identical, avoiding deviations caused by differing test conditions and improving test accuracy. Furthermore, users only need to pre-set the test conditions to fully automatically perform parameter testing on the field-effect transistor pair, significantly accelerating testing speed.

[0083] As an optional implementation, after step S202 , the field effect transistor pair testing method may further include: determining the matching degree of the field effect transistor pair according to the detection result.

[0084] In the embodiment of the present application, after obtaining the test parameters of the two field effect transistors in the field effect transistor pair, the matching degree of the field effect transistor pair can be determined by comparing the test parameters of the two field effect transistors.

[0085] See also Figure 5 , Figure 5 This is a schematic diagram of the transfer characteristic curve of the field effect transistor provided in the embodiment of the present application. Figure 5 As shown in the figure, six junction field effect transistor pairs were tested, and each figure represents the measurement results of the transfer characteristics of a junction field effect transistor pair. Among them, figure 123 represents one junction field effect transistor of the junction field effect transistor pair, and figure 567 represents one junction field effect transistor of the junction field effect transistor pair. According to the comparison of the transfer characteristic curves of the two junction field effect transistors, the I DS The maximum deviation can be used to determine the matching degree of the junction field effect transistor pair.

[0086] Figure 5 The transfer characteristics of the junction field effect transistors No. 1 and No. 2 are poorly matched, and their drain-source current I DS The maximum deviations are 6.51mA and 4.82mA respectively. The transfer characteristics of the junction field effect transistors No. 3 and No. 4 are generally matched. DS The maximum deviations are 0.19mA and 1.46mA respectively; the transfer characteristics of the No. 5 and No. 6 junction field effect transistors are the best matched, I DS The maximum deviation is less than 0.05mA.

[0087] By comparing the transfer characteristic curves or output characteristic curves of the two field effect transistors in a field effect transistor pair, the matching degree of the field effect transistor pair can be quickly determined, greatly improving the test efficiency.

[0088] In the embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interface, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0089] In addition, the units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0090] Furthermore, the functional modules in each embodiment of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0091] It should be noted that if the function is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0092] In this document, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any actual relationship or order between these entities or operations.

[0093] The above description is merely an embodiment of the present application and is not intended to limit the scope of protection of the present application. For those skilled in the art, various modifications and variations of the present application are possible. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A field effect transistor pair test device, characterized in that: include: A field effect transistor pair selection circuit is connected to the field effect transistor pair; A detection circuit connected to the field effect transistor pair selection circuit; a controller, connected to the field effect transistor pair selection circuit and the detection circuit, respectively, for controlling the field effect transistor pair selection circuit and one of the field effect transistors in the field effect transistor pair to be turned on, and further for controlling the detection circuit to detect the turned-on field effect transistor; Isolator; The field effect transistor pair selection circuit includes: a first relay, a second relay and a relay driver; one end of the relay driver is connected to the controller, and the other end is connected to the first relay and the second relay respectively; the first relay is respectively connected to the drain of the two field effect transistors of the field effect transistor pair; the second relay is respectively connected to the gate of the two field effect transistors of the field effect transistor pair; The detection circuit includes: a sampling resistor, an instrumentation amplifier, an analog-to-digital converter, a digital-to-analog converter, and a programmable power supply module; one end of the sampling resistor is connected to the drains of the two field-effect transistors of the field-effect transistor pair via the first relay, and the other end is connected to the programmable power supply module; one end of the programmable power supply module is connected to the sampling resistor, and the other end is connected to the controller; the input end of the instrumentation amplifier is connected to both ends of the sampling resistor for detecting the voltage across the sampling resistor; the output end of the instrumentation amplifier is connected to the controller via the analog-to-digital converter; and the digital-to-analog converter is connected between the controller and the second relay; Wherein, the isolator is respectively arranged between the controller and the instrumentation amplifier, the analog-to-digital converter, the digital-to-analog converter, and the programmable power supply module; or, the isolator is arranged between the controller and the relay driver.

2. The field effect transistor pair test device according to claim 1, characterized in that: The device further comprises: a host computer connected to the controller.

3. The field effect transistor pair test device according to claim 1, characterized in that: The field effect transistor pair includes two junction field effect transistors, and both of the two junction field effect transistors are N-channel junction field effect transistors or P-channel junction field effect transistors.

4. A field effect transistor pair testing method, applied to the controller of the field effect transistor pair testing device according to any one of claims 1 to 3, characterized in that: The controller is connected to the field effect transistor pair selection circuit and the detection circuit respectively, and the method includes: Controlling the field effect transistor pair selection circuit to sequentially connect to one field effect transistor in the field effect transistor pair and disconnect the other field effect transistor; The detection circuit is controlled to detect the turned-on field effect transistor.

5. The field effect transistor pair testing method according to claim 4, characterized in that: After controlling the detection circuit to detect the turned-on field effect transistor, the method includes: According to the detection result, the matching degree of the field effect transistor pair is determined.

6. The field effect transistor pair testing method according to claim 4, characterized in that: The field effect transistor pair selection circuit includes: a first relay, a second relay, and a relay driver; one end of the relay driver is connected to the controller, and the other end is connected to the first relay and the second relay respectively; the first relay is connected to the drain of the two field effect transistors of the field effect transistor pair; the second relay is connected to the gate of the two field effect transistors of the field effect transistor pair respectively; controlling the field effect transistor pair selection circuit to sequentially turn on one field effect transistor of the field effect transistor pair and disconnect the other field effect transistor, including: The relay driver is controlled to drive the first relay to be connected to the drain of one of the field effect transistors and disconnected from the drain of the other field effect transistor in sequence, and to drive the second relay to be connected to the gate of the field effect transistor with the drain connected and disconnected from the gate of the other field effect transistor in sequence.

7. The field effect transistor pair testing method according to claim 6, characterized in that: The detection circuit includes: a programmable power supply module, a digital-to-analog converter, a sampling resistor, and an instrumentation amplifier. The controller is connected to the programmable power supply module, the digital-to-analog converter, and the instrumentation amplifier respectively. The instrumentation amplifier is connected to both sides of the sampling resistor. The programmable power supply module is connected to the first relay through the sampling resistor, and the digital-to-analog converter is connected to the second relay. Controlling the detection circuit to detect the turned-on field effect transistor includes: Controlling the programmable power supply module to input a fixed drain-source voltage to the drain of the conductive field effect transistor; Controlling the digital-to-analog converter to input a variable gate-source voltage to the gate of the conductive field effect transistor; Controlling the instrument amplifier to detect the voltages on both sides of the sampling resistor at different gate-source voltages; The drain-source current of the turned-on field effect transistor is determined according to the voltage across the sampling resistor.

8. The field effect transistor pair testing method according to claim 6, characterized in that: The detection circuit includes: a programmable power supply module, a digital-to-analog converter, a sampling resistor, and an instrumentation amplifier. The controller is connected to the programmable power supply module, the digital-to-analog converter, and the instrumentation amplifier respectively. The instrumentation amplifier is connected to both sides of the sampling resistor. The programmable power supply module is connected to the first relay through the sampling resistor, and the digital-to-analog converter is connected to the second relay. Controlling the detection circuit to detect the turned-on field effect transistor includes: Controlling the digital-to-analog converter to input a fixed gate-source voltage to the gate of the conductive field effect transistor; Controlling the programmable power supply module to input a variable drain-source voltage to the drain of the conductive field effect transistor; Controlling the instrument amplifier to detect the voltages on both sides of the sampling resistor at different drain-source voltages; The drain-source current of the turned-on field effect transistor is determined according to the voltage across the sampling resistor.

Images