Back-to-Back Power Switch Controller

Abstract

Various embodiments of the present disclosure relate to back-to-back power switch controllers. In one embodiment, a power switch controller for driving back-to-back power switches includes an amplifier having a power supply terminal configured to receive a power supply voltage, an output configured to be coupled to a gate terminal of the back-to-back power switch, a first input configured to be coupled to a source terminal of the back-to-back power switch, and a second input coupled to the output of the amplifier. The amplifier is configured to generate an output voltage at the output of the amplifier that is an offset voltage higher than a voltage at the first input of the amplifier.

Description

Technical Field

[0001] The present disclosure relates generally to electronic systems and methods, and in particular embodiments, to a novel back-to-back power switch controller. Background Art

[0002] Traditional relays allow analog or digital signals to flow through the relay path in either direction when the relay is on, and block such signals when the relay is off. Relays are typically implemented using mechanical components based on electromagnet actuation.

[0003] Bidirectional switches, also known as analog switches or bilateral switches, operate in a similar manner as traditional relays, but without the need for mechanical parts. Typically, analog switches are implemented using back-to-back power metal oxide semiconductor field effect transistors (MOSFETs). For example, Figure 1 A schematic diagram of a conventional back-to-back power switch 102 and a power switch controller 104 is shown.

[0004] During normal operation, when a voltage (e.g., 5V) is applied to the power supply terminal V CC When the current sources 106 and 114 generate their respective currents I H and I L , so that the current I R flows through resistor 108. Current I R So that the voltage V GS Increase the threshold voltage V of the power MOSFETs 110 and 112 TH , thereby turning on power MOSFETs 110 and 112. When power MOSFETs 110 and 112 are turned on, analog or digital signals can flow from terminal VA to terminal VB and from terminal VB to terminal VA.

[0005] When removing the power supply terminal V CC When the voltage at the power supply terminal V CC 0V), voltage V GS falls below the threshold V TH , thereby turning off power MOSFETs 110 and 112. When power MOSFETs 110 and 112 are turned off, a signal cannot flow from terminal VA to terminal VB or from terminal VB to VA because intrinsic diodes (not shown) of power MOSFETs 110 and 112 are opposite each other in back-to-back power switch 102. Summary of the Invention

[0006] According to one embodiment, a power switch controller for driving back-to-back power switches includes an amplifier having a power supply terminal configured to receive a power supply voltage, an output configured to be coupled to a gate terminal of the back-to-back power switches, a first input configured to be coupled to a source terminal of the back-to-back power switches, and a second input coupled to the output of the amplifier. The amplifier is configured to generate an output voltage at the output of the amplifier that is an offset voltage higher than a voltage at the first input of the amplifier.

[0007] According to one embodiment, a circuit includes: a first terminal configured to be coupled to gate terminals of back-to-back power switches; a second terminal configured to be coupled to source terminals of the back-to-back power switches; the first power supply terminal configured to receive a first power supply voltage; a second power supply terminal configured to receive a second power supply voltage lower than the first power supply voltage; a first transistor having a current path coupled to the second power supply terminal; a current mirror coupled to the first power supply terminal; a second transistor having a gate coupled to the second terminal and a current path coupled between the current path of the first transistor and the current mirror; a third transistor having a gate coupled to the second terminal and a current path coupled between the current path of the first transistor and the current mirror; a current generator configured to generate a reference current; and an offset generator configured to generate an offset voltage based on the reference current. The offset generator is coupled between the current path of the third transistor and the current path of the first transistor.

[0008] According to one embodiment, a method for driving back-to-back power switches includes: receiving a reference voltage; receiving a power supply voltage higher than the reference voltage; generating a reference current based on the reference voltage; generating an offset voltage based on the reference current; and applying the offset voltage between gate terminals of the back-to-back power switches and source terminals of the back-to-back power switches using an amplifier, the amplifier including an output coupled to the gate terminal and a first input coupled to the source terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] For a more complete understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 A schematic diagram of a conventional back-to-back power switch and a power switch controller is shown;

[0011] Figure 2 A schematic diagram of a back-to-back power switch and a power switch controller according to an embodiment of the present invention is shown;

[0012] Figure 3A A schematic diagram of a power switch controller according to an embodiment of the present invention is shown;

[0013] Figure 3BThe embodiment of the present invention is shown. Figure 3A The V applied to the power switch by the power switch controller under different temperature and process variations GS The simulation waveform of

[0014] Figure 4 A schematic diagram showing a power switch controller according to an embodiment of the present invention; and

[0015] Figure 5 FIG. 1 is a schematic diagram of a power switch controller according to an embodiment of the present invention.

[0016] Unless otherwise indicated, corresponding numerals and symbols in the different figures generally indicate corresponding parts.The figures are drawn to clearly illustrate the relevant aspects of the preferred embodiments and are not necessarily drawn to scale. DETAILED DESCRIPTION

[0017] The following describes in detail the making and using of the disclosed embodiments. However, it should be understood that the present invention provides many applicable inventive concepts that can be embodied in a variety of specific contexts. The specific embodiments discussed are merely illustrative of specific methods of making and using the invention and do not limit the scope of the invention.

[0018] This specification describes various specific details below to provide a deeper understanding of some example embodiments in light of this specification. An embodiment may be obtained without one or more of the specific details, or by other methods, components, materials, etc. In other cases, known structures, materials, or operations are not shown or described in detail to avoid confusing different aspects of the embodiment. References to "embodiments" in this specification refer to specific configurations, structures, or features related to the embodiment that are included in at least one embodiment. Therefore, phrases such as "in one embodiment" that may appear in different places in this specification do not necessarily explicitly refer to the same embodiment. In addition, specific configurations, structures, or features may be combined in any suitable manner in one or more embodiments.

[0019] Embodiments of the present invention will be described in a specific context, such as a zero current turn-on back-to-back power switch controller for IDDQ testing applications. Embodiments of the present invention may be used in other applications, such as other applications that may benefit from zero current turn-on of back-to-back power switches.

[0020] In embodiments of the present invention, a power switch controller is capable of maintaining the back-to-back power switches in an on state, with the current supplied or absorbed by the back-to-back power switches from the power supply terminals of the power switch controller being substantially zero. The power switch controller is also capable of maintaining a stable on-state potential across the power switches, resulting in minimal deviation in the on-resistance of the power switches. In some embodiments, the current consumed by the power switch controller can be regulated to a very low value.

[0021] like Figure 1 As shown, power switch controller 104 includes current sources 106 and 114, and resistor 108. When currents IH and IL generated by current sources 106 and 114, respectively, are mismatched (e.g., when current IH is higher than current IL, or when current IL is higher than current IH), back-to-back power switch 102 sources or sinks excess current when back-to-back power switch 102 is turned on.

[0022] Some applications rely on sinking / sourcing essentially zero current to turn on back-to-back power switches for normal operation. An example of such an application is IDDQ testing. During IDDQ testing, the current consumption of the IC (e.g., the current flowing through the power supply terminal V CC The current flowing through the power supply terminal V CC If the current is above a predetermined threshold (e.g., several μA or mA, depending on the application), the IC may fail detection. Therefore, having back-to-back power switches with zero current turn-on advantageously allows the use of the power switches, for example, during IDDQ testing, without substantially affecting the current measurement during the IDDQ test, thereby increasing the effectiveness of the IDDQ test in detecting manufacturing defects.

[0023] In an embodiment of the present invention, zero current drawn or supplied by back-to-back power switches from a power switch controller is achieved by using a first-stage amplifier buffer for driving the gates of the transistors of the back-to-back power switches. The first-stage amplifier buffer has its positive input coupled to the source of the transistors of the back-to-back power switches. An offset voltage is introduced between the inverting input of the first-stage amplifier buffer and its output.

[0024] Figure 2 A schematic diagram of a back-to-back power switch 102 and a power switch controller 204 including an amplifier 206 and an offset generator 208 is shown in accordance with an embodiment of the present invention.

[0025] During normal operation, the offset generator generates an offset voltage V REF, and amplifier 206 acts as a buffer for the offset, where the offset is equal to the offset voltage V REF Therefore, amplifier 206 applies a voltage V at node G that is higher than the voltage at node S. REF , thereby maintaining a constant voltage V GS Equal to V REF , regardless of the voltage of the signal flowing between terminals VA and VB.

[0026] like Figure 2 As shown, the output of amplifier 206 drives a high impedance node because the output of amplifier 206 drives the gates of power MOSFETs 110 and 112. Figure 2 As shown, the sources of power MOSFETs 110 and 112 are coupled to the positive input of amplifier 206, which is a high impedance input. Thus, power switch controller 204 is advantageously able to keep power switch 102 turned on without causing power switch 102 to sink or source current from power switch controller 204.

[0027] During normal operation, amplifier 206 receives a supply voltage V CC Amplifier 206 turns on power switch 102 by turning on offset generator 208 and turns off power switch 102 by turning off offset generator 208. When offset generator 208 is on, offset generator 208 generates a voltage VREF high enough to turn on transistors 110 and 112 in saturation mode, thereby minimizing the on-resistance of power MOSFETs 110 and 112.

[0028] In some embodiments, the power supply voltage V CC At least a voltage V higher than the maximum voltage between terminals VA and VB REF For example, if power switch 102 is configured to receive a voltage of 0V to 3V at terminals VA and VB, and if power transistors 110 and 112 are configured to operate at their respective voltages V gs When it is in saturation mode, the voltage V REF is 3.3V, and the power supply voltage V CC It should be understood that V CC 、V REF The voltage at terminals VA and VB may be different. A person skilled in the art will know how to modify the voltage to suit a specific technology and application.

[0029] In some embodiments, when the power supply voltage VCC is removed (eg, 0V), the power switch 102 is turned off.

[0030] Back-to-back power switch 102 can be implemented using n-type transistor power MOSFETs 112 and 110. In some embodiments, power MOSFETs 110 and 112 are implemented using diffused MOS (DMOS) transistors, such as vertical DMOS (VDMOS) or lateral DMOS (LDMOS). Other transistor types of power transistors, such as p-type power transistors, can also be used.

[0031] like Figure 2 As shown, the offset generator 208 can receive a reference voltage V from an external circuit (not shown). ref , where the voltage V REF and V ref In some embodiments, the external circuit is a bandgap circuit that generates a voltage that is substantially stable over the temperature range. In other embodiments, the reference voltage V REF is derived from a bandgap circuit, such as by using a voltage regulator such as an LDO that uses the voltage generated by the bandgap as a reference voltage.

[0032] In some embodiments, the offset voltage V REF Different from the reference voltage V ref For example, in some embodiments, the offset voltage V REF is the reference voltage V ref A shortened version of .

[0033] In some embodiments, the offset generator 208 can be controlled by gating the reference voltage V ref In some embodiments, an external signal can be used to shut down the offset generator 208. In some embodiments, if the reference voltage V ref If provided by an LDO, then the LDO can be turned off to turn off the offset generator 208. Other implementations are also possible.

[0034] Figure 3A FIG2 shows a schematic diagram of a power switch controller 304 according to an embodiment of the present invention. The power switch controller 304 includes a first-stage amplifier buffer 306. The first-stage amplifier buffer 306 includes transistors 314, 320, 322, 324, and 326. The gate of transistor 320 can be understood as the positive input of the first-stage amplifier 306, the gate of transistor 322 can be understood as the negative input of the first-stage amplifier 306, and the drain of transistor 322 can be understood as the output of the first-stage amplifier 306. Figure 3A 、 Figure 4 and Figure 5 In the embodiment, the offset voltage V REF Equal to the reference voltage V ref .

[0035] Power switch controller 304 also includes current generator 307 and offset generator 315. Current generator 307 and offset generator 315 are matching circuits. In other words, resistors 316 and 310 are matched and transistors 308 and 318 are matched (e.g., process variations and temperature variations affect resistors 316 and 310 in a similar manner and transistors 318 and 308 in a similar manner). Matching circuits can be implemented through layout placement or any other method known in the art.

[0036] During normal operation, when the power supply terminal V CC When there is power (for example, 6V), and when the reference voltage V REF When V REF When transitioning from low (eg, 0V) to high (eg, 3.3V), transistor 328 is fully turned on (ie, in saturation mode), thereby pulling node G high to V CC and turns on power switch 102. When power switch 102 is on (i.e., closed), the voltage at node S is substantially similar to the voltage at terminals VA and VB (because the on-resistance of power MOSFETs 110 and 112 is very small, such as a few mΩ, when turned on). After startup, node G reaches voltage V REF or higher, causing transistor 328 to turn off.

[0037] When the voltage V REF When the voltage is high (eg, 3.3V), transistor 308 is fully turned on, so that the reference current I REF1 Flows through transistor 308. Current I REF1 The current I is mirrored by the current mirror 329 REF2 As shown in the figure, the ratio of the current mirror 329 is 2 to 1, so that the current I REF2 is the current I REF1 Twice the current I REF2 The current I is mirrored by the current mirror 311 REF3 As shown in the figure, the ratio of the current mirror 311 is 1:1, so that the current I REF3 Equal to I REF2 .

[0038] Since the current I REF3 is the current I REF1 If transistors 318 and 308 have the same size (eg, similar width and length) and resistors 310 and 316 have the same resistance, then the first-stage amplifier 306 maintains the voltage V at node G. REF above node S, thereby maintaining V GS Constant.

[0039] In embodiments where current generator 307 and offset generator 315 are matching circuits, power switch controller 304 advantageously maintains a substantially constant V GS .For example, Figure 3B 1 shows the V applied to the power switch 102 by the power switch controller 304 under different temperatures and process variations according to an embodiment of the present invention. GS The curve 352 shows the V at -40°C at the first process corner. GS Curve 354 shows the V at 25°C at the first process corner. GS Curve 356 shows the V at 150°C at the first process corner. GS Curve 358 shows the V at -40°C at the second process corner. GS Curve 360 ​​shows the V at 25°C at the second process corner. GS Curve 362 shows the V at 150°C at the second process corner. GS Curve 364 shows the V at -40°C at the third process corner. GS Curve 366 shows the V at 25°C at the third process corner. GS Curve 368 shows the V at 150°C at the third process corner. GS .

[0040] As shown by curve 352, V GS At the first process corner (TYP corner), it is 2.94V. As shown by curve 354, at 25°C, V GS At the first process corner, it is 2.97V. As shown by curve 356, at 150°C, V GS At the first process corner, it is 3.02V. As shown by curve 358, at -40℃, V GS At the second process corner (MAX corner), it is 3.01V. As shown by curve 360, at 25°C, V GS At the second process corner, it is 3.05V. As shown by curve 362, at 150°C, V GS At the second process corner, it is 3.14V. As shown by curve 364, at -40℃, V GS At the third process corner (MIN corner), it is 2.91V. As shown by curve 366, at 25°C, V GS At the third process corner, it is 2.93V. As shown by curve 368, V GS At the third process corner it is 2.97V.

[0041] Figure 4FIG2 shows a schematic diagram of a power switch controller 404 according to an embodiment of the present invention. The power switch controller 404 operates in a similar manner to the power switch controller 304. However, the power switch controller 404 has an independent power supply terminal V DD Powers the current mirror 329.

[0042] In some embodiments, the independent power supply terminal V DD Receives below power supply terminal V CC For example, in some embodiments, the power supply terminal can receive a voltage of 6.3V or higher, while the independent power supply terminal V DD Receive 3V voltage. Use independent terminal V DD This can be achieved by allowing the use of smaller transistors (e.g., transistors 330 and 332) without sacrificing performance by providing separate power supply terminals V DD Providing lower voltages advantageously allows for reduced power consumption and silicon surface area.

[0043] Figure 5 FIG2 shows a schematic diagram of a power switch controller 504 according to an embodiment of the present invention. The power switch controller 504 operates in a similar manner to the power switch controller 304. However, the power switch controller 504 generates a current I by using a current generator 507. REF4 The current generator 507 and the offset generator 515 are matching circuits.

[0044] The offset generator 515 generates V by a resistor 516 having a resistance twice that of the resistor 510 and a transistor 518 having a size twice that of the transistor 508 (eg, twice the width and the same length). REF offset.

[0045] It should be understood that modifications of the disclosed embodiments are possible. Figure 2 , offset generator 208 may be coupled to the positive input of amplifier 206 instead of the negative input of amplifier 206. In some embodiments, offset generator 208 may be implemented as two or more offset generators coupled to the negative and / or positive inputs of amplifier 206. For further non-limiting examples, with respect to Figure 3A , the current mirrors 329, 311 and 323 can have different scaling ratios, which can be achieved by modifying the voltage V REF , resistors 310 and 316, and / or transistor sizing of one or more transistors of power switch controller 304. Other modifications are possible.

[0046] Example embodiments of the invention are summarized here. Other embodiments may also be understood from the overall description and claims presented herein.

[0047] Example 1. A power switch controller for driving back-to-back power switches, the back-to-back power switches including a gate terminal, a source terminal, a first terminal, and a second terminal, the power switch controller comprising: an amplifier having a power supply terminal configured to receive a power supply voltage, an output configured to couple to the gate terminal of the back-to-back power switches, a first input configured to couple to the source terminal of the back-to-back power switches, and a second input coupled to the output of the amplifier. The amplifier is configured to generate an output voltage at the output of the amplifier, the output voltage being an offset voltage higher than a voltage at the first input of the amplifier.

[0048] Example 2. A power switch controller as described in Example 1, wherein the amplifier includes: a second power supply terminal configured to receive a second power supply voltage lower than the power supply voltage; a first transistor having a current path coupled to the second power supply terminal; a current mirror coupled to the power supply terminal; a second transistor having a gate coupled to the first input of the amplifier and a current path coupled between the current path of the first transistor and the current mirror; and a third transistor having a gate coupled to the second input of the amplifier and a current path coupled between the current path of the first transistor and the current mirror.

[0049] Example 3. The power switch controller of one of Examples 1 or 2 further includes a fourth transistor having a current path coupled to the power terminal, the current path of the fourth transistor being configured to couple to the gate terminal of the back-to-back power switch.

[0050] Example 4. The power switch controller of one of Examples 1 to 3 further includes: a current generator configured to output a reference current; and an offset generator configured to generate the offset voltage based on the reference current.

[0051] Example 5. The power switch controller of one of Examples 1 to 4, wherein the offset generator is coupled between the current path of the first transistor and the current path of the third transistor.

[0052] Example 6. The power switch controller of one of Examples 1 to 5, wherein the offset generator and the current generator are matching circuits.

[0053] Example 7. The power switch controller of one of Examples 1 to 6, wherein the current generator includes the first transistor and a first resistor coupled in series with the first transistor.

[0054] Example 8. The power switch controller of one of Examples 1 to 7, wherein the current generator includes a fourth transistor and a first resistor coupled in series with the fourth transistor, wherein the offset generator includes a fifth transistor and a second resistor coupled in series with the fifth transistor, and wherein a resistance of the first resistor is equal to a resistance of the second resistor.

[0055] Example 9. The power switch controller of one of Examples 1 to 8, further comprising: a second current mirror coupled to the current generator; and a third current mirror coupled to the second current mirror, the third current mirror comprising the first transistor.

[0056] Example 10. The power switch controller of one of Examples 1 to 9, further comprising a controller configured to receive a third power supply voltage that is higher than the second power supply voltage and lower than the power supply voltage, wherein the second current mirror is coupled to the third power supply terminal.

[0057] Example 11. The power switch controller of one of Examples 1 to 10, wherein the second current mirror comprises a current ratio of 2 to 1.

[0058] Example 12. The power switch controller of one of Examples 1 to 11, wherein the first transistor, the second transistor, and the third transistor are n-type transistors.

[0059] Example 13. The power switch controller of one of Examples 1 to 12, wherein the power switch controller is configured to receive a reference voltage, and wherein the amplifier is configured to generate the offset voltage based on the reference voltage.

[0060] Example 14. The power switch controller of one of Examples 1 to 13, wherein the power supply voltage is higher than the reference voltage.

[0061] Example 15. The power switch controller of one of Examples 1 to 14, wherein the amplifier is configured to: turn on the back-to-back power switches when the reference voltage is at a first voltage; and turn off the back-to-back power switches when the reference voltage is at a second voltage.

[0062] Example 16. The power switch controller of one of Examples 1 to 15, wherein the first voltage is higher than the second voltage.

[0063] Example 17. The power switch controller of one of Examples 1 to 16, wherein the reference voltage is a bandgap voltage.

[0064] Example 18. A circuit comprises: a first terminal configured to be coupled to a gate terminal of a back-to-back power switch; a second terminal configured to be coupled to a source terminal of the back-to-back power switch; a first power supply terminal configured to receive a first power supply voltage; a second power supply terminal configured to receive a second power supply voltage lower than the first power supply voltage; a first transistor having a current path coupled to the second power supply terminal; a current mirror coupled to the first power supply terminal; a second transistor having a gate coupled to the second terminal and a current path coupled between the current path of the first transistor and the current mirror; a third transistor having a gate coupled to the second terminal and a current path coupled between the current path of the first transistor and the current mirror; a current generator configured to generate a reference current; and an offset generator configured to generate an offset voltage based on the reference current, the offset generator being coupled between the current path of the third transistor and the current path of the first transistor.

[0065] Example 19. The circuit of Example 18 further comprises the back-to-back power switch, the gate terminal of the back-to-back switch coupled to the first terminal, the source terminal coupled to the second terminal, the back-to-back switch further comprising a third terminal and a fourth terminal.

[0066] Example 20. The circuit of Example 18 or 19, wherein the back-to-back power switch comprises: a first diffused metal oxide semiconductor (DMOS) transistor of n-type; and a second n-type DMOS transistor, wherein the first and second DMOS transistors each have a gate coupled to the gate terminal and a source coupled to the source terminal, wherein the drain of the first DMOS transistor is coupled to the third terminal and the drain of the second DMOS transistor is coupled to the fourth terminal.

[0067] Example 21. A method of driving back-to-back power switches, the method comprising: receiving a reference voltage; receiving a power supply voltage higher than the reference voltage; generating a reference current based on the reference voltage; generating an offset voltage based on the reference current; and applying the offset voltage between a gate terminal of the back-to-back power switch and a source terminal of the back-to-back power switch using an amplifier, the amplifier comprising an output coupled to the gate terminal and a first input coupled to the source terminal.

[0068] Example 22. The method of Example 21, further comprising: turning on the back-to-back power switches by increasing the offset voltage to a first voltage; and turning off the back-to-back power switches by decreasing the offset voltage to a second voltage.

[0069] Example 23. The method of Example 21 or 22, wherein the first voltage is higher than the second voltage, and wherein the second voltage is 0V.

[0070] Example 24. The method described in Examples 21 to 23 further includes: receiving the power supply voltage at a power supply terminal; increasing the reference voltage from a first voltage to a second voltage; turning on a first transistor using the reference voltage when the reference voltage is at the second voltage, the first transistor having a current path coupled between the power supply terminal and the gate terminal; and increasing the offset voltage based on the increase in the reference voltage; and turning off the first transistor when the offset voltage reaches the second voltage.

[0071] Although the present invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments and other embodiments of the present invention will be apparent to those skilled in the art in view of this description. Accordingly, the appended claims encompass any such modifications or embodiments.

Claims

1. A power switch controller for driving a back-to-back power switch, the back-to-back power switch having a gate terminal, a source terminal, a first terminal, and a second terminal, the power switch controller comprising: an amplifier having: a power supply terminal configured to receive a power supply voltage, an output configured to be coupled to the gate terminal of the back-to-back power switch, a first input configured to be coupled to the source terminal of the back-to-back power switch, and a second input coupled to the output of the amplifier, wherein the amplifier is configured to generate an output voltage at the output of the amplifier that is an offset voltage higher than a voltage at the first input of the amplifier; The amplifier comprises: a second power supply terminal configured to receive a second power supply voltage lower than the power supply voltage; a first transistor having a current path coupled to the second power supply terminal; a current mirror coupled to the power supply terminal; a second transistor having a gate coupled to the first input of the amplifier and a current path coupled between the current path of the first transistor and the current mirror; and a third transistor having a gate coupled to the second input of the amplifier and a current path coupled between the current path of the first transistor and the current mirror; The power switch controller further comprises: a current generator configured to generate a reference current; and an offset generator configured to generate the offset voltage based on the reference current; wherein the offset generator is coupled between the current path of the first transistor and the current path of the third transistor. 2 . The power switch controller of claim 1 , further comprising a fourth transistor having a current path coupled to the power terminal, the current path of the fourth transistor being configured to be coupled to the gate terminal of the back-to-back power switch. 3 . The power switch controller of claim 1 , wherein the offset generator and the current generator are matching circuits. 4 . The power switch controller of claim 1 , wherein the current generator comprises a sixth transistor and a first resistor coupled in series with the sixth transistor.

5. The power switch controller of claim 1 , wherein the current generator comprises a fourth transistor and a first resistor coupled in series with the fourth transistor, wherein the offset generator comprises a fifth transistor and a second resistor coupled in series with the fifth transistor, and wherein the first resistor has a first resistance equal to a second resistance of the second resistor.

6. The power switch controller according to claim 1 , further comprising: a second current mirror coupled to the current generator; and A third current mirror is coupled to the second current mirror, wherein the third current mirror includes the first transistor. 7 . The power switch controller of claim 6 , further comprising a third power supply terminal configured to receive a third power supply voltage that is higher than the second power supply voltage and lower than the power supply voltage, wherein the second current mirror is coupled to the third power supply terminal. 8 . The power switch controller of claim 6 , wherein the second current mirror comprises a current ratio of 2 to 1. 9 . The power switch controller of claim 1 , wherein the first transistor, the second transistor, and the third transistor are n-type transistors. 10 . The power switch controller of claim 1 , wherein the power switch controller is configured to receive a reference voltage, and wherein the amplifier is configured to generate the offset voltage based on the reference voltage. The power switch controller according to claim 10 , wherein the power supply voltage is higher than the reference voltage.

12. The power switch controller of claim 11 , wherein the amplifier is configured to: When the reference voltage is at a first voltage, turning on the back-to-back power switch; and When the reference voltage is at a second voltage, the back-to-back power switches are turned off. 13 . The power switch controller of claim 12 , wherein the first voltage is higher than the second voltage.

14. The power switch controller of claim 10, wherein the reference voltage is a bandgap voltage.

15. A circuit comprising: The power switch controller according to any one of claims 1 to 14; as well as A back-to-back power switch having a gate terminal, a source terminal, a first terminal, and a second terminal; wherein the gate terminal of the back-to-back power switch is coupled to the first input of the power switch controller, and the source terminal of the back-to-back power switch is coupled to the second input of the power switch controller.

16. The circuit of claim 15, wherein the back-to-back power switches comprise: a first n-type diffused metal oxide semiconductor (DMOS) transistor; and the n-type second diffused metal oxide semiconductor (DMOS) transistor, the first diffused metal oxide semiconductor (DMOS) transistor and the second diffused metal oxide semiconductor (DMOS) transistor having respective gates coupled to the gate terminal and respective sources coupled to the source terminal, wherein the drain of the first diffused metal oxide semiconductor (DMOS) transistor is coupled to the first terminal and the drain of the second diffused metal oxide semiconductor (DMOS) transistor is coupled to the second terminal.

17. A method for driving a back-to-back power switch, the method comprising: Receive reference voltage; receiving a power supply voltage higher than the reference voltage; generating a reference current based on the reference voltage; generating an offset voltage based on the reference current; and applying the offset voltage between a gate terminal of the back-to-back power switch and a source terminal of the back-to-back power switch using an amplifier, the amplifier including an output coupled to the gate terminal and a first input coupled to the source terminal; The method further comprises: receiving the supply voltage at a supply terminal; increasing the reference voltage from a first voltage to a second voltage; turning on a first transistor with the reference voltage when the reference voltage is at the second voltage, the first transistor having a current path coupled between the power terminal and the gate terminal; and increasing the offset voltage based on the increase in the reference voltage; and When the offset voltage reaches the second voltage, the first transistor is turned off.

18. The method according to claim 17, further comprising: turning on the back-to-back power switch by increasing the offset voltage to the second voltage; and The back-to-back power switches are turned off by reducing the offset voltage to the first voltage. The method of claim 18 , wherein the second voltage is higher than the first voltage, and wherein the first voltage is 0V.

Images