Electronic circuit with a set of weighted capacitors

Abstract

Embodiments of the present disclosure relate to an electronic circuit having a set of weighted capacitors. An electronic circuit includes a capacitive structure connected to one or more nodes, wherein each capacitive structure in the capacitive structure is formed by a capacitor or a plurality of capacitors connected in parallel. The electronic circuit further includes additional capacitors each connected to one or more nodes. For at least one distance between the capacitors, the capacitive structure has an identical average value, which is defined for each capacitor of each capacitive structure by the number of capacitors of the circuit that are connected to one or more nodes and are located at a distance from the capacitors of the capacitive structure.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority to French Patent Application No. 1904920, filed on May 13, 2019, the application of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure generally relates to electronic circuits, and more particularly to electronic circuits including weighted-capacitance capacitors, and more particularly to analog-to-digital converters having weighted-capacitance capacitors. Background Art

[0004] Some circuits include weighted-capacitance capacitors, that is, capacitive structures having a capacitance equal to the same unit value multiplied by an integer coefficient. In particular, in an analog-to-digital converter, the digital value output by the converter is a function of the weighted-capacitance value. Thus, the accuracy of this conversion is related to the accuracy of the weighted-capacitance value actually obtained. Summary of the Invention

[0005] There is a need to improve the accuracy of the weighted-capacitance value of an electronic circuit.

[0006] There is a need to reduce the volume of an electronic circuit including weighted-capacitance capacitors.

[0007] One embodiment overcomes all or some of the disadvantages of known circuits including weighted-capacitance capacitors.

[0008] One embodiment provides a circuit including weighted-capacitance capacitors having a smaller volume and / or a more accurate capacitance value than known weighted-capacitance capacitors.

[0009] Thus, one embodiment provides an electronic circuit, wherein: a capacitive structure is connected to one or more nodes, each capacitive structure in the capacitive structure being formed by a capacitor or a plurality of capacitors (200) connected in parallel; additional capacitors are each connected to the one or more nodes; and for at least one distance between the capacitors, the capacitive structure has the same average value, the same average value being defined by the number of capacitors of the circuit connected to the one or more nodes and located at the distance from the capacitors of the capacitive structure for each capacitor of each capacitive structure.

[0010] According to one embodiment, the additional capacitors and the capacitors of the capacitive structure are capacitor units.

[0011] According to one embodiment, the additional capacitors and the capacitors of the capacitive structure are located in array positions.

[0012] According to one embodiment, capacitors of a capacitive structure occupy all positions of a central portion of an array, and additional capacitors occupy all adjacent positions of the central portion.

[0013] According to one embodiment, the at least one distance includes a distance between adjacent capacitors in a column of the array and / or a distance between adjacent capacitors in a row of the array.

[0014] According to one embodiment, the at least one distance is the same distance between adjacent capacitors in a row of the array and between adjacent capacitors in a column of the array.

[0015] According to one embodiment, the capacitive structure is switchable.

[0016] According to one embodiment, the capacitive structure has the same number of switching positions, which is preferably equal to three.

[0017] According to one embodiment, the switching positions are directed towards a common node.

[0018] According to one embodiment, the additional capacitors are further connected to one or more additional nodes, and the circuit is configured such that the additional node or each additional node is brought to a fixed potential during at least one switching phase of the capacitive structure.

[0019] According to one embodiment, the capacitive structure has a number of capacitors equal to 1, an integer multiple, or a power of 2.

[0020] According to one embodiment, each of all powers of 2 less than a given value is the number of capacitors of a single capacitive structure in the capacitive structure.

[0021] According to one embodiment, the circuit further includes a comparator, and the one or more nodes are input nodes of the comparator.

[0022] One embodiment provides an analog-to-digital converter including the circuit defined above.

[0023] According to one embodiment, the converter is of the successive approximation register type. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The foregoing and other features and advantages will be discussed in detail in the non-limiting description of specific embodiments in conjunction with the accompanying drawings, in which:

[0025] Figure 1 An example of a type of circuit to which the described embodiments are applied is schematically shown;

[0026] Figure 2 An embodiment of a capacitive structure is schematically shown;

[0027] Figure 3A top view schematically showing another embodiment of a capacitive structure;

[0028] Figure 4 A partially simplified cross-sectional view showing an example of two adjacent capacitor units 400;

[0029] Figure 5 An embodiment of four capacitive structures is schematically shown;

[0030] Figure 6 A top view schematically showing another embodiment of four capacitive structures;

[0031] Figure 7 A top view schematically showing an embodiment of eight capacitive structures. Detailed Description

[0032] In different figures, the same elements are denoted by the same reference numerals. In particular, structural and / or functional elements common to different embodiments may be denoted by the same reference numerals and may have the same structure, dimensions, and material properties.

[0033] For clarity of illustration, only the steps and elements contributing to an understanding of the embodiments are shown and described in detail. In particular, an analog-to-digital converter control circuit is not shown, and the embodiments are compatible with a conventional analog-to-digital converter control circuit.

[0034] Throughout this disclosure, the term "connected" is used to denote a direct electrical connection between circuit elements, while the term "coupled" is used to denote an electrical connection that may be direct or may be via one or more intermediate elements between circuit elements.

[0035] In the following description, when referring to terms defining an absolute position (such as the terms "front", "rear", "top", "bottom", "left", "right", etc.) or a relative position (such as the terms "above", "below", "higher", "lower", etc.) or a term defining a direction (such as the terms "horizontal", "vertical", etc.), unless otherwise specified, it refers to the direction of the figure.

[0036] In this document, the terms "about", "substantially", and "approximately" are used to denote a deviation of plus or minus 10% of the value in question, preferably plus or minus 5%.

[0037] Figure 1 An example of a circuit 100 of the type to which the embodiments are applied is schematically shown. More specifically, in this example, the circuit 100 is an analog-to-digital converter, preferably of the successive approximation register type (SAR). This example is not restrictive, and the described embodiments are compatible with all types of circuits including capacitive structures having weighted capacitance values.

[0038] The circuit 100 includes a capacitive structure Ck, for example, a number N of capacitive structures C1, C2, C3, …, CN, where k is an integer in the range from 1 to N. For example, the number N is greater than or equal to 3, preferably greater than or equal to 4, more preferably greater than or equal to 6, and even more preferably greater than or equal to 8. The capacitive structure Ck has a weighted capacitance value. For example, the capacitance value of the capacitive structure C1 is a unit value. Thus, the capacitance values of the other capacitive structures Ck (k not equal to 1) are integer multiples of the capacitance value of the capacitive structure C1.

[0039] In the example shown, the capacitance values of the capacitive structures other than the structure C1 are integer powers of 2 multiplied by the capacitance value of the capacitive structure C1. Preferably, each capacitive structure Ck has a capacitance equal to 2k−1 times the capacitance of the capacitive structure C1. In other words, each integer power of 2 less than or equal to 2N−1 is the capacitance value of one and only one capacitive structure Ck. This example is not restrictive, and the described embodiment is compatible with circuits including multiple structures with the same weighted capacitance value and / or capacitive structures having capacitance values different from integer powers of 2 multiplied by a unit value.

[0040] In the example shown, the capacitive structure Ck is switchable, i.e., each capacitive structure Ck has a terminal or node 111-k (111-1, 111-2, 111-3, …, 111-N) coupled to, preferably connected to, a switch 110. Each switch 110 is configured to connect the relevant capacitive structure one by one to a plurality of nodes according to a control signal 112. The switch 110 is able to switch the capacitive structure Ck towards three nodes 114, 116, and 118. In other words, the switchable capacitive structure has three switching positions, towards the nodes 114, 116, and 118 respectively. This example is not restrictive, and the described embodiment is compatible with circuits including switchable capacitive structures having any same number of switching positions, circuits including switchable capacitive structures having different numbers of switching positions, and circuits including or further including non-switchable capacitive structures.

[0041] Here, the nodes 114, 116, and 118 are common and form the nodes for the application of respective potentials V−, V+, and Vin. However, the described embodiment is compatible with circuits where, for different capacitive structures, the capacitive structures can be switched towards different nodes.

[0042] In the example shown, the capacitor structure Ck has terminals 120-k (120-1, 120-2, 120-3, …, 120-N) that are all connected to the same node 120. This is not restrictive, and the described embodiments are compatible with a circuit that includes a capacitor structure having terminals that form different nodes 120-k, or with a group of capacitor structures having terminals that are commonly connected within each group and form different nodes between the groups. Then the different nodes 120-k can be coupled together, for example, by capacitor structures having weighted capacitance values.

[0043] The analog-to-digital converter further includes a comparator 130. The node 120 corresponds to the input of the comparator 130, i.e., the inverting input in this example. The comparator may include another input, for example, a non-inverting input coupled to a node to which a voltage Vref is applied.

[0044] The analog-to-digital converter further includes a control circuit 140 (SAR CTRL). The control circuit 140 receives the output of the comparator 130 and controls the switches of the capacitor structure Ck.

[0045] In operation, the control circuit 140 derives a digital value 150 of, for example, N bits from the analog value corresponding to the potential Vin. To achieve this, during the conversion phase, the control circuit 140 controls the successive positions of the switches 110. The successive positions of the switches 110 are not described in detail herein, and the described embodiments are compatible with the successive positions of the switches of a conventional analog-to-digital converter, such as a successive approximation register type converter.

[0046] Figure 2 An embodiment of the capacitor structure of the circuit is schematically shown. More specifically, Figure 2 an embodiment of the capacitor structure C1 (in the left part) and of one of the capacitor structures Ck of the type of circuit 100 (in the right part) Figure 1 is shown. Although Figure 2 capacitors and stray capacitances separated from the capacitors have been shown, the stray capacitances do not include additional elements relative to those capacitors. Only the stray capacitances included in the capacitance value represented by the capacitor structure Ck between its terminals are shown and described in detail herein.

[0047] The capacitive structure C1 is formed by the capacitor 200. Each of the capacitive structures Ck (where k is greater than 1) is formed by an integral multiple (preferably equal to 2k - 1) of capacitors 200 connected in parallel between the nodes 111 - k and 120 - k. The capacitive structure described herein is formed or defined by the capacitor 200 or multiple capacitors 200 connected in parallel. When this or these capacitors 200 are formed, the entire capacitor unit of the circuit is connected in parallel between the terminals of the capacitive structure, except for possible stray capacitance. Preferably, this or these capacitors 200 form the entire capacitor of the circuit connected in parallel between the terminals of the capacitive structure. In other words, the circuit includes no other capacitor units connected in parallel with the capacitor 200, except for the (multiple) capacitors 200 that form the capacitive structure and may form stray capacitance, and preferably no other capacitors connected in parallel with the (multiple) capacitors 200. In other words, within the range of possible stray capacitance, the capacitance value between the nodes 111 - k and 120 - k of the capacitive structure is equal to that of the capacitor 200 or equal to the sum of the values of the capacitors 200 forming the structure.

[0048] The capacitor 200 is a capacitor unit. A capacitor unit is a capacitor having the same capacitance value in the absence of possible stray capacitance. Preferably, within the manufacturing tolerance, all the capacitor units are the same. In this example, the capacitor units 200 of the capacitive structure Ck are periodically repeated at a pitch d.

[0049] In fact, the stray capacitance 230 is caused by adjacent capacitor units 200. Two capacitors that are next to each other or adjacent, that is, not separated from other capacitor units, and preferably not separated from other capacitors, are called adjacent capacitors. In other words, the distance between the centers of adjacent capacitor units 200 is equal to the pitch d. Each stray capacitance 230 is formed between the electrode connected to the terminal 111 - k of one of the capacitors 200 and the electrode connected to the terminal 120 - k of the adjacent capacitor. The value of the stray capacitance increases as the distance d between the capacitors decreases.

[0050] The additional capacitor 220, which is not included in the capacitors forming the capacitive structure Ck, is connected to the nodes 120 - 1 and 120 - k. In other words, the additional capacitor 220 is not connected in parallel with the capacitors 200 forming the structure Ck. Preferably, within the manufacturing tolerance, the additional capacitor 220 is the same capacitor unit as the capacitor units 200 of the capacitive structure Ck.

[0051] In this example, the additional capacitor 220 is located at the same distance on either side of the capacitor of the capacitive structure C1 and on either side of the capacitor 200 of the capacitive structure Ck. Preferably, this distance is the same as the distance between adjacent capacitors 200 in the weighted capacitive structure Ck. Thus, a stray capacitance 232 having the same value as the stray capacitance 230 is located between the additional capacitor 220 and the capacitor 200 of the capacitive structures C1 and Ck.

[0052] In this example, in each of the capacitive structures C1 or Ck, each capacitor in the capacitor 200 has two adjacent capacitors between the capacitor 200 of the capacitive structure Ck and the additional capacitor 220. In other words, each of the capacitors C1 or Ck has two capacitors located at positions where the distance is equal to the distance d.

[0053] Each additional capacitor 220 has a terminal 221 connected to one of the nodes 120-1 and 120-k. More specifically, the nodes 120-1 and 120-k of each of the capacitive structures C1 and Ck are connected to the terminal 221 of the additional capacitor adjacent to the capacitive structure. Thus, due to the fact that the additional capacitor 220 adjacent to the structure C1 has a terminal 221 connected to the node 120-1, the capacitance value of the capacitive structure C1 between the terminals 111-1 and 120-1 is formed by the capacitor 200 of the capacitive structure C1 and two stray capacitances 232. In fact, the capacitor 200 of the capacitive structure C1 and the two stray capacitances 231 are electrically connected in parallel between the terminals 111-1 and 120-2. Similarly, the capacitance value of the capacitive structure Ck is the sum of the values of the capacitor 200 of the capacitive structure Ck and the two stray capacitance capacitors 200. In other words, the number of stray capacitances for each capacitor in the capacitive structures C1 and Ck is equal to 2. Thus this number is the same in the capacitive structures C1 and Ck. In particular, in the preferred case where the capacitive structure Ck includes 2k - 1 capacitor units, between the nodes 111-k and 120-k, regardless of the value of the stray capacitance, the value of the capacitive structure Ck is equal to 2k - 1 multiplied by the value of the capacitive structure C1. For example, the value of each stray capacitance can be in the range of 1% to 5% of the values of the capacitor units 200 and 220.

[0054] It can be designed to obtain the value of the capacitive structure Ck, which is equal to 2k - 1 multiplied by the value of the capacitive structure C1, without providing the additional capacitor 220 or without coupling the additional capacitor 220 to the nodes 120-1 and 120-k. However, the capacitive structure C1 only shows the value of its capacitor unit 200 between its terminals, while in the capacitive structure Ck, the value of the stray capacitance 230 is added to the sum of the values of the 2k - 1 capacitor units 200. This results in an accuracy problem with the weighted capacitance value of the capacitive structure. In such as Figure 1In the converter, this causes problems with the accuracy of the conversion, especially linearity problems. Then the value of the stray capacitance must be limited, for example, by separating the capacitor cells from each other so as not to damage the converter body.

[0055] By comparison, additional capacitors 220 are provided and connected to nodes 120-1, 120-k and positioned as described above, which enables an improvement in accuracy and / or a reduction in the volume of the capacitance structure Ck. In particular, an analog-to-digital converter including such additional capacitors 220 is more accurate and / or compact than a converter without such additional capacitors.

[0056] Preferably, each of the additional capacitors 220 has a terminal 222 that is coupled to, preferably connected to, a node for the application of a fixed potential, preferably ground. This potential is fixed during at least one switching phase of the capacitance structure Ck. Such a phase preferably includes the switching of all switchable capacitance structures between the capacitance structures Ck, i.e., in Figure 1 the example of the circuit, the switching of all capacitance structures Ck. Preferably, this phase is the phase in which the analog value is converted into a digital value. Preferably, the potentials Vref, V+ and V- ( Figure 1 ) are then selected such that the analog-to-digital conversion is performed from a selected range of the potential Vin.

[0057] The preferred example of the terminal 222 coupled to ground is not restrictive. Different terminals 222 can be coupled to different nodes for the application of different fixed potentials. As a variant, for at least some of the additional capacitors 220, the terminal 221 of each additional capacitor is connected to the terminal 222 (and thus to one of the terminals 120-k). During the switching phase, the potential of the terminal 222 cannot be fixed.

[0058] The capacitance structures C1 and Ck having their capacitors 200 arranged at regular intervals d have been described above in connection with Figure 2 However, preferably, the capacitors 200 occupy positions in the array. Then additional capacitors 220 are provided at other positions in the array, as described below in connection with the drawings.

[0059] Figure 3 A top view schematically shows an embodiment of the capacitance structure of the circuit. More specifically, the structures C1 and C2 of the Figure 1 circuit are shown.

[0060] Capacitors 200 and 220 are identical capacitor units. Capacitors 200 and 220 occupy certain positions 302 of the array 300. One or more other positions of the array 300, e.g., all positions of the array 300, are occupied by capacitors 305. Two terminals 306, 307 of each capacitor 305 are coupled together, preferably connected to the same node of an application of a fixed potential such as ground. Capacitors 305 are connected to nodes 120-1 and 120-2. Further, except for capacitors 200 and 220 and possible stray capacitance, the circuit does not include other capacitors located at positions of the array and connected to one of nodes 120-1 and node 120-2. In other words, all capacitor units of the circuit located in the array and connected to nodes 120-1 and / or 120-2 are between capacitor 200 of the capacitive structure and additional capacitor 220.

[0061] In this example, capacitors 200 and 220 occupy rectangular positions, i.e., the array has different spacings in the row direction and the column direction of the array. Thus, the stray capacitance between adjacent capacitors in the same row can be different from the stray capacitance between adjacent capacitors in the same column. For example, the spacings in the column direction and the row direction are in the range of 0.1 μm to 1.5 μm.

[0062] Preferably, each capacitor unit 200, 220 includes an electrode 310. Preferably, another electrode 315 of the capacitor unit is completely located below electrode 310, i.e., hidden by electrode 310 in a top view. Each capacitor unit occupies the central part of one of the positions 302. Preferably, the capacitor unit occupies the main part of this position. For example, the distance between two adjacent capacitors in the same row and / or the same column is 5% to 25% of the distance between the centers of adjacent capacitors. Stray capacitance 320, similar to stray capacitance 230 ( Figure 2 ) exists between adjacent capacitors in the same column. Similarly, stray capacitance 322 exists between adjacent capacitors in the same row or the same rank of the matrix.

[0063] In the example shown, in the column direction, two additional capacitors 220 are provided on both sides of capacitor 200 of capacitive structure C1, and two additional capacitors 220 are provided on both sides of capacitor 200 of capacitive structure C2. Thus, in the column direction, in each capacitive structure C1 or C2, each capacitor 200 has two adjacent capacitors in the column direction between the capacitor 200 of the capacitive structure and the additional capacitor. Thus each capacitor 200 of each capacitive structure is associated with two stray capacitances 320. Thus, capacitive structure C2 includes twice the stray capacitance 320 of capacitive structure C1.

[0064] In the row direction, the capacitor 200 of the capacitive structure C1 has a single adjacent capacitor. The capacitive structure C2 includes capacitors 200 having two adjacent capacitors in the row direction and capacitors 200 having no adjacent capacitors in the column direction. In other words, although the number of adjacent capacitors of the two capacitors 200 in the row direction is different, the average value of the number of adjacent capacitors in the row direction is equal to 1. Therefore, on average, each capacitor 200 of the capacitive structure C2 is associated with the same number of stray capacitances 322 as the capacitor 200 of the capacitive structure C1.

[0065] Therefore, the capacitance value of the capacitive structure C1 between its terminals 111-1 and 120-1 ( Figure 2 ) is equal to the capacitance value of the capacitor unit 200 plus one stray capacitance 322 and two stray capacitances 320. Regardless of the values of the stray capacitances 320 and 322, the value of the capacitive structure C2 between the terminals 111-2 and 120-2 is twice the value of the capacitive structure C1 between the terminals 111-1 and 120-1.

[0066] In the capacitive structure Ck including more than two capacitor units, the additional capacitor 220 is provided and positioned in the same manner as the examples of the capacitive structures with one or two capacitor units Figure 2 above.

[0067] Therefore, in the case where the circuit includes the capacitive structure Ck, for each capacitor 200 of the capacitive structure Ck, a first value equal to the number of adjacent capacitors of the capacitor in the row direction is defined. More specifically, the adjacent capacitors of each capacitor 200 are between all the capacitors 200 and the additional capacitor 220 of the structure. In the capacitive structure Ck, the average value of the first value is equal to the number of adjacent capacitors of the capacitor 200 of the capacitive structure C1 in the row direction.

[0068] Between all the capacitors 200 and 220, for each capacitor 200 of the capacitive structure Ck, a second value equal to the number of capacitors adjacent to the considered capacitor 200 in the column direction is defined. In the capacitive structure Ck, the second value has an average value equal to the number of adjacent capacitors of the capacitor 200 of the capacitive structure C1 in the column direction.

[0069] Therefore, compared with the circuit that does not include the additional capacitor, the accuracy and / or volume of the circuit including the capacitive structure Ck is improved.

[0070] Examples of circuits include the capacitive structure C1 defined by the single capacitor cell described above. This is not restrictive, and the capacitor structure C1 may include multiple capacitor cells 200. The number and location of the additional capacitors 220 are then selected such that the first value has the same average value among different capacitive structures Ck, and such that the second value has the same average value among different capacitive structures Ck.

[0071] Although for each capacitor 200, a capacitive structure having on average two adjacent capacitors in the column direction and on average one adjacent capacitor in the row direction has been described above, these average values can take any value less than or equal to 2.

[0072] In the above example, the number of adjacent capacitors in the row direction and the number of adjacent capacitors in the column direction were considered. This is not restrictive. According to an embodiment, only the number of adjacent capacitors in the row direction or only the number of adjacent capacitors in the column direction is considered. According to other embodiments, the number of adjacent capacitors along the array diagonal is further considered. Then, for each capacitor, a value equal to at least one-third of the number of the capacitor's diagonal adjacent capacitors is defined in the same manner as the above first and second values.

[0073] An array having different spacings in the row direction and the column direction has been described above. This is not restrictive and the array may have the same spacing in the row direction and the column direction. Then the stray capacitances 320 and 322 preferably have equal values. The number and location of the additional capacitors 220 are selected such that if a value equal to the number of adjacent capacitors is defined for each capacitor 200 of the capacitive structure, then the average value of the defined value in different capacitive structures is the same. Here the adjacent capacitors are in any direction between the column direction and the row direction.

[0074] The above preferred examples of the capacitors located at the positions of the array are not restrictive. In fact, in the above example, the distance (center to center) between adjacent capacitors corresponding to the spacing in the respective row and column directions can be defined. For example, in the case where the array has the same spacing in the row and column directions, a single distance between adjacent capacitors corresponding to the same spacing can be defined. Similarly, for capacitors not located at the positions of the array, one or more distances between adjacent capacitors are defined. Thus, for each of this distance or these distances, if a value equal to the number of capacitors located at a distance from the considered capacitor 200 is defined for each capacitor 200, then the defined value has the same average value in each capacitive structure Ck.

[0075] The fact of providing the additional capacitors 220 arranged and connected as described above, as Figure 2As mentioned, it is possible to optimize the accuracy and / or volume of the capacitor structure Ck. Additionally, according to an advantage, due to the fact that the additional capacitor 220 adjacent to one of the capacitors 200 in the capacitor structure Ck is connected to the same node 120-k as the capacitor 200, running conductors between and / or above the capacitors is avoided. Therefore, the pitch of the array can be reduced without degrading the accuracy due to additional stray capacitance between the conductors and the capacitors.

[0076] For example, in a particular example of the ratio between the stray capacitance and the capacitance cell, approximately 40% of the surface area occupied by the capacitor structure can be saved compared to an analog-to-digital converter that does not include the additional capacitor. For example, in a 12-bit analog-to-digital converter, such a reduction in surface area can be achieved when the linear error is less than 8% of the least significant bit.

[0077] Figure 4 A partially simplified cross-sectional view of two adjacent capacitor cells 400 is shown. In particular, the connection is represented in a very simple manner. Each capacitor 400 can form either the capacitor 200 of the capacitor structure Ck or the capacitor 200 of the additional capacitor 220 of the embodiment.

[0078] The capacitors 400 are identical within the manufacturing tolerances. Each capacitor among the capacitors 400 includes a set of metal plates 410 alternating with metal plates 420. The alternating plates are separated by a dielectric layer, not shown. Each capacitor includes a plurality of interconnected conductive plates 410, thereby forming an electrode 310. Preferably, the two upper and lower plates in the stack are the first plates 410. Then, the first plates 410 are preferably coupled to, for example, connected to, the terminal 222 ( Figure 2 ) of the application of a fixed potential, such as ground. Thus, the upper and lower plates 410 in the stack form a shield for the electrode 420 that allows for a reduction in stray capacitance. Each capacitor preferably includes a plurality of interconnected second metal plates 420, thereby forming an electrode 315.

[0079] Preferably, the metal plates 410 and 420 are formed above the substrate 430 at the above-mentioned metal level, for example, a semiconductor substrate such as silicon. The metal level is defined by a layer including conductors (not shown) between components such as transistors located inside and on top of the substrate. The conductors are surrounded by insulators and are located between insulator layers. For example, the substrate is a semiconductor wafer that defines an electronic integrated circuit chip, and its components are located inside and on top of the semiconductor wafer.

[0080] One advantage of the capacitor cells 400 is that they can be simply formed simultaneously with the formation of the metal level of the chip.

[0081] Figure 5A top view of an embodiment schematically showing four capacitor structures C1, C2, C3, and C4 is shown. More specifically, capacitor structure C1 is defined by capacitor unit 200, and capacitor structures C2, C3, and C4 are defined by 2, 4, and 8 capacitor units 200 connected in parallel, respectively. The capacitors 200 are not shown individually, and a part of the array occupied by the capacitors 200 is shown. Positions not occupied by one of the capacitors 200 of the capacitor structures or one of the additional capacitors 220 are indicated by dashed lines.

[0082] The capacitors 200 of capacitor structures C1, C2, C3, and C4 each occupy a column of the array. The columns occupied by capacitor structures C1, C2, C3, and C4 are placed side by side in the order of capacitor structures C1, C2, C3, and C4. In each column, the occupied positions are adjacent and extend from the same row 510. The positions occupied by the capacitors 200 of the capacitor structures define a central portion 520 of the array.

[0083] Therefore, all positions of the central portion 520 are occupied by the capacitors 200. Preferably, the central portion is full, that is, each position therein is occupied by a capacitor between the capacitors 200 of the capacitor structure and the additional capacitor 220.

[0084] The additional capacitor 220 occupies all positions adjacent to or neighboring the central portion. Therefore, each capacitor 200 has two adjacent capacitors in the row direction and two adjacent capacitors in the column direction. In the case of an array having the same pitch in the row and column directions, each capacitor 200 has four adjacent capacitors. As described above, increased accuracy regarding a circuit not including the additional capacitor 200 is obtained thereby.

[0085] Figure 6 A top view of another embodiment schematically showing four capacitor structures C1, C2, C3, and C4 is shown. The capacitor structures are as Figure 5 shown and are defined by 1, 2, 4, and 8 capacitor units occupying array positions, respectively.

[0086] The array sequentially includes from the same row 601:

[0087] - a column 602 that sequentially includes an additional capacitor 220, a capacitor 200 of structure C1, and a capacitorless position;

[0088] - a column 604 that sequentially includes a capacitorless position, two capacitors 200 of structure C2, and a capacitorless position;

[0089] - a column 606 that sequentially includes two capacitorless positions, two of the capacitors 200 of structure C3, two capacitorless positions, and two additional capacitors 220;

[0090] - Column 608, successively including additional capacitor 220, two capacitor-free positions, the other two of the capacitors 200 of structure C3, one capacitor-free position, and two (C4-1) of the capacitors 200 of structure C4; and

[0091] - Column 610, successively including one (C4-3) of the capacitors 200 of structure C4, one capacitor-free position, one (C4-2) of the capacitors 200 of structure C4, one capacitor-free position, and the other four capacitors 200 of structure C4.

[0092] The capacitor-free positions optionally include capacitor 305, as Figure 3 defined but not shown.

[0093] Therefore, in each capacitive structure, for each capacitor, the average value of the values defined by the number of adjacent capacitors of the capacitor in the row direction is equal to 1. Therefore, these average values are equal. In each capacitive structure, for each capacitor, the average value of the values defined by the number of adjacent capacitors of the capacitor in the column direction is equal to 1. Therefore, these average values are equal.

[0094] As described above, higher accuracy is obtained for the circuit that does not include additional capacitor 220. In addition, compared with Figure 5 the assembly of the capacitive structure and the additional capacitor, Figure 6 the assembly of the capacitive structure and the additional capacitor is more compact.

[0095] In the case of an array with the same pitch in the row and column directions, in each capacitive structure, for each capacitor, the average value of the numerical values defined by the number of adjacent capacitors of the capacitance is equal to 2. Therefore, these numerical values are equal, which also provides improved accuracy and reduced volume in this case.

[0096] Figure 7 A top view of an embodiment of eight capacitive structures Ck is schematically shown, where k ranges from 1 to 8 (C1, C2, C3, C4, C5, C6, C7, and C8). Each capacitive structure Ck is formed by 2k - 1 capacitor units 200.

[0097] The capacitors of the capacitive structure occupy all positions of the central portion 802 of the array. The central portion 802 is successively composed of one column 804 having fifteen positions from row 808 and fifteen columns 806 having sixteen positions from the same row 808. Column 804 successively includes eight capacitors 200 of structure C4, four capacitors 200 of structure C3, two capacitors 200 of structure C2, and the capacitor 200 of structure C1 from row 808. The capacitors 200 of structures C5, C6, C7, and C8 respectively occupy 1, 2, 4, and 8 in column 806.

[0098] The additional capacitor 220 occupies all positions adjacent to the central portion 802. Thus, each capacitor 200 of the capacitive structure has two adjacent capacitors in the row direction and two adjacent capacitors in the column direction. In the case where the array has the same pitch in the row and column directions, each capacitive structure has four adjacent capacitors. This provides increased accuracy for a circuit that does not include the additional capacitor.

[0099] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these different embodiments and variations can be combined, and that those skilled in the art will make other variations.

[0100] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variations is within the capabilities of those skilled in the art.

Claims

1. An electronic circuit, comprising: a capacitive structure connected to one or more nodes, wherein each capacitive structure in the capacitive structure is formed by a capacitor or formed by a plurality of capacitors connected in parallel, and wherein the capacitive structure is switchable and has a weighted capacitance value; and additional capacitors, wherein each additional capacitor is connected to the one or more nodes; wherein, for at least one distance between capacitors, the capacitive structure has the same average value, and the same average value is defined for each capacitor of each capacitive structure by the number of capacitors of the electronic circuit that are connected to the one or more nodes and are located at the distance from the capacitors of the capacitive structure.

2. The electronic circuit according to claim 1, wherein the additional capacitors and the capacitors of the capacitive structure are capacitor units.

3. The electronic circuit according to claim 1, wherein the additional capacitors and the capacitors of the capacitive structure are located in positions of an array.

4. The electronic circuit according to claim 3, wherein the capacitors of the capacitive structure occupy all the positions of the central part of the array, and the additional capacitors occupy all the positions adjacent to the central part of the array.

5. The electronic circuit according to claim 3, wherein the at least one distance includes the distance between adjacent capacitors in a column of the array and / or the distance between adjacent capacitors in a row of the array.

6. The electronic circuit according to claim 3, wherein the at least one distance is the same distance between adjacent capacitors in a row of the array and between adjacent capacitors in a column of the array.

7. The electronic circuit according to claim 1, wherein the capacitive structure has the same number of switching positions.

8. The electronic circuit according to claim 7, wherein the number of switching positions is equal to three.

9. The electronic circuit according to claim 7, wherein the switching positions are directed towards a common node.

10. The electronic circuit according to claim 1, wherein the additional capacitors are further connected to one or more additional nodes, and wherein the electronic circuit is configured such that each additional node is brought to a fixed potential during at least one switching stage of the capacitive structure.

11. The electronic circuit according to claim 1, wherein the capacitive structure has a number of capacitors equal to 1, an integer multiple, or an integer power of 2.

12. The electronic circuit according to claim 11, wherein each integer power of 2 less than a given value is the number of capacitors of a single capacitive structure in the capacitive structure.

13. The electronic circuit according to claim 1, further comprising a comparator, wherein the one or more nodes are input nodes of the comparator.

14. The electronic circuit according to claim 1, wherein the electronic circuit is an analog-to-digital converter.

15. The electronic circuit according to claim 14, wherein the analog-to-digital converter is a successive approximation register type analog-to-digital converter.

16. The electronic circuit according to claim 1, wherein the one or more nodes include a plurality of independent nodes.

17. The electronic circuit according to claim 16, wherein each capacitive structure is connected to a respective independent node.

18. The electronic circuit according to claim 17, wherein the independent nodes are coupled together by additional capacitive structures.

19. The electronic circuit according to claim 18, wherein each of the additional capacitive structures has a weighted capacitance value.

20. The electronic circuit according to claim 16, further comprising a plurality of groups of capacitive structures, wherein each group of capacitive structures in the groups of capacitive structures is connected to a respective independent node.

21. The electronic circuit according to claim 20, wherein the independent nodes are coupled together by additional capacitive structures.

22. The electronic circuit according to claim 21, wherein each of the additional capacitive structures has a weighted capacitance value.

23. An electronic circuit, comprising: a capacitive structure connected to one or more nodes, wherein each of the capacitive structures is formed by a capacitor or by a plurality of capacitors connected in parallel, the capacitive structure being switchable and having a weighted capacitance value; and additional capacitors, wherein each additional capacitor is connected to the one or more nodes; and a comparator, wherein the one or more nodes are input nodes of the comparator; wherein, for at least one distance between capacitors, the capacitive structure has the same average value, the same average value being defined for each capacitor of each capacitive structure by the number of capacitors of the electronic circuit that are connected to the one or more nodes and are located at the distance from the capacitors of the capacitive structure.

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