Device and method for supporting multi-clock domain clock transfer

Abstract

The present application provides a device and method for supporting clock transmission in multiple clock domains. The device includes: N frequency detectors, N filters, N clock reconstructors and N clock domain interfaces, wherein N is an integer greater than or equal to 2, and the N clock domain interfaces correspond to the N frequency detectors, the N filters and the N clock reconstructors respectively, and the N frequency detectors are connected to N clock sources respectively, and at least two of the N clock sources are different. The above-mentioned device can reconstruct multiple different clock signals by transmitting a common clock signal, digitized phase difference information and frequency difference information, and apply them to the clock domain interfaces of each clock domain, so as to flexibly adapt to multiple different clock domains, realize a single device to support clock transmission in multiple clock domains at the same time, without the need to add or replace equipment, and can flexibly meet user needs.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and more specifically, to a device and method for supporting clock transfer in multiple clock domains. Background Art

[0002] During the network evolution process, for example, during the metropolitan area network transformation and evolution process, the original fixed network services are carried by Synchronous Digital Hierarchy (SDH) equipment. The newly built mobile services are carried by Internet Protocol (IP) equipment. These two services may coexist for a long time, so hybrid service carrying equipment is needed to carry multiple services at the same time.

[0003] The SDH service itself requires that the hybrid service bearer equipment build a top-down frequency synchronization network. In the era of Long Term Evolution-Advanced (LTE-A), mobile services require that the hybrid service bearer equipment has the ability to carry synchronous Ethernet and 1588v2 clocks, and can obtain frequency synchronization and time synchronization from the Global Navigation Satellite System (GNSS). In addition, hybrid service bearer equipment may also need to support the evolution to a higher-precision synchronization network in the future. Different synchronization networks may have different accuracies and different clock sources. At present, hybrid service bearer equipment can only transmit the data of multiple different services to the corresponding devices separately, and cannot transmit the clock signals generated by the clock sources of multiple different services at the same time. With the evolution of wireless technology and fixed-line technology, the demand for network equipment to support synchronization of multiple different clock domains is becoming more and more common.

[0004] The International Telecommunication Union Telecommunication Standardization Sector (ITU-T) defines reference models for various synchronization network devices, but does not define how to use the same device to simultaneously carry clock signals from multiple different clock domains. Summary of the invention

[0005] In view of this, an embodiment of the present application provides a device and method for supporting clock transfer in multiple clock domains, which can use the same device to simultaneously support clock transfer in multiple different clock domains.

[0006] In a first aspect, a device supporting multi-clock domain clock transfer is provided, which includes: N frequency and phase detectors, N filters, N clock reconstructors, and N clock domain interfaces.

[0007] Wherein, N is an integer greater than or equal to 2. The N clock domain interfaces correspond one-to-one to the N frequency detectors, the N filters, and the N clock reconstructors. The N frequency detectors are connected to N clock sources, respectively, and at least two of the N clock sources are different.

[0008] The i-th phase frequency detector among the N phase frequency detectors is used to receive a clock signal generated by a clock source connected to the i-th phase frequency detector, determine the i-th phase difference information between a common clock signal and the clock signal, and send the i-th phase difference information to the i-th filter among the N filters corresponding to the i-th phase frequency detector.

[0009] The i-th filter is used to receive the i-th phase difference information sent by the i-th phase and frequency detector, convert the i-th phase difference information into the i-th frequency difference information, and send the i-th frequency difference information to the i-th clock reconstructor corresponding to the i-th filter among the N clock reconstructors.

[0010] The i-th clock reconstructor is used to receive the i-th frequency difference information sent by the i-th filter, reconstruct the i-th network timing clock within the device according to the common clock signal and the i-th frequency difference information, and send the i-th network timing clock to the i-th clock domain interface among the N clock domain interfaces.

[0011] Here, i is an integer and satisfies 1≤i≤N.

[0012] In this way, since a device only supports the transmission of one clock signal, after receiving clock signals from multiple different clock sources, the device still transmits the common clock signal, but the clock reconstructor reconstructs the clock signals of different clock domains at each clock source interface, and then sends them to other clock domain interfaces of the clock domain, further realizing network-level clock synchronization. The above device realizes clock transmission in multiple clock domains by extracting the difference between the clock signals of different clock sources and the common clock.

[0013] The device supporting multi-clock domain clock transmission in the embodiment of the present application obtains the phase difference information between the clock signal generated by the clock source of each clock domain and the common clock signal through a frequency detector and a phase detector, and then converts the phase difference information into frequency difference information through a filter. Finally, the clock signal of the required clock domain is synthesized through a clock reconstructor, and applied to the clock domain interface of each clock domain, so as to flexibly adapt to multiple different clock domains and realize a single device supporting multi-clock domain clock transmission at the same time. There is no need to add or replace equipment, and it can flexibly meet user needs.

[0014] Optionally, the N frequency and phase detectors may be dual-D digital phase detectors or time-to-digital converters (TDC).

[0015] Optionally, the N filters may be respectively composed of a digital filter module and a conversion module, wherein the digital filter module may adopt a general 7th-order finite impulse response (FIR) filter module.

[0016] Optionally, the N clock reconstructors may be direct digital frequency synthesizers (Direct Digital Frequency Synthesis, DDS) or number controlled oscillators (Number Controlled Oscillator, NCO).

[0017] Optionally, the phase difference information and the frequency difference information may be encapsulated into a layer 2 Ethernet message for transmission.

[0018] In a first possible implementation manner of the first aspect, the device further includes: an N+1th phase frequency detector and an external synchronization interface, wherein the N+1th phase frequency detector is connected to an external clock source through the external synchronization interface.

[0019] The N+1th frequency detector is used to receive the clock signal generated by the external clock source, determine the N+1th phase difference information between the clock signal generated by the external clock source and the common clock signal, and send the N+1th phase difference information to the jth filter among the N filters.

[0020] The j-th filter is used to receive the N+1-th phase difference information sent by the N+1-th frequency detector, convert the N+1-th phase difference information into the N+1-th frequency difference information, and send the N+1-th frequency difference information to the j-th clock reconstructor corresponding to the j-th filter among the N clock reconstructors.

[0021] The jth clock reconstructor is used to receive the N+1th frequency difference information sent by the jth filter, reconstruct the N+1th network timing clock within the device according to the common clock signal and the N+1th frequency difference information, and send the N+1th network timing clock to the jth clock domain interface among the N clock domain interfaces.

[0022] Here, j is an integer and satisfies 1≤j≤N.

[0023] In this way, the device can receive and reconstruct the clock signal from the external synchronization interface while supporting the transmission of clock signals from multiple different clock domains, ensuring that each clock domain interface of the device can receive the clock signal of the external synchronization interface as needed. If the clock signal of the external synchronization interface is more accurate than the clock signal of each clock domain interface, each clock domain interface can use the clock signal of the external synchronization interface as its own network timing clock, thereby improving the accuracy of the clock signal in the device.

[0024] In combination with the foregoing possible implementation manner of the first aspect, in a second possible implementation manner of the first aspect, the device further includes: an N+1th clock reconstructor.

[0025] The kth filter among the N filters is also used to send the kth frequency difference information generated by the kth filter to the N+1th clock reconstructor.

[0026] The N+1th clock reconstructor is used to receive the kth frequency difference information sent by the kth filter, reconstruct the kth network timing clock in the device according to the kth frequency difference information, and send the kth network timing clock to the external synchronization interface.

[0027] Here, k is an integer and satisfies 1≤k≤N.

[0028] Through the device of the embodiment of the present application, clock signals from multiple different clock domains can not only be transmitted on the various clock domain interfaces of the device, but also be transmitted to other devices connected to the device through the external synchronization interface, thereby realizing performance testing of the internal clock signal of the device.

[0029] In combination with the foregoing possible implementation manner of the first aspect, in a third possible implementation manner of the first aspect, the device further includes: an input selector.

[0030] The i-th frequency and phase detector is specifically used for:

[0031] The i-th phase difference value information is sent to the input selector.

[0032] The input selector is used to receive the i-th phase difference information sent by the i-th phase frequency detector, and based on the corresponding relationship between the i-th phase frequency detector and the i-th filter, send the i-th phase difference information to the i-th filter.

[0033] In combination with the foregoing possible implementation manner of the first aspect, in a fourth possible implementation manner of the first aspect, the input selector is further used to:

[0034] When the clock sources of the N clock domain interfaces correspond to M types of services, M phase difference information is selected from the phase difference information sent by the N frequency detectors and phase detectors, and the M phase difference information corresponds one-to-one to the M types of services, and based on the correspondence between the N frequency detectors and the N filters, the corresponding phase difference information is sent to each of the N filters, where M is an integer less than N.

[0035] Specifically, if the N services corresponding to the N clock domain interfaces include the same service, the same service is divided into one service, so it is assumed that the N services include M types of services. The input selector can perform a source selection operation on the phase difference value information from the clock sources of the N services, and select M phase difference value information corresponding to M types of services from the N phase difference value information corresponding to the N services, so that the same type of services in the N services can track the optimal clock source in the type.

[0036] Optionally, the input selector can be implemented in the device through software of a central processing unit (CPU) or through hardware of a field programmable gate array (FPGA), which is not limited in the embodiments of the present application.

[0037] In combination with the foregoing possible implementation manner of the first aspect, in a fifth possible implementation manner of the first aspect, the device further includes: an output selector.

[0038] The i-th filter is specifically used for:

[0039] The i-th frequency difference information is sent to the output selector.

[0040] The output selector is used to receive the i-th frequency difference information sent by the i-th filter, and based on the corresponding relationship between the i-th filter and the i-th clock reconstructor, send the i-th frequency difference information to the i-th clock reconstructor.

[0041] Optionally, the output selector mentioned above can be implemented in the device through software of a central processing unit CPU, or through hardware of a field programmable gate array FPGA, which is not limited in the embodiments of the present application.

[0042] In combination with the foregoing possible implementation manner of the first aspect, in a sixth possible implementation manner of the first aspect, the device further includes:

[0043] The common clock generator is used to generate the common clock signal before determining the i-th phase difference information between the common clock signal and the clock signal, and send the common clock signal to the i-th frequency and phase detector and the i-th clock reconstructor.

[0044] In a second aspect, a method for supporting multi-clock domain clock transfer is provided, the method comprising:

[0045] An i-th phase frequency detector among the N phase frequency detectors receives a clock signal generated by a clock source connected to the i-th phase frequency detector, determines an i-th phase difference information between a common clock signal and the clock signal, and sends the i-th phase difference information to an i-th filter among the N filters corresponding to the i-th phase frequency detector.

[0046] The i-th filter receives the i-th phase difference information sent by the i-th phase and frequency detector, converts the i-th phase difference information into i-th frequency difference information, and sends the i-th frequency difference information to the i-th clock reconstructor corresponding to the i-th filter among the N clock reconstructors.

[0047] The i-th clock reconstructor receives the i-th frequency difference information sent by the i-th filter, reconstructs the i-th network timing clock within the device according to the common clock signal and the i-th frequency difference information, and sends the i-th network timing clock to the i-th clock domain interface among the N clock domain interfaces.

[0048] Among them, N is an integer greater than or equal to 2, the N clock domain interfaces correspond one-to-one to the N frequency detectors, the N filters and the N clock reconstructors, respectively, the N frequency detectors are connected to N clock sources, respectively, and at least two of the N clock sources are different, and i is an integer and satisfies 1≤i≤N.

[0049] In a first possible implementation manner of the second aspect, the method further includes:

[0050] The N+1th phase frequency detector receives a clock signal generated by an external clock source, determines the N+1th phase difference information between the clock signal generated by the external clock source and the common clock signal, and sends the N+1th phase difference information to the jth filter among the N filters.

[0051] The j-th filter receives the N+1-th phase difference information sent by the N+1-th frequency detector and phase detector, converts the N+1-th phase difference information into the N+1-th frequency difference information, and sends the N+1-th frequency difference information to the j-th clock reconstructor corresponding to the j-th filter among the N clock reconstructors.

[0052] The jth clock reconstructor receives the N+1th frequency difference information sent by the jth filter, reconstructs the N+1th network timing clock within the device according to the common clock signal and the N+1th frequency difference information, and sends the N+1th network timing clock to the jth clock domain interface among the N clock domain interfaces.

[0053] The N+1th frequency detector and phase detector are connected to the external clock source via an external synchronization interface, and j is an integer and satisfies 1≤j≤N.

[0054] In combination with the foregoing possible implementation manner of the second aspect, in a second possible implementation manner of the second aspect, the method further includes:

[0055] The kth filter among the N filters sends the kth frequency difference information generated by the kth filter to the N+1th clock reconstructor.

[0056] The N+1th clock reconstructor receives the kth frequency difference information sent by the kth filter, reconstructs the kth network timing clock in the device according to the kth frequency difference information, and sends the kth network timing clock to the external synchronization interface, wherein k is an integer and satisfies 1≤k≤N.

[0057] In combination with the foregoing possible implementation manner of the second aspect, in a third possible implementation manner of the second aspect, sending the i-th phase difference information to the i-th filter corresponding to the i-th frequency detector and phase detector among the N filters includes:

[0058] The i-th phase frequency detector sends the i-th phase difference information to the input selector.

[0059] The input selector receives the i-th phase difference information sent by the i-th phase frequency detector, and sends the i-th phase difference information to the i-th filter based on the corresponding relationship between the i-th phase frequency detector and the i-th filter.

[0060] In combination with the foregoing possible implementation manner of the second aspect, in a fourth possible implementation manner of the second aspect, after the input selector receives the i-th phase difference value information sent by the i-th frequency and phase detector, the method further includes:

[0061] When the clock sources of the N clock domain interfaces correspond to M types of services, the input selector selects M phase difference information from the phase difference information sent by the N frequency and phase detectors, and the M phase difference information corresponds one-to-one to the M types of services.

[0062] The step of sending the i-th phase difference information to the i-th filter includes:

[0063] Based on the corresponding relationship between the N frequency and phase detectors and the N filters, corresponding phase difference information is sent to each of the N filters.

[0064] Here, M is an integer smaller than N.

[0065] In combination with the foregoing possible implementation manner of the second aspect, in a fifth possible implementation manner of the second aspect, sending the i-th frequency difference information to an i-th clock reconstructor corresponding to the i-th filter among the N clock reconstructors includes:

[0066] The i-th filter sends the i-th frequency difference information to the output selector.

[0067] The output selector receives the i-th frequency difference information sent by the i-th filter, and based on the corresponding relationship between the i-th filter and the i-th clock reconstructor, sends the i-th frequency difference information to the i-th clock reconstructor.

[0068] In combination with the foregoing possible implementation manner of the second aspect, in a sixth possible implementation manner of the second aspect, before determining the i-th phase difference information between the common clock signal and the clock signal, the method further includes:

[0069] The common clock generator generates the common clock signal and sends the common clock signal to the i-th phase and frequency detector and the i-th clock reconstructor.

[0070] The method in the second aspect may be executed by a device in the first aspect or any possible implementation of the first aspect.

[0071] According to a third aspect, a computer-readable medium is provided for storing a computer program, wherein the computer program comprises instructions for executing the method in the second aspect or any possible implementation of the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0072] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0073] Figure 1 It is a schematic diagram of an application scenario of an embodiment of the present application.

[0074] Figure 2 It is a schematic block diagram of a device supporting multi-clock domain clock transfer provided by an embodiment of the present application.

[0075] Figure 3 It is a schematic block diagram of another device supporting multi-clock domain clock transfer provided by an embodiment of the present application.

[0076] Figure 4 It is a schematic block diagram of another device supporting multi-clock domain clock transfer provided by an embodiment of the present application.

[0077] Figure 5 It is a schematic block diagram of a method for supporting multi-clock domain clock transfer provided by an embodiment of the present application. DETAILED DESCRIPTION

[0078] The technical solutions in the embodiments of the present application will be described in detail below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, other embodiments can be obtained by ordinary technicians in this field without making creative work.

[0079] The embodiments of the present application can be applied to various communication systems. Therefore, the application scenario of the technical solution provided in the embodiments of the present application is not limited to a specific communication system. The communication system adopted in the application scenario of the technical solution can be a global system of mobile communication (Global System of Mobile communication, GSM) system, a code division multiple access (Code Division Multiple Access, CDMA) system, a wideband code division multiple access (Wideband Code Division Multiple Access, WCDMA) system, a general packet radio service (General Packet Radio Service, GPRS), a long term evolution (Long Term Evolution, LTE) system, a LTE frequency division duplex (Frequency Division Duplex, FDD) system, a LTE time division duplex (Time Division Duplex, TDD) or a universal mobile communication system (Universal Mobile Telecommunication System, UMTS).

[0080] The device in the embodiment of the present application may be a network device, a terminal device, or other transmission nodes, which is not limited in the embodiment of the present application. Among them, the network device may include a base station and a base station controller. The base station may be a device for communicating with a terminal device. For example, the base station may be a base station (Base Transceiver Station, BTS) in a GSM system or CDMA, or a base station (Node B, NB) in a WCDMA system, or an evolved base station (Evolutional Node B, eNB or eNodeB) in an LTE system. Alternatively, the base station may be a relay station, an access point, a vehicle-mounted device, or a network-side device in a future 5G network. The base station controller may schedule services between base stations through a transmission node. The transmission node may be an Ethernet switch, an IP router, a packet transport network (Packet Transport Network, PTN), a microwave (Microwave) device, or an optical transport network (Optical Transport Network, OTN). The terminal device may refer to an access terminal, a user equipment (User Equipment, UE), a user unit, a user station, a mobile station, a mobile station, a remote station, a remote terminal, a mobile device, a user terminal, a terminal, a wireless communication device, a user agent, or a user device. The access terminal can be a cellular phone, a cordless phone, a Session Initiation Protocol (SIP) phone, a Wireless Local Loop (WLL) station, a Personal Digital Assistant (PDA), a handheld device with wireless communication function, a computing device or other processing device connected to a wireless modem, a vehicle-mounted device, a wearable device, a terminal device in the future 5G network, or a terminal device in the future evolved Public Land Mobile Network (PLMN), etc.

[0081] Figure 1 A schematic diagram of an application scenario of an embodiment of the present application is shown. Figure 1 The application scenario shown includes clock source A, clock source B, device A, device B, device C, device D, and device E. Among them, clock source A and clock source B are clock sources for two different services. The clock source of device A is clock source A. The clock source of device B is clock source B. The service data packets carried by devices A and B are simultaneously delivered to device C, and device C then delivers the service data packets of device A to device D and the service data packets of device B to device E. This architecture carries two different services, namely two synchronization networks, so device C can be called a hybrid service carrying device.

[0082] It should be understood that Figure 1 Only an application scenario including two clock sources is exemplarily shown. Optionally, the system may also include more clock sources and more devices, which is not limited in the embodiments of the present application.

[0083] Figure 2 A schematic block diagram of a device 100 supporting multi-clock domain clock transfer provided by an embodiment of the present application is shown. The device 100 may correspond to Figure 1 The hybrid service bearing device C in the embodiment of the present invention. The device 100 includes: N clock domain interfaces (including a first clock domain interface 101 to an Nth clock domain interface 102), N frequency detectors (including a first frequency detector 103 to an Nth frequency detector 104), N filters (including a first filter 105 to an Nth filter 106), and N clock reconstructors (including a first clock reconstructor 107 to an Nth clock reconstructor 108).

[0084] Wherein, N is an integer greater than or equal to 2. The N clock domain interfaces correspond one-to-one to the N frequency detectors, the N filters, and the N clock reconstructors. The N frequency detectors are connected to N clock sources, respectively, and at least two of the N clock sources are different.

[0085] The i-th phase frequency detector among the N phase frequency detectors is used to receive a clock signal generated by a clock source connected to the i-th phase frequency detector, determine the i-th phase difference information between a common clock signal and the clock signal, and send the i-th phase difference information to the i-th filter among the N filters corresponding to the i-th phase frequency detector.

[0086] It should be understood that the common clock signal can be generated by a common clock generator and sent through a bus to each frequency detector and each clock reconstructor in the device 100. In addition, there is only one common clock signal in a device.

[0087] The i-th filter is used to receive the i-th phase difference information sent by the i-th phase and frequency detector, convert the i-th phase difference information into the i-th frequency difference information, and send the i-th frequency difference information to the i-th clock reconstructor corresponding to the i-th filter among the N clock reconstructors.

[0088] The i-th clock reconstructor is used to receive the i-th frequency difference information sent by the i-th filter, reconstruct the i-th network timing clock within the device according to the common clock signal and the i-th frequency difference information, and send the i-th network timing clock to the i-th clock domain interface among the N clock domain interfaces.

[0089] Here, the above i is an integer and satisfies 1≤i≤N.

[0090] Specifically, the N clock domain interfaces of the device correspond one-to-one to the N frequency detectors, N filters and N clock reconstructors inside the device. For example, the first clock domain interface 101 corresponds to the first frequency detector 103, the first filter 105, and the first clock reconstructor 107, and so on. The Nth clock domain interface 102 corresponds to the Nth frequency detector 104, the Nth filter 106, and the Nth clock reconstructor 108. They can process the clock signals from the N clock domain interfaces independently. The N frequency detectors are connected to N clock sources respectively, and at least two of the N clock sources are different. Here, it should be understood that a clock domain interface has only one clock source, and a clock source can be connected to multiple clock domain interfaces at the same time to provide clock signals for them. Therefore, the clock signals from the N clock domain interfaces in the embodiment of the present application can be completely different, or they can be partially the same, that is, the same clock signal comes from the same clock source, and the embodiment of the present application is not limited to this.

[0091] The above i is an integer and satisfies 1≤i≤N, that is, each of the N frequency detectors, N filters, N clock reconstructors and N clock domain interfaces can be used to perform the above operations. Specifically, each of the N frequency detectors can receive a common clock signal and a clock signal generated by a clock source of a clock domain interface corresponding to each frequency detector, and then determine the phase difference information between the common clock signal and the clock signal generated by the clock source of the clock domain interface corresponding to each frequency detector, so that the N frequency detectors can determine N phase difference information. Then, the N frequency detectors send the corresponding phase difference information to the filters corresponding to them respectively. After the N filters receive their respective phase difference information, they convert the phase difference information into frequency difference information, and then send it to the clock reconstructors corresponding to them respectively. After the N clock reconstructors receive their respective frequency difference information, they can reconstruct the network timing clock of the clock domain interface corresponding to them respectively according to the common clock signal and the received frequency difference information, and finally send it to the clock domain interface corresponding to them.

[0092] The above network timing clock should be understood as the same frequency signal after the clock signal of the clock source is filtered. The purpose of network element timing itself is to filter the reference source input from a certain interface and distribute it to other interfaces in the clock domain, so as to achieve network-level synchronization.

[0093] Since only one clock signal is supported within a device, the embodiment of the present application first calculates the phase difference information between the clock signals from different clock domains and the common clock signal, converts the phase difference information into frequency difference information, and then reconstructs the clock signal of the required clock domain based on the common clock signal at each clock source interface by the clock reconstructor. After receiving clock signals from multiple different clock sources, the common clock signal is still transmitted within the device, but the clock signals of different clock domains are reconstructed by the clock reconstructor at each clock source interface, and then sent to other clock domain interfaces of the clock domain, further realizing network-level clock synchronization. The above-mentioned device realizes clock transmission in multiple clock domains by extracting the difference between the clock signals of different clock sources and the common clock.

[0094] The device supporting multi-clock domain clock transmission in the embodiment of the present application obtains the phase difference information between the clock signal generated by the clock source of each clock domain interface and the common clock signal through a frequency detector and a phase detector, and then converts the phase difference information into frequency difference information through a filter. Finally, the clock signal of the required clock domain is synthesized through a clock reconstructor, and applied to the clock domain interface of each clock domain, so as to flexibly adapt to multiple different clock domains and realize a single device supporting multi-clock domain clock transmission at the same time. There is no need to add or replace equipment, and it can flexibly meet user needs.

[0095] It should be understood that in the embodiment of the present application, because the various devices are independent of each other, the clock signals of the above-mentioned N clock domains are also transmitted independently of each other. The transmission of the clock signals of the N clock domains can be serial or parallel, which is not limited in the embodiment of the present application.

[0096] In a specific implementation, after receiving two clock signals, the phase frequency detector can compare the rising edge (i.e., the first clock edge) phase of the two same-frequency clock signals through a logic circuit to obtain a phase difference signal, and then sample and quantize the phase difference signal through a high-frequency clock signal to obtain and output the phase difference information, which is a digital quantity. Optionally, the phase frequency detector (PFD) can use a double-D digital phase detector or a time-to-digital converter (TDC).

[0097] The filter is mainly composed of a digital filtering module and a conversion module. The digital filtering module can adopt a general 7th-order finite impulse response (Finite Impulse Response, FIR) filtering module. The filter takes the phase difference information as input, and the digital filtering module performs low-pass filtering on the phase difference information, and then the conversion module integrates the filtered phase difference information to obtain the frequency difference information. The final filter takes the frequency difference information as output. It should be understood that all processing in the middle of the filter is digital processing. In an embodiment of the present application, the filter can be an Ethernet Equipment Clock (EEC) filter, a Synchronous Digital Hierarchy Equipment Clock (SEC) filter or an Optical Transport Network Equipment Clock (OEC) filter, which is determined by the type of service. In addition, the filter can be implemented by digital signal processing (DSP) using a common finite impulse response (FIR) structure. This embodiment of the present application is not limited to this.

[0098] The clock reconstructor may be a direct digital frequency synthesizer (DDS) or a digital controlled oscillator (NCO), which is not limited in the present embodiment.

[0099] Optionally, the phase difference information and the frequency difference information may be encapsulated in a message for transmission. The message may be an Ethernet message, or a message encapsulated by a High-Level Data Link (HDLC) or a Generic Framing Procedure (GFP). In addition, the phase difference information and the frequency difference information may also be encapsulated in a message carrying a Virtual Local Area Network (VLAN) tag or a Multiprotocol Label Switching (MPLS) tag, etc., which is not limited in the embodiments of the present application.

[0100] Optionally, the encapsulation of the phase difference information and the frequency difference information may adopt two-layer encapsulation or three-layer encapsulation, which is not limited in the embodiments of the present application. Whether to adopt two-layer encapsulation or three-layer encapsulation depends on the forwarding technology. If two-layer forwarding is adopted, two-layer encapsulation must be adopted; if three-layer forwarding is selected, three-layer encapsulation must be adopted. It should be understood that the "layer" here refers to the layer in the Transmission Control Protocol / Internet Protocol (TCP / IP protocol), the second layer is the data link layer, and the third layer is the network layer. For different layers of message forwarding, the addressing method is different. The second layer is addressed by the Media Access Control (MAC) address, and the third layer is addressed by the Internet Protocol (IP) address.

[0101] Optionally, the encapsulation of phase difference information and frequency difference information can also adopt any one of the frame structure in time division multiplexing mode (Testing Data Management, TDM), the frame structure in asynchronous transfer mode (Asynchronous Transfer Mode, ATM), virtual container 4 (Virtual Containers-4, VC-4), the frame structure in optical transport network (Optical Transport Network, OTN), GFP frame, synchronous transfer mode (Synchronous Transfer Mode, STM) frame, and the embodiments of the present application are not limited to this.

[0102] It should be understood that the internal system of the above device can be implemented by multiple boards plugged into a common backplane. Different boards also need management and configuration channels. Currently, 100M Ethernet or 1G Ethernet is often used to achieve communication within the device.

[0103] It should also be understood that the transmission path of the phase difference information and the frequency difference information is a system bus, which may include but is not limited to a Fast Ethernet (FE) / Gigabit Ethernet (GE) interface, a local bus, an Inter-Integrated Circuit (I2C) bus, a Serial Peripheral Interface (SPI) bus, a High-level Data Link Control (HDLC) bus, and other common forms within the system. The embodiments of the present application are not limited to this.

[0104] As an optional embodiment, the device further includes: an N+1th phase frequency detector and an external synchronization interface, wherein the N+1th phase frequency detector is connected to an external clock source via the external synchronization interface.

[0105] It should be understood that the external synchronization interface is a device interface that does not carry services but only carries clock signals. If the interface is connected to a high-precision clock source, it can be used to use the clock signal of the high-precision clock source as the signal of the network timing clock in the internal clock domain of the device; if the interface is connected to a test device, it can be used to extract the clock signal of a certain clock domain and observe the performance of the clock signal. Here, the external clock source should be understood as a clock source connected to the external synchronization interface. The clock source can be one of the N clock sources mentioned above, or other clock sources, and the embodiments of the present application do not limit this.

[0106] The N+1th frequency detector is used to receive the clock signal generated by the external clock source, determine the N+1th phase difference information between the clock signal generated by the external clock source and the common clock signal, and send the N+1th phase difference information to the jth filter among the N filters.

[0107] The j-th filter is used to receive the N+1-th phase difference information sent by the N+1-th frequency detector, convert the N+1-th phase difference information into the N+1-th frequency difference information, and send the N+1-th frequency difference information to the j-th clock reconstructor corresponding to the j-th filter among the N clock reconstructors.

[0108] The jth clock reconstructor is used to receive the N+1th frequency difference information sent by the jth filter, reconstruct the N+1th network timing clock within the device according to the common clock signal and the N+1th frequency difference information, and send the N+1th network timing clock to the jth clock domain interface among the N clock domain interfaces.

[0109] Here, j is an integer and satisfies 1≤j≤N.

[0110] Here, j and i may be equal or unequal, and this is not limited in the embodiments of the present application.

[0111] Specifically, the device also includes an N+1th phase frequency detector and an external synchronization interface, which can transmit the clock signal from the external synchronization interface. The N+1th phase frequency detector receives the clock signal generated by the external clock source connected to the external synchronization interface, determines the N+1th phase difference information between the clock signal generated by the clock source of the external synchronization interface and the common clock signal, and sends it to the jth filter among the above-mentioned N filters. The jth filter converts the N+1th phase difference information into the N+1th frequency difference information, and sends the N+1th frequency difference information to the jth clock reconstructor corresponding to the jth filter among the N clock reconstructors. The jth clock reconstructor can reconstruct the network timing clock of the external synchronization interface in the device, and send it to the clock domain interface corresponding to the jth clock reconstructor among the N clock domain interfaces.

[0112] It should be understood that the N+1th phase frequency detector can send phase difference information according to the needs of the clock domain interface. The clock synchronization of any synchronous network may need to obtain the clock signal of the external synchronization source through the external synchronization interface, so any filter can process the phase difference information between the clock source of the external synchronization interface and the common clock. The N+1th phase frequency detector can send the generated N+1th phase difference information to the corresponding filter according to the needs of the clock domain interface.

[0113] In this way, the device can receive and reconstruct the clock signal from the external synchronization interface while supporting the transmission of clock signals from multiple different clock domains, ensuring that each clock domain interface of the device can receive the clock signal of the external synchronization interface as needed. If the clock signal of the external synchronization interface is more accurate than the clock signal of each clock domain interface, each clock domain interface can use the clock signal of the external synchronization interface as its own network timing clock, thereby improving the accuracy of the clock signal in the device.

[0114] As an optional embodiment, the device also includes: an N+1th clock reconstructor.

[0115] The kth filter among the N filters is also used to send the kth frequency difference information generated by the kth filter to the N+1th clock reconstructor.

[0116] The N+1th clock reconstructor is used to receive the kth frequency difference information sent by the kth filter, reconstruct the kth network timing clock in the device according to the kth frequency difference information, and send the kth network timing clock to the external synchronization interface.

[0117] Here, k is an integer and satisfies 1≤k≤N.

[0118] Here, k and i may be equal or unequal, and k and j may be equal or unequal, and this embodiment of the present application does not limit this.

[0119] In this embodiment, the user can test the performance of the clock signal inside the device as needed. Specifically, when the device is docked with another device, it is necessary to test the performance of the clock signal inside the device. Alternatively, a certain test device (for example, an instrument) is directly used to connect the device. Then, the device needs to output the clock signal from multiple clock domains inside the device through the external synchronization interface, or output any one of the clock signals according to the needs of the user. After the device knows which clock domain interface's network timing clock is being tested, it will send the kth frequency difference information between the tested clock domain interface and the common clock signal to the N+1th clock reconstructor through the filter corresponding to the tested clock domain interface (i.e., the kth filter), and the N+1th clock reconstructor will reconstruct the corresponding kth network timing clock and send it to the external synchronization interface. The above docking device or test device can obtain different clock signals of the device through the external synchronization interface to test the performance of the clock signal inside the device.

[0120] It should be understood that the testing device or docking device can choose to test the clock source of a specific clock domain interface among the above-mentioned N clock domain interfaces as needed, or can test the clock source of each clock domain interface among the above-mentioned N clock domain interfaces in turn, and the embodiments of the present application are not limited to this.

[0121] Therefore, through the device of the embodiment of the present application, clock signals from multiple different clock domains can not only be transmitted in each clock domain interface of the device, but also be transmitted to other devices connected to the device through the external synchronization interface, thereby realizing the testing of the internal clock signal performance of the device.

[0122] As an optional embodiment, Figure 3 As shown, the device further includes: an input selector 109 .

[0123] The i-th frequency and phase detector is specifically used for:

[0124] The i-th phase difference value information is sent to the input selector.

[0125] The input selector is used to receive the i-th phase difference information sent by the i-th phase frequency detector, and based on the corresponding relationship between the i-th phase frequency detector and the i-th filter, send the i-th phase difference information to the i-th filter.

[0126] As an optional embodiment, the input selector 109 is further used for:

[0127] When the clock sources of the N clock domain interfaces correspond to M types of services, M phase difference information is selected from the phase difference information sent by the N frequency detectors and phase detectors, and the M phase difference information corresponds one-to-one to the M types of services, and based on the correspondence between the N frequency detectors and the N filters, the corresponding phase difference information is sent to each of the N filters, where M is an integer less than N.

[0128] Specifically, the N clock domain interfaces may include clock domain interfaces of the same service, that is, some of the N services corresponding to the N clock domain interfaces are the same. The same services among the N services are divided into one service, and it is assumed that the N services include M types of services. Therefore, an input selector is required to perform a source selection operation on the phase difference information of the clock sources from the N services, and select M phase difference information corresponding to M types of services from the N phase difference information corresponding to the N services, so that the same type of services among the N services can track the optimal clock source in the type.

[0129] After the input selector receives N phase difference information corresponding to N clock sources, M phase difference information can be selected from the N phase difference information. If the N phase difference information respectively carry synchronization status information (Synchronization Status Message, SSM), then the input selector can automatically select the source according to the SSM, and the source selection operation can be performed according to the source selection protocol, such as the SSM protocol, wherein the SSM protocol can be any version of ITU-T G.8264. If the N phase difference information does not carry synchronization status information, the input selector can also manually select the source according to the user's instructions, and the embodiment of the present application is not limited to this.

[0130] After the source selection operation is completed, the input selector will select M phase difference information, which corresponds to the M services one by one, that is, the clock domain interfaces of the same service in the N clock domain interfaces all use the phase difference information corresponding to the same clock source selected by the input selector. Then, based on the correspondence between the M phase difference information and the N filters, the input selector sends the corresponding phase difference information to each of the N filters.

[0131] In a specific implementation, the input selector can be processed according to the requirements of the upper layer protocol. For example, the phase frequency detector will carry the identification information of the corresponding filter in the phase difference information, and when configured in the input selector, the input selector can determine the corresponding relationship between the phase frequency detector and the filter according to the phase difference information. The identification information is only used to distinguish each filter, and can be an identifier, port number, etc. of the filter corresponding to the phase frequency detector, and the embodiment of the present application does not limit this.

[0132] It should be understood that the above-mentioned input selector can be implemented in the device through software of a central processing unit (CPU) or through hardware of a field programmable gate array (FPGA), and the embodiments of the present application are not limited to this.

[0133] As an optional embodiment, Figure 3 As shown, the device further includes: an output selector 110 .

[0134] The i-th filter is specifically used for:

[0135] The i-th frequency difference information is sent to the output selector.

[0136] The output selector is used to receive the i-th frequency difference information sent by the i-th filter, and based on the corresponding relationship between the i-th filter and the i-th clock reconstructor, send the i-th frequency difference information to the i-th clock reconstructor.

[0137] Specifically, the output selector can transmit the above frequency difference information to N clock reconstructors by broadcast, multicast or unicast. Optionally, the output selector can construct a multicast message carrying the frequency difference information and send it to each clock reconstructor. Optionally, the output selector can also send the corresponding frequency difference information only to the clock reconstructor corresponding to the service that needs to transmit the clock according to the user's settings, which is not limited in the embodiment of the present application.

[0138] In addition, if the performance of the internal clock signal of the device needs to be measured through the external synchronization interface, the output selector can also be used to send the N+1th frequency difference information corresponding to the clock signal to be measured to the N+1th clock reconstructor.

[0139] In the specific implementation, the frequency difference information sent by the output selector is encapsulated in a message, which can carry the source address and the destination address. The message itself can be forwarded. The device has a device dedicated to message switching. By adding different addresses to the front of each frequency difference information, forwarding can be achieved through the message switching device. In this way, the output selector can forward each frequency difference information to each clock reconstructor according to the corresponding relationship.

[0140] It should be understood that the above-mentioned output selector can be implemented in the device through software of a central processing unit (CPU) or through hardware of a field programmable gate array (FPGA), and the embodiments of the present application do not limit this.

[0141] As an optional embodiment, the device 100 further includes:

[0142] The common clock generator is used to generate the common clock signal before determining the i-th phase difference information between the common clock signal and the clock signal, and send the common clock signal to the i-th frequency and phase detector and the i-th clock reconstructor.

[0143] It should be understood that the common clock signal is generated by the common clock generator and sent to each frequency detector and each clock reconstructor through the bus, and there is only one common clock signal in one device. Optionally, the common clock signal can be implemented using a general phase-locked loop technology.

[0144] Optionally, the device 100 further includes:

[0145] The system bus is used to connect the N frequency detectors, the N filters, the N clock reconstructors and the N clock domain interfaces, and bidirectionally transmit the phase difference information determined by the N frequency detectors and the frequency difference information converted by the N filters.

[0146] The “connection” involved in this embodiment and subsequent embodiments should be understood as an electrical connection, not a direct connection, and this connection can be indirectly achieved through a third-party device.

[0147] The device supporting multi-clock domain clock transmission in the embodiment of the present application obtains the phase difference information between the clock signal generated by the clock source of each clock domain interface and the common clock signal through a frequency detector and a phase detector, and then converts the phase difference information into frequency difference information through a filter. Finally, the clock signal of the required clock domain is synthesized through a clock reconstructor, and applied to the clock domain interface of each clock domain, so as to flexibly adapt to multiple different clock domains and realize a single device supporting multi-clock domain clock transmission at the same time. There is no need to add or replace equipment, and it can flexibly meet user needs.

[0148] Figure 4 FIG. 2 shows a schematic block diagram of another device 200 supporting multi-clock domain clock transfer provided by an embodiment of the present application. The device 200 may correspond to Figure 1 The hybrid service bearing device C in the embodiment of the present invention can be understood as Figure 2 or Figure 3 A specific implementation of the device 100. Figure 4 As shown, the device 200 includes:

[0149] The Ethernet Physical Layer Network (ETY) clock domain interface is used to send a clock signal generated by a clock source of a synchronous Ethernet line clock to the first phase and frequency detector PFD.

[0150] The STM-N (Synchronous Transport Module level N) clock domain interface is used to send a clock signal generated by a clock source of a synchronous digital hierarchy SDH line clock to the second PFD.

[0151] The first PFD is used to determine the first phase difference information between the common clock signal and the clock signal of the synchronous Ethernet line clock, and send the first phase difference information to the Ethernet equipment clock EEC filtering module.

[0152] The second PFD is used to determine the second phase difference information between the common clock signal and the clock signal of the SDH line clock, and send the second phase difference information to the synchronous digital hierarchy equipment clock SEC filtering module.

[0153] The EEC filtering module is used to perform low-pass filtering on the first phase difference information, convert the first phase difference information into the first frequency difference information between the common clock signal and the network timing clock of the ETY clock domain interface, and send the first frequency difference information to the first DDS. Preferably, the above-mentioned EEC filtering module is used to perform low-pass filtering on the first phase difference information in accordance with standard ITU-T G.8262.

[0154] The SEC filtering module is used to perform low-pass filtering on the second phase difference information, convert the second phase difference information into the second frequency difference information between the common clock and the network timing clock of the STM-N clock domain interface, and send the second frequency difference information to the second DDS. Preferably, the above-mentioned SEC filtering module is used to perform low-pass filtering on the second phase difference information in accordance with standard ITU-T G.813.

[0155] The first direct digital frequency synthesizer DDS is used to receive the first frequency difference information sent by the EEC filtering module, reconstruct the network timing clock of the ETY clock domain interface according to the common clock signal and the first frequency difference information, and send it to the ETY clock domain interface for application to the corresponding business flow interface.

[0156] The second DDS is used to receive the second frequency difference information sent by the SEC filtering module, reconstruct the network timing clock of the STM-N clock domain interface according to the common clock signal and the second frequency difference information, and send it to the STM-N clock domain interface for application to the corresponding service flow interface.

[0157] It should be understood that the first DDS and the second DDS are the above Figure 2 or Figure 3 A specific implementation of a clock reconstructor in .

[0158] The device supporting multi-clock domain clock transmission in the embodiment of the present application obtains the phase difference information between the clock signal generated by the clock source of each clock domain interface and the common clock signal through a frequency detector and a phase detector, and then converts the phase difference information into frequency difference information through a filter. Finally, the clock signal of the required clock domain is synthesized through a clock reconstructor, and applied to the clock domain interface of each clock domain, so as to flexibly adapt to multiple different clock domains and realize a single device supporting multi-clock domain clock transmission at the same time. There is no need to add or replace equipment, and it can flexibly meet user needs.

[0159] As an optional embodiment, the device 200 further includes: a common clock generator, which is used to generate a common clock signal and send the common clock signal to the first PFD, the second PFD and the first DDS, the second DDS through a bus. The device 200 shares a common clock signal.

[0160] As an optional embodiment, the above device 200 also includes: a third PFD and an external synchronization interface.

[0161] The common clock generator is also used to send a common clock signal to the third PFD.

[0162] The third PFD is used to determine third phase difference information between the common clock signal and the clock signal of the external synchronization interface, and send the third phase difference information to the EEC filtering module or the SEC filtering module.

[0163] It should be understood that the clock signal of the external synchronous interface can be processed by either the SEC filtering module or the EEC filtering module, and the device can determine to which filtering module the clock signal of the external synchronous interface is sent according to business needs.

[0164] If the clock signal of the external synchronization interface is a clock signal generated by a clock source of a synchronous Ethernet line clock, the EEC filter module can also be used to perform low-pass filtering on the third phase difference information, convert the third phase difference information into third frequency difference information between the common clock and the network timing clock of the ETY clock domain interface, and send the third frequency difference information to the first DDS. Preferably, the above-mentioned EEC filter module is used to perform low-pass filtering on the third phase difference information in accordance with standard ITU-T G.8262.

[0165] The first DDS can also be used to receive the third frequency difference information sent by the EEC filter module, and reconstruct the network timing clock of the external synchronization interface according to the common clock signal and the third frequency difference information, and apply it to the corresponding business flow interface.

[0166] If the clock signal of the external synchronization interface is a clock signal generated by the clock source of the SDH line clock, the SEC filtering module can also be used to perform low-pass filtering on the third phase difference information, convert the third phase difference information into the third frequency difference information between the common clock and the network timing clock of the STM-N clock domain interface, and send the third frequency difference information to the second DDS. Preferably, the above-mentioned SEC filtering module is used to perform low-pass filtering on the third phase difference information in accordance with standard ITU-TG.813.

[0167] The second DDS can also be used to receive the third frequency difference information sent by the SEC filtering module, and reconstruct the network timing clock of the external synchronization interface according to the common clock signal and the third frequency difference information, and apply it to the corresponding business flow interface.

[0168] As an optional embodiment, the above device 200 also includes: a third DDS.

[0169] The common clock generator is also used to send a common clock signal to the third DDS.

[0170] The EEC filter module is also used to send the first frequency difference information to the third DDS.

[0171] The SEC filtering module is also used to send second frequency difference information to the third DDS.

[0172] The third DDS is used to receive the first frequency difference information sent by the EEC filtering module or the second frequency difference information sent by the SEC filtering module, reconstruct the network timing clock of the corresponding clock domain interface according to the first frequency difference information or the second frequency difference information and the common clock signal, and send it to the external synchronization interface.

[0173] As an optional embodiment, the above device 200 further includes: an input selector.

[0174] The first PFD is specifically used to send the first phase difference information to the input selector.

[0175] The second PFD is specifically used to send the second phase difference information to the input selector.

[0176] The third PFD is specifically used to send the third phase difference information to the input selector.

[0177] The input selector is used to receive the first phase difference information, the second phase difference information and the third phase difference information, and respectively send the first phase difference information to the Ethernet device clock EEC filtering module, send the second phase difference information to the synchronous digital system device clock SEC filtering module, and send the third phase difference information to the SEC filtering module or the EEC filtering module.

[0178] As an optional embodiment, the above device 200 also includes: an output selector.

[0179] The EEC filter module is specifically configured to send the first frequency difference information or the third frequency difference information to the output selector.

[0180] The SEC filtering module is specifically used to send the second frequency difference information or the third frequency difference information to the output selector.

[0181] The output selector is used to receive first frequency difference information, second frequency difference information and third frequency difference information, and respectively send the first frequency difference information to the first DDS, send the second frequency difference information to the second DDS, and send the third frequency difference information to the first DDS or the second DDS as needed.

[0182] The output selector may also send the first frequency difference information or the second frequency difference information to the third DDS, so that other equipment (such as a test equipment) can measure the performance of the internal clock signal of the equipment through an external synchronization interface.

[0183] Combined with the above Figures 1 to 4 The device supporting multi-clock domain clock transmission in the embodiment of the present application is described in detail. Figure 5 A method for supporting multi-clock domain clock transfer according to an embodiment of the present application is described.

[0184] Figure 5 FIG. 3 is a schematic diagram of a method 300 for supporting multi-clock domain clock transfer according to an embodiment of the present application. The method 300 may be performed by the above-mentioned device 100 or device 200. Figure 5 As shown, the method 300 includes:

[0185] S310, an i-th frequency detector among N phase frequency detectors receives a clock signal generated by a clock source connected to the i-th frequency detector, determines an i-th phase difference information between a common clock signal and the clock signal, and sends the i-th phase difference information to an i-th filter among N filters corresponding to the i-th frequency detector.

[0186] S320, the i-th filter receives the i-th phase difference information sent by the i-th phase and frequency detector, converts the i-th phase difference information into i-th frequency difference information, and sends the i-th frequency difference information to the i-th clock reconstructor corresponding to the i-th filter among the N clock reconstructors.

[0187] S330, the i-th clock reconstructor receives the i-th frequency difference information sent by the i-th filter, reconstructs the i-th network timing clock within the device according to the common clock signal and the i-th frequency difference information, and sends the i-th network timing clock to the i-th clock domain interface among the N clock domain interfaces.

[0188] Among them, N is an integer greater than or equal to 2, the N clock domain interfaces correspond one-to-one to the N frequency detectors, the N filters and the N clock reconstructors, respectively, the N frequency detectors are connected to N clock sources, respectively, and at least two of the N clock sources are different, and i is an integer and satisfies 1≤i≤N.

[0189] As an optional embodiment, the method further includes:

[0190] The N+1th phase frequency detector receives a clock signal generated by an external clock source, determines the N+1th phase difference information between the clock signal generated by the external clock source and the common clock signal, and sends the N+1th phase difference information to the jth filter among the N filters.

[0191] The j-th filter receives the N+1-th phase difference information sent by the N+1-th frequency detector and phase detector, converts the N+1-th phase difference information into the N+1-th frequency difference information, and sends the N+1-th frequency difference information to the j-th clock reconstructor corresponding to the j-th filter among the N clock reconstructors.

[0192] The jth clock reconstructor receives the N+1th frequency difference information sent by the jth filter, reconstructs the N+1th network timing clock within the device according to the common clock signal and the N+1th frequency difference information, and sends the N+1th network timing clock to the jth clock domain interface among the N clock domain interfaces.

[0193] The N+1th frequency detector and phase detector are connected to the external clock source via an external synchronization interface, and j is an integer and satisfies 1≤j≤N.

[0194] In this way, the device can receive and reconstruct the clock signal from the external synchronization interface while supporting the transmission of clock signals from multiple different clock domains, ensuring that each clock domain interface of the device can receive the clock signal of the external synchronization interface as needed. If the clock signal of the external synchronization interface is more accurate than the clock signal of each clock domain interface, each clock domain interface can use the clock signal of the external synchronization interface as its own network timing clock, thereby improving the accuracy of the clock signal in the device.

[0195] As an optional embodiment, the method further includes:

[0196] The kth filter among the N filters sends the kth frequency difference information generated by the kth filter to the N+1th clock reconstructor.

[0197] The N+1th clock reconstructor receives the kth frequency difference information sent by the kth filter, reconstructs the kth network timing clock in the device according to the kth frequency difference information, and sends the kth network timing clock to the external synchronization interface, wherein k is an integer and satisfies 1≤k≤N.

[0198] Specifically, the kth filter can send the kth frequency difference information to the kth clock reconstructor in addition to the kth frequency difference information. In this way, the clock signals from multiple different clock domains can not only be transmitted on each clock domain interface of the device, but also be transmitted to other devices connected to the device through the external synchronization interface, thereby realizing the test of the internal clock signal performance of the device.

[0199] As an optional embodiment, sending the i-th phase difference information to the i-th filter corresponding to the i-th frequency and phase detector among the N filters includes:

[0200] The i-th phase frequency detector sends the i-th phase difference information to the input selector.

[0201] The input selector receives the i-th phase difference information sent by the i-th phase frequency detector, and sends the i-th phase difference information to the i-th filter based on the corresponding relationship between the i-th phase frequency detector and the i-th filter.

[0202] As an optional embodiment, after the input selector receives the i-th phase difference information sent by the i-th frequency and phase detector, the method further includes:

[0203] When the clock sources of the N clock domain interfaces correspond to M types of services, the input selector selects M phase difference information from the phase difference information sent by the N frequency and phase detectors, and the M phase difference information corresponds one-to-one to the M types of services.

[0204] The step of sending the i-th phase difference information to the i-th filter includes:

[0205] Based on the corresponding relationship between the N frequency and phase detectors and the N filters, corresponding phase difference information is sent to each of the N filters.

[0206] Here, M is an integer smaller than N.

[0207] As an optional embodiment, sending the i-th frequency difference information to the i-th clock reconstructor corresponding to the i-th filter among the N clock reconstructors includes:

[0208] The i-th filter sends the i-th frequency difference information to the output selector.

[0209] The output selector receives the i-th frequency difference information sent by the i-th filter, and based on the corresponding relationship between the i-th filter and the i-th clock reconstructor, sends the i-th frequency difference information to the i-th clock reconstructor.

[0210] As an optional embodiment, before determining the i-th phase difference information between the common clock signal and the clock signal, the method further includes:

[0211] The common clock generator generates the common clock signal and sends the common clock signal to the i-th phase and frequency detector and the i-th clock reconstructor.

[0212] The method for supporting clock transfer in multiple clock domains in the embodiment of the present application obtains the phase difference information between the clock signal generated by the clock source of each clock domain interface and the common clock signal through a frequency detector and a phase detector, and then converts the phase difference information into frequency difference information through a filter. Finally, the clock signal of the required clock domain is synthesized through a clock reconstructor and applied to the clock domain interface of each clock domain, so as to flexibly adapt to multiple different clock domains and realize a single device supporting clock transfer in multiple clock domains at the same time. There is no need to add or replace equipment, and it can flexibly meet user needs.

[0213] It should be understood that "one embodiment" or "an embodiment" mentioned in the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner.

[0214] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0215] Those of ordinary skill in the art will appreciate that the various method steps and units described in the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the steps and components of each embodiment have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Those of ordinary skill in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0216] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0217] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, or it can be an electrical, mechanical or other form of connection.

[0218] The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiments of the present application.

[0219] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0220] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), disk or optical disk and other media that can store program codes.

[0221] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A communication device supporting multi-clock domain clock transfer, characterized in that: include: N frequency detectors, N filters, N clock reconstructors, N clock domain interfaces, the N+1th frequency detector and an external synchronization interface, where N is an integer greater than or equal to 2; wherein, The N frequency and phase detectors are used for: receiving N clock signals, at least two of the N clock signals being different; and Respectively determining N phase difference information between the N clock signals and a common clock signal; The N filters are used to obtain N frequency difference information according to the N phase difference information; The N clock reconstructors are used to: Reconstructing N network timing clocks in the communication device according to the common clock signal and the N frequency difference information; and Sending the N network timing clocks to the N clock domain interfaces respectively, wherein the N network timing clocks correspond to the N clock domain interfaces one by one; The N+1th frequency detector and phase detector are used for: receiving an N+1th clock signal generated from an external clock source; and Determine the N+1th phase difference information between the N+1th clock signal and the common clock signal; the jth filter among the N filters is used for: According to the N+1th phase difference information, obtaining the N+1th frequency difference information; and Sending the (N+1)th frequency difference information to the jth clock reconstructor corresponding to the jth filter among the N clock reconstructors; wherein, The j-th clock reconstructor is used for: Receiving the N+1th frequency difference information sent by the jth filter; reconstructing the N+1th network timing clock in the device according to the common clock signal and the N+1th frequency difference information; and Sending the (N+1)th network timing clock to the jth clock domain interface among the N clock domain interfaces; Wherein, j is an integer and satisfies 1≤j≤N.

2. The communication device according to claim 1, characterized in that The device further comprises: an N+1th clock reconstructor, The kth filter among the N filters is further used to send the kth frequency difference information generated by the kth filter to the N+1th clock reconstructor; The N+1th clock reconstructor is used to receive the kth frequency difference information sent by the kth filter, reconstruct the kth network timing clock in the device according to the kth frequency difference information, and send the kth network timing clock to the external synchronization interface; Wherein, k is an integer and satisfies 1≤k≤N.

3. The communication device according to claim 1 or 2, characterized in that: The device also includes: an input selector coupled to the N frequency detectors and the N filters, The N frequency and phase detectors are further used for: Sending the N phase difference value information to the input selector; The input selector is used to receive the N phase difference information, and based on the corresponding relationship between the N frequency and phase detectors and the N filters, send the N phase difference information to the N filters respectively.

4. The communication device according to claim 3, characterized in that The input selector is also used to: When the clock sources of the N clock domain interfaces correspond to M types of services, M phase difference information is selected from the phase difference information sent by the N frequency detectors and phase detectors, and the M phase difference information corresponds one-to-one to the M types of services, and based on the correspondence between the N frequency detectors and the N filters, the corresponding phase difference information is sent to each of the N filters, wherein M is an integer less than N.

5. The communication device according to claim 1 or 2, characterized in that: The device further comprises: an output selector, The N filters are further used to: Sending the N frequency difference information to the output selector; The output selector is used to: receiving the N frequency difference information sent by the N filters; and Based on the corresponding relationship between the N filters and the N clock reconstructors, the N frequency difference information is sent to the N clock reconstructors respectively.

6. The communication device according to claim 1 or 2, characterized in that: The device further comprises: a common clock generator, configured to: generating the common clock signal; and The common clock signal is sent to the N frequency and phase detectors and the N clock reconstructors respectively.

7. The communication device according to claim 1 or 2, characterized in that: The communication device is any one of the following devices: code division multiple access CDMA device, wideband code division multiple access WCDMA device, general packet radio service GPRS device, long term evolution LTE device, LTE frequency division duplex FDD device, LTE time division duplex TDD device or universal mobile telecommunications system UMTS device.

8. The communication device according to claim 1 or 2, characterized in that: The communication device is a network device or a terminal device.

9. A communication system, characterized in that: A communication device comprising any one of claims 1 to 8.

10. A method for supporting multi-clock domain clock transfer, characterized in that: include: Receiving N clock signals, at least two of the N clock signals are different, and N is an integer greater than or equal to 2; Respectively determining N phase difference information between the N clock signals and a common clock signal; Obtaining N frequency difference information according to the N phase difference information; Reconstructing N network timing clocks in the communication device according to the common clock signal and the N frequency difference information; as well as Sending the N network timing clocks to the N clock domain interfaces respectively, wherein the N network timing clocks correspond to the N clock domain interfaces one by one; Receive the N+1th clock signal generated by an external clock source; Acquire N+1th frequency difference information according to the N+1th phase difference information between the N+1th clock signal and the common clock signal; reconstructing the N+1th network timing clock in the device according to the common clock signal and the N+1th frequency difference information; and The N+1th network timing clock is sent to one clock domain interface among the N clock domain interfaces.

11. The method according to claim 10, characterized in that The method further comprises: According to the kth frequency difference information among the N frequency difference information, a kth network timing clock is reconstructed in the device, and the kth network timing clock is sent to an external synchronization interface, wherein k is an integer and satisfies 1≤k≤N.

12. The method according to claim 10 or 11, characterized in that: When the clock sources of the N clock domain interfaces correspond to M types of services, the N phase difference value information includes M phase difference value information, and the M phase difference value information corresponds one-to-one to the M types of services; Wherein, the M is an integer smaller than the N.

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