Device and method for controlling switching

Abstract

The present invention relates to a device and method for controlling the switching of a semiconductor power switch for supplying current to a load from a conducting state to a non-conducting state or from a non-conducting state to a conducting state, wherein the device receives an input signal for driving the semiconductor power switch. The present invention: - senses the differential value of a drain-source current flowing through the semiconductor power switch so as to obtain a voltage representing the sensed differential value of the drain-source current, - amplifies the voltage representing the sensed differential value of the drain-source current, - adds the amplified voltage representing the sensed differential value of the drain-source current to the input signal during a given time period.

Description

Technical Field

[0001] The present invention generally relates to an apparatus and method for controlling switching of at least one first power semiconductor switch providing current to a load. Background Art

[0002] The classic gate driver circuit contains fixed positive and negative voltage / current sources, which are called V for the positive voltage and V for the negative voltage. cc and V for negative voltages ee , both are related to the source of the semiconductor switch. The power semiconductor switch gate is connected to either supply rail with the help of a switch and an optional gate resistor, depending on the desired state of the semiconductor switch. To turn on the semiconductor switch, a positive voltage / current source is connected to the gate control of the semiconductor switch, and to turn off the semiconductor switch, a negative voltage / current source is connected to the gate control of the device.

[0003] Today, the switching frequencies of power converters are increasing. Wide-bandgap devices such as GaN and SiC devices offer faster switching capabilities than traditional technologies.

[0004] Wide bandgap power semiconductor devices are capable of switching at high speeds, for example above 10 V / ns. This reduces switching losses, allowing the use of higher switching frequencies.

[0005] For example, high switching speeds can generate voltage overshoots between the drain and source of power semiconductor transistors due to wiring stray inductance increasing switching losses and overstressing the transistors. Overshoots can also generate conducted and radiated EMI.

[0006] Several techniques applied to gate driver circuits are used to reduce switching speed (voltage and current transient rates) and / or voltage overshoot and ringing.

[0007] Passive techniques basically consist of changing the switching behavior of the power semiconductor switch by inserting passive components, changing the external gate resistor and the voltage / current source values. These techniques can be used to adjust the switching speed of the semiconductor switch. However, such permanent modifications to the gate driver circuit affect the performance of the power semiconductor switch. In addition, the switching characteristics depend on the operating point of the power semiconductor switch. Summary of the invention

[0008] An object of the present invention is to allow fast switching with low voltage overshoot and reduced ringing at the end of switching during turn-on or turn-off by using an effective controlled feedback signal injected into the gate driver circuit.

[0009] To this end, the present invention relates to a device for controlling the switching of a semiconductor power switch for supplying current to a load from a conducting state to a non-conducting state or from a non-conducting state to a conducting state, the device receiving an input signal intended to drive the semiconductor power switch, wherein the device comprises:

[0010] - means for sensing a differential value of a drain-source current flowing through the semiconductor power switch in order to obtain a voltage representative of the sensed differential value of the drain-source current,

[0011] - means for amplifying a voltage representing a differential value of the sensed drain-source current,

[0012] - means for adding an amplified voltage representing a differential value of the sensed drain-source current to the input signal during a given time period.

[0013] The present invention also relates to a method for controlling the switching of a semiconductor power switch for supplying current to a load from a conducting state to a non-conducting state or from a non-conducting state to a conducting state, wherein the method comprises the following steps:

[0014] - receiving an input signal intended to drive a semiconductor power switch, wherein the device comprises:

[0015] - sensing a differential value of a drain-source current flowing through the semiconductor power switch so as to obtain a voltage representing the sensed differential value of the drain-source current,

[0016] - amplifying a voltage representing the differential value of the sensed drain-source current,

[0017] - Adding an amplified voltage representing the differential value of the sensed drain-source current to the input signal during a given time period.

[0018] Thus, the present invention reduces current transient rate and / or voltage overshoot.

[0019] According to particular characteristics, the means for sensing the differential value of the drain-source current flowing through the semiconductor power switch consist of a Rogowski coil.

[0020] Therefore, compared to current sensors that require a differential block, no additional circuitry is required. In addition, the Rogowski coil is able to measure the differential value contactlessly and is independent of the switch parasitic inductance.

[0021] According to a particular feature, the given time period is the sum of the gate transition time, the voltage transition time and the current transition time plus a predetermined margin.

[0022] Therefore, the current sensor controls the semiconductor power switch only during the transition period, avoiding any surges during the remaining switching period.

[0023] According to a particular feature, the semiconductor power switch is included in a buck converter.

[0024] According to a particular feature, the semiconductor power switch is included in a boost converter.

[0025] According to a specific feature, the semiconductor power switch is included in a half-bridge configuration, which includes a first semiconductor power switch and a second semiconductor power switch, and the switching of each semiconductor power switch is controlled by a corresponding device for controlling the switching from a conducting state to a non-conducting state or from a non-conducting state to a conducting state.

[0026] Features of the present invention will become more apparent from a reading of the following description of exemplary embodiments, which is made with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] [ Figure 1 ]

[0028] Figure 1 represents an example of an architecture in which a half-bridge configuration of the present invention may be implemented.

[0029] [ Figure 2 ]

[0030] Figure 2 An example of an architecture of a buck converter in which the present invention may be implemented is shown.

[0031] [ Figure 3 ]

[0032] Figure 3 An example of an architecture of a boost converter in which the present invention may be implemented is shown.

[0033] [ Figure 4 ]

[0034] Figure 4 An example of a current differential sensor used in the present invention is shown.

[0035] [ Figure 5 ]

[0036] Figure 5 A first example of an electronic circuit of a gate trajectory control device according to the invention is shown.

[0037] [ Figure 6 ]

[0038] Figure 6 An example of an electronic circuit showing a feedback amplifier of a gate trajectory control device according to the invention.

[0039] [ Figure 7a ]

[0040] Figure 7a A timing diagram showing signals provided in accordance with the present invention.

[0041] [ Figure 7b ]

[0042] Figure 7b A timing diagram showing signals provided in accordance with the present invention.

[0043] [ Figure 8 ]

[0044] Figure 8 Detailed timing diagram showing current and voltage across a power semiconductor switch during switch-off when the present invention is implemented and not implemented.

[0045] [ Fig. 9 ]

[0046] Fig. 9 Detailed timing diagram showing current and voltage across a power semiconductor switch during switch-on when the present invention is implemented and not implemented.

[0047] [ Fig.10 ]

[0048] Fig.10 A second example of the architecture of the gate trajectory control device according to the present invention is shown.

[0049] [ Fig.11 ]

[0050] Fig.11 An algorithm executed by a gate trajectory control device according to a second example of a gate trajectory control device is shown. DETAILED DESCRIPTION

[0051] Figure 1 represents an example of an architecture in which a half-bridge configuration of the present invention may be implemented.

[0052] exist Figure 1 In the example, a first gate track control device consisting of a current differential value sensing device 10a, a feedback amplifier 11a, a blanking circuit 12a, a summing circuit 13a and a buffer 14a controls the switching of a power semiconductor switch S1, and a second gate track control device consisting of a current differential value sensing device 10b, a feedback amplifier 11b, a blanking circuit 12b, a summing circuit 13b and a buffer 14b controls the switching of a power semiconductor switch S2.

[0053] The invention is disclosed in an example based on MOSFET applications, but it can be extended to any unipolar (JFET, IGFET, HEMT) or bipolar transistor (BJT or IGBT), only requiring a change in the names of the electrodes.

[0054] The present invention performs switching of the power MOSFET in two steps. In the first step, during the voltage transition, the control of the gate-source voltage is performed only by conventional input signals (i.e., square wave signals). These signals are named PW1 and PW2. Using only the PW1 and PW2 signals during the voltage transition helps to reduce switching losses by fast transition. Then, during the second step (i.e., during the current transition), two different operating modes occur depending on the power semiconductor switch S1 or S2 function.

[0055] One mode operates on a conducting power semiconductor switch. The gate-source voltage of the conducting power semiconductor switch is controlled by a combination of the signal PW1 or PW2 and the amplified feedback signal provided by the feedback amplifier 11. The positive current slope in the conducting power semiconductor switch produces a negative voltage at the feedback amplifier output. The resulting signal controls the current differential value and thus limits the overvoltage after the transition.

[0056] The other mode is intended for passive devices such as MOSFETs and their anti-parallel diodes used in synchronous rectification. In this mode, the gate-source voltage is pulled down to the negative rail by the signal PW1 or PW2. Only the feedback signal can modify the gate-source voltage.

[0057] After the current transition, in both modes, the feedback signal dampens the resonance by partially saturating the power semiconductor switch. The power semiconductor switch acts like a variable resistor that absorbs the energy stored in the parasitic elements. This energy is considered small compared to the total switching energy, while the reduced ringing greatly improves the electromagnetic disturbance.

[0058] The reference signal PW1 is provided to a summing module 13a. The output of the summing module 13a is provided to a buffer 14a, and the output of the buffer 14a is provided to the gate of the power semiconductor switch S1.

[0059] The drain of the power semiconductor switch S1 is connected to the positive power supply of the bus, and the current flowing through this connection is sensed by the current differential value sensing device 10a.

[0060] The output of the current differential value device 10a is supplied to a feedback amplifier 11a. The output of the feedback amplifier 11a is supplied to a blanking circuit 12a, and the output of the blanking circuit 12a is supplied to a summing module 13a.

[0061] The reference signal PW2 is provided to the summing module 13b. The output of the summing module 13b is provided to the buffer 14b, and the output of the buffer 14b is provided to the gate of the power semiconductor switch S2.

[0062] The drain of the power semiconductor switch S2 is connected to the source of the power semiconductor switch S1 and the load.

[0063] The source of the power semiconductor switch S2 is connected to the negative power supply of the bus, and the current flowing through this connection is sensed by the current differential value sensing device 10b.

[0064] The output of the current differential value device 10b is supplied to a feedback amplifier 11b. The output of the feedback amplifier 11b is supplied to a blanking circuit 12b, and the output of the blanking circuit 12b is supplied to a summing module 13b.

[0065] Figure 2 represents an example of an architecture of a buck converter in which the present invention may be implemented.

[0066] exist Figure 2 In the example of FIG. 1 , a gate trajectory control device composed of a current differential value sensing device 10 a , a feedback amplifier 11 a , a blanking circuit 12 a , a summing circuit 13 a and a buffer 14 a controls switching of a power semiconductor switch S1 connected to a diode Da and a load.

[0067] The reference signal PW1 is provided to a summing module 13a. The output of the summing module 13a is provided to a buffer 14a, and the output of the buffer 14a is provided to the gate of the power semiconductor switch S1.

[0068] The drain of the power semiconductor switch S1 is connected to the positive power supply of the bus, and the current flowing through this connection is sensed by the current differential value sensing device 10a.

[0069] The source of the power semiconductor switch S1 is connected to the cathode of the diode Da, and the anode of the diode Da is connected to the negative power supply.

[0070] The output of the current differential value device 10a is supplied to a feedback amplifier 11a. The output of the feedback amplifier 11a is supplied to a blanking circuit 12a, and the output of the blanking circuit 12a is supplied to a summing module 13a.

[0071] Figure 3 represents an example of an architecture of a boost converter in which the present invention may be implemented.

[0072] exist Figure 3 In the example of FIG. 1 , a gate trajectory control device consisting of a current differential value sensing device 10 b, a feedback amplifier 11 b, a blanking circuit 12 b, a summing circuit 13 b and a buffer 14 b controls switching of a power semiconductor switch S2 connected to a diode Db and a load.

[0073] The reference signal PW2 is provided to the summing module 13b. The output of the summing module 13b is provided to the buffer 14b, and the output of the buffer 14b is provided to the gate of the power semiconductor switch S2.

[0074] The drain of the power semiconductor switch S2 is connected to the anode of the diode and the load, and the cathode of the diode is connected to the positive power supply.

[0075] The source of the power semiconductor switch S2 is connected to the negative power supply of the bus, and the current flowing through this connection is sensed by the current differential value sensing device 10b.

[0076] The output of the current differential value device 10b is supplied to a feedback amplifier 11b. The output of the feedback amplifier 11b is supplied to a blanking circuit 12b, and the output of the blanking circuit 12b is supplied to a summing module 13b.

[0077] Figure 4 An example of a current differential sensor used in the present invention is shown.

[0078] exist Figure 4 An example of a current differential sensor is a Rogowski coil. A Rogowski coil is an electronic device used to measure high-speed current pulses. It consists of a spiral coil of wire with a lead that runs from one end through the center of the coil and back to the other end so that both terminals are at the same end of the coil. The entire assembly is then wound around a straight conductor whose current differential is to be measured. There is no magnetic material core. Winding density, coil diameter, and winding stiffness are critical to maintaining immunity to external magnetic fields and sensitivity to the position of the conductor being measured.

[0079] Figure 5 A first example of an electronic circuit of a gate trajectory control device according to the invention is shown.

[0080] The feedback amplifier 11 comprises two transistors Q connected in a push-pull configuration. 51 and Q 52 , four resistors R 51 To R 54 And two capacitors C 51 and C 52 .

[0081] The first output A of the Rogowski coil 10 is connected to a capacitor C 51 and C 52 The first terminal and the resistor R 53 and R 54 The first terminal.

[0082] The second output B of the Rogowski coil 10 is connected to the transistor Q 51 and Q 52 of the emitter.

[0083] Transistor Q 51 is an NPN transistor, and the transistor Q 52It is a PNP transistor.

[0084] Resistor R 53 and capacitor C 51 The second terminal is connected to the transistor Q 51 The base of.

[0085] Resistor R 54 and capacitor C 52 The second terminal is connected to the transistor Q 52 The base of.

[0086] Transistor Q 51 The collector is connected to the resistor R 51 The first terminal of the resistor R 51 The second terminal is connected to the positive power supply Vcc.

[0087] Transistor Q 52 The collector is connected to the resistor R 52 The first terminal of the resistor R 52 The second terminal is connected to the negative power supply Vee.

[0088] Transistor Q 51 and Q 52 The emitter of is the output of the feedback amplifier 11.

[0089] The output of the feedback amplifier 11 is connected to the input of the blanking circuit 12 .

[0090] Blanking circuit 12 includes a resistor R 56 、Capacitor C 53 , logical XOR gate and switch S 50 .

[0091] Switch S 50 The first terminal of the switch S is connected to the input terminal of the blanking circuit 12, and 50 The second terminal of is connected to the output end of the blanking circuit 12.

[0092] The output of the XOR gate controls the switch S 50 If the logic gate power is not enough to directly control the switch S 50 , you can add an optional buffering level.

[0093] A first input of the XOR gate is connected to the reference signal PW.

[0094] The reference signal PW is applied to the resistor R 56 The first terminal.

[0095] Resistor R 56 The second terminal of is connected to the second input of the XOR gate and to the capacitor C 53The first terminal of capacitor C 53 The second terminal is connected to the negative power supply Vee.

[0096] Capacitor C 53 and resistor R 56 A delay is formed, which is, for example, equal to the sum of the gate transition delay, the voltage transition time and the current transition time plus a predetermined margin.

[0097] The output of the blanking circuit 12 is connected to the input of a summing module 13, which includes a resistor R 55 .

[0098] Resistor R 55 The first terminal is connected to the input of the summing module 13, and the resistor R 55 The second terminal of is connected to a reference signal PW.

[0099] The output of the summing module 13 is connected to the input of a buffer 14, which comprises two transistors Q 53 and Q 54 .

[0100] The input of buffer 14 is connected to transistor Q 53 and Q 54 The base of.

[0101] Transistor Q 53 is an NPN transistor, and the transistor Q 54 It is a PNP transistor.

[0102] Transistor Q 53 The collector is connected to the positive power supply Vcc.

[0103] Transistor Q 54 The collector of is connected to the negative power supply Vee.

[0104] Transistor Q 53 and Q 54 The emitter of is the output of buffer 14.

[0105] The output of the buffer 14 is connected to the gate of the power semiconductor switch S1 or S2 .

[0106] Figure 6 An example of an electronic circuit showing a feedback amplifier of a gate trajectory control device according to the invention.

[0107] The feedback amplifier 11 includes two transistors Q 61 and Q 62 , nine resistors R 61 To R 69 and five capacitors C 61 and C 65 .

[0108] The first output A of the Rogowski coil 10 is connected to a capacitor C 61 and C 62 The first terminal and the resistor R 63 and R 64 The first terminal.

[0109] The second output B of the Rogowski coil 10 is connected to a resistor R 66 , R 67 and R 69 The first terminal of the capacitor C 63 , C 64 and C 65 The first terminal.

[0110] Transistor R 63 and capacitor C 61 The second terminal is connected to the resistor R 65 The first terminal and transistor Q 61 The base of.

[0111] Transistor Q 61 is an NPN transistor, and the transistor Q 62 It is a PNP transistor.

[0112] Resistor R 65 The second terminal is connected to the positive power supply Vcc.

[0113] Resistor R 64 and capacitor C 62 The second terminal is connected to the transistor Q 62 The base and resistor R 68 The first terminal.

[0114] Resistor R 68 The second terminal is connected to the negative power supply Vee.

[0115] Transistor Q 61 The collector is connected to the resistor R 61 The first terminal of the resistor R 61 The second terminal is connected to the positive power supply Vcc.

[0116] Transistor Q 62 The collector is connected to the resistor R 62 The first terminal of the resistor R 62 The second terminal is connected to the negative power supply Vee.

[0117] The second terminal of the resistor R69 and the capacitor C65 is the output of the feedback amplifier 11 .

[0118] Figure 7aand Figure 7b A timing diagram showing signals provided in accordance with the present invention.

[0119] Figure 7a and Figure 7b shows the drain-source voltage VDS of the power semiconductor switch S1 S1 , the drain-source voltage VDS of the power semiconductor switch S2 S2 , the drain-source current ID of the power semiconductor switch S1 S1 , the drain-source current ID of the power semiconductor switch S2 S2 , reference signals PW1 and PW2, gate-source voltage VGS of power semiconductor switch S1 S1 , the gate-source voltage VGS of the power semiconductor switch S2 S2 , the temporal evolution of the output 12aOut of the blanking circuit 12a, the output 12bOut of the blanking circuit 12b, the output 10aOut of the current differential value sensing device 10a, and the output 10bOut of the current differential value sensing device 10b.

[0120] Before time t0 in FIG. 7 , the reference signal PW2 is at a high level and the reference signal PW1 is at a low level. Before time t0 , the drain-source voltage VDS of the power semiconductor switch S1 is S1 Equal to the bus voltage Vbus (i.e., bus V DD and V SS The absolute value of the positive power supply and the negative power supply), the drain-source voltage VDS of the power semiconductor switch S2 S2 is empty, the drain-source current ID of the power semiconductor switch S1 S1 is empty, the drain-source current ID of the power semiconductor switch S2 S2 Equal to the current I0 supplied to the load, the gate-source voltage VGS of the power semiconductor switch S1 S1 At negative rail voltage V ee , the gate-source voltage VGS of the power semiconductor switch S2 S2 At a high level (Vcc), the output 12aOut of the blanking circuit 12a is empty, the output 12bOut of the blanking circuit 12b is empty, the output 10aOut of the current differential value sensing device 10a is empty, and the output 10bOut of the current differential value sensing device 10b is empty.

[0121] At time t0 , the reference signal PW2 moves from a high state to a low state, and the output 12bOut of the blanking circuit moves from a low state to a high state.

[0122] Drain-source voltage VDS of power semiconductor switch S1 S1 =Equal to the bus voltage Vbus, the drain-source voltage VDS of the power semiconductor switch S2 S2is empty, the drain-source current ID of the power semiconductor switch S1 S1 is empty, the drain-source current ID of the power semiconductor switch S2 S2 =I0, the gate-source voltage VGS of the power semiconductor switch S1 S1 is empty, the gate-source voltage VGS of the power semiconductor switch S2 S2 is empty, the output 12aOut of the blanking circuit 12a is empty, the output 10aOut of the current differential value sensing device 10a is empty, and the output 10bOut of the current differential value sensing device 10b is empty.

[0123] At time t1 , reference signal PW1 and signal 12aOut at the output of blanking circuit 12a move to a high state.

[0124] Drain-source voltage VDS of power semiconductor switch S1 S1 Equal to the bus voltage minus the voltage drop in parasitic inductance, the drain-source voltage VDS of the power semiconductor switch S2 S2 is empty, the drain-source current ID of the power semiconductor switch S1 S1 The drain-source current ID of the power semiconductor switch S2 begins to increase. S2 When the power semiconductor switch has a gate, the gate-source voltage VGS of the power semiconductor switch S1 starts to decrease. S1 The gate-source voltage VGS of the power semiconductor switch S2 is increased to the Miller platform voltage or increased to the voltage that ensures the target current differential value of the power semiconductor switch in di / dt. S2 is empty, the output 12aOut of the blanking circuit 12a is high as is the output of the blanking circuit 12b, the output 10aOut of the current differential value sensing device 10a is negative, and the output 10bOut of the current differential value sensing device 10b is negative.

[0125] At time t2, the reference signal PW1 and the signal 12aOut at the output of the blanking circuit 12a are in a high state.

[0126] Drain-source voltage VDS of power semiconductor switch S1 S1 Equal to the bus voltage minus the voltage drop in parasitic inductance, the drain-source voltage VDS of the power semiconductor switch S2 S2 is empty, the drain-source current ID of the power semiconductor switch S1 S1 Stop increasing, the drain-source current ID of the power semiconductor switch S2 S2 Stop decreasing, the gate-source voltage VGS of the power semiconductor switch S1 S1 Towards the positive supply voltage V cc The gate-source voltage VGS of the power semiconductor switch S2 rises S2is empty, the output 12aOut of the blanking circuit 12a is high as is the output of the blanking circuit 12b, the output 10aOut of the current differential value sensing device 10a is positive, and the output 10bOut of the current differential value sensing device 10b is positive.

[0127] At time t2, the current flowing through the power semiconductor switch S1 has reached the output current plus the recovery current of the anti-parallel diode of the power semiconductor switch S2. The current drops back to the output current, resulting in the addition of the positive feedback voltage to the already positive reference signal. Therefore, the gate voltage of the power semiconductor switch S1 is pulled up to the positive power supply voltage. On the power semiconductor switch S2, the feedback voltage is also positive; this voltage is added to the reference signal PW2 that is pulled down, resulting in a positive voltage on the gate of the power semiconductor switch S2. Both the power semiconductor switches S1 and S2 are in a linear state. In this case, the power semiconductor switch can be modeled as a variable resistor to attenuate the oscillation circuit formed by parasitic inductance and capacitance. The anti-parallel diode of the power semiconductor switch S2 is blocked at time t2, causing the voltage on the power semiconductor switch S1 to drop, and vice versa, causing the voltage on the power semiconductor switch S1 to rise.

[0128] At time t3, the voltage across the power semiconductor switch S2 has reached the bus voltage V bus . Therefore, the voltage across the power semiconductor switch S1 is null. No current flows in the power semiconductor switch S2, and the entire load current I0 flows in the power semiconductor switch S1. The gate-source voltage VGS of the power semiconductor switch S1 is S1 has reached the positive supply voltage V cc The gate-source voltage VGS of the power semiconductor switch S2 S2 Pulled down to the negative power supply voltage V by signal PW2 ee . The output 10bOut of the current differential value sensing device 10b is null. As a result, no feedback is added to PW2. On the power semiconductor switch S2, there is an overshoot voltage directly related to the current slope in the power semiconductor switch immediately before time t3. The value of this current slope is proportional to the current slope controlled by the power semiconductor switch S1 during the interval between t1 and t2.

[0129] The cut-off phase starts at time t4. At this time, the reference signal PW1 moves from a high state to a low state, and the output 12aOut of the blanking circuit moves from a low state to a high state. The gate of the power semiconductor switch S1 is pulled down to the negative power supply V ee The gate-source of the power semiconductor switch S1 is directed toward the negative power supply V ee All other signals remain the same until the gate-source voltage of the power semiconductor switch S1 reaches the Miller plateau voltage.

[0130] At time t5, the voltage across the power semiconductor switch S1 increases without any feedback compensation. An opposite voltage transition occurs across the power semiconductor switch S2. This voltage change induces a current in the power semiconductor switch capacitor:

[0131]

[0132] Then, at time t6, the current starts to decrease, and feedback compensation is added to the reference signal PW1 of the power semiconductor switch S1, slowing down the current transition. At the same time, the blanking circuit prevents the feedback on the power semiconductor switch S2 from turning on the power semiconductor switch S2, causing the pin to short-circuit. Since the PW2 signal provided to the power semiconductor switch S2 is at a low level, the output 12aOut of the blanking circuit 12a remains low during the entire off phase. The gate-source voltage VGS of the power semiconductor switch S2 S2 is pulled down to the negative supply voltage.

[0133] At time t6, the voltage across the power semiconductor switch S2 is zero, and the voltage across the power semiconductor switch S1 is equal to the bus voltage V bus At this point, the current can begin to drop in the power semiconductor switch S2 and thus rise in the power semiconductor switch S1. The current slope at this stage induces a positive voltage at the output 10bOut of the current differential value sensing device 10. This voltage is added to the negative voltage of the reference signal PW2. Therefore, the gate-source voltage VGS of the power semiconductor switch S1 is S1 Increases to a voltage that ensures the target di / dt in the power semiconductor switch S1. During this time interval, the current slope in the switch is regulated by the feedback loop.

[0134] Between the interval t6 and t7, an overvoltage is present across the power semiconductor switch S1. This overvoltage is determined by the current slope in the power semiconductor switch during the above-mentioned interval.

[0135] At t7, the current in the power semiconductor switch S1 is empty, and the current in the power semiconductor switch S2 has reached the load current I0. The output 10bOut of the current differential value sensing device 10 is empty. The gate-source voltage VGS of the power semiconductor switch S1 is S1 Pulled down to the negative power supply V SS .

[0136] Figure 8 Detailed timing diagram showing the current and voltage across a power semiconductor switch during switch off when the present invention is implemented and not implemented.

[0137] The curve labeled VDSS' shows the drain-source voltage of the power semiconductor switch during switch off when the present invention is not implemented, and the curve labeled VDSS shows the drain-source voltage of the power semiconductor switch during switch off when the present invention is implemented.

[0138] The curve marked IDS' shows the drain-source current of the power semiconductor switch during switch off when the present invention is not implemented, and the curve marked IDS shows the drain-source current of the power semiconductor switch during switch off when the present invention is implemented.

[0139] The curve labeled VGSS' shows the gate-source voltage of the power semiconductor switch during switch off when the present invention is not implemented, and the curve labeled VGSS shows the gate-source voltage of the power semiconductor switch during switch off when the present invention is implemented.

[0140] from Figure 8 It can be seen that the present invention reduces current transient rate and / or voltage overshoot.

[0141] Fig. 9 Detailed timing diagram showing current and voltage across a power semiconductor switch during switch-on when the present invention is implemented and not implemented.

[0142] The curve labeled VDSS' shows the drain-source voltage of the power semiconductor switch during switch on when the present invention is not implemented, and the curve labeled VDSS shows the drain-source voltage of the power semiconductor switch during switch on when the present invention is implemented.

[0143] The curve marked IDS' shows the drain-source current of the power semiconductor switch during switch-on when the present invention is not implemented, and the curve marked IDS shows the drain-source current of the power semiconductor switch during switch-on when the present invention is implemented.

[0144] The curve labeled VGSS' shows the gate-source voltage of the power semiconductor switch during switch on when the present invention is not implemented, and the curve labeled VGSS shows the drain-source voltage of the power semiconductor switch during switch on when the present invention is implemented.

[0145] from Fig. 9 It can be seen that the present invention reduces the current transient rate and / or voltage overshoot.

[0146] Fig.10 A second example of the architecture of the gate trajectory control device according to the present invention is shown.

[0147] The gate track control device has an architecture based on components connected together by a bus 101, and is composed of Fig.11A processor 100 controlled by a disclosed program.

[0148] The bus 101 links the processor 100 to a read-only memory ROM 102 , a random access memory RAM 103 , and an input-output I / O IF interface 105 .

[0149] Memory 103 contains data intended to receive variables and Fig.11 The algorithm disclosed in the program is related to the instructions of the register.

[0150] The processor 100 receives the measured value of the differential of the drain-source current, the input signal PW1 or PW2 through the input / output I / O IF 105 .

[0151] Read-only memory or possibly flash memory 102 contains Fig.11 The instructions of the program related to the algorithm disclosed in the reference module 102 are stored in the random access memory 103 when the reference module 102 is powered on.

[0152] The gate trajectory control device can be implemented in software by executing a set of instructions or programs by a programmable computer such as a PC (personal computer), DSP (digital signal processor) or microcontroller; or the gate trajectory control device can be implemented in hardware by a machine or dedicated component such as an FPGA (field programmable gate array) or ASIC (application-specific integrated circuit).

[0153] In other words, the gate trajectory control device includes a gate trajectory control device that performs the same Fig.11 A circuit of a program related to the disclosed algorithm or a device including the circuit.

[0154] Fig.11 An algorithm executed by a gate trajectory control device according to a second example of a gate trajectory control device is shown.

[0155] In step S110, the gate trajectory control device receives an input signal intended to drive a semiconductor power switch, wherein the device comprises:

[0156] In step S111, the gate trajectory control device senses the drain-source current flowing through the semiconductor power switch to obtain a voltage representing the sensed drain-source current.

[0157] In step S112, the gate trajectory control device amplifies the voltage representing the sensed drain-source current.

[0158] In step S113, the gate trajectory control means adds an amplified voltage representing the sensed drain-source current to the input signal during a given time period.

[0159] Naturally, many modifications can be made to the embodiments of the invention described above without departing from the scope of the invention.

Claims

1. A device for controlling the switching of a semiconductor power switch for supplying current to a load from a conducting state to a non-conducting state or from a non-conducting state to a conducting state, the device receiving an input signal intended to drive the semiconductor power switch, wherein: The device comprises: - means for sensing a differential value of a drain-source current flowing through said semiconductor power switch in order to obtain a voltage representative of the sensed differential value of the drain-source current, - means for amplifying said voltage representing a differential value of said sensed drain-source current, - means for adding an amplified voltage representing the differential value of the sensed drain-source current to the input signal during a given time period, wherein the given time period is equal to the sum of the gate transition time, the voltage transition time and the current transition time plus a predetermined margin, and the addition is controlled by the result of an exclusive OR logic operation of the input signal with the input signal delayed by the given time period.

2. The device according to claim 1, wherein: The means for sensing the differential value of the drain-source current flowing through the semiconductor power switch is composed of a Rogowski coil.

3. The device according to any one of claims 1 or 2, wherein: The semiconductor power switch is included in a buck converter.

4. The device according to any one of claims 1 or 2, wherein: The semiconductor power switch is included in a boost converter.

5. The device according to any one of claims 1 or 2, wherein: The semiconductor power switch is included in a half-bridge configuration, which includes a first semiconductor power switch and a second semiconductor power switch, and the switching of each semiconductor power switch is controlled by a corresponding device for controlling the switching from the conductive state to the non-conductive state or from the non-conductive state to the conductive state.

6. A method for controlling the switching of a semiconductor power switch for supplying current to a load from a conducting state to a non-conducting state or from a non-conducting state to a conducting state, wherein: The method comprises the following steps: - receiving an input signal intended to drive said semiconductor power switch, - sensing a differential value of a drain-source current flowing through the semiconductor power switch so as to obtain a voltage representing the sensed differential value of the drain-source current, - amplifying said voltage representing a differential value of said sensed drain-source current, - adding an amplified voltage representing the differential value of the sensed drain-source current to the input signal during a given time period, wherein the given time period is equal to the sum of a gate transition time, a voltage transition time and a current transition time plus a predetermined margin, and the addition is controlled by a result of an exclusive OR logic operation of the input signal and the input signal delayed by the given time period.

7. The method according to claim 6, wherein: The sensing of a differential value of a drain-source current flowing through the semiconductor power switch is performed using a Rogowski coil.

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