Test Structure for High-Frequency Pin

Abstract

The present invention discloses a test structure for high-frequency pins. The test structure for high-frequency pins includes a PCB board, an IC circuit and signal pads arranged on the PCB board. The IC circuit includes high-frequency signal pins, and the signal pads are connected to the high-frequency signal pins through signal gold wires. The length of the signal gold wires is less than or equal to 0.5941 mm and greater than or equal to 0.4242 mm. By the above method, the test cost can be effectively reduced.

Description

Technical Field

[0001] The present invention relates to the field of communications, and particularly to a test structure for high-frequency pins. Background Art

[0002] In the development process of millimeter-wave, terahertz chips, etc., it is necessary to package and perform performance tests on the chips. Since the operating signal frequencies of some pins of the chips reach the GHz level, a dedicated probe station needs to be used for testing. Due to the high cost of the probe station, the testing cost is relatively high. Summary of the Invention

[0003] The present invention provides a test structure for high-frequency pins to solve the problem of excessively high testing costs in the prior art.

[0004] To solve the above technical problems, a technical solution adopted by the present invention is: to provide a test structure for high-frequency pins, the test structure includes a PCB board and an IC circuit and signal pads arranged on the PCB board. The IC circuit includes high-frequency signal pins, and the signal pads are connected to the high-frequency signal pins through signal gold wires; wherein, the length of the signal gold wire is less than or equal to 0.5941 mm and greater than or equal to 0.4242 mm.

[0005] According to an embodiment provided by the present invention, the length of the signal gold wire is 0.5296 mm.

[0006] According to an embodiment provided by the present invention, an ink layer is further arranged on the PCB board, and the signal gold wire is attached to the ink layer.

[0007] According to an embodiment provided by the present invention, at least part of the signal gold wire is spaced from the PCB board.

[0008] According to an embodiment provided by the present invention, the test structure further includes two reference signal pins arranged on both sides of the high-frequency signal pin and two ground pads arranged on the PCB board.

[0009] According to an embodiment provided by the present invention, the two ground pads are respectively connected to the two reference signal pins through reference gold wires in a one-to-one correspondence, and the two reference gold wires and the signal gold wire do not cross each other.

[0010] According to an embodiment provided by the present invention, the distance between the high-frequency signal pin and the adjacent reference signal pin is less than or equal to 0.1200 mm and greater than or equal to 0.0889 mm.

[0011] According to an embodiment provided by the present invention, the distance between the high-frequency signal pin and the adjacent reference signal pin is 0.1000 mm.

[0012] According to an embodiment provided by the present invention, the distance between the ground pad and the signal pad is greater than or equal to 0.1300 mm and less than or equal to 0.1700 mm.

[0013] According to an embodiment provided by the present invention, the distance between the ground pad and the signal pad is 0.1554 mm.

[0014] Beneficial effects: Different from the prior art, the present invention sets signal pads on the PCB board, and connects the signal pads and the high-frequency signal pins on the IC circuit through signal gold wires, so that common test instruments such as oscilloscopes can be directly used to connect to the signal pads to realize the performance test of the high-frequency signal pins, thereby effectively saving costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a schematic structural diagram of the first embodiment of the test structure of the high-frequency pin provided by the present invention;

[0016] Figure 2 is Figure 1 an enlarged schematic diagram of the partial area A of the test structure of the high-frequency pin shown;

[0017] Figure 3 is a schematic structural diagram of the second embodiment of the test structure of the high-frequency pin provided by the present invention;

[0018] Figure 4 is Figure 3 an enlarged schematic diagram of the partial area B of the test structure of the high-frequency pin shown;

[0019] Figure 5 is Figure 1 a return loss schematic diagram of the test structure of the high-frequency pin shown;

[0020] Figure 6 is Figure 3 a return loss schematic diagram of the test structure of the high-frequency pin shown;

[0021] Figure 7 is Figure 1 a standing wave ratio schematic diagram of the test structure of the high-frequency pin shown;

[0022] Figure 8 is Figure 3 a standing wave ratio schematic diagram of the test structure of the high-frequency pin shown. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0023] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0024] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, such descriptions of "first", "second", etc. are only for descriptive purposes and should not be construed as indicating or implying their relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In addition, the technical solutions between various embodiments can be combined with each other, but it must be based on the fact that those of ordinary skill in the art can implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the protection scope required by the present invention.

[0025] Please refer to Figures 1 - 8 together. The present invention provides a test structure 10 for high-frequency pins. The test structure 10 includes a PCB board 100, an IC circuit 200, and a signal pad 300. The IC circuit 200 and the signal pad 300 are both disposed on the PCB board 100.

[0026] As Figure 1 and Figure 2 shown, the IC circuit 200 includes high-frequency signal pins 210. The IC circuit 200 is spaced apart from the signal pad 300. Specifically, the high-frequency signal pins 210 are spaced apart from the signal pad 300. And the high-frequency signal pins 210 and the signal pad 300 can be connected by signal gold wires 310.

[0027] Optionally, the IC circuit 200 includes one or more millimeter-wave chips, that is, it can be an integrated circuit of multiple millimeter-wave chips.

[0028] Optionally, the length of the signal gold wire 310 is less than or equal to 0.5941 mm and greater than or equal to 0.4242 mm. Specifically, it can be 0.5941 mm, 0.5296 mm, 0.5000 mm, 0.4300 mm, or 0.4242 mm, and no specific limitation is made here.

[0029] Optionally, by setting signal pads 300 on the PCB 100 and connecting the signal pads 300 and the high-frequency signal pins 210 on the IC circuit 200 through signal gold wires 310, the performance test of the high-frequency signal pins 210 can be directly implemented using the signal pads 300. The specific test process can be as follows: After inputting a high-frequency clock signal into the IC circuit 200, through a series of processes, it can be output via the high-frequency signal pins 210, signal gold wires 310, and signal pads 300. Subsequently, by connecting a detection device such as an oscilloscope to the signal pads 300, the output high-frequency clock signal can be processed, thereby completing the performance test of the high-frequency signal pins 210.

[0030] That is, the PCB 100 can be used to package the IC circuit 200, signal pads 300 are set on the PCB 100, and the high-frequency signal pins 210 and the signal pads 300 are further connected through signal gold wires 310, thereby enabling the test of the high-frequency signal pins 210 on the IC circuit 200.

[0031] In an optional scenario, the length of the signal gold wire 310 directly affects the frequency of the high-frequency signal pins 210 to be tested. That is, the length of the signal gold wire 310 needs to meet the following conditions:

[0032]

[0033]

[0034] Where l is the length of the signal gold wire 310, Trise is the signal rise time, L is the inductance per unit length of the signal gold wire 310, C is the capacitance per unit length of the signal gold wire 310. Optionally, since the impedance between the high-frequency signal pins 210 and the signal pads 300 is discontinuous, when the high-frequency signal pins 210 are connected to the signal pads 300 through the signal gold wire 310, the signal gold wire 310 is actually a discontinuous transmission line. And when the length of the discontinuous transmission line is less than one-sixth of the length of the signal transmission during the rise time, the discontinuous transmission line can be regarded as a continuous transmission line.

[0035] Where v is the transmission rate of electromagnetic waves in the medium, c is the transmission rate of electromagnetic waves in a vacuum, and Er is the relative dielectric constant of the transmission medium.

[0036] Combining Formula 1 and Formula 2, the following Formula 3 can be obtained:

[0037]

[0038] And when the length l of the signal gold wire 310 satisfies less than or equal to 0.5941 mm and greater than or equal to 0.4242 mm, and calculated with the longest 0.5941 mm, the actual value of Trise can be obtained as 1.1882*10-10S. Optionally, since the transmission line used in this application is the signal gold wire 310, it can be calculated that this length can satisfy a 3GHZ sine wave clock signal. That is, the length of the signal gold wire 310 designed in this application is sufficient to satisfy the clock signal of the Ghz level frequency, that is, it can meet the test requirements of the high-frequency signal pin 210 in this application.

[0039] And in terms of cost, in the existing scenario, since the probe station is expensive and needs to be maintained in real time, generally only specialized test companies are equipped with probe stations. After the chip design is completed, the chip needs to be sent to a specialized test company to complete the test, which often takes several weeks and the test price is also very expensive. Both the time cost and the money cost are high. However, this application can directly use the signal pad 300 and common equipment such as an oscilloscope to achieve the test, with high efficiency and low cost, and problems can be found in time, thus greatly accelerating the chip design process.

[0040] In the above embodiment, by setting the signal pad 300 on the PCB board 100 and connecting the signal pad 300 and the high-frequency signal pin 210 on the IC circuit 200 through the signal gold wire 310, the performance test of the high-frequency signal pin 210 can be directly realized by using a common test instrument such as an oscilloscope externally connected to the signal pad 300, thereby effectively saving costs.

[0041] In an alternative embodiment, at least a part of the signal gold wire 310 is spaced from the PCB board 100, that is, the signal gold wire 310 is floating relative to the PCB board 100, thereby effectively reducing the processing requirements, that is, manual soldering can also be realized.

[0042] In another alternative embodiment, an ink layer (not shown in the figure) is further provided on the PCB board 100, and the signal gold wire 310 is attached to the ink layer. By attaching the signal gold wire 310 to the ink layer, on the one hand, it is beneficial to the stability of the signal gold wire 310 and it is not easy to break. On the other hand, compared with the floating setting, the length of the signal gold wire 310 can be effectively reduced, and thus a higher test standard can be achieved. And when the signal gold wire 310 is attached to the ink layer, the surrounding medium also changes, not only air, so Er in formula 2 also changes and is improved compared with the air medium, thereby further improving the test standard.

[0043] Such as Figure 3 And Figure 4As shown, the test structure 10 further includes two reference signal pins 220 disposed on both sides of the high-frequency signal pin 210 and two ground pads 400 disposed on the PCB board 100. Among them, the two ground pads 400 are respectively connected to the two reference signal pins 220 through reference gold wires 410 in a one-to-one correspondence, and the two reference gold wires 410 and the signal gold wire 310 do not cross each other. That is, each ground pad 400 is connected to the corresponding reference signal pin 220 through only one reference gold wire 410. And the two reference gold wires 410 and the signal gold wire 310 are arranged in parallel.

[0044] Optionally, by setting the two ground pads 400 and the reference gold wires 410, when a high-frequency clock signal enters the high-frequency signal pin 210 from the signal pad 300 via the signal gold wire 310, a return signal of the same frequency returns to the two ground pads 400 via the reference signal pin 220 and the reference gold wire 410. Since there will be mutual inductance M between the reference gold wire 410 and the signal gold wire 310, and when the current directions of the reference gold wire 410 and the signal gold wire 310 are the same, M>0, when the current directions of the reference gold wire 410 and the signal gold wire 310 are opposite, then M<0. Since the high-frequency clock signal and the return signal are in opposite directions, the mutual inductance M between the reference gold wire 410 and the signal gold wire 310 is less than 0, thereby reducing the overall inductance of the entire structure to facilitate the integrity transmission of the signal.

[0045] As shown in the comparison Figure 5 and Figure 6 shown, Figure 5 is Figure 1 the echo loss schematic diagram of the test structure 10 shown, Figure 6 is Figure 3 the echo loss schematic diagram of the test structure 10 shown. Among them, obviously the overall echo loss is effectively improved. For example, at the low frequency of 3 GHz, Figure 6 is about Figure 5 15 dB less than Figure 6 than Figure 5 about 5 dB less at the intermediate frequency of 13 GHz, and at the high frequency of 18 GHz Figure 6 is about Figure 5 0.5 less than Figure 3 indicating that the corresponding structure has a better signal transmission effect.

[0046] And further referring to Figure 7 and Figure 8 shown, Figure 7 is Figure 1 the standing wave ratio schematic diagram of the test structure 10 shown, Figure 8 is Figure 3 the standing wave ratio schematic diagram of the test structure 10 shown. Obviously, Figure 8 the standing wave ratio shown is compared withFigure 7 In terms of the frequency band below 18 GHz, it is closer to 1, indicating better overall impedance performance, that is, better signal transmission performance.

[0047] And the above can show that the solution provided by this application is sufficient to meet the bandwidth requirement of 14.75 GHz, and in certain cases, it can meet the bandwidth requirement of 18.75 GHz.

[0048] In an alternative embodiment, the distance between the high-frequency signal pin 210 and the adjacent reference signal pin 220 is less than or equal to 0.1200 mm and greater than or equal to 0.0889 mm. Specifically, it can be 0.1200 mm, 0.900 mm or 0.0889 mm, and no specific limitation is made here.

[0049] In an alternative embodiment, under the requirements of meeting the conventional processing requirements and the required test standards, the distance between the high-frequency signal pin 210 and the adjacent reference signal pin 220 can be 0.1000 mm.

[0050] Among them, the distance between the ground pad 400 and the signal pad 300 is greater than or equal to 0.1300 mm and less than or equal to 0.1700 mm. Specifically, it can be 0.1300 mm, 0.1400 or 0.1700, and no specific limitation is made here.

[0051] In an alternative embodiment, under the requirements of meeting the conventional processing requirements and the required test standards, the distance between the ground pad 400 and the signal pad 300 is 0.1554 mm.

[0052] Optionally, since the reference gold wire 410 and the signal gold wire 310 are not parallel, the distance between the reference gold wire 410 and the signal gold wire 310 is based on the shortest distance, and the shortest distance is less than or equal to 0.1200 mm and greater than or equal to 0.0889 mm. Specifically, it can be 0.1200 mm, 0.9000 mm or 0.0889 mm, and no specific limitation is made here.

[0053] Optionally, under the conditions that the length of the signal gold wire 310 is 0.5296 mm, the spacing between the high-frequency signal pin 210 and the adjacent reference signal pin 220 can be 0.1000 mm, and the spacing between the ground pad 400 and the signal pad 300 is 0.1554 mm, this application is sufficient to meet the test requirements of a 14.75 GHz bandwidth. Moreover, based on the current general processing accuracy in our country, the processing difficulty of the above values can be generally achieved by most processing factories in our country, that is, most companies or factories can produce the test structure 10, thus making the production of the entire test structure 10 very simple and convenient, and the process cost is relatively low. Therefore, it should be understood that in the chip processing technology, any progress in accuracy is a huge change, accompanied by an exponential increase in cost. The test structure 10 of this application can be produced under relatively low accuracy requirements and can meet the test requirements of a 14.75 GHz bandwidth. Compared with the prior art that requires the probe station solution, it has extremely low cost and extremely high efficiency, which is an extremely important advantage of this solution, that is, low-cost popularity.

[0054] Furthermore, the test bandwidth requirements can be effectively improved by further reducing the length of the signal gold wire 310, the spacing between the high-frequency signal pin 210 and the adjacent reference signal pin 220, and the spacing between the ground pad 400 and the signal pad 300.

[0055] In summary, a test structure for high-frequency pins provided by the present invention sets a signal pad 300 on the PCB board 100, and connects the signal pad 300 and the high-frequency signal pin 210 on the IC circuit 200 through the signal gold wire 310, so that the performance test of the high-frequency signal pin 210 can be directly realized by connecting an external oscilloscope and other common test instruments to the signal pad 300, thus effectively saving costs. Moreover, the parameters such as the length of the signal gold wire 310, the spacing between the high-frequency signal pin 210 and the adjacent reference signal pin 220, and the spacing between the ground pad 400 and the signal pad 300 provided by this application can all be realized based on the current general processing requirements in our country. Therefore, the entire test structure 10 can be well popularized and the cost can be well optimized.

[0056] The above is only the implementation mode of the present invention, and it does not limit the patent scope of the present invention accordingly. Any equivalent result or equivalent process transformation made by using the content of the specification and drawings of the present invention, or directly or indirectly applied in other related technical fields, shall be equally included in the patent protection scope of the present invention.

Claims

1. A test structure for high-frequency pins, characterized in that, The test structure includes a PCB board, an IC circuit disposed on the PCB board, and signal pads. The IC circuit includes high-frequency signal pins, and the signal pads are connected to the high-frequency signal pins through signal gold wires. Among them, the length of the signal gold wire is less than or equal to 0.5941 mm and greater than or equal to 0.4242 mm. The length of the signal gold wire satisfies the following conditions: Combining Formula 1 and Formula 2 gives the following Formula 3: In the formula, l is the length of the signal gold wire, Trise is the signal rise time, L is the inductance per unit length of the signal gold wire, C is the capacitance per unit length of the signal gold wire, v is the transmission rate of electromagnetic waves in the medium, c is the transmission rate of electromagnetic waves in a vacuum, and Er is the relative dielectric constant of the transmission medium. Among them, the IC circuit is used to receive and process high-frequency clock signals, and output the processed high-frequency clock signals via the signal pads, the high-frequency signal pins, and the signal gold wires. The signal pads are used to externally connect detection devices to process the output high-frequency clock signals to complete the performance test of the high-frequency signal pins.

2. The test structure according to claim 1, wherein The length of the signal gold wire is 0.5296 mm.

3. The test structure according to claim 1, characterized in that, An ink layer is also disposed on the PCB board, and the signal gold wire is attached to the ink layer.

4. The test structure according to claim 3, wherein, At least a part of the signal gold wire is spaced apart from the PCB board.

5. The test structure according to claim 1, wherein The test structure further includes two reference signal pins disposed on both sides of the high-frequency signal pin and two ground pads disposed on the PCB board.

6. The test structure according to claim 5, wherein The two ground pads are respectively connected to the two reference signal pins through reference gold wires, and the two reference gold wires and the signal gold wire do not cross each other.

7. The test structure according to claim 5, wherein The distance between the high-frequency signal pin and the adjacent reference signal pin is less than or equal to 0.1200 mm and greater than or equal to 0.0889 mm.

8. The test structure according to claim 7, wherein The distance between the high-frequency signal pin and the adjacent reference signal pin is 0.1000 mm.

9. The test structure according to claim 5, characterized in that The distance between the ground pad and the signal pad is greater than or equal to 0.1300 mm and less than or equal to 0.1700 mm.

10. The test structure according to claim 9, wherein, The distance between the ground pad and the signal pad is 0.1554 mm.

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