An analog multiplier-adder circuit based on memristor
By directly converting the multiplication current into analog-to-digital conversion in the analog multiplication circuit, the problems of large circuit overhead and high power consumption in traditional circuits are solved, and a simpler circuit architecture and lower power consumption are achieved.
Patent Information
- Application Number
- CN202010758045.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2020-07-31
- Publication Date
- 2025-03-28
- Estimated Expiration
- 2040-07-31
AI Technical Summary
Traditional memristor-based analog multiplier circuits have problems with large circuit overhead and high power consumption, especially when converting the multiplier current to voltage and then performing analog-to-digital conversion.
An analog multiplier circuit based on memristor is designed, which directly converts the multiplier current through the column memristor analog multiplier unit, reducing circuit complexity and power consumption.
The circuit architecture is simpler and has low circuit overhead. There is no need to convert current to voltage before performing analog-to-digital conversion. Multiplying current can directly convert it to digital signals, reducing circuit complexity and power consumption.
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Figure CN111953349B_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the field of integrated circuit design, and in particular relates to an analog multiplier-adder circuit based on a memristor. Background Art
[0002] The software and hardware of the von Neumann computer are completely separated, and it is suitable for numerical calculations. There is a large gap in semantics between the machine language of this computer and the high-level language, which is called the von Neumann semantic gap. One of the important reasons for this gap is the different memory organization. The memory of the von Neumann machine is a one-dimensional linear arrangement of units, which are accessed by sequentially arranged addresses. The memory represented by the high-level language is a group of named variables, which are called by name without considering the access method, and the data structure is often multi-dimensional (such as arrays, tables).
[0003] As the gap in process improvement between processors and memories widens, the storage wall scissors fork under the von Neumann architecture continues to grow, and the problem of memory access power consumption wall becomes increasingly prominent. Industry and academia are beginning to pay attention to the integrated storage and computing architecture.
[0004] A memristor is a nonlinear resistor with a memory function. Its resistance value can be changed by controlling the change of current. If a high resistance value is defined as "1" and a low resistance value is defined as "0", this resistor can store data. In fact, it is a nonlinear resistor with a memory function.
[0005] The architecture using memristors for storage and computing takes advantage of the non-volatile and multi-valued characteristics of memristors, and accordingly uses memristor crossbar arrays and related circuits to implement matrix multiplication and addition operations in the analog domain. Compared with traditional CMOS circuits for matrix multiplication and addition, it has higher energy efficiency and hardware overhead advantages.
[0006] The traditional memristor-based analog multiplier-adder circuit consists of a memristor crossbar array, a multiply-add current-to-voltage module, and a voltage analog-to-digital converter. Since the multiply-add current needs to be converted into voltage and then converted into analog-to-digital, this architecture has the problems of high circuit overhead and high power consumption. Summary of the invention
[0007] The technical problem to be solved by the present invention is mainly to propose an analog multiplier-adder circuit based on a memristor, which can directly perform analog-to-digital conversion on the multiplication-addition current, thereby reducing the circuit scale and the circuit power consumption.
[0008] To achieve the above object, the technical solution of the present invention is as follows:
[0009] A memristor-based analog multiplier-adder circuit comprises N column memristor analog multiplier-adder units, wherein the column memristor analog multiplier-adder unit comprises a column memristor module, a multiplication-addition current generator and a current analog-to-digital converter, wherein the column memristor analog multiplier-adder unit has K input terminals, and N and K are positive integers; wherein the column memristor module receives K voltage values inputted from the K input terminals and performs analog multiplication-addition operations; the input terminal of the multiplication-addition current generator is connected to the output terminal of the column memristor module, and the output terminal of the multiplication-addition current generator outputs the multiplication-addition current of the analog multiplication-addition operation; the current analog-to-digital converter is used for converting the output current of the multiplication-addition current generator into a digital signal, and the input terminal of the current analog-to-digital converter is connected to the output terminal of the multiplication-addition current generator; and the output terminal of the current analog-to-digital converter is the output terminal of the column memristor analog multiplier-adder unit.
[0010] Furthermore, the column memristor unit comprises:
[0011] The first NMOS tube, the second NMOS tube, ... and the Kth NMOS tube, and
[0012] a first memristor, a second memristor, ... and a Kth memristor; wherein,
[0013] The sources of the first NMOS tube, the second NMOS tube, ... and the Kth NMOS tube are respectively connected to one end of the corresponding first memristor, the second memristor, ... and the Kth memristor;
[0014] The first memristor RRAM1, the second memristor RRAM2 . . . and the Kth memristor RRAM K The other end of each of the memristor units is commonly connected to a node SL1; the node SL1 is an output end of the column memristor unit;
[0015] The gates of the first NMOS tube, the second NMOS tube, ... and the Kth NMOS tube are commonly connected to a node S1;
[0016] The drains of the first NMOS tube, the second NMOS tube ... and the Kth NMOS tube are connected to the node BL1, the node BL2 ... and the node BL K , the N column memristor analog multiplier-adder units have K input terminals; the nodes BL1, BL2... and BL K The K input terminals of the multiplier-adder unit are simulated for the N column memristors.
[0017] Furthermore, the multiplication-addition current generator comprises a first MOS tube, a second MOS tube and an eleventh MOS tube, wherein the source electrodes of the first MOS tube and the second MOS tube are connected to the drain electrode of the third MOS tube; the gate electrode of the second MOS tube is connected to the reference voltage V ref ; The drain of the first MOS tube, the drain of the fifth MOS tube, the gate of the fifth MOS tube, and the gate of the sixth MOS tube are connected together; the drain of the sixth MOS tube, the gate of the seventh MOS tube, the drain of the seventh MOS tube, the gate of the eighth MOS tube, and the gate of the ninth MOS tube are connected together; the drain of the second MOS tube, the drain of the fourth MOS tube, the gate of the fourth MOS tube, the gate of the ninth MOS tube, and the gate of the eleventh MOS tube are connected together; the drain of the ninth MOS tube, the drain of the eighth MOS tube, the gate of the first MOS tube, and the output end of the column memristor unit are connected; the drain of the tenth MOS tube is connected to the drain of the eleventh MOS tube and serves as the output end of the multiplication and addition current generator; the source of the fifth MOS tube, the source of the sixth MOS tube, the source of the fourth MOS tube, the source of the ninth MOS tube, and the source of the eleventh MOS tube are connected to the negative electrode of the power supply; the source of the third MOS tube, the source of the seventh MOS tube, the source of the eighth MOS tube, and the source of the tenth MOS tube are connected to the positive electrode of the power supply.
[0018] Further, the first MOS tube, the second MOS tube, the third MOS tube, the seventh MOS tube, the eighth MOS tube, and the tenth MOS tube are PMOS tubes; the fourth MOS tube, the fifth MOS tube, the sixth MOS tube, the ninth MOS tube, and the eleventh MOS tube are NMOS tubes.
[0019] It can be seen from the above technical solution that compared with the traditional memristor-based analog multiplier-adder circuit, the memristor-based analog multiplier-adder circuit proposed in the present invention has a simpler circuit architecture and low circuit overhead. It does not need to convert the current into voltage and then perform analog-to-digital conversion. Moreover, the multiplication and addition current can be directly converted into a digital signal, which reduces both the circuit complexity and the circuit power consumption. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 The schematic diagram of the structure of the analog multiplier-adder circuit based on memristor in the embodiment of the present invention is shown as follows
[0021] Figure 2 FIG. 1 is a schematic diagram of various modules included in the analog multiplier-adder circuit based on a memristor in an embodiment of the present invention.
[0022] Figure 3The figure shows a schematic diagram of the specific circuits of each module of the analog multiplier-adder circuit based on a memristor in an embodiment of the present invention. DETAILED DESCRIPTION
[0023] The following is combined with Figure 1-3 , the specific implementation modes of the present invention are further described in detail.
[0024] See also Figure 1 , Figure 1 FIG. 1 is a schematic diagram of the structure of an analog multiplier-adder circuit based on a memristor in an embodiment of the present invention. Figure 1 As shown, the memristor-based analog multiplier-adder circuit is composed of N column memristor analog multiplier-adder units, each of which includes K input terminals, wherein N and K are both positive integers.
[0025] As attached Figure 2 As shown, the column memristor analog multiplier and adder unit is composed of a column memristor unit 1, a multiplication and addition current generator unit 2, and a current analog-to-digital converter unit 3. The column memristor unit 1 in the column memristor module receives the K voltage values inputted from the K input terminals and performs analog multiplication and addition operations; the input terminal of the multiplication and addition current generator 2 is connected to the output terminal 1 of the column memristor module, and is used to output the multiplication and addition current of the analog multiplication and addition operation; the current analog-to-digital converter 3 is used to convert the output current of the multiplication and addition current generator into a digital signal, and the input terminal of the current analog-to-digital converter 3 is connected to the output terminal of the multiplication and addition current generator 3; the output terminal of the current analog-to-digital converter 3 is the output terminal of the column memristor analog multiplier and adder unit. That is to say, in the embodiment of the present invention, the multiplication and addition current directly outputted by the column memristor unit 1 can be directly converted into analog digital, so that the circuit scale can be reduced and the circuit power consumption can be reduced.
[0026] See also Figure 3 , Figure 3 FIG. 2 is a schematic diagram of a specific circuit of each module of the analog multiplier-adder circuit based on a memristor in an embodiment of the present invention. Figure 3 As shown, the column memristor unit 1 for performing analog multiplication and addition operations may include a first NMOS tube, a second NMOS tube ... and a Kth NMOS tube, and a first memristor, a second memristor ... and a Kth memristor.
[0027] As shown in the figure, the sources of the first NMOS tube, the second NMOS tube... and the Kth NMOS tube are respectively connected to one end of the corresponding first memristor, the second memristor... and the Kth memristor; the other ends of the first memristor, the second memristor... and the Kth memristor are commonly connected to the node SL1; the node SL1 is the output end of the column memristor unit; the gates of the first NMOS tube, the second NMOS tube... and the Kth NMOS tube are commonly connected to the node S1; the drains of the first NMOS tube, the second NMOS tube... and the Kth NMOS tube are respectively connected to the nodes BL1, BL2... and BL K , the N column memristor analog multiplier-adder units have K input terminals; the nodes BL1, BL2... and BL K The K input terminals of the multiplier-adder unit are simulated for the N column memristors.
[0028] In an embodiment of the present invention, the multiplication-addition current generator comprises a first MOS tube, a second MOS tube and an eleventh MOS tube, wherein the source electrodes of the first MOS tube and the second MOS tube are connected to the drain electrode of the third MOS tube; the gate electrode of the second MOS tube is connected to the reference voltage V ref ; The drain of the first MOS tube, the drain of the fifth MOS tube, the gate of the fifth MOS tube, and the gate of the sixth MOS tube are connected together; the drain of the sixth MOS tube, the gate of the seventh MOS tube, the drain of the seventh MOS tube, the gate of the eighth MOS tube, and the gate of the ninth MOS tube are connected together; the drain of the second MOS tube, the drain of the fourth MOS tube, the gate of the fourth MOS tube, the gate of the ninth MOS tube, and the gate of the eleventh MOS tube are connected together; the drain of the ninth MOS tube, the drain of the eighth MOS tube, the gate of the first MOS tube, and the output end of the column memristor unit are connected; the drain of the tenth MOS tube is connected to the drain of the eleventh MOS tube and serves as the output end of the multiplication and addition current generator; the source of the fifth MOS tube, the source of the sixth MOS tube, the source of the fourth MOS tube, the source of the ninth MOS tube, and the source of the eleventh MOS tube are connected to the negative electrode of the power supply; the source of the third MOS tube, the source of the seventh MOS tube, the source of the eighth MOS tube, and the source of the tenth MOS tube are connected to the positive electrode of the power supply.
[0029] The current analog-to-digital converter unit 3 is used to convert the output current of the multiplication-addition current generator 2 into a digital signal. The input end of the current analog-to-digital converter unit 3 is connected to the output end of the multiplication-addition current generator 2; the output end of the current analog-to-digital converter unit 3 is the output end of the column memristor analog multiplier-addition unit.
[0030] Combine the following Figure 3The circuit diagram of the column memristor analog multiplier-adder unit shown in the figure introduces the working principle of the present invention. Figure 3 The first MOS tube, the second MOS tube, the third MOS tube, the seventh MOS tube, the eighth MOS tube, and the tenth MOS tube are PMOS tubes; the fourth MOS tube, the fifth MOS tube, the sixth MOS tube, the ninth MOS tube, and the eleventh MOS tube are NMOS tubes.
[0031] In the figure, nodes BL1, BL2, ... and BL K The voltage on the K , the first memristor RRAM1, the second memristor RRAM2... and the Kth memristor RRAM K The resistance values are R1, R2…R K , the corresponding conductivities are G1, G2…G K , the VOUT voltage is:
[0032] VOUT = V ref (1)
[0033] Then the multiplication and addition current I1 is:
[0034] I1=VBL1 / R1+VBL2 / R2+…+VBL K / R K =VBL1*G1+VBL2*G2+…+VBL K *G K (2)
[0035] Among them, the leakage current of MOS tube M8 and MOS tube M9 are Id M8 、Id M9 , according to the current conservation principle:
[0036] I1=Id M8 -Id M9 (3)
[0037] like Figure 3 In the equation, since the ratio of the aspect ratio of M9 to that of M10 is the same as the ratio of the aspect ratio of S to that of M9 and M11, I2 is:
[0038] I2=I1 / S (4)
[0039] From the above, it can be seen that compared with the traditional memristor-based analog multiplier-adder circuit, the memristor-based analog multiplier-adder circuit proposed in the present invention has a simpler architecture and low circuit overhead, and there is no need to convert the current into voltage and then perform analog-to-digital conversion. The multiplier-adder current can be directly converted into a digital signal, which reduces both the circuit complexity and the circuit power consumption.
[0040] The above-described embodiments are only preferred embodiments of the present invention, and the embodiments are not intended to limit the patent protection scope of the present invention. Therefore, any equivalent structural changes made using the description and drawings of the present invention should also be included in the protection scope of the present invention.
Claims
1. A memristor-based analog multiplier-adder circuit, characterized in that: The invention comprises N column memristor analog multiplier-adder units, wherein the column memristor analog multiplier-adder unit comprises a column memristor module, a multiplier-adder current generator and a current analog-to-digital converter, and the column memristor analog multiplier-adder unit has K input terminals, where N and K are positive integers; wherein, The column memristor module receives K voltage values inputted from the K input terminals and performs analog multiplication and addition operations; the input terminal of the multiplication and addition current generator is connected to the output terminal of the column memristor module, and the output terminal of the multiplication and addition current generator outputs the multiplication and addition current of the analog multiplication and addition operation; the current analog-to-digital converter is used to convert the output current of the multiplication and addition current generator into a digital signal, and the input terminal of the current analog-to-digital converter is connected to the output terminal of the multiplication and addition current generator; the output terminal of the current analog-to-digital converter is the output terminal of the column memristor analog multiplier unit; The column memristor module comprises: The first NMOS tube, the second NMOS tube, ... and the Kth NMOS tube, and a first memristor, a second memristor, ... and a Kth memristor; wherein, The sources of the first NMOS tube, the second NMOS tube, ... and the Kth NMOS tube are respectively connected to one end of the corresponding first memristor, the second memristor, ... and the Kth memristor; The first memristor RRAM1, the second memristor RRAM2 . . . and the Kth memristor RRAM K The other end of is commonly connected to a node SL1; the node SL1 is the output end of the column memristor module; The gates of the first NMOS tube, the second NMOS tube, ... and the Kth NMOS tube are commonly connected to a node S1; The drains of the first NMOS tube, the second NMOS tube ... and the Kth NMOS tube are connected to the node BL1, the node BL2 ... and the node BL K , the N column memristor analog multiplier-adder units have K input terminals; the nodes BL1, BL2... and BL K Simulating K input terminals of a multiplier-adder unit for the N column memristors; The multiplication and addition current generator comprises a first MOS tube, a second MOS tube and an eleventh MOS tube, wherein the source of the first MOS tube and the second MOS tube are connected to the drain of the third MOS tube; the gate of the second MOS tube is connected to the reference voltage V ref ; The drain of the first MOS tube, the drain of the fifth MOS tube, the gate of the fifth MOS tube, and the gate of the sixth MOS tube are connected together; the drain of the sixth MOS tube, the gate of the seventh MOS tube, the drain of the seventh MOS tube, the gate of the eighth MOS tube, and the gate of the tenth MOS tube are connected together; the drain of the second MOS tube, the drain of the fourth MOS tube, the gate of the fourth MOS tube, the gate of the ninth MOS tube, and the gate of the eleventh MOS tube are connected together; the drain of the ninth MOS tube, the drain of the eighth MOS tube, the gate of the first MOS tube, and the output end of the column memristor module are connected; the drain of the tenth MOS tube and the drain of the eleventh MOS tube are connected and serve as the output end of the multiplication and addition current generator; the source of the fifth MOS tube, the source of the sixth MOS tube, the source of the fourth MOS tube, the source of the ninth MOS tube, and the source of the eleventh MOS tube are connected to the negative electrode of the power supply; the source of the third MOS tube, the source of the seventh MOS tube, the source of the eighth MOS tube, and the source of the tenth MOS tube are connected to the positive electrode of the power supply.
2. The memristor-based analog multiplier-adder circuit according to claim 1, characterized in that: The first MOS tube, the second MOS tube, the third MOS tube, the seventh MOS tube, the eighth MOS tube, and the tenth MOS tube are PMOS tubes; the fourth MOS tube, the fifth MOS tube, the sixth MOS tube, the ninth MOS tube, and the eleventh MOS tube are NMOS tubes.
Citation Information
Patent Citations
A method of mitigating latent path effects in memristor cross array and related devices
CN111210859A