Integrated circuit data processing engine tile architecture

Abstract

An example data processing engine (DPE) (110) for use in an integrated circuit (IC) array (105) includes a core (202); a memory (204) including a data memory (208) and a program memory (206) coupled to the core, the data memory coupled to the core and including at least one connection (316) to a respective at least one additional core (202) external to the DPE; support circuitry including hardware synchronization circuitry (218) and direct memory access (DMA) circuitry (220) each coupled to the data memory; a stream interconnect (210) connected to the DMA circuitry and the core; and a memory mapped interconnect (212) coupled to the core, the memory, and the support circuitry.

Description

Technical Field

[0001] Various examples of the present disclosure relate generally to electronic circuits and, more particularly, to a data processing engine tile architecture for an integrated circuit (IC). Background Art

[0002] Processors, systems on a chip (SoCs), and application specific integrated circuits (ASICs) may include multiple cores for performing computing operations such as processing digital signals, performing encryption, executing software applications, rendering graphics, etc. In some examples, the cores may transfer data between each other while performing computing operations. Typically, transferring data between cores requires the data to pass through a core-to-core interface, which increases latency and does not efficiently utilize memory. Summary of the invention

[0003] Techniques related to a data processing engine tile architecture for an integrated circuit (IC) are described. In one example, a data processing engine (DPE) for an array of DPEs in an integrated circuit (IC) includes a core; a memory including a data memory and a program memory, the program memory coupled to the core, the data memory coupled to the core and including at least one connection to a corresponding at least one additional core external to the DPE; support circuitry including hardware synchronization circuitry and direct memory access (DMA) circuitry, each coupled to the data memory; a stream interconnect coupled to the DMA circuitry and the core; and a memory mapped interconnect coupled to the core, the memory, and the support circuitry.

[0004] In some embodiments, the support circuitry may also include debug circuitry coupled to the core and the memory.

[0005] In some embodiments, the data memory may include one or more random access memory (RAM) banks and arbitration logic configured to arbitrate access to the one or more RAM banks.

[0006] In some embodiments, the hardware synchronization circuitry may be configured to lock access to one or more RAM banks by a core, a core in another DPE in the DPE array, and the DMA circuitry.

[0007] In some embodiments, the hardware synchronization circuitry may be configured to provide synchronization between the core and at least one other core in at least one other DPE in the DPE array.

[0008] In some embodiments, the DPE may also include a plurality of registers coupled to the memory mapped interconnect.

[0009] In some embodiments, the flow interconnect may include a flow switch having at least one connection to at least one additional DPE in the array of DPEs.

[0010] In some embodiments, the flow switch may include a connection to the core.

[0011] In some embodiments, the flow interconnect may include a plurality of flow switches, each flow switch having at least one connection in a different direction to a different DPE in the DPE array.

[0012] In some embodiments, the memory mapped interconnect may include a memory mapped switch having at least one connection to at least one additional DPE in the array of DPEs.

[0013] In some embodiments, a core may include a cascade interface to another core in another DPE disposed in the DPE array.

[0014] In some embodiments, a core may include a plurality of registers coupled to a memory mapped interconnect.

[0015] In some embodiments, the core may include a very long instruction word (VLIW) processor, a single instruction multiple data (SIMD) processor, or a VLIW SIMD processor.

[0016] In some embodiments, program memory may be provided in the core and may also include a memory module having data memory and supporting circuitry.

[0017] In some embodiments, a memory module may include at least one interface configured to be shared by at least one additional DPE in the DPE array.

[0018] In some embodiments, the DMA circuitry may include a first DMA circuit having an output coupled to the streaming interconnect and an input coupled to the data memory; and a second DMA circuit having an input coupled to the streaming interconnect and an output coupled to the data memory.

[0019] In one example, an integrated circuit (IC) includes a data processing engine (DPE) array having a plurality of DPEs, each of the plurality of DPEs including a core; a memory including a data memory and a program memory, the program memory coupled to the core, the data memory coupled to the core and including at least one connection to a corresponding at least one additional core external to the DPE; support circuitry including hardware synchronization circuitry and direct memory access (DMA) circuitry, each coupled to the data memory; a stream interconnect coupled to the DMA circuitry and the core; and a memory mapped interconnect coupled to the core, the memory, and the support circuitry.

[0020] In some embodiments, program memory may be provided in the core and may also include a memory module having data memory and supporting circuitry.

[0021] In some embodiments, a memory module may include at least one interface configured to be shared by at least one additional DPE in the DPE array.

[0022] In some embodiments, the core may include a very long instruction word (VLIW) processor, a single instruction multiple data (SIMD) processor, or a VLIW SIMD processor.

[0023] These and other aspects can be understood with reference to the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order that the manner in which the above features are understood in detail, a more specific description briefly outlined above may be obtained by reference to example implementations, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings only illustrate typical example implementations and therefore should not be considered as limiting the scope thereof.

[0025] Figure 1 is a block diagram of a system on a chip (SoC) according to one example.

[0026] Figure 2 is a block diagram depicting a tile circuit according to one example.

[0027] Figure 3 is described in more detail based on an example Figure 2 Block diagram of the patchwork circuit.

[0028] Figure 4 is a block diagram depicting interconnected circuitry according to one example.

[0029] Figure 5 is a block diagram depicting processing circuitry 350 according to another example.

[0030] Figure 6 is a block diagram depicting a data processing engine according to one example.

[0031] Figure 7 is a block diagram depicting a pipeline in a vector processor according to one example.

[0032] Figure 8 is a table showing an example configuration of a vector register file according to one example.

[0033] Fig. 9 is a diagram showing an example Figure 7 A block diagram of a logical view of the pipeline of a vector processor is shown.

[0034] Fig.10 is a flow chart depicting the operation of a stall circuit according to one example.

[0035] Fig.11 It depicts a Figure 1 An implementation of a SoC is shown as a block diagram of a programmable IC according to one example.

[0036] Fig.12 The diagram shows a Figure 5 Field Programmable Gate Array (FPGA) implementation of programmable IC.

[0037] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements of one example may be beneficially incorporated in other examples. DETAILED DESCRIPTION

[0038] Various features are described below with reference to the accompanying drawings. It should be noted that the drawings may or may not be drawn to scale, and that throughout the drawings, elements of similar structure or function are represented by similar reference numerals. It should be noted that the drawings are intended only to facilitate the description of the features. They are not intended to be an exhaustive description of the claimed invention or a limitation on the scope of the claimed invention. In addition, the illustrated examples do not necessarily have all the aspects or advantages shown. The aspects or advantages described in conjunction with a particular example are not necessarily limited to that example, and may be practiced in any other example even if not illustrated or explicitly described as such.

[0039] Figure 1 is a block diagram of a device 100 including a data processing engine (DPE) array 105 according to one example. In an example, the device 100 is a system-on-chip (SoC) type device. Generally speaking, a SoC refers to an IC that includes two or more subsystems that can interact with each other. As an example, the SoC may include a processor that executes program code and one or more other circuits. The other circuits may be implemented as hardwired circuitry, programmable circuitry, other subsystems, and / or any combination thereof. The circuits may collaborate with each other and / or with the processor. The DPE array 105 includes a plurality of data processing engines (DPEs) 110, which may be arranged in a grid, cluster, or checkerboard pattern in the device 100. Although Figure 1 The DPEs 110 are illustrated as being arranged in a 2D array having rows and columns, but examples are not limited to such an arrangement. Further, the array 105 may be of any size and have any number of rows and columns formed by the DPEs 110 .

[0040] In one embodiment, the DPEs 110 are identical. That is, each DPE 110 (also referred to as a tile or block) in the DPE 100 may have identical hardware components or circuitry. Further, the examples herein are not limited to the DPE 110. Instead, the device 100 may include an array of any kind of processing elements or data processing engines. Moreover, the DPE 110 may be a cryptographic engine or other specialized hardware for performing one or more specialized tasks. As such, the DPE 110 may generally be referred to as a data processing engine.

[0041] exist Figure 1 In the embodiment of the present invention, array 105 includes DPEs 110 that are all of the same type (e.g., a homogeneous array). However, in another embodiment, array 105 may include engines of different types. For example, array 105 may include DPEs 110, encryption engines, forward error correction (FEC) engines, etc. Regardless of whether array 105 is homogeneous or heterogeneous, DPEs 110 may include connections to memory modules in adjacent DPEs 110 that permit DPEs 110 to share memory modules as described in more detail below.

[0042] In one embodiment, DPE 110 is formed of non-programmable logic, i.e., hardened. One advantage of this is that DPE 110 can occupy less space in device 100 relative to using programmable logic to form hardware elements in DPE 110. That is, using hardened logic circuitry or non-programmable logic circuitry to form hardware elements in DPE 110 (such as program memory, instruction fetch / decode units, fixed-point vector units, floating-point vector units, arithmetic logic units (ALUs), multiply accumulators (MACs), etc.) can significantly reduce the footprint of array 105 in device 100. Although DPE 110 can be hardened, this does not mean that DPE 110 is not programmable. That is, DPE 110 can be configured when device 100 is powered on or restarted to perform different functions or tasks.

[0043] The DPE array 105 also includes a SoC interface block 115, which serves as a communication interface between the DPE 110 and other hardware components in the device 100. In this example, the device 100 includes a network on chip (NoC) 120, which is communicatively coupled to the SoC interface block 115. Although not shown, the NoC 120 can be extended to the entire device 100 to permit various components in the device 100 to communicate with each other. For example, in one physical implementation, the DPE array 105 can be disposed in the upper right portion of the integrated circuit forming the device 100. However, using the NoC 120, the array 105 can still communicate with various subsystems (e.g., programmable logic (PL)) 120, processor subsystem (PS) 130, or input / output (I / O) 135) that may be disposed at different locations throughout the device 100.

[0044] In addition to providing an interface between DPE 110 and NoC 120, SoC interface block 115 may also provide a connection directly to communication fabric in PL 122. In one embodiment, SoC interface block 115 includes separate hardware components for communicatively coupling DPE 110 to NoC 120 and to PL 122 disposed near array 105 in device 100.

[0045] although Figure 1 One block of PL 122 is illustrated, but device 100 may include multiple blocks of PL 122 (also referred to as configuration logic blocks), which may be provided at different locations in device 100. For example, device 100 may include hardware elements forming a field programmable gate array (FPGA). However, in other embodiments, device 100 may not include any PL 122, for example, device 100 is an ASIC.

[0046] Figure 2 is a block diagram depicting a DPE 110 according to one example. As discussed above and as Figure 1 As shown, DPE 110 can be used to implement a DPE in a DPE array. DPE 110 includes core 202, memory 204, DPE interconnect 209, and support circuit system 214. DPE interconnect 209 includes stream interconnect 210 and memory mapping (MM) interconnect 212. In one example, support circuit system 214 includes debug / trace / profile circuit system 216, hardware (HW) synchronization circuit system ("HW lock 218"), and direct memory access (DMA) circuit system ("DMA 220"). Memory 204 includes program memory ("PM 206") and data memory ("DM 208").

[0047] Core 202 includes one or more computing units for processing data according to one or more instructions stored in PM 206. In one example, core 202 includes a very long instruction word (VLIW) processor, a single instruction multiple data (SIMD) or a vector processor, or a VLIW SIMD / vector processor. In one example, PM 206 is dedicated to core 202 (e.g., PM 206 stores one or more instructions used only by core 202 in DPE 200). In one example, PM 206 includes a single-port random access memory (RAM). PM 206 can be coupled to MM interconnect 212 for configuration and loading of instructions. In one example, PM 206 supports parity check, error correction code (ECC) protection and reporting, or both parity check and ECC. For example, PM 206 can support 9-bit ECC and can correct 1-bit error or 2-bit error (e.g., 128-bit) in program instructions.

[0048] The core 202 may be directly coupled to the stream interconnect 210 to receive one or more input streams and / or provide one or more output streams. In addition, the core 202 may read data and write data to the DM 208 in the DPE 200. As further discussed below, the core 202 in the DPE 200 may also access the DM in one or more adjacent tile circuits (e.g., north adjacent tile circuits, south adjacent tile circuits, east adjacent tile circuits, and west adjacent tile circuits). In one example, as further discussed below, the core 202 may also include a direct connection (e.g., one or more input and output cascade connections) to the data processing engine in one or more adjacent tiles to forward the accumulator output. In one example, the core 202 treats the DM 208 in the DPE 200 and one or more other DMs in one or more adjacent tiles as a continuous memory block. The core 202 may also include an interface to the HW lock 218 and an interface to the debug / trace / profile circuit system 216. Debug / trace / profile circuitry 216 may include trace, debug, and / or profile circuitry.

[0049] MM interconnect 212 may be an AXI memory mapped interconnect or the like, which is configured to transfer data using address transactions between components. In one example, MM interconnect 212 is used for configuration, control, and debugging functions of DPE 200. MM interconnect 212 includes one or more switches that route transactions based on addresses. Circuitry may use MM interconnect 212 to access memory 204, core 202, DMA 220, and configuration registers in DPE 200.

[0050] The stream interconnect 210 may be an Advanced eXtensible Interconnect (AXI) stream interconnect or the like, which is configured for transmission of stream data between components. The stream interconnect 210 is used to transmit data between the DPE 200 and external circuits. The stream interconnect 210 may simultaneously support circuit switch structures and packet switch structures for both data and control.

[0051] In one example, as further described below, DM 208 may include one or more memory groups (e.g., random access memory (RAM) groups). DMA 220 is coupled between stream interconnect 210 and DM 208. DMA 220 is configured to move data from stream interconnect 210 to DM 208, and to move data from DM 208 to stream interconnect 210. In this way, an external circuit (e.g., a circuit in an embedded processing system of a circuit or IC configured with programmable logic) can use DMA to read data from DM 208 through stream interconnect 210 and write data to DM 208. DMA 220 can be controlled by MM interconnect 212 and / or stream interconnect 210. In one example, DM 208 supports parity checking, error correction code (ECC) protection and reporting, or both parity checking and ECC. For example, DM 208 can support 9-bit ECC (e.g., 128-bit data).

[0052] The HW lock 218 may be used to lock a specific memory bank of the DM 208 for access by the core 202, another data processing engine in another tile, or the DMA 220. The HW lock 218 provides synchronization between adjacent data processing engines in adjacent tiles, between the core 202 and the DMA 220, and between the core 202 and external circuits (e.g., external processors). The HW lock 218 may also be used to lock a specific buffer in the DM 208, which may be stored in one or more memory banks or in a portion of a single memory bank. The debug / trace / profile circuitry 216 is configured to provide debug, trace, and profile functions. The debug / trace / profile circuitry 216 may track events generated by circuits in the DPE 200. The debug / trace / profile circuitry 216 may provide profile functions, such as configurable performance counters.

[0053] Figure 32 is a block diagram depicting DPE 200 in more detail according to an example. In this example, DPE 200 includes core 202, memory module 351, and DPE interconnect 209. Core 202 includes compute circuitry 203 and PM 206. Memory module 351 includes memory interfaces 302N, 302S, 302E, and 302W (collectively, memory interfaces or individually, "mem IF"), RAM group 318, HW lock 218, registers ("reg 304"), DMA interface 204A, and DMA interface 220B. Computation circuitry 203 includes registers ("reg 306"). DPE interconnect 209 includes MM interconnect 212 and stream interconnect 210 (e.g., Figure 2 MM interconnect 212 and stream interconnect 210 can both access RAM groups 318. RAM groups 318 include arbitration logic 319 for each group. Arbitration logic 319 is configured to control which interface (N, S, E, W, DMA, external PS, etc.) can access which group. Figure 4 Additional details of DPE interconnect 209 are discussed in detail in the example of FIG.

[0054] The DPE interconnect 209 includes a stream connection 314W to the west tile, a stream connection 314E to the east tile, a stream connection 314N to the north tile, and a stream connection 314S to the south tile. Each stream connection 314 includes one or more independent stream interfaces (e.g., buses), each stream interface having a specific bit width. The DPE interconnect 209 also includes a memory mapped connection 312S from the south tile and a memory mapped connection 312N to the north tile. Although only a north MM connection and a south MM connection are shown, it should be understood that the DPE interconnect 209 may include other configurations for MM interconnection (e.g., east to west, west to east, north to south, etc.). It should be understood that the DPE interconnect 209 may include other configurations besides Figure 3 In general, DPE interconnect 209 includes at least one streaming connection 314 and at least one memory mapped connection 312.

[0055] Computation circuitry 203 includes connections 308W to memory circuitry in the west tile, connections 308S to memory circuitry in the south tile, connections 308N to memory circuitry in the north tile, and connections 308E to memory module 351. Computation circuitry 203 includes a stream interface to DPE interconnect 209. Computation circuitry 203 also includes connections 310A from cores in the west tile and connections 310B to cores in the east tile (e.g., cascade connections). It should be understood that the DPE may include other components in addition to the DPE interconnect 209. Figure 3Other arrangements of memory connections and cascade connections other than those shown in the examples of FIG. 1 . In general, computing circuitry 203 includes at least one memory connection and may include at least one cascade connection.

[0056] 308E of computing circuitry 203. mem IF 302N is coupled to a memory connection of a data processing engine in the north tile. mem IF 302E is coupled to a memory connection of a data processing engine in the east tile. mem IF 302S is coupled to a memory connection of a data processing engine in the south tile. mem IFs 302W, 302N, 302E, and 302S are coupled to RAM bank 318. DMA 220A includes an output coupled to DPE interconnect 209 for handling memory to interconnect streams. DMA 220B includes an input coupled to DPE interconnect 209 for handling interconnect to memory streams. reg 304 and reg 306 are coupled to DPE interconnect 209 to receive configuration data therefrom (e.g., using a memory mapped interconnect).

[0057] Figure 4 2 is a block diagram depicting a DPE interconnect 209 according to an example. The DPE interconnect 209 includes a stream switch 402 and an MM switch 404. The stream switch 402 is coupled to a west stream interface 406W, a north stream interface 406N, an east stream interface 406E, and a south stream interface 406S. The west stream interface 406W receives a stream and provides the stream to the DPE interconnect of the west tile. The north stream interface 406N receives a stream and provides it to the DPE interconnect of the north tile. The west stream interface 406W receives a stream and provides the stream to the DPE interconnect of the west tile. The south stream interface 406S receives a stream and provides the stream to the DPE interconnect of the south tile. The MM switch 404 is coupled to a north MM interface 408N and a south MM interface 408S. The north MM interface 408N is coupled to the DPE interconnect in the north tile. The south MM interface 408S is coupled to the DPE interconnect in the south tile.

[0058] Stream switch 402 includes a first-in, first-out (FIFO) circuit (FIFO 412) and registers (registers 410). FIFO 412 is configured to buffer streams passing through stream switch 402. Reg 410 stores configuration data for stream switch 402, which controls the routing of streams through the stream switch. Reg 410 receives configuration data from MM switch 404. Stream switch 402 may include additional interfaces to compute circuitry 203 and additional interfaces to DMA circuitry 220. Stream switch 402 may send and receive control streams, and receive trace streams (e.g., from debug / trace / profile circuitry 216).

[0059] Figure 5 is a block diagram depicting a core 202 according to another example. Figure 5 Elements in FIG. 5 that are the same or similar to those discussed above are designated using the same reference numerals. In this example, core 202 also includes a stall circuit 502 . Fig.10 is a flow chart depicting the operation of the stall circuit 502 according to one example.

[0060] refer to Figure 5 and 10 , stall circuit 502 is coupled to computing circuit system 203 and is configured to provide a stall signal. Stall circuit 502 also provides a stall signal to memory module 351. Stall circuit 502 can assert the stall signal to stall computing circuit system 203 (e.g., suspend the operation of computing circuit system 203 so that it does not process data). When the stall signal is deasserted, computing circuit system 203 is not stalled and processes data. Stall circuit 502 sets the state of the stall signal based on various inputs from circuits in DPE 200 or circuits external to DPE 200. In addition, once stall circuit 502 stops computing circuit system 203, stall circuit 502 can stop other components of DPE 200. For example, stall circuit 502 can stop specific blocks in memory module 351 that provide data to computing circuit system 203. That is, because computing circuit system 203 is stopped, "flying" data from memory module 351 can be stalled to avoid data loss. In another example, stall circuit 502 may perform a similar function for program memory 206. That is, because computing circuitry 203 is stopped, "in-flight" instructions from program memory 206 may be stalled to avoid instruction loss.

[0061] In one example, stall circuit 502 includes inputs 504, 506, 508, 510, 512, and 514. Input 504 is coupled to arbitration logic 319 and is configured to receive a signal indicating a memory conflict (step 1002). For example, another data processing engine may be accessing a particular RAM bank 318 in DPE 200, and then computing circuit system 203 may not be able to access the particular RAM bank 318. Arbitration logic 319 signals stall circuit 502, which asserts a stall signal to stall computing circuit system 203 and prevent computing circuit system 203 from accessing RAM bank 318 under contention.

[0062] Input 506 is coupled to PS 130 and is configured to receive a control signal for stalling computing circuitry 203 (step 1004). For example, software executing on PS 130 may stall computing circuitry 203 and restore computing circuitry 203 as required.

[0063] Input 508 is coupled to flow switch 402 and is configured to receive a signal indicating an empty condition or a full condition of FIFO 412 (step 1006). For example, if FIFO 412 is in a full condition, FIFO 412 cannot store additional data output from computation circuitry 203. Therefore, computation circuitry 203 is stalled to prevent FIFO 412 from overflowing. Once FIFO 412 is no longer in a full condition (e.g., in an empty condition), computation circuitry 203 may be restored.

[0064] Input 510 is coupled to register 514 and is configured to receive a signal indicating stall or recovery (step 1008). In one example, register 514 can be programmed through MM interconnect 212 and allows a user to program stall or recovery of computing circuitry 203 through configuration of the array.

[0065] Input 512 is coupled to debug / trace / profile circuitry 216 and is configured to receive a signal indicating one or more events that require a stall of computing circuitry 203 (step 1010). Event actions may include enabling, disabling single-step debugging, etc., and may be configured to be triggered when a particular event occurs.

[0066] Input 514 is coupled to HW lock 218 and is configured to receive a signal indicating whether RAM bank 418 has been locked for access by another circuit (e.g., another data processing engine) (step 1012). In this case, computing circuit system 203 is stalled until the specific RAM bank 418 being accessed becomes free.

[0067] At step 1014, in response to the resolution of all conditions that caused assertion of the stall signal, the stall circuit 502 de-asserts the stall signal. That is, when each condition that caused assertion of the stall signal is resolved, the stall circuit 502 de-asserts the stall signal to restore full operation of the DPE.

[0068] Figure 66 is a block diagram depicting a core 202 according to an example. The core 202 includes a register file 602, a computational circuit system 203, and a support circuit system 606. The register file 602 includes a scalar register file 608 and a vector register file 610. The scalar register file 608 includes general registers, pointer registers, modification registers, configuration registers, etc. The vector register file 610 includes high-width registers (compared to scalar registers) that support SIMD instructions for vector data paths. The vector register file 610 may include vector registers, accumulator registers, etc. The register file 602 may include other types of registers, such as a program counter, a stack pointer, a link register, various configuration, control and status registers, etc.

[0069] The computational circuit system 203 includes a scalar processor 612 and a vector processor 614. The scalar processor 612 is configured to perform scalar arithmetic, which includes signed and unsigned multiplication, addition / subtraction, shifting, comparison, and logical operations, basic functions (such as square root, sine / cosine, etc.). The vector processor 614 is configured to perform vector arithmetic, which includes a permutation function, a pre-addition function, a multiplication function, a post-addition function, an accumulation function, a shift, a rounding and saturation function, an upward shift function, etc. The vector processor 614 supports multiple precisions of complex operands and real operands. The vector processor 614 may include a fixed-point data path and a floating-point data path.

[0070] The support circuit system 606 includes a memory interface 616, an address generator 618, an instruction acquisition and decoding circuit system 620, and one or more additional interfaces 622. The instruction acquisition and decoding circuit system 620 is configured to acquire instructions from the PM 206, decode the acquired instructions, and provide control signals to the processor 604 to control its operation according to the decoded instructions. The address generator 618 is configured to generate addresses for data storage to load data from the data storage or store data to the data storage. The memory interface 616 is configured to communicate with the data storage to send data to the data storage and receive data from the data storage according to the decoded instructions and the addresses generated by the address generator 618. Other interfaces 622 may include an interface to the HW lock 218, an interface to the stream interconnect 210, an interface to receive one or more cascade streams from other data processing engines, an interface to the debug / trace / profile circuit system 216, etc.

[0071] Figure 7is a block diagram depicting a pipeline 700 in a vector processor 614 according to an example. Pipeline 700 is configured to perform fixed-point vector processing and includes a multiply-accumulate (MAC) path 701 and an upshift path 703. MAC path 701 reads values ​​from vector registers, permutes them in a user-controllable manner, performs an optional pre-addition, post-adds them before multiplying, and then accumulates them to the previous value of the accumulator register. Upshift path 703 operates in parallel with MAC path 701 and is configured to read vectors, shift them up, and feed the results to an accumulator. Pipeline 700 also includes control circuitry 750, which is configured to control various circuits in MAC path 701 and upshift path 703, as discussed further below.

[0072] Figure 8 800 is a table showing an example configuration of a vector register file 610 according to an example. As shown in table 800, core 202 includes three separate vector register files represented as R, C and D, and their additional prefixes specify their widths. In this example, the width of each of the underlying hardware registers in the underlying hardware registers is 128 bits. The hardware registers are prefixed with the letter "V" (for vectors). Two "V" registers can be combined together to form a 256-bit register, which is prefixed with "W" (for wide vectors). Further, WR, VC and WD registers can be grouped in pairs to form registers (XA, XB, XC and XD) with a width of 512 bits. Finally, registers XA and XB together form a YA register with a width of 1024 bits, while XD and XB form a partially overlapping YD register with a width of 1024 bits. In YD, the XD register is the LSB part, and the XB register is the MSB part.

[0073] The vector registers in the vector register file 610 may store data in different formats. For example, a 128-bit register may be used to represent 8-bit signed data for 16 lanes (v16int8), 8-bit unsigned real data for 16 lanes (v16uint8), 16-bit signed data for 8 lanes (v8int16), 16-bit complex data for 4 lanes (v4cint16), and 32-bit complex data for 2 lanes (v2cint32).

[0074] Figure 8The table 800 shown depicts only one possible configuration of the vector register file 610. For example, the vector register file 610 may include fewer or more than 16 hardware registers, which may have any bit width and may be grouped into larger registers, which also have a bit width different from that shown. For example, various register files may be combined to provide a smaller number of larger registers. Alternatively, various registers may be divided into a larger number of smaller registers.

[0075] return Figure 7 , pipeline 700 includes register file 702 (which is formed by the cascade of XA and XB), register file 704 (XC), and register file 706 (XD). Figure 8 In the example of the embodiment of the present invention, register file 702 includes eight 128-bit hardware registers, register file 704 includes four 128-bit hardware registers, and register file 706 includes four 128-bit hardware registers. In other examples, register files 702, 704, and 706 may include other numbers of registers with different bit widths. The configuration of register files 702, 704, and 706 is an example. In another example, register files 702, 704, and 706 may be unified into a single register file. In other examples, pipeline 700 may include more than three register files.

[0076] The pipeline 700 also includes a MAC path 701, which has a permutation circuit 708 (PMXL), a permutation circuit 710 (PMXR), a permutation circuit 712 (PMC), a pre-adder 714, a special operation circuit 716 (YMX), a multiplier 720 (MPY), a post-adder 723, an accumulator 730 (ACC), and an accumulation register file 732 (AM). In one example, the post-adder 723 includes two separate stages, namely, the post-adder 722 and the post-adder 724. The pipeline 700 includes an upward shift path 703, which has a multiplexer 718 (MUX), an upward shift circuit 726 (UPS), and an accumulator multiplexer 734 (ACM). Although three permutation circuits 708, 710, and 712 are shown in the example, in other examples, the pipeline 700 may include a single permutation circuit that combines the functions of the permutation circuits 708, 710, and 712.

[0077] An input of permute circuit 708 is coupled to the output of register file 702, an input of permute circuit 710 is coupled to the output of register file 702, and an input of permute circuit 712 is coupled to the output of register file 704. A first input of pre-adder 714 is coupled to the output of permute circuit 708, and a second input of pre-adder 714 is coupled to the output of permute circuit 710. A first input of special operation circuit 716 is coupled to the output of permute circuit 710, and a second input of special operation circuit 716 is coupled to the output of permute circuit 712. The outputs of pre-adder 714 and special operation circuit 716 are coupled to the input of multiplier 720. The output of multiplier 720 is coupled to the input of post-adder 722. The output of post-adder 722 is coupled to the input of post-adder 724. The output of post-adder 724 is coupled to the input of accumulator 730. The output of accumulator 730 is coupled to the input of register file 732.

[0078] In one example, register file 702 contains a 1024-bit vector (e.g., a concatenation of XA::XB, each of which is 512 bits). An input (pmxA) to permute circuits 708 and 710 may be 512 bits. Likewise, another input (pmxB) to permute circuits 708 and 710 may be 512 bits. Thus, each permute circuit 708 and 710 receives a concatenation of pmxA::pmxB (e.g., 1024 bits) from register file 702.

[0079] The permutation circuit 708 is configured to permute the data from the register file 702 for the "left" input of the pre-adder 714. The permutation circuit 710 is configured to permute the data from the register file 702 for the "right" input of the pre-adder 714 or alternatively for the first input of the special operation circuit 716. The permutation circuit 712 is configured to permute the data from the register file 704 for the input of the special operation circuit 716. In one example, the permutation circuits 708 and 710 are functionally identical. The operation of the permutation circuits 708, 710 and 712 as the data selection network of the vector processor 614 is further discussed below. The permutation circuit 708 includes an output (praXL) that can be 512 bits. The permutation circuit 710 includes an output (praXR), which can also be 512 bits. The permutation circuit 712 includes an output pmcR, which can also be 512 bits. As discussed below, each of permutation circuits 708 , 710 , and 712 may receive control signals from control circuit 750 to operate.

[0080] The pre-adder 714 can operate in multiple modes based on the control signal from the control circuit 750. In the first mode, the pre-adder 714 feeds the input data (praXL::praXR) to the multiplier 720. In the first mode, no pre-addition is performed. In the second mode, the pre-adder 714 can add / subtract the output (praXL) of the permutation circuit 708 with the output (praXR) of the permutation circuit 708. The special operation circuit 716 can operate in multiple modes. In the first mode, the special operation circuit 716 feeds the input data to the multiplier 720 (praXR::pmcR). In the additional mode, the special operation circuit 716 can output a constant "1" value, perform sign extension on the input data, and perform the same type of operation on the input data.

[0081] The multiplier 720 is configured to multiply the output of the pre-adder 714 with the output of the special operation circuit 716. The multiplier 720 may include a multiplier circuit array, which is configured to multiply a plurality of different parts of the output of the pre-adder 714 with different parts of the output of the special operation circuit 716. The operation of the multiplier 720 is determined by a control signal from the controller 750. The post-adder 722 is configured to reduce the output path of the multiplier 720 by adding / subtracting a specific path. For example, the post-adder 722 can use adjacent even paths and adjacent odd paths and add (or subtract) them. The post-adder 722 is configured to operate in different modes. In the first mode, the post-adder 722 passes the output from the post-adder 722 and does not perform additional functions. That is, the post-adder 724 is optionally included in the processing of the pipeline 700. In the second mode, the post-adder 724 performs a function similar to the post-adder 722. For example, the post adder 724 can take adjacent even paths and adjacent odd paths and add (or subtract) them. The accumulator 730 is configured to accumulate (e.g., add or subtract) the output of the post adder 724. The functions of the post adder 722, the post adder 724, and the accumulator (for addition or subtraction) are determined by control signals from the control circuit 750. The output of the accumulator is stored in the register file 732.

[0082] The shift-up path 703 operates in parallel with the MAC path 701. The shift-up path 703 may read data from the register file 706 or from any of the permutation circuits 708, 710, and 712 via the multiplexer 718. The shift-up circuit 726 is configured to shift (e.g., left shift) the output of the multiplexer 718 by a selectable amount under the control of the control circuit 750. The multiplexer 734 selects the output of the shift-up circuit 726 or the output of the post adder 724 for coupling to the accumulator 730. The shift-up path 703 may be used to initialize the accumulator 730 with a value prior to processing.

[0083] Fig. 9 is a block diagram depicting a logical view 900 of a pipeline 700 for a vector processor 614 according to one example. The logical view 900 shows a register file 902, a permute circuit 904, and a computation circuit 906. The register file 902 is coupled to the computation circuit 906 via the permute circuit 904. The register file 902 may include, for example, Figure 7 and Figure 8 The calculation circuit 906 includes a pre-adder, a special operation circuit, a multiplier, a post-adder, an accumulator, etc., which are configured to process the data in the register file 902. Examples of the calculation circuit 906 are as follows: Figure 7 As shown and described above (eg, circuitry of MAC path 701 ), permutation circuit 904 serves as a data selection network for computation circuit 906 .

[0084] In one example, as discussed above, register file 902 includes register file 702 and register file 704. In one example, permutation circuit 904 includes permutation circuits 708, 710, and 712 as described above. Each register file 702 and 704 provides multiple output paths, wherein each path includes M bits (e.g., 32 paths, each 32 bits). Permutation circuit 708 is coupled to register file 702 and is configured to generate a vector by selecting a set of output paths provided by register file 702. Permutation circuit 710 is also coupled to register file 702 and is configured to generate another vector by selecting a set of output paths provided by register file 702 (e.g., a set of output paths that may be different from the set of output paths selected by permutation circuit 708). Similar to register file 702, register file 704 is configured to provide multiple output paths (e.g., a number different from the number of output paths of register file 702). Permutation circuit 712 is coupled to register file 704 and is configured to generate another vector by selecting its set of output paths. The output of the permutation circuit 904 is provided to the calculation circuit 906 , which performs, for example, a MAC operation on the output of the permutation circuit 904 .

[0085] In one example, each permutation circuit 708 and 710 is configured to select 16 32-bit blocks from each 32-bit path of the thirty-two 32-bit paths of the input vector. The 16 32-bit output paths each form a 512-bit output vector. Each permutation circuit 708 and 710 is a complete multiplexer, and any input can be selected. In one example, each permutation circuit 708 and 710 can be implemented using a series of 16 multiplexers, which are 32 bits wide and selected from 32 different source paths. Alternative structures such as Benes networks can be used. Permutation circuit 712 is similar in function to permutation circuits 708 and 710, but in one example, only selects from an input vector with a width of 256 bits. The selection granularity is 16 bits, so each path of the multiplier can be selected separately. Note that the numbers, widths, etc. discussed above for permutation circuits 708 , 710 , and 712 are exemplary, and the permutation circuits 708 , 710 , and 712 may be configured to have different widths to select from different numbers of paths having different widths.

[0086] Fig.11 is a block diagram depicting a programmable IC 1 according to one example, which can be used as Figure 1 Implementation of the device 100 shown. The programmable IC 1 includes a programmable logic 3, a configuration logic 25, and a configuration memory 26. The programmable IC 1 can be coupled to external circuits such as non-volatile memory 27, DRAM 28, and other circuits 29. The programmable logic 3 includes a logic unit 30, a support circuit 31, and a programmable interconnect 32. The logic unit 30 includes a circuit that can be configured to implement a general logic function of multiple inputs. The support circuit 31 includes a dedicated circuit such as a transceiver, an input / output block, a digital signal processor, a memory, etc. The logic unit and the support circuit 31 can be interconnected using a programmable interconnect 32. Information for programming the logic unit 30, for setting parameters of the support circuit 31, and for programming the programmable interconnect 32 is stored in the configuration memory 26 by the configuration logic 25. The configuration logic 25 can obtain configuration data from the non-volatile memory 27 or any other source (e.g., DRAM 28 or from other circuits 29). In some examples, the programmable IC 1 includes a processing system 2. The processing system 2 may include one or more microprocessors, memory, support circuits, IO circuits, and the like.

[0087] Fig.12A field programmable gate array (FPGA) implementation of a programmable IC 1 is illustrated, which includes a large number of different programmable tiles, including transceivers 37, configurable logic blocks ("CLBs") 33, random access memory blocks ("BRAMs") 34, input / output blocks ("IOBs") 36, configuration and clock logic ("CONFIG / CLOCKS") 42, digital signal processing blocks ("DSPs") 35, dedicated input / output blocks ("I / Os") 41 (e.g., configuration ports and clock ports), and other programmable logic 39 (such as digital clock managers, analog-to-digital converters, system monitoring logic, etc.). The FPGA may also include a PCIe interface 40, an analog-to-digital converter (ADC) 38, etc.

[0088] In some FPGAs, each programmable tile may include at least one programmable interconnect element ("INT") 43 having connections to input and output terminals 48 of programmable logic elements within the same tile, such as Fig.12 As shown in the example included at the top of . Each programmable interconnect element 43 may also include a connection to an interconnect segment 49 of one or more adjacent programmable interconnect elements in the same tile or one or more other tiles. Each programmable interconnect element 43 may also include a connection to an interconnect segment 50 of a general routing resource between logic blocks (not shown). The general routing resources may include routing channels between logic blocks (not shown) and switch blocks (not shown), the logic blocks including tracks of interconnect segments (e.g., interconnect segments 50), and the switch blocks are used to connect the interconnect segments. The interconnect segments of the general routing resources (e.g., interconnect segments 50) may span one or more logic blocks. The programmable interconnect elements 43, together with the general routing resources, implement a programmable interconnect structure ("programmable interconnect") for the illustrated FPGA.

[0089] In one example implementation, the CLB 33 may include a configurable logic element ("CLE") 44, which may be programmed to implement user logic; and a single programmable interconnect element ("INT") 43. In addition to one or more programmable interconnect elements, the BRAM 34 may also include a BRAM logic element ("BRL") 45. Typically, the number of interconnect elements included in a tile depends on the height of the tile. In the depicted example, the BRAM tile has the same height as five CLBs, but other numbers (e.g., four) may also be used. In addition to an appropriate number of programmable interconnect elements, the DSP tile 35 may also include a DSP logic element ("DSPL") 46. In addition to one instance of the programmable interconnect element 43, the IOB 36 may also include, for example, two instances of an input / output logic element ("IOL") 47. It should be clear to those skilled in the art that, for example, the actual I / O pads connected to the I / O logic element 47 are generally not limited to the area of ​​the input / output logic element 47.

[0090] In the depicted example, the horizontal area near the center of the die (eg Fig.12 ) is used for configuration, clock and other control logic. Vertical columns 51 extending from this horizontal area or column are used to distribute clock and configuration signals across the entire width of the FPGA.

[0091] use Fig.12 Some FPGAs of the architecture shown include additional logic blocks that disrupt the regular columnar structure that makes up a large portion of the FPGA. The additional logic blocks can be programmable blocks and / or dedicated logic.

[0092] Notice, Fig.12 It is intended only to illustrate an exemplary FPGA architecture. For example, the number of logic blocks in a row, the relative width of the rows, the number and order of the rows, the types of logic blocks included in the rows, the relative sizes of the logic blocks, and Fig.12 The interconnect / logic implementation included at the top of is purely exemplary. For example, in an actual FPGA, wherever CLBs appear, more than one adjacent CLB row is typically included to facilitate efficient implementation of user logic, but the number of adjacent CLB rows varies with the overall size of the FPGA.

[0093] While the foregoing is directed to particular examples, other examples may be contemplated without departing from the basic scope thereof, and the scope of which is to be determined by the following claims.

Claims

1. A data processing engine (DPE) for use in an integrated circuit (IC) array, comprising: a core comprising computational circuitry and a stall circuit coupled to the computational circuitry; a memory module comprising: one or more memory banks, a first interface coupled to the core, and a second interface coupled to a corresponding at least one additional core external to the DPE; Direct memory access DMA circuitry; hardware synchronization circuitry coupled to the memory module and configured to lock memory in the one or more memory banks so that the locked memory is accessible by one of the cores on the DPE, the DMA circuitry, or the at least one additional core external to the DPE; arbitration logic for each of the one or more memory banks, wherein the arbitration logic is configured to control which of the first interface and the second interface accesses each of the one or more memory banks, and wherein the arbitration logic is further configured to: generate a first signal indicating a memory conflict in response to detecting that the core is attempting to access a same memory bank of the one or more memory banks that is being accessed by at least one additional core external to the DPE; a stream interconnect comprising a stream switch coupled to the DMA circuitry and the core, the stream switch configured to route a data stream through the stream switch based on configuration data stored in a configuration register in the stream switch; and a memory mapped interconnect comprising a memory mapped switch coupled to the core, the memory module, the DMA circuitry, the hardware synchronization circuitry, and the configuration register in the stream switch, the memory mapped switch configured to route address transactions based on memory addresses of corresponding transactions, Wherein the stall circuit is configured to provide a stall signal to the computational circuitry, and wherein the stall signal is configured to stall the computational circuitry in the core in response to the first signal.

2. The DPE of claim 1 further comprising debug circuitry coupled to the core and the memory.

3. The DPE of claim 1, wherein the one or more memory banks are each one or more random access memory (RAM) banks, and the arbitration logic is configured to arbitrate access to the one or more RAM banks.

4. The DPE of claim 3, wherein the hardware synchronization circuitry is configured to: locking access to the one or more RAM banks by the core, a core in another DPE in the DPE array, and the DMA circuitry; or Synchronization is provided between the core and at least one other core in at least one other DPE in the array of DPEs.

5. The DPE of claim 1, wherein the flow switch has at least one connection to at least one additional DPE in the DPE array.

6. The DPE of claim 1, wherein the flow interconnect comprises a plurality of flow switches, each flow switch having at least one connection in a different direction to a different DPE in the DPE array.

7. The DPE of claim 1, wherein the memory mapped switch has at least one connection to at least one additional DPE in the array of DPEs.

8. The DPE of claim 1, wherein the core comprises a cascade interface to another core in another DPE disposed in the DPE array; or a plurality of registers coupled to the memory mapped interconnect.

9. The DPE of claim 1, wherein the core comprises a very long instruction word (VLIW) processor, a single instruction multiple data (SIMD) processor, or a VLIW SIMD processor.

10. The DPE of claim 1 , wherein the DMA circuit system comprises a first DMA circuit having an output coupled to the stream interconnect and an input coupled to the memory module; and a second DMA circuit having an input coupled to the stream interconnect and an output coupled to the memory module.

11. The DPE of claim 1 , wherein the second interface is directly connected to the corresponding at least one additional core external to the DPE.

12. An integrated circuit comprising: A data processing engine (DPE) array having DPEs, each of the DPEs comprising: a core comprising computational circuitry and a stall circuit coupled to the computational circuitry; A memory module comprising: one or more memory banks, a first interface connected to the core, and a second interface connected to a core of a neighboring DPE of the DPE; Direct memory access DMA circuitry; hardware synchronization circuitry coupled to the memory module and configured to lock memory in the one or more memory banks so that the locked memory is accessible by one of the cores on the DPE, the DMA circuitry, or at least one additional core external to the DPE; arbitration logic for each of the one or more memory banks, wherein the arbitration logic is configured to control which of the first interface and the second interface accesses each of the one or more memory banks, and wherein the arbitration logic is further configured to: generate a first signal indicating a memory conflict in response to detecting that the core is attempting to access a same memory bank of the one or more memory banks that is being accessed by at least one additional core external to the DPE; a stream switch connected to the DMA circuitry and the core, the stream switch comprising one or more configuration registers operable to store configuration data to configure the stream switch, the stream switch being configured to route a data stream through the stream switch based on the configuration data; and a memory mapped switch coupled to the core, the memory module, and the one or more configuration registers of the stream switch, the one or more configuration registers being writable by one or more transactions via the memory mapped switch; and in: The flow switches of the DPEs are coupled together to form a flow interconnect, The memory mapped switches of the DPEs are coupled together to form a memory mapped interconnect, and Wherein the stall circuit is configured to provide a stall signal to the computational circuitry, and wherein the stall signal is configured to stall the computational circuitry in the core in response to the first signal.

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