Wide switching frequency range switching mode power supply control topology

Abstract

Embodiments of the present disclosure relate to wide switching frequency range switching mode power supply control topologies. Aspects of the present disclosure provide a circuit (300). In some examples, the circuit includes a timing circuit (302) and a state machine circuit (308). The timing circuit determines a relationship between a duty cycle of a power converter and a threshold value. The state machine circuit is coupled to the timing circuit and includes a plurality of states, including a buck state, a boost state, and a buck-boost state. The state machine circuit transitions between the plurality of states according to a time domain control and a voltage domain control based at least in part on the determined relationship between the duty cycle and the threshold value, transitions between the states according to the time domain control when the time domain control indicates an exit from the buck-boost state, and transitions between the states according to the voltage domain control when the voltage domain control indicates the exit from the buck-boost state.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 850,775, filed on May 21, 2019, entitled “Buck-Boost DC-DC Converter with Wide Switching Frequency Range,” which is hereby incorporated by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate to power supply technology, and more particularly, to a wide switching frequency range switched-mode power supply control topology. Background Art

[0004] A switched-mode power supply (SMPS) transfers power from an input power source to a load by switching one or more power transistors coupled via switching nodes / terminals to an energy storage element (e.g., an inductor / transformer and / or capacitor), which is capable of being coupled to the load. The power transistors may be included in a power converter that includes or is capable of being coupled to the energy storage element. The SMPS may include an SMPS controller to provide one or more gate drive signals to the power transistors. Different switching frequencies are suitable for specific SMPS applications, but optimizing the SMPS controller for a wide range of switching frequencies can be challenging. Summary of the Invention

[0005] Aspects of the present disclosure provide a circuit. In at least some examples, the circuit includes a timing circuit and a state machine circuit. The timing circuit is configured to determine a relationship between a duty cycle of a power converter and a threshold value. The state machine circuit is coupled to the timing circuit and includes a plurality of states, including a buck state, a boost state, and a buck-boost state. The state machine circuit is configured to transition between the plurality of states according to time domain control and voltage domain control based at least in part on the determined relationship between the duty cycle of the power converter and the threshold value, transition between the plurality of states according to the time domain control when the time domain control indicates an exit from the buck-boost state, and transition between the plurality of states according to the voltage domain control when the voltage domain control indicates the exit from the buck-boost state.

[0006] Other aspects of the present disclosure provide a circuit. In at least some examples, the circuit includes a timing circuit and a state machine circuit. The timing circuit is configured to determine a relationship between a duty cycle of a power converter and a threshold value. The state machine circuit is coupled to the timing circuit and includes a plurality of states, including a buck-boost state and at least one other state. The state machine circuit is configured to transition from the other state to the buck-boost state based at least in part on the determined relationship between the duty cycle of the power converter and the threshold value when both time domain control and voltage domain control indicate entry into the buck-boost state. The state machine circuit is further configured to transition from the buck-boost state to the other state based at least in part on the determined relationship between the duty cycle of the power converter and the threshold value when either the time domain control or the voltage domain control indicates exit from the buck-boost state.

[0007] Other aspects of the present disclosure provide a system. In at least some examples, the system includes a load, a power converter, and a controller. The power converter is coupled to the load and is configured to provide an output voltage (VOUT) to the load that is switched from an input voltage (VIN) by the power converter. The controller is coupled to the power converter and is configured to control the power converter to switch VIN to VOUT. The controller switches VIN to VOUT by: generating a plurality of clock signals; determining a relationship between a duty cycle of the power converter and a threshold value determined based on at least some of the plurality of clock signals; and controlling the power converter to operate in the buck-boost mode of operation based at least in part on the determined relationship between the duty cycle of the power converter and the threshold value when both time domain control and voltage domain control specify that the power converter operate in the buck-boost mode of operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] To describe various examples in detail, reference is now made to the accompanying drawings, in which:

[0009] Figure 1 shows a block diagram of an illustrative SMPS according to various examples;

[0010] Figure 2 shows a schematic diagram of an illustrative buck-boost power converter according to various examples;

[0011] Figure 3 Schematic diagrams showing illustrative mode transition control circuits according to various examples;

[0012] Figure 4 presents illustrative state diagrams according to various examples;

[0013] Figure 5illustrative graphs showing buck-boost region width versus switching frequency according to various examples;

[0014] Figure 6 Schematic diagrams showing illustrative timing detection circuits according to various examples;

[0015] Figure 7 presents illustrative timing diagrams according to various examples;

[0016] Figure 8 presents illustrative timing diagrams according to various examples;

[0017] Figure 9 presents illustrative timing diagrams according to various examples;

[0018] Figure 10 shows illustrative timing diagrams according to various examples; and

[0019] Figure 11 Illustrative timing diagrams according to various examples are shown. DETAILED DESCRIPTION

[0020] In some architectures (e.g., buck-boost), a switched-mode power supply (SMPS) includes or can be coupled to an output / bulk capacitor in parallel with a load. The SMPS controller switches a power transistor to form a circuit configuration that causes an energy storage element to supply a load current to the load and / or the output / bulk capacitor to maintain a regulated output voltage (e.g., by filtering the switched load current). For example, the power transistor may be coupled to an energy storage inductor via a switching node / terminal. The energy storage inductor is switched between charge and discharge cycles by the SMPS controller to supply an inductor current (e.g., current through the energy storage inductor) to the load and the output / bulk capacitor to filter the inductor current to maintain a regulated output voltage. In some examples, the SMPS can be configured to operate as a constant current source, with an energy storage element but without an output / bulk capacitor.

[0021] The power transistors may be implemented as metal oxide semiconductor field effect transistors (MOSFETs) or any other suitable solid-state transistor devices (e.g., bipolar junction transistors (BJTs)). As the input voltage (VIN) or output voltage (VOUT) of the power converter changes, the SMPS controller may control the power converter to operate in different operating modes. For example, when VIN is greater than VOUT, the SMPS controller may control the power converter to operate in a buck operating mode. When VIN is less than VOUT, the SMPS controller may control the power converter to operate in a boost operating mode. When VIN is approximately equal to VOUT, the SMPS controller may control the power converter to operate in a buck-boost operating mode. In at least some examples, minimizing the amount of time the power converter operates in the buck-boost operating mode may be advantageous. For example, when operating in the buck-boost operating mode, the output ripple of the power converter, such as present in the power converter's VOUT or inductor current, is greater when operating in the buck or boost operating modes. In at least some embodiments, the ripple in the buck-boost operating mode is approximately twice the ripple during the buck or boost operating modes. For at least some buck-boost power converter implementations, it is advantageous to minimize ripple to, for example, reduce the need or intensity of filtering VOUT generated and output by the buck-boost power converter.

[0022] To control the operating mode of the power converter, the SMPS controller provides gate control signals to one or more power transistors of the power converter. The value of each of these gate control signals determines whether the corresponding power transistor receiving the gate control signal is in a conductive state (e.g., turned on) or a non-conductive state (e.g., turned off). To change the operating mode of the power converter, the SMPS controller modifies the value of one or more of the gate control signals to turn one or more of the power transistors on or off. Furthermore, while remaining in the operating mode of the power converter, the SMPS controller can modify the value of one or more of the gate control signals to, for example, alternately turn one or more power transistors on and off.

[0023] Typically, an SMPS controller controls a power converter to operate at a specific frequency. Some frequencies, such as high frequencies (e.g., greater than approximately 1.8 megahertz (MHz)), enable a smaller physical footprint for the power converter and / or SMPS controller by enabling the use of smaller circuit components. Other frequencies, such as low frequencies (e.g., less than approximately 500 kilohertz (kHz)), enable increased efficiency of the power converter by reducing switching losses in the power converter. Typically, an SMPS controller implements a fixed frequency control scheme that is optimized for either high-frequency operation or low-frequency operation. However, an SMPS controller optimized for operation across a wide frequency range can advantageously provide increased flexibility when implementing the SMPS controller.

[0024] At least some aspects of the present disclosure relate to a controller suitable for controlling a power converter, such as in an SMPS. In at least one example, the controller includes elements suitable for implementing a dual hysteresis control scheme. In at least some examples, the dual hysteresis control scheme is dominated by one type of control when the power converter is operating at a low frequency (e.g., less than about 1.2 MHz, less than about 500 kHz, etc.) and dominated by another type of control when the power converter is operating at a high frequency (e.g., greater than about 1.2 MHz, greater than about 1.8 MHz, etc.). For example, the dual hysteresis control scheme is dominated by time-domain hysteresis control when the power converter is operating at a low frequency and dominated by voltage-domain hysteresis control when the power converter is operating at a high frequency.

[0025] The controller controls the power converter to operate in a certain mode of operation according to the dual hysteresis control scheme. For example, the controller controls the power converter to operate in a certain mode of operation based on the minimum of the buck-boost region determined by the time-domain hysteresis control and the voltage-domain hysteresis control. For example, if the buck-boost operation region is defined according to the ratio of VOUT to VIN, the value of the buck-boost region under control of the dual hysteresis control scheme is minimized when compared to the values of the buck-boost region under individual control of the time-domain hysteresis control or the voltage-domain hysteresis control. In at least some examples, implementing the dual hysteresis control of the present disclosure provides a minimized duration of operation in buck-boost mode and a minimum achievable inductor current ripple in buck-boost mode over a wide range of switching frequencies (e.g., such as about 200 kHz to about 2 MHz). For example, for a power converter inductor with an inductance of about 4 micro-henries (uH) operating at a switching frequency of about 400 kHz and a VOUT of about 10 volts (V), the dual hysteresis control of the present disclosure limits the inductor current ripple to about 1.5 amperes (A) when the power converter is in buck-boost operation mode.

[0026] Turning now Figure 1, a block diagram of an illustrative SMPS 100 is shown. In at least one example, the SMPS 100 includes a controller 102 and a power converter 104. The SMPS 100 switches power provided by a power source 106 from a node 150 to a load 108 via at least the power converter 104. The power converter 104 is, for example, a buck-boost power converter capable of operating in a buck mode of operation, a boost mode of operation, and a buck-boost mode of operation. In at least one example, the controller 102 includes or is configured to be coupled to a feedback circuit 112, a timing generator 114, an oscillator 116, a frequency circuit 118, a ramp generator 120, a comparator 122, a comparator 124, a mode transition control circuit 126, and a gate driver 128. For purposes of this description, the SMPS 100 is illustrated and described as implementing average current mode control for the power converter 104. However, the dual-hysteretic control scheme of the present disclosure is equally applicable to other control methods, such as peak current mode control, voltage mode control, or any other suitable form of control implemented in a fixed frequency system.

[0027] At least one example of the SMPS 100 includes at least some aspects of the controller 102 and the power converter 104 on the same semiconductor die and / or the same component package, but in other examples, the controller 102 and the power converter 104 may be manufactured separately and configured to be coupled together. For example, at least some aspects of the controller 102 may be manufactured separately and coupled together. Thus, although illustrated as including the gate driver 128, in at least one example, the controller 102 does not include the gate driver 128 and is instead configured to be coupled to the gate driver 128. Similarly, other components illustrated as being included in the controller 102 may alternatively be configured to be coupled to the controller 102 in whole or in part and not included on the same semiconductor die and / or the same component package as the controller 102.

[0028] In at least one example, feedback circuit 112 includes resistor 130 coupled between node 152 and node 154, and resistor 132 coupled between node 154 and ground node 156. Feedback circuit 112 further includes amplifier 134, whose first input terminal (e.g., non-inverting input terminal) is coupled to node 158 and configured to receive a reference voltage (VREF) at node 158. Amplifier 134 further has a second input terminal (e.g., inverting input terminal) coupled to node 154 and an output terminal coupled to node 160. A feedback signal (FB) is present at node 154 and is a scaled representation of VOUT, scaled according to the ratio of the resistance of resistor 132 to the resistance of resistor 130. A signal (VC) is present at node 160 and is output by amplifier 134 based on the difference between VREF and FB. Resistor 136 is coupled between node 160 and the top plate of capacitor 138, and the bottom plate of capacitor 138 is coupled to ground node 156. Feedback circuit 112 further includes a current sensing circuit 140 and an amplifier 142. Current sensing circuit 140 is configured to couple to power converter 104 to generate an output signal (VI), which is a voltage representation of the current flowing through power converter 104. Amplifier 142 has a first input terminal (e.g., a positive or non-inverting input terminal) coupled to node 160, a second input terminal (e.g., a negative or inverting input terminal) coupled to the output terminal of current sensing circuit 140, and an output terminal coupled to node 162. A current control signal (CC) is present at node 162, which is output by amplifier 142 based on the difference between VC and VI. Resistor 144 is coupled between node 162 and the top plate of capacitor 146, and the bottom plate of capacitor 146 is coupled to ground node 156.

[0029] In at least some examples, timing generator 114 has a first output terminal coupled to oscillator 116 and mode transition control circuit 126, a second output terminal coupled to ramp generator 120, and a third output terminal coupled to mode transition control circuit 126. In at least some examples, timing generator 114 includes any one or more components suitable for generating additional clock signals based on a received clock signal. For example, timing generator 114 includes one or more delay cells (not shown) configured to implement a fixed or variable delay in the received clock signal to generate the additional clock signals. In at least one example, timing generator 114 receives CLK_HYS from oscillator 116, generates and outputs CLK to ramp generator 120, and generates and outputs CLK_TMIN to mode transition control circuit 126.

[0030] In at least some instances, oscillator 116 is suitable for generating Figure 114. The clock signal CLK_HYS is any component of the clock signal illustrated as CLK_HYS in FIG. In at least some examples, the frequency of CLK_HYS is determined based on the value of a signal received from frequency circuit 118. For example, frequency circuit 118 generates current signal ICLK based at least in part on the value of resistor 148 coupled to frequency circuit 118. Frequency circuit 118 outputs ICLK to oscillator 116 so that oscillator 116 can generate CLK_HYS based at least in part on ICLK. In at least some examples, frequency circuit 118 further outputs ICLK to ramp generator 120.

[0031] In at least some examples, ramp generator 120 is any one or more components suitable for generating buck and boost ramp signals for use in controlling power converter 104. In at least some examples, the buck and boost ramp signals are generated by charging and resetting (e.g., discharging) one or more capacitors (not shown) at a specified charging rate (specified by the current value of the signal charging the one or more capacitors). In at least some examples, ramp generator 120 generates and outputs the buck ramp signal and the boost ramp signal based on the received CLK and ICLK signals.

[0032] Comparator 122 includes a first input terminal (e.g., a positive or non-inverting input terminal) coupled to node 162, a second input terminal (e.g., a negative or inverting input terminal) coupled to ramp generator 120 and configured to receive a step-down ramp signal from ramp generator 120, and an output terminal. Comparator 124 includes a first input terminal (e.g., a positive or non-inverting input terminal) coupled to node 162, a second input terminal (e.g., a negative or inverting input terminal) coupled to ramp generator 120 and configured to receive a step-up ramp signal from ramp generator 120, and an output terminal. In at least some examples, control signal PWM_BK is present at the output terminal of comparator 122, and control signal PWM_BST is present at the output terminal of comparator 124. In some examples, PWM_BK has an asserted value when the value of CC is greater than the step-down ramp, and has a deasserted value when the value of CC is less than the step-down ramp. Similarly, in some examples, PWM_BST has an asserted value when the value of CC is greater than the boost ramp, and has a de-asserted value when the value of CC is less than the boost ramp.

[0033] Mode transition control circuit 126 has a plurality of input terminals configured to receive at least CLK_TMIN, CLK_HYS, PWM_BK, PWM_BST, VOUT, and VIN (collectively referred to as received signals with respect to mode transition control circuit 126). In at least some examples, mode transition control circuit 126 includes or implements a state machine to generate one or more control signals for controlling power converter 104 based on the received signals. The operation of mode transition control circuit 126 is discussed in more detail below.

[0034] In at least one example, SMPS 100 is configured to receive VIN from power source 106 at node 150 and provide VOUT at node 152 for supplying load 108. VOUT is based at least in part on VIN and VREF, as received by SMPS 100 at node 158. VREF can be received from any suitable device (not shown), such as a processor, microcontroller, or any other device that controls SMPS 100 to control the value of VOUT. In at least one example, the value of VREF represents a desired (e.g., user-desired, target, pre-configured, programmed, etc.) value for FB. Thus, in at least some embodiments, controller 102 receives one or more signals from power converter 104. For example, controller 102 may receive VOUT from power converter 104 and / or receive the inductor current (IL) of power converter 104. In various examples, IL may be a value measured directly from an inductor (not shown) of power converter 104 (or a terminal of another component of power converter 104 to which the inductor is also coupled) or a value sensed from a sensing element (not shown) of power converter 104. The sensing element is, for example, a sense resistor, a transistor, or any other component or combination of components capable of measuring IL of power converter 104 and providing a value representative of IL to controller 102. In at least one example, the value representative of IL is provided to feedback circuit 112 for use in generating V1, and VOUT is provided to feedback circuit 112 and mode transition control circuit 126.

[0035] In at least one example, feedback circuit 112 is configured to receive VREF and VOUT and generate V, which indicates the change in VREF from VFB. In some examples, V is referred to as an error signal. In at least some examples, FB is the output of a voltage divider formed by resistors 130 and 132, where the input to the voltage divider is VOUT. V is then filtered by resistor 136 and capacitor 138 before being received by amplifier 142. In at least one example, amplifier 142 is configured to receive V and V1 and generate C, which indicates the change in V from V1. C is then filtered by resistor 144 and capacitor 146 before being received by comparators 122 and 124.

[0036] As discussed above, in at least one example, frequency circuit 118 generates and outputs signal ICLK based on the resistance of resistor 148. ICLK at least partially determines the frequency of clock signal CLK_HYS generated and output by oscillator 116. Timing generator 114 receives CLK_HYS and generates one or more additional clock signals ( Figure 1 CLK and CLK_TMIN). For example, in at least one embodiment, the timing generator 114 modifies CLK_HYS to generate CLK and CLK_TMIN by delaying CLK_HYS by one or more predetermined time periods. In at least one example, the timing generator 114 generates CLK and CLK_TMIN by delaying t hys (For example, make CLK=CLK_HYS+t hys ) delays CLK_HYS to generate CLK, and according to the delay t hys minus t min (For example, make CLK_TMIN=CLK_HYS+t hys -t min ) to generate CLK_TMIN. In at least some instances, the delay t hys is substantially equal to the lag time (Ton_hys) of the on-time of the power converter 104 when operating in the buck mode of operation and the lag time (Toff_hys) of the off-time of the power converter 104 when operating in the boost mode of operation. min is substantially equal to the minimum on-time (Ton_min) of power converter 104 when operating in the boost mode of operation and the off-time (Toff_min) of power converter 104 when operating in the buck mode of operation. In at least one example, timing generator 114 generates CLK and CLK_TMIN by implementing one or more delay cells of any suitable architecture. However, in at least one example, a series of digital circuit components implement the delays. For example, the delays are implemented by one or more D-flip flops, one or more digital inverter circuits, or any other circuit components suitable for implementing delays, the scope of which is not limited herein.

[0037] The mode transition control circuit 126 receives CLK_TMIN, CLK_HYS, PWM_BK, PWM_BST, VOUT, and VIN and generates control signals for controlling the gate driver 128 to control the power converter 104. In at least one example, the mode transition control circuit 126 includes or otherwise implements a digital state machine to generate the control signals based on the values ​​of CLK_TMIN, CLK_HYS, PWM_BK, PWM_BST, VOUT, and / or VIN. In at least some examples, the mode transition control circuit 126 implements a dual-hysteresis control scheme to generate the control signals. In the dual-hysteresis control scheme, at low frequencies of CLK_HYS, the mode transition control circuit 126 generates control signals according to time-domain hysteresis control, and at high frequencies of CLK_HYS, the mode transition control circuit 126 generates control signals according to voltage-domain hysteresis control. The operation of the mode transition control circuit 126 will be discussed in more detail below.

[0038] Based on the control signals received from the mode transition control circuit 126, the gate driver 128 generates gate control signals for controlling the power transistors of the power converter 104, as discussed above. For example, the gate driver 128 generates gate control signals that alternately and selectively turn the power transistors of the power converter on and off to energize and de-energize components such as an inductor and / or capacitor (each not shown). This energization and de-energization provides the buck, boost, and / or buck-boost functionality discussed herein. The gate driver 128 is implemented according to any suitable architecture, the scope of which is not limited herein.

[0039] Now turn Figure 2 , shows a schematic diagram of an illustrative buck-boost power converter 200. In at least one example, the buck-boost power converter 200 is suitable for implementing the above-discussed Figure 1 The power converter 104 of the SMPS 100 is described as follows. Figure 2 Time Reference Figure 1 at least some components or signals of .

[0040] In one example, buck-boost power converter 200 includes a plurality of metal oxide semiconductor field effect transistors (MOSFETs) 205, 210, 215, and 220 and at least one energy storage device (illustrated in this example as inductor 225). In another example, buck-boost power converter 200 further includes a second inductor (not shown) and / or a flying capacitor (not shown). In one example, MOSFETs 205 and 220 are implemented as p-type MOSFETs (PMOS), and MOSFETs 210 and 215 are implemented as n-type MOSFETs (NMOS). In at least one example, buck-boost power converter 200 further includes a sensing element 230 adapted to sense the IL of inductor 225 and generate a signal representative of the IL. Sensing element 230 is, for example, a MOSFET, a resistor, or any other suitable circuit capable of sensing, measuring, or detecting the IL or having a means for sensing, measuring, or detecting the IL. In at least one example, sensing element 230 is implemented by one of MOSFETs 205, 210, 215, or 220, such that sensing element 230 is not a separate, additional component of buck-boost power converter 200. Additionally, in at least some examples, sensing element 230 also serves as, or is a component of, current sensing circuit 140.

[0041] In one example architecture, the source terminal of MOSFET 205 is coupled to node 150 and configured to receive VIN, the drain terminal of MOSFET 205 is coupled to node 235, and the gate terminal of MOSFET 205 is coupled to a controller. The controller is, for example, gate driver 128. The drain terminal of MOSFET 210 is coupled to node 235, the source terminal of MOSFET 210 is coupled to ground node 156, and the gate terminal of MOSFET 210 is coupled to the controller. A first terminal of inductor 225 is coupled to node 235, and a second terminal of inductor 225 is coupled to node 245. In at least one example, sensing element 230 is coupled in series between node 235 and the first terminal of inductor 225. The drain terminal of MOSFET 215 is coupled to node 245, the source terminal of MOSFET 215 is coupled to ground node 156, and the gate terminal of MOSFET 215 is coupled to the controller. The source terminal of MOSFET 220 is coupled to node 245, the drain terminal of MOSFET 220 is coupled to ground node 152 where VOUT is present, and the gate terminal of MOSFET 220 is coupled to the controller. In at least one example, inductor 225 is implemented as an external component such that buck-boost power converter 200 does not include inductor 225 but is configured to be coupled to inductor 225 between node 235 and node 245. In at least one example, buck-boost power converter 200 is configured to be coupled to capacitor 250 (e.g., such as a filter capacitor) between the drain terminal of MOSFET 220 and ground node 156.

[0042] In one example, the MOSFETs 205, 210, 215, and / or 220 are controlled to be turned on (e.g., to conduct current between their respective drain and source terminals) and / or turned off (e.g., to stop conducting current between their respective drain and source terminals) based on signals received at their respective gate terminals. For example, one or more of the MOSFETs 205, 210, 215, and / or 220 are controlled to be turned on or off based on a gate control signal received from a controller (e.g., as an output of a gate driver 128 under the control of the mode transition control circuit 126). The MOSFETs 205, 210, 215, and / or 220 may be turned on (or off) based on a value, or a relationship between values, present at one or more of their respective gate and / or source terminals. Based on which of the MOSFETs 205, 210, 215, or 220 is turned on at a given time, which of the MOSFETs 205, 210, 215, or 220 is turned off at a given time, and the order in which the MOSFETs 205, 210, 215, and / or 220 are turned on and / or off, the buck-boost power converter 200 operates in a buck mode of operation, a boost mode of operation, or a buck-boost mode of operation.

[0043] Now turn Figure 3 , a schematic diagram showing an illustrative embodiment of the mode transition control circuit 126 is shown. Figure 3 The mode transition control circuit 126 shown in FIG. 1 is suitable for implementation in Figure 1 Thus, the description of the controller 102 of the SMPS 100 is as follows: Figure 3 Please refer to the above Figure 1 At least some of the components and / or signals introduced and / or described.

[0044] In at least one example, mode transition control circuit 126 includes a timing detection circuit 302, a comparator 304, a comparator 306, and a state machine circuit 308. Timing detection circuit 302 is configured to receive PWM_BK, PWM_BST, CLK_HYS, and CLK_TMIN. Based on at least some of PWM_BK, PWM_BST, CLK_HYS, and / or CLK_TMIN, timing detection circuit 302 makes a plurality of timing determinations and outputs a plurality of signals indicating the results of respective ones of the timing determinations to state machine circuit 308. For example, timing detection circuit 302 performs one or more calculations to determine whether the on-time (Ton_bst) of the boost operating mode of power converter 104 is greater than or equal to Ton_hys and whether Ton_bst is less than or equal to Ton_min. The timing detection circuit 302 further performs one or more calculations to determine whether the off time (Toff_bk) of the buck mode of operation is greater than or equal to Toff_hys and whether Toff_bk is less than or equal to Toff_min. In at least some instances, one or more signals indicating the results of these determinations are output by the timing detection circuit 302 to the state machine circuit 308. In at least some instances, Ton_hys and Toff_hys are determined according to the following equations (1) and (2), respectively, where t min is the minimum on / off time achievable by power converter 104 and gate driver 128 , and Δ is a hysteresis factor used to prevent control of power converter 104 from oscillating between operating modes.

[0045] Ton_hys=3t min +Δ (1)

[0046] Toff_hys=3t min +Δ (2)

[0047] In at least some examples, the minimum VIN to VOUT ratio that the power converter 104 can adjust when in the buck mode of operation is defined as R bk In at least one embodiment of SMPS 100, R is determined according to the following equation (3): bk , where k is a hysteresis factor used to prevent the control of the power converter 104 from oscillating between operating modes, and T min is the switching period of the power converter 104 when operating at its highest supported switching frequency.

[0048]

[0049] In at least some examples, the maximum VIN to VOUT ratio that the power converter 104 can adjust when in the boost mode of operation is defined as R bstIn at least one embodiment of SMPS 100, R is determined according to equation (4) below: bst , where k2 is a hysteresis factor used to prevent the control of the power converter 104 from oscillating between operating modes.

[0050]

[0051] The comparator 304 is configured to receive a voltage substantially equal to VOUT*R at a first input terminal (eg, a positive or non-inverting input terminal). bst and receives VIN at a second input terminal (e.g., a negative or inverting input terminal). Figure 3 Not shown, but in at least some instances, the signal VOUT*R bst is generated by a voltage divider that receives VOUT. In other examples, VOUT*R bst is formed in any suitable manner and by any suitable components. The output terminal of comparator 304 is coupled to the input terminal of state machine circuit 308. In at least some instances, the signal output by comparator 304 is actuated when VIN / VOUT is less than R bst Asserted when VIN / VOUT is greater than R bst The comparator 306 is configured to receive a voltage substantially equal to VIN / R at a first input terminal (eg, a positive or non-inverting input terminal). bk and receives VOUT at a second input terminal (e.g., a negative or inverting input terminal). Figure 3 Not shown, but in at least some instances, the signal VIN / R bk is generated by a voltage divider that receives VOUT. In other examples, VIN / R bk is formed in any suitable manner and by any suitable components. The output terminal of comparator 306 is coupled to the input terminal of state machine circuit 308. In at least some instances, the signal output by comparator 306 is actuated when VIN / VOUT is greater than R bk Asserted when VIN / VOUT is less than R bk The assertion is revoked.

[0052] In at least some examples, state machine circuit 308 receives a plurality of signals as discussed herein and implements a state machine to generate control signals for controlling gate driver 128 to control power converter 104. Figure 4, an illustrative state diagram 400 is shown. In at least some examples, state diagram 400 illustrates states and transition conditions of a state machine implemented by state machine circuit 308 of mode transition control circuit 126. Therefore, reference may be made to components and / or signals of one or more other figures of the present disclosure when describing state diagram 400. Furthermore, the description of state diagram 400 begins in buck state 402, assuming that power converter 104 is initially controlled to operate in the buck operating mode. However, if power converter 104 is instead controlled to initially operate in the boost operating mode, the first state of state diagram 400 that may be implemented may be boost state 406.

[0053] In buck state 402, state machine circuit 308 generates a control signal for controlling power converter 104 to operate in the buck mode of operation. When controlling power converter 104 to operate in the buck mode of operation, state machine circuit 308 monitors a plurality of received input signals to determine whether to transition to buck-boost state 404 or boost state 406. For example, when operating in buck state 402 and state machine circuit 308 determines based on the received input signals that VIN / VOUT is less than R bst , the state machine circuit 308 transitions to the boost state 406. Similarly, when operating in the buck state 402 and the state machine circuit 308 determines based on the received input signal that Toff_bk is less than or equal to Toff_min and VIN / VOUT is greater than or equal to R bst , the state machine circuit 308 transitions to the buck-boost state 404 .

[0054] In the buck-boost state 404, the state machine circuit 308 generates control signals for controlling the power converter 104 to operate in the buck-boost mode of operation. For example, the state machine circuit 308 generates control signals to cause the power converter 104 to operate alternately in the buck mode of operation and the boost mode of operation. For example, as long as the state machine circuit 308 operates in the buck-boost state 404, the control signals generated by the state machine circuit 308 cause the power converter 104 to perform a buck operation cycle, followed by a boost operation cycle, followed by another buck operation cycle, and continue in this alternating manner. When controlling the power converter 104 to operate in the buck-boost mode of operation, the state machine circuit 308 monitors a plurality of received input signals to determine whether to transition to the buck state 402 or the boost state 406. For example, when operating in the buck-boost state 404 and the state machine circuit 308 determines based on the received input signal that Toff_bk is greater than or equal to Toff_hys and Ton_bst is less than or equal to Ton_min or VIN / VOUT is greater than R bst, the state machine circuit 308 transitions back to the buck state 402. Similarly, when operating in the buck-boost state 404 and the state machine circuit 308 determines based on the received input signal that Ton_bst is greater than or equal to Ton_hys and Toff_bk is less than or equal to Toff_min or VIN / VOUT is less than R bst , the state machine circuit 308 transitions to the boost state 406 .

[0055] In the boost state 406, the state machine circuit 308 generates a control signal for controlling the power converter 104 to operate in the boost mode of operation. When controlling the power converter 104 to operate in the boost mode of operation, the state machine circuit 308 monitors a plurality of received input signals to determine whether to transition to the buck state 402 or the buck-boost state 404. For example, when operating in the boost state 406 and the state machine circuit 308 determines based on the received input signals that VIN / VOUT is greater than R bk , the state machine circuit 308 transitions back to the buck state 402. Similarly, when operating in the boost state 406 and the state machine circuit 308 determines based on the received input signal that Ton_bst is less than or equal to Ton_min and VIN / VOUT is less than R bk , the state machine circuit 308 transitions back to the buck-boost state 404 .

[0056] As illustrated by state diagram 400, transitions to and from the buck-boost state 404 are controlled by either time-domain or voltage-domain control. In this manner, state machine circuit 308 implements the dual-hysteresis control scheme of the present disclosure to minimize the amount of time that state machine circuit 308 operates in the buck-boost state 404. For example, by transitioning to the buck-boost state 404 only when both time-domain and voltage-domain requirements are met, and transitioning out of the buck-boost state 404 when either the time-domain or voltage-domain requirements are met, state machine circuit 308 minimizes the amount of time that operates in the buck-boost state 404. In at least some examples, the control scheme implemented by state machine circuit 308 is referred to as a dual-hysteresis control scheme, rather than simply a dual-control scheme. This reference is derived from the hysteresis factors used to calculate at least some of the values ​​relied upon by state machine circuit 308 to prevent rapid oscillations between states, as discussed above.

[0057] Turn briefly Figure 5, an illustrative graph 500 of buck-boost region width versus switching frequency is shown. In at least some examples, graph 500 corresponds to the width of the buck-boost operating region of the power converter 104 of the SMPS 100 under the control of the controller 102 (including the mode transition control circuit 126). Graph 500 illustrates the ratio of VOUT to VIN of the power converter 104 on the y-axis and the switching frequency of the power converter 104 in MHz on the x-axis. As shown by graph 500, when operating according to the dual-hysteretic control scheme of the present disclosure, the width of the buck-boost operating region of the power converter 104 is reduced when compared to a single control scheme. For example, as shown by graph 500, at a switching frequency of approximately 200 kHz (e.g., 0.2 MHz), the width of the buck-boost operating region of the power converter 104 is approximately 0.06. As illustrated in graph 500, this width of 0.06 is less than the approximately 0.2 width of the buck-boost operating region at the same switching frequency when operating solely according to time-domain hysteresis. Similarly, at a switching frequency of approximately 2 MHz, the width of the buck-boost operating region of the power converter is approximately 0.58.

[0058] Now return to Figure 3 As discussed above, timing detection circuit 302 makes a plurality of timing determinations and outputs a plurality of signals indicative of the results of respective ones of the timing determinations to state machine circuit 308. Turning now to Figure 6 , a schematic diagram showing an illustrative embodiment of the timing detection circuit 302 is shown. Figure 3 The timing detection circuit 302 shown in FIG. 3 is suitable for implementation in Figure 3 Thus, the description of the mode transition control circuit 126 is as follows: Figure 6 When doing so, reference may be made to at least some of the components and / or signals introduced and / or described above with respect to other figures of the present disclosure.

[0059] In at least one implementation, the timing detection circuit 302 includes a D flip-flop 602, a D flip-flop 604, a D flip-flop 606, and a D flip-flop 608. In at least some examples, the D flip-flop 602 is configured to receive a D input signal at a data input terminal ( Figure 6 The flip-flop 602 is further configured to receive PWM_BK at the clock input terminal ( Figure 6 d flip-flop 602 receives CLK_TMIN at the output terminal ( Figure 6 In at least some instances, the data input terminal is coupled to Figure 1 The output terminal of the comparator 122 is coupled to the clock input terminal of the timing generator 114, and the output terminal is coupled to Figure 3 The state machine circuit 308.

[0060] In at least some instances, the D flip-flop 604 is configured to receive PWM_BK at the data input terminal. The D flip-flop 604 is further configured to receive CLK_HYS at the clock input terminal. The D flip-flop 604 receives CLK_HYS at the inverting output terminal ( Figure 6 In at least some instances, the data input terminal is coupled to Figure 1 The output terminal of the comparator 122 is coupled to the clock input terminal of the oscillator 116, and the output terminal is coupled to Figure 3 The state machine circuit 308.

[0061] In at least some instances, the D flip-flop 606 is configured to receive PWM_BST at a data input terminal. The D flip-flop 606 is further configured to receive CLK_HYS at a clock input terminal. The D flip-flop 606 outputs Ton_bst>=Ton_hys at an output terminal. In at least some instances, the data input terminal is coupled to Figure 1 The output terminal of the comparator 124 is coupled to the clock input terminal of the oscillator 116, and the output terminal is coupled to Figure 3 The state machine circuit 308.

[0062] In at least some instances, the D flip-flop 608 is configured to receive PWM_BST at the data input terminal. The D flip-flop 608 is further configured to receive CLK_TMIN at the clock input terminal. The D flip-flop 608 outputs Ton_bst<=Ton_min at the inverting output terminal. In at least some instances, the data input terminal is coupled to Figure 1 The output terminal of the comparator 124 is coupled to the clock input terminal of the timing generator 114, and the output terminal is coupled to the Figure 3 The state machine circuit 308.

[0063] Based on the values ​​of PWM_BK, PWM_BST, CLK_TMIN and CLK_HYS, the timing detection circuit 302 generates and outputs Toff_bk<=Toff_min, Toff_bk>=Toff_hys, Ton_bst>=Ton_hys and Ton_bst<=Ton_min. Figure 7-10 , various illustrative timing diagrams showing the operation of timing detection circuit 302 are shown. Figure 7-10As shown in FIG, the duration between the rising edge of CLK_TMIN and the rising edge of PWM_BK is Toff_min. Similarly, the duration between the rising edge of CLK_TMIN and the falling edge of PWM_BST is Ton_min. The duration between the rising edge of CLK_HYS and the rising edge of PWM_BK is Toff_hys, and the duration between the rising edge of CLK_HYS and the falling edge of PWM_BST is Ton_hys.

[0064] For example, Figure 7 Timing diagram 700 illustrates the generation of a control signal indicating that Toff_bk is greater than Toff_hys. As discussed above, timing detection circuit 302 receives PWM_BK, PWM_BST, CLK_TMIN, and CLK_HYS. Based on the value of PWM_BK at the rising edge of CLK_HYS, timing detection circuit 302 generates an output signal indicating that Toff_bk>Toff_hys. For example, when PWM_BK is deasserted (e.g., having a logic low value in at least one example) at the rising edge of CLK_HYS, timing detection circuit 302 asserts that Toff_bk>Toff_hys. In at least some examples, Toff_bk>=Toff_hys remains asserted until the next rising edge of PWM_BK.

[0065] Figure 8 Timing diagram 800 illustrates the generation of a control signal indicating that Ton_bst is greater than Ton_hys. As discussed above, timing detection circuit 302 receives PWM_BK, PWM_BST, CLK_TMIN, and CLK_HYS. Based on the value of PWM_BST at the rising edge of CLK_HYS, timing detection circuit 302 generates an output signal indicating that Ton_bst > Ton_hys. For example, when PWM_BST is asserted (e.g., having a logic high value in at least one example) at the rising edge of CLK_HYS, timing detection circuit 302 asserts that Ton_bst > Ton_hys. In at least some examples, Ton_bst >= Ton_hys remains asserted until the next rising edge of PWM_BST.

[0066] Figure 9Timing diagram 900 illustrates the generation of a control signal indicating that Toff_bk is less than or equal to Toff_min. As discussed above, timing detection circuit 302 receives PWM_BK, PWM_BST, CLK_TMIN, and CLK_HYS. Based on the value of PWM_BK at the rising edge of CLK_TMIN, timing detection circuit 302 generates an output signal Toff_bk<=Toff_min. For example, when PWM_BK is asserted (e.g., having a logic high value in at least one example) at the rising edge of CLK_TMIN, timing detection circuit 302 asserts Toff_bk<=Toff_min. In at least some examples, Toff_bk<=Toff_min remains asserted until the next rising edge of PWM_BK.

[0067] Figure 10 Timing diagram 1000 illustrates the generation of a control signal indicating that Ton_bst is less than or equal to Ton_min. As discussed above, timing detection circuit 302 receives PWM_BK, PWM_BST, CLK_TMIN, and CLK_HYS. Based on the value of PWM_BST at the rising edge of CLK_TMIN, timing detection circuit 302 generates the output signal Ton_bst<=Ton_min. For example, when PWM_BST is deasserted (e.g., having a logic low value in at least one example) at the rising edge of CLK_TMIN, timing detection circuit 302 asserts Ton_bst<=Ton_min. In at least some examples, Ton_bst<=Ton_min remains asserted until the next rising edge of PWM_BST.

[0068] Now turn Figure 11 , shows an illustrative timing diagram 1100. In at least some examples, the timing diagram 1100 illustrates the Figure 1 Therefore, the description of at least some of the signals of the SMPS 100 Figure 11 Please refer to the above Figure 1 At least some of the components and / or signals introduced and / or described herein. Timing diagram 1100 illustrates CLK_HYS as generated and output by oscillator 116. As discussed above, timing generator 114 generates CLK and CLK_TMIN by delaying or otherwise manipulating CLK_HYS. For example, as shown by timing diagram 1100, timing generator 114 manipulates CLK_HYS to generate a rising edge that is delayed t from the rising edge of CLK_HYS. hys As further shown by the timing diagram 1100, the timing generator 114 controls CLK_HYS to generate a rising edge delayed t from the rising edge of CLK_HYS. hys minus tmin In this way, the rising edge of CLK_TMIN precedes the rising edge of CLK by t min .

[0069] In the foregoing discussion, the terms "comprising" and "including" are used in an open-ended manner and, therefore, should be interpreted as meaning "including, but not limited to." The term "coupled" is used throughout this specification. The term can encompass any connection, communication, or signal path that enables a functional relationship consistent with the description of this disclosure. For example, if device A generates a signal to control device B to perform an action, then device A is coupled to device B in the first instance, or in the second instance, device A is coupled to device B via an intervening component C, provided that the intervening component C does not substantially alter the functional relationship between devices A and B such that device B is controlled by device A via the control signal generated by device A. A device "configured to" perform a task or function can be configured (e.g., programmed and / or hardwired) to perform the function at the time of manufacture, and / or can be configured (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. Configuration can be implemented through firmware and / or software programming of the device, through the construction and / or layout of the device's hardware components and interconnections, or a combination thereof. Furthermore, a circuit or device that is said to include certain components may alternatively be configured to be coupled to those components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage and / or current sources) may alternatively include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package) and may be configured to be coupled to at least some of the passive elements and / or sources to form the described structure at the time of manufacture or after manufacture, for example, by an end user and / or a third party.

[0070] Although certain components are described herein as belonging to a particular process technology (e.g., FETs, MOSFETs, n-type, p-type, etc.), these components can be swapped with components of other process technologies (e.g., replacing FETs and / or MOSFETs with BJTs, replacing n-type with p-type or vice versa, etc.) and the circuits including the replacement components reconfigured to provide the desired functionality at least partially similar to the functionality available before the component replacement. Unless otherwise stated, a component described as a resistor generally represents any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the described resistor. Furthermore, the use of the phrase "ground voltage potential" in the foregoing discussion is intended to include chassis ground, ground line ground, floating ground, virtual ground, digital ground, universal ground, and / or any other form of ground connection suitable or appropriate for the teachings of the present disclosure. Unless otherwise stated, the words "about," "substantially," or "substantially" preceding a value mean + / - 10% of the stated value.

[0071] The above discussion is intended to illustrate the principles and various examples of the present disclosure. Once the above disclosure is fully understood, many changes and modifications will become apparent to those skilled in the art. It is intended that the present disclosure be interpreted as encompassing all such changes and modifications.

Claims

1. A circuit comprising: A voltage measurement circuit having a first input and a first output, the first input being adapted to be coupled to a power converter, the voltage measurement circuit being configured to: receiving an input voltage of the power converter and an output voltage of the power converter via the first input; as well as providing, via the first output, a first control signal based on the input voltage and the output voltage; a timing circuit having a second input and a second output, the timing circuit being configured to: receiving via the second input a timing signal indicative of an on-time for a boost mode of operation of the power converter and an off-time for a buck mode of operation of the power converter; as well as providing a second control signal based on the on-time of the boost mode and providing a third control signal based on the off-time of the buck mode via the second output; as well as a mode control circuit having a third input and a third output, the third input being coupled to the first output and the second output, the third output being adapted to be coupled to the power converter, the mode control circuit being configured to: in the buck mode, provide a buck mode signal via the third output; providing a boost mode signal via the third output in the boost mode; providing a buck-boost signal via the third output in a buck-boost mode; receiving the first control signal, the second control signal, and the third control signal via the third input; and Transitions are made between the buck-boost mode and the buck mode and between the buck-boost mode and the boost mode based on at least one of the first control signal, the second control signal, or the third control signal.

2. The circuit of claim 1 , wherein the mode control circuit is configured to: transitioning from the buck mode to the boost mode based on the first control signal indicating that a ratio between the input voltage and the output voltage is less than a first ratio threshold; and transitioning from the buck mode to the buck-boost mode based on: (a) the third control signal indicating that the off-time of the buck mode of operation is less than or equal to an off-time threshold; and (b) the first control signal indicating that the ratio between the input voltage and the output voltage is greater than or equal to a second ratio threshold.

3. The circuit of claim 2 , wherein the off-time threshold is a first off-time threshold; and wherein the mode control circuit is configured to: Transitioning from the buck-boost mode to the buck mode based on at least one of: the second control signal and the third control signal respectively indicating that the on-time of the boost mode is less than or equal to an on-time threshold and the off-time of the buck mode is greater than or equal to a second off-time threshold; or The first control signal indicates that the ratio between the input voltage and the output voltage is greater than a third ratio threshold.

4. The circuit of claim 3, wherein: at least one of the first ratio threshold or the second ratio threshold is based on a maximum ratio between the input voltage and the output voltage for the boost mode; the third ratio threshold being based on a minimum ratio between the input voltage and the output voltage for the buck mode; At least one of the first off-time threshold or the second off-time threshold is based on a minimum off-time of the buck mode; The on-time threshold is based on a minimum on-time of the boost mode.

5. The circuit of claim 1 , wherein the mode control circuit is configured to: transitioning from the boost mode to the buck mode based on the first control signal indicating that a ratio between the input voltage and the output voltage is greater than a first ratio threshold; transitioning from the boost mode to the buck-boost mode based on: (a) the second control signal indicating that the on-time of the boost mode of operation is less than or equal to an on-time threshold; and (b) the first control signal indicating that the ratio between the input voltage and the output voltage is less than or equal to a second ratio threshold.

6. The circuit of claim 5 , wherein the on-time threshold is a first on-time threshold; and wherein the mode control circuit is configured to transition from the buck-boost mode to the boost mode based on at least one of: the second control signal and the third control signal respectively indicating that the on-time of the boost mode is greater than or equal to a second on-time threshold and the off-time of the buck mode is less than or equal to an off-time threshold; or The first control signal indicates that the ratio between the input voltage and the output voltage is less than a third ratio threshold.

7. The circuit of claim 6, wherein: at least one of the first ratio threshold or the second ratio threshold is based on a minimum ratio between the input voltage and the output voltage for the buck mode; the third ratio threshold being based on a maximum ratio between the input voltage and the output voltage for the boost mode; At least one of the first on-time threshold or the second on-time threshold is based on a minimum on-time of the boost mode; and The off-time threshold is based on the minimum off-time of the buck mode.

8. The circuit of claim 1 , wherein the mode control circuit is configured to: transitioning between the buck-boost mode and the buck mode and between the buck-boost mode and the boost mode based on the second control signal and the third control signal when the power converter operates below a first frequency; as well as transitioning between the buck-boost mode and the buck mode and between the buck-boost mode and the boost mode based on the first control signal when the power converter operates above a second frequency; The second frequency is higher than the first frequency.

9. The circuit of claim 8, wherein the first frequency is equal to 500 kilohertz; and wherein the second frequency is equal to 1.8 megahertz.

10. The circuit of claim 1 , wherein the timing signal comprises: a first clock signal; a second clock signal; a third timing signal based on a first duty cycle of the power converter in the boost mode; a fourth timing signal based on a second duty cycle of the power converter in the buck mode; and wherein the timing circuit is configured to: determining, based on the first clock signal, the second clock signal, and the third timing signal: (a) a first relationship between the on-time of the boost mode and a first on-time threshold; and (b) a second relationship between the on-time of the boost mode and a second on-time threshold; determining, based on the first clock signal, the second clock signal, and the fourth timing signal: (a) a third relationship between the off-time of the buck mode and a first off-time threshold; and (b) a fourth relationship between the off-time of the buck mode and a second off-time threshold; providing at least one of the first relationship or the second relationship as part of the second control signal; as well as At least one of the third relationship or the fourth relationship is provided as part of the third control signal.

11. The circuit of claim 1 , wherein the voltage measurement circuit comprises a comparator having a comparator output and first and second comparator inputs, the comparator output coupled to the third input, and the comparator configured to provide an indication signal at the comparator in response to: a first voltage at the first comparator input, wherein the first voltage represents the output voltage multiplied by a ratio threshold for the boost mode; and a second voltage at the comparator input, wherein the second voltage represents the input voltage; The indication signal indicates whether the ratio between the input voltage and the output voltage is less than the ratio threshold.

12. The circuit of claim 1 , wherein the voltage measurement circuit comprises a comparator having a comparator output and first and second comparator inputs, the comparator output coupled to the third input, and the comparator configured to provide an indication signal at the comparator output in response to: a first voltage at a first comparator input, wherein the first voltage represents the input voltage divided by the ratio threshold of the buck mode; and a second voltage at the comparator input, wherein the second voltage represents the output voltage; The indication signal indicates whether a ratio between the input voltage and the output voltage is greater than a ratio threshold.

13. The circuit of claim 1, wherein the buck-boost mode signal is configured to cause the power converter to operate in alternating cycles of the buck mode and the boost mode.

14. A circuit comprising: a timing circuit having a first input and a first output, the first input being adapted to be coupled to a power converter, the timing circuit being configured to: receiving, via the first input, a timing signal indicative of an on-time for a boost mode of operation of the power converter and an off-time for a buck mode of operation of the power converter; as well as providing, via the first output, a first control signal based on the on-time of the boost mode and a second control signal based on the off-time of the buck mode; and a control circuit having a second input coupled to the first output and a second output adapted to be coupled to the power converter, the mode control circuit being configured to: providing a buck mode signal or a boost mode signal via the second output in a first mode; in buck-boost mode, providing a buck-boost mode signal via the second output; receiving the first and second control signals via the second input; and Transitioning between the first mode and the buck-boost mode is performed based on at least one of the first control signal or the second control signal.

15. The circuit of claim 14 , further comprising a voltage measurement circuit having a third input and a third output, the third input being adapted to be coupled to the power converter, the third output being coupled to the second input, the voltage measurement circuit being configured to: receiving an input voltage and an output voltage of the power converter via the third input; and providing a third control signal via the third output based on the input voltage and the output voltage; wherein the first mode is a buck mode; and wherein the control circuit is configured to: receiving the third control signal via the second input; and Transitioning from buck-boost mode to buck mode based on at least one of the following: the second control signal and the first control signal respectively indicating that the off-time of the buck mode is greater than or equal to an off-time threshold and the on-time of the boost mode is less than or equal to an on-time threshold; or The third control signal indicates that a ratio between the input voltage and the output voltage is greater than a ratio threshold.

16. The circuit of claim 15, wherein: The off-time threshold is a first off-time threshold; The on-time threshold is a first on-time threshold; The ratio threshold is a first ratio threshold; and The mode control circuit is configured to transition from the buck-boost mode to a boost mode based on at least one of: the first control signal and the second control signal respectively indicating that the on-time of the boost mode is greater than or equal to a second on-time threshold and the off-time of the buck mode is less than or equal to a second off-time threshold; or The third control signal indicates that the ratio between the input voltage and the output voltage is less than a second ratio threshold.

17. The circuit of claim 16, wherein: At least one of the first off-time threshold or the second off-time threshold is based on a minimum off-time of the buck operating mode; at least one of the first on-time threshold or the second on-time threshold is based on a minimum on-time of the boost operating mode; The first ratio threshold is based on a minimum ratio between the input voltage and the output voltage for the buck mode of operation; and The second ratio threshold is based on a maximum ratio between the input voltage and the output voltage for the boost mode of operation.

18. The circuit of claim 15, wherein the mode control circuit is configured to: transitioning from the buck-boost mode to a buck mode or to a boost mode based on the first and second control signals when the power converter operates below a first frequency; and transitioning from the buck-boost mode to the buck mode or to the boost mode based on the third control signal when the power converter operates above a second frequency; The second frequency is higher than the first frequency.

19. A circuit system comprising: load; a power converter coupled to the load and configured to provide an output voltage to the load that is switched from an input voltage by the power converter; as well as a controller coupled to the power converter, the controller comprising: a timing circuit having a first input and a first output, the first input being coupled to the power converter, the timing circuit being configured to: receiving via the first input a timing signal indicative of an on-time for a boost mode of operation of the power converter and an off-time for a buck mode of operation of the power converter; and providing a first control signal based on the on-time of the boost mode and providing a second control signal based on the off-time of the buck mode via the first output; as well as a mode control circuit having a second input coupled to the first output of the timing circuit and a second output coupled to the power converter, the mode control circuit being configured to: providing a buck mode signal or a boost mode signal via the second output in a first mode; in buck-boost mode, providing a buck-boost mode signal via the second output; receiving the first and second control signals via the second input; and Based on at least one of the first control signal or the second control signal, transition is made between a first mode and the buck-boost mode.

20. The circuit system of claim 19, wherein the timing circuit is configured to: receiving timing signals, the timing signals comprising a first clock signal, a second clock signal, a third timing signal, and a fourth timing signal, wherein the third timing signal is based on a first duty cycle of the power converter in the boost mode and the fourth timing signal is based on a second duty cycle of the power converter in the buck mode; determining, based on the first clock signal, the second clock signal, and the third timing signal: (a) a first relationship between the on-time of the boost mode and a first on-time threshold; and (b) a second relationship between the on-time of the boost mode and a second on-time threshold; determining, based on the first clock signal, the second clock signal, and the fourth timing signal: (a) a third relationship between the off-time of the buck mode and a first off-time threshold; and (b) a fourth relationship between the off-time of the buck mode and a second off-time threshold; providing at least one of the first relationship or the second relationship as part of the first control signal; as well as At least one of the third relationship or the fourth relationship is provided as part of the second control signal.

21. The circuit system of claim 19, wherein the controller further comprises a voltage measurement circuit having a third input and a third output, the third input being coupled to the power converter, the third output being coupled to the second input, the voltage measurement circuit being configured to: receiving an input voltage and an output voltage of the power converter via the third input; and providing a third control signal via the third output based on the input voltage and the output voltage; and wherein the mode control circuit is configured to: transitioning from the first mode to the buck-boost mode based on the third control signal and one of the first control signal or the second control signal; and Based on at least one of the first control signal, the second control signal, or the third control signal, a transition is made from the buck-boost mode to the first mode.

22. The circuit system of claim 21 , wherein: The first mode is a buck mode; and The mode control circuit is configured to: transitioning from the buck mode to the buck-boost mode based on: (a) the second control signal indicating that the off-time of the buck mode is less than or equal to an off-time threshold; and (b) the third control signal indicating that a ratio between the input voltage and the output voltage is greater than or equal to a first ratio threshold; and transitioning from a boost mode to the buck-boost mode based on: (a) the first control signal indicating that the on-time of the boost mode is less than or equal to an on-time threshold; and (b) the third control signal indicating that the ratio between the input voltage and the output voltage is less than or equal to a second ratio threshold.

23. The circuit system of claim 22, wherein: The off-time threshold is a first off-time threshold; The on-time threshold is a first on-time threshold; and The mode control circuit is configured to: transitioning from the buck-boost mode to the buck mode based on at least one of: the second control signal and the first control signal respectively indicating that the off-time of the buck mode is greater than or equal to a second off-time threshold and the on-time of the boost mode is less than or equal to a second on-time threshold; or the third control signal indicating that the ratio between the input voltage and the output voltage is greater than a third ratio threshold; and Transitioning from the buck-boost mode to the boost mode based on at least one of: the first control signal and the second control signal indicating that the on-time of the boost mode is greater than or equal to a third on-time threshold and the off-time of the buck mode of operation is less than or equal to a third off-time threshold, respectively; or The third control signal indicates that the ratio between the input voltage and the output voltage is less than a fourth ratio threshold.

24. The circuit system of claim 21 , wherein the mode control circuit is configured to: transitioning from the buck-boost mode to a buck mode or to a boost mode based on the first and second control signals when the power converter operates below a first frequency; and transitioning from the buck-boost mode to the buck mode or to the boost mode based on the third control signal when the power converter operates above a second frequency; The second frequency is higher than the first frequency.

25. The circuit system of claim 23, wherein: at least one of the first off-time threshold, the second off-time threshold, or the third off-time threshold is based on a minimum off-time of the buck operating mode; at least one of the first on-time threshold, the second on-time threshold, or the third on-time threshold is based on a minimum on-time of the boost operating mode; at least one of the first ratio threshold or the fourth ratio threshold is based on a maximum ratio between the input voltage and the output voltage for the boost mode of operation; and At least one of the second ratio threshold or the third ratio threshold is based on a minimum ratio between the input voltage and the output voltage for the buck mode of operation.

26. A circuit comprising: A voltage measurement circuit having a first input and a first output, the first input being adapted to be coupled to a power converter, the voltage measurement circuit being configured to: receiving an input voltage of the power converter and an output voltage of the power converter via the first input; and providing, via the first output, a first control signal based on the input voltage and the output voltage; a timing circuit having a second input and a second output, the second input being adapted to be coupled to the power converter, the timing circuit being configured to: receiving, via the second input, a timing signal indicative of a first timing of a boost mode of operation of the power converter and a second timing of a buck mode of operation of the power converter; and providing, via the second output, a second control signal based on the first timing of the boost mode and a third control signal based on the second timing of the buck mode; and a mode control circuit having a third input coupled to the first output of the voltage measurement circuit and the second output of the timing circuit and a third output adapted to be coupled to the power converter, the mode control circuit being configured to: providing a buck mode signal or a boost mode signal via the third output in a first mode; in buck-boost mode, providing a buck-boost mode signal via the third output; receiving the first control signal, the second control signal, and the third control signal via the third input; and Transitioning between the buck-boost mode and the first mode is performed based on at least one of the first control signal, the second control signal, or the third control signal.

27. The circuit of claim 26, wherein the mode control circuit is configured to: transitioning from the first mode to the buck-boost mode based on the first control signal and one of the second control signal or the third control signal; and Transitioning from the buck-boost mode to the first mode is based on at least one of: (a) the first control signal; or (b) the second control signal and the third control signal.

28. The circuit of claim 26, wherein the first mode is a buck mode; and The mode control circuit is configured to transition between the buck mode and the boost mode based on the first control signal.

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