Semiconductor unit structure and method for forming the same

Abstract

A semiconductor unit structure and a method for forming the same, the semiconductor unit structure comprising: a first gate structure group located on a substrate, the first gate structure group comprising a first gate structure, the first gate structure extending along a first direction to a first region, a second region, and a third region on both sides of the first region; a first source region and a first drain region respectively located in the first region on both sides of the first gate structure, and respectively located in the second region on both sides of the first gate structure. The performance of the semiconductor unit structure is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor unit structure and a forming method thereof. Background Art

[0002] The semiconductor unit structure is a standard unit commonly used in circuit design. Specifically, required semiconductor unit structures are spliced ​​together to form a required circuit.

[0003] Typically, a semiconductor unit structure has both PMOS transistors and NMOS transistors, the PMOS transistor is located in the P region, the NMOS transistor is located in the N region, the PMOS transistor and the NMOS transistor share a gate structure, the gate structure extends to the P region and the N region, and both ends of the gate structure are cut off.

[0004] However, the performance of existing semiconductor unit structures needs to be improved. Summary of the invention

[0005] The problem solved by the present invention is to provide a semiconductor unit structure and a forming method thereof, so as to improve the performance of the semiconductor unit structure.

[0006] To solve the above problems, the present invention provides a method for forming a semiconductor unit structure, comprising: a substrate, the substrate comprising a first region and a third region located on both sides of the first region along a first direction, the first region comprising a first region and a second region arranged along the first direction, the transistor type formed in the first region and the second region is opposite to the transistor type formed in the third region; a first gate structure group located on the substrate, the first gate structure group comprising a first gate structure, the first gate structure extending along the first direction to the first region, the second region, and the third region on both sides of the first region.

[0007] Optionally, it also includes: a first source region and a first drain region respectively located in the first region on both sides of the first gate structure, and respectively located in the second region on both sides of the first gate structure; a second source region and a second drain region respectively located in the third region on both sides of the first gate structure.

[0008] Optionally, the semiconductor unit structure is an inverter unit structure; the semiconductor unit structure further includes: a first plug located on the first drain region; a second plug located on the second drain region; and a first connection structure connecting each first plug and each second plug.

[0009] Optionally, the first connection structure includes: a first connection layer located on the first area, the first connection layer connecting the top surfaces of the first plugs of each first area; a second connection layer located on the second area, the second connection layer connecting the top surfaces of the first plugs of each second area; a third connection layer located on the third area on one side of the first area in the first direction, the third connection layer connecting the top surfaces of the second plugs on one side of the first area in the first direction; a fourth connection layer located on the third area on the other side of the first area in the first direction, the fourth connection layer connecting the top surfaces of the second plugs on the other side of the first area in the first direction; and a fifth connection layer, the fifth connection layer connecting the first connection layer, the second connection layer, the third connection layer and the fourth connection layer.

[0010] Optionally, it also includes: a second gate structure respectively located on the substrate on both sides of the first gate structure group; part of the second gate structure extends along the first direction to the adjacent first area and third area, part of the second gate structure extends along the first direction to the adjacent second area and third area, and the second gate structure on the first area and the second gate structure on the second area are disconnected; or, the second gate structure extends along the first direction to the first area, the second area, and the third area on both sides of the first area.

[0011] Optionally, the first region and the second region are used to form a PMOS transistor, and the third region is used to form an NMOS transistor.

[0012] Optionally, the first region and the second region are used to form an NMOS transistor, and the third region is used to form a PMOS transistor.

[0013] Optionally, the number of the first gate structure is one.

[0014] Optionally, there are multiple first gate structures.

[0015] Optionally, it further includes: a first gate plug located on each first gate structure, the first gate plug is located between adjacent first regions and third regions; and a second gate plug located on each first gate structure, the second gate plug is located between adjacent second regions and third regions.

[0016] Optionally, the semiconductor unit structure is an inverter unit structure; the semiconductor unit structure further includes: a sixth connection layer connecting each first gate plug; and a seventh connection layer connecting each second gate plug.

[0017] Optionally, the method further includes: third plugs respectively located on the first source regions; and fourth plugs respectively located on the second source regions.

[0018] Optionally, the semiconductor unit structure is an inverter unit structure; when the transistor type formed in the first area and the second area is P-type, and the transistor type formed in the third area is N-type, the third plug is electrically connected to the power line, and the fourth plug is electrically connected to the ground line; when the transistor type formed in the first area and the second area is N-type, and the transistor type formed in the third area is P-type, the third plug is electrically connected to the ground line, and the fourth plug is electrically connected to the power line.

[0019] The present invention also provides a method for forming any of the above-mentioned semiconductor unit structures, comprising: providing a substrate, the substrate comprising a first region and a third region located on both sides of the first region along a first direction, the first region comprising a first region and a second region arranged along the first direction, the transistor types formed in the first region and the second region are opposite to the transistor type formed in the third region; forming a first gate structure group on the substrate, the first gate structure group comprising a first gate structure, the first gate structure extending along the first direction to the first region, the second region, and the third region on both sides of the first region.

[0020] Optionally, it also includes: forming a first source region and a first drain region in the first region on both sides of the first gate structure and in the second region on both sides of the first gate structure respectively; and forming a second source region and a second drain region in the third region on both sides of the first gate structure respectively.

[0021] Optionally, the semiconductor unit structure is an inverter unit structure; the method for forming the semiconductor unit structure also includes: forming a first plug on the first drain region; forming a second plug on the second drain region; and forming a first connection structure connecting each first plug and each second plug.

[0022] Optionally, the method for forming a first connection structure includes: forming a first connection layer on the first region, the first connection layer connecting the top surfaces of the first plugs of each first region; forming a second connection layer on the second region, the second connection layer connecting the top surfaces of the first plugs of each second region; forming a third connection layer on the third region on one side of the first direction of the first region, the third connection layer connecting the top surfaces of the second plugs on one side of the first direction of the first region; forming a fourth connection layer on the third region on the other side of the first direction of the first region, the fourth connection layer connecting the top surfaces of the second plugs on the other side of the first direction of the first region; forming a fifth connection layer, the fifth connection layer connecting the first connection layer, the second connection layer, the third connection layer and the fourth connection layer.

[0023] Optionally, the semiconductor unit structure is an inverter unit structure; the method for forming the semiconductor unit structure also includes: forming a first gate plug and a second gate plug on each first gate structure, the first gate plug is located between adjacent first regions and third regions, and the second gate plug is located between adjacent second regions and third regions; forming a sixth connection layer connecting each first gate plug; forming a seventh connection layer connecting each second gate plug.

[0024] Optionally, it also includes: forming a third plug on the first source region respectively; forming a fourth plug on the second source region respectively; the semiconductor unit structure is an inverter unit structure; when the transistor type formed in the first area and the second area is P-type, and the transistor type formed in the third area is N-type, the third plug is electrically connected to the power line, and the fourth plug is electrically connected to the ground line; when the transistor type formed in the first area and the second area is N-type, and the transistor type formed in the third area is P-type, the third plug is electrically connected to the ground line, and the fourth plug is electrically connected to the power line.

[0025] Optionally, it also includes: forming a second gate structure on the substrate on both sides of the first gate structure group; part of the second gate structure extends along the first direction to the adjacent first area and third area, part of the second gate structure extends along the first direction to the adjacent second area and third area, and the second gate structure on the first area and the second gate structure on the second area are disconnected; or, the second gate structure extends along the first direction to the first area, the second area, and the third area on both sides of the first area.

[0026] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0027] In the semiconductor unit structure provided by the technical solution of the present invention, the transistor type formed in the first area and the second area is opposite to the transistor type formed in the third area, and the first area is located between the third areas in the first direction, so that the first gate structure on the first area does not need to be cut off, which effectively reduces the gate stress of the first gate structure in the first area, thereby reducing the stress influence in the channel area at the bottom of the first gate structure, avoiding the reduction of carriers in the channel of the first area, thereby improving the operating speed of the semiconductor unit structure and improving the performance of the semiconductor unit structure.

[0028] Furthermore, the first connection structure includes: a first connection layer, a second connection layer, a third connection layer, a fourth connection layer and a fifth connection layer, and the fifth connection layer connects the first connection layer, the second connection layer, the third connection layer and the fourth connection layer. Since the lengths of the first connection layer, the second connection layer, the third connection layer and the fourth connection layer in the extension direction are relatively short, the rise time and the fall time of the semiconductor unit structure are reduced, and the operation speed of the semiconductor unit structure is further improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a schematic diagram of an inverter unit structure;

[0030] Figures 2 to 5 FIG. 4 is a schematic diagram of a semiconductor unit structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0031] As described in the background art, the performance of the semiconductor unit structure formed by the prior art is relatively poor.

[0032] An inverter unit structure, please refer to Figure 1 , comprising: a substrate 100, the substrate 100 comprising a first region 10 and a second region 20 arranged in a first direction X, the first region 10 being used to form an NMOS transistor, and the second region 20 being used to form a PMOS transistor; a plurality of first gate structures 120 located on the substrate 100, the first gate structures 120 extending along the first direction X to the first region 10 and the second region 20; a first source region and a first drain region respectively located in the first region 10 on both sides of the first gate structure 120; a second source region respectively located in the second region 20 on both sides of the first gate structure 120 and a second drain region; a first plug 131 located on the first drain region; a second plug 132 located on the second drain region; a first connection structure connecting each first plug 131 and each second plug 132, the first connection structure comprising: a first connection layer 140 connecting each first plug 131; a second connection layer 150 connecting each second plug 132; a third connection layer 160 connecting the first connection layer 140 and the second connection layer 150; a gate plug (not shown) located on the first gate structure 120; and a fourth connection layer (not shown) connecting each gate plug.

[0033] In the above-mentioned inverter unit structure, since the first gate structure 120 is cut off at both ends in the first direction, gate stress is formed on the first gate structure 120, and the gate stress is transmitted to the channel region at the bottom of the first gate structure 120, resulting in unpredictable stress in the channel region at the bottom of the first gate structure 120, such as reducing the carriers in the channel of the second region, resulting in a reduction in the operating speed of the inverter unit structure.

[0034] On this basis, the present invention provides a semiconductor unit structure, comprising: a substrate, the substrate comprising a first region and a third region located on both sides of the first region along a first direction, the first region comprising a first region and a second region arranged along the first direction, the first region and the second region being used to form transistors of a type opposite to the type of transistors formed in the third region; a first gate structure group located on the substrate, the first gate structure group comprising a first gate structure, the first gate structure extending along the first direction to the first region, the second region, and the third region on both sides of the first region. The performance of the semiconductor unit structure is improved.

[0035] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0036] Figures 2 to 5 FIG. 4 is a schematic diagram of a semiconductor unit structure according to an embodiment of the present invention.

[0037] In this embodiment, the semiconductor unit structure is an inverter unit structure as an example for description. In other embodiments, the semiconductor unit structure includes a CMOS unit device.

[0038] refer to Figure 2 , providing a substrate 200, the substrate 200 includes a first area A and a third area B located on both sides of the first area A along a first direction X, the first area A includes a first area A1 and a second area A2 arranged along the first direction X, and the transistor types formed in the first area A1 and the second area A2 are opposite to the transistor types formed in the third area B.

[0039] In one embodiment, the base 200 includes a semiconductor substrate and a fin located on the semiconductor substrate, wherein the extension direction of the fin is perpendicular to the first direction X and parallel to the surface of the semiconductor substrate, and the first area A1, the second area A2 and the third area B of the semiconductor substrate each have a fin.

[0040] In another embodiment, the base is a planar semiconductor substrate.

[0041] The material of the semiconductor substrate includes single crystal silicon, single crystal germanium or single crystal silicon germanium.

[0042] In this embodiment, the first area A1 and the second area A2 are used to form a PMOS transistor, and the third area B is used to form an NMOS transistor.

[0043] In other embodiments, the first region A1 and the second region A2 are used to form an NMOS transistor, and the third region B is used to form a PMOS transistor.

[0044] Figure 2 The area marked by the middle hatched line is the active area.

[0045] refer to Figure 3 A first gate structure group is formed on a substrate 200, the first gate structure group including a first gate structure 210, the first gate structure 210 extending along a first direction X to a first region A1, a second region A2, and a third region B on both sides of the first region A; a first source region and a first drain region are respectively formed in the first region A1 on both sides of the first gate structure 210, and in the second region A2 on both sides of the first gate structure 210; a second source region and a second drain region are respectively formed in the third region B on both sides of the first gate structure 210.

[0046] The first gate structure 210 includes a first gate dielectric layer and a first gate electrode layer on the first gate dielectric layer. In one embodiment, the material of the first gate dielectric layer is silicon oxide, and the material of the first gate electrode layer is polysilicon. In another embodiment, the material of the first gate dielectric layer is a high-K (K greater than 3.9) dielectric material, and the material of the first gate electrode layer is a metal.

[0047] The number of the first gate structure 210 is one or more. In this embodiment, the description is made by assuming that the number of the first gate structure 210 is more than one.

[0048] In this embodiment, it also includes: forming second gate structures 220 on the substrate 200 on both sides of the first gate structure group, part of the second gate structure 220 extends along the first direction X to the adjacent first area A1 and the third area B, part of the second gate structure 220 extends along the first direction X to the adjacent second area A2 and the third area B, and the second gate structure 220 on the first area A1 and the second gate structure 220 on the second area A2 are disconnected; or, the second gate structure extends along the first direction to the first area, the second area, and the third area on both sides of the first area.

[0049] The second gate structure 220 includes a second gate dielectric layer and a second gate electrode layer on the second gate dielectric layer. In one embodiment, the material of the second gate dielectric layer is silicon oxide, and the material of the second gate electrode layer is polysilicon. In another embodiment, the material of the second gate dielectric layer is a high-K (K greater than 3.9) dielectric material, and the material of the second gate electrode layer is metal.

[0050] The functions of the second gate structure 220 include: the second gate structure 220 is not electrically connected, and the second gate structure is located on both sides of the first gate structure group, so that when adjacent semiconductor unit structures are spliced ​​together, the second gate structure isolates the first gate structures in adjacent semiconductor unit structures to avoid short circuits in the first gate structures in adjacent semiconductor unit structures.

[0051] In one embodiment, the base includes a semiconductor substrate and fins, and accordingly, the first gate structure 210 spans the fins of the first region A1, the second region A2 and the third region B, a portion of the second gate structure 220 spans the fins on the adjacent first region A1 and the third region B, and a portion of the second gate structure 220 spans the fins on the adjacent second region A2 and the third region B.

[0052] In this embodiment, the method further includes: forming a first dielectric layer on the substrate 200 , wherein the first dielectric layer covers the sidewalls of the first gate structure 210 and the sidewalls of the second gate structure 220 and exposes the top surfaces of the first gate structure 210 and the second gate structure 220 .

[0053] It should be noted that, in other embodiments, a first dummy gate structure group is formed on the substrate, the first dummy gate structure group includes a first dummy gate structure, the first dummy gate structure extends along the first direction X to the first region, the second region, and the third region on both sides of the first region; second dummy gate structures are respectively formed on the substrate on both sides of the first dummy gate structure group, part of the second dummy gate structure extends along the first direction X to the adjacent first region and the third region, part of the second dummy gate structure extends along the first direction to the adjacent second region and the third region, the second dummy gate structure on the first region and the second dummy gate structure on the second region are disconnected, or the second dummy gate structure extends along the first direction to the first region, the second region, and the third region on both sides of the first region. On the substrate, a first source region and a first drain region are formed in the first region on both sides of the first dummy gate structure and in the second region on both sides of the first dummy gate structure respectively; a second source region and a second drain region are formed in the third region on both sides of the first dummy gate structure respectively; then, a first dielectric layer is formed on the substrate, the first dielectric layer covers the sidewalls of the first dummy gate structure and the sidewalls of the second dummy gate structure and exposes the top surfaces of the first dummy gate structure and the second dummy gate structure; then, the first dummy gate structure is removed to form a first gate opening, and the second dummy gate structure is removed to form a second gate opening; a first gate structure is formed in the first gate opening, and a second gate structure is formed in the second gate opening, wherein both the first gate structure and the second gate structure are metal gate structures.

[0054] refer to Figure 4 , a first plug 240 is formed on the first drain region; a second plug 230 is formed on the second drain region; a first gate plug 261 and a second gate plug 262 are formed on each first gate structure 210, the first gate plug 261 is located between the adjacent first region A1 and the third region B, and the second gate plug 262 is located between the adjacent second region A2 and the third region B.

[0055] Specifically, a second dielectric layer is formed on the first dielectric layer, the first gate structure 210 and the second gate structure 220; a first plug 240 penetrating the first dielectric layer and the second dielectric layer is formed on the first drain region; a second plug 230 penetrating the first dielectric layer and the second dielectric layer is formed on the second drain region; a first gate plug 261 penetrates the second dielectric layer on the first gate structure 210, and a second gate plug penetrates the second dielectric layer on the first gate structure 210.

[0056] The method for forming a semiconductor unit structure further includes: forming third plugs on the first source regions respectively; and forming fourth plugs on the second source regions respectively.

[0057] The semiconductor unit structure is an inverter unit structure. When the transistor type formed by the first area and the second area is a P type, and the transistor type formed by the third area is an N type, the third plug is electrically connected to the power line, and the fourth plug is electrically connected to the ground line; when the transistor type formed by the first area and the second area is an N type, and the transistor type formed by the third area is a P type, the third plug is electrically connected to the ground line, and the fourth plug is electrically connected to the power line.

[0058] refer to Figure 5 , forming a first connection structure connecting each first plug 240 and each second plug 230 .

[0059] The method for forming the first connection structure includes: forming a first connection layer 251 on the first area A1, the first connection layer 251 connecting the top surfaces of the first plugs 240 of each first area A1; forming a second connection layer 252 on the second area A2, the second connection layer 252 connecting the top surfaces of the first plugs 240 of each second area A2; forming a third connection layer 253 on the third area B on one side of the first direction X of the first area A, the third connection layer 253 connecting the top surfaces of the second plugs 230 on one side of the first direction X of the first area A; forming a fourth connection layer 254 on the third area B on the other side of the first direction X of the first area A, the fourth connection layer 254 connecting the top surfaces of the second plugs 230 on the other side of the first direction X of the first area A; forming a fifth connection layer 255, the fifth connection layer 255 connecting the first connection layer 255, the second connection layer 252, the third connection layer 253 and the fourth connection layer 254.

[0060] The materials of the first connection layer 251 , the second connection layer 252 , the third connection layer 253 , the fourth connection layer 254 and the fifth connection layer 255 are conductive materials, such as metal.

[0061] The semiconductor unit structure is an inverter unit structure. The method for forming the semiconductor unit structure further includes: forming a sixth connection layer 271 connecting the first gate plugs 261 ; and forming a seventh connection layer 272 connecting the second gate plugs 262 .

[0062] The sixth connection layer 271 and the seventh connection layer 272 are made of conductive materials, such as metal.

[0063] Accordingly, the present invention provides a semiconductor unit structure, please refer to Figure 5 ,include:

[0064] A substrate 200, wherein the substrate 200 includes a first area A and a third area B located on both sides of the first area A along a first direction X, wherein the first area A includes a first area A1 and a second area A2 arranged along the first direction X, and the transistor types formed in the first area A1 and the second area A2 are opposite to the transistor type formed in the third area B;

[0065] The first gate structure group is located on the substrate 200 , and the first gate structure group includes a first gate structure 210 . The first gate structure 210 extends along a first direction X to the first area A1 , the second area A2 , and the third area B on both sides of the first region A.

[0066] The semiconductor unit structure also includes: a first source region and a first drain region respectively located in the first area A1 on both sides of the first gate structure 210, and respectively located in the second area A2 on both sides of the first gate structure 210; a second source region and a second drain region respectively located in the third area B on both sides of the first gate structure 210; a first plug 240 located on the first drain region; and a second plug 230 located on the second drain region.

[0067] The semiconductor unit structure is an inverter unit structure. The semiconductor unit structure further includes: a first connection structure connecting each first plug 240 and each second plug 230 .

[0068] The semiconductor unit structure also includes: a second gate structure 220 respectively located on the substrate 200 on both sides of the first gate structure group, part of the second gate structure 220 extends along the first direction X to the adjacent first area A1 and the third area B, part of the second gate structure 220 extends along the first direction X to the adjacent second area A2 and the third area B, the second gate structure 220 on the first area A1 and the second gate structure 220 on the second area A2 are disconnected; or, the second gate structure extends along the first direction to the first area, the second area, and the third area on both sides of the first area.

[0069] In this embodiment, the first area A1 and the second area A2 are used to form a PMOS transistor, and the third area B is used to form an NMOS transistor.

[0070] In other embodiments, the first region A1 and the second region A2 are used to form an NMOS transistor, and the third region B is used to form a PMOS transistor.

[0071] In this embodiment, the first connection structure includes: a first connection layer 251 located on the first area A1, the first connection layer 251 connects the top surfaces of the first plugs 240 of each first area A1; a second connection layer 252 located on the second area A2, the second connection layer 252 connects the top surfaces of the first plugs 240 of each second area A2; a third connection layer 253 located on the third area B on one side of the first region A in the first direction X, the third connection layer 253 connects the top surfaces of the second plugs 230 on one side of the first region A in the first direction X; a fourth connection layer 254 located on the third area B on the other side of the first region A in the first direction X, the fourth connection layer 254 connects the top surfaces of the second plugs 230 on the other side of the first region A in the first direction X; and a fifth connection layer 255, the fifth connection layer 255 connects the first connection layer 251, the second connection layer 252, the third connection layer 253 and the fourth connection layer 254.

[0072] The extension directions of the first connection layer 251 , the second connection layer 252 , the third connection layer 253 and the fourth connection layer 254 are all perpendicular to the first direction X. The extension direction of the fifth connection layer 255 is parallel to the first direction X.

[0073] The number of the first gate structure 210 is one or more.

[0074] In this embodiment, a plurality of first gate structures 210 is taken as an example for description.

[0075] The semiconductor unit structure further includes: a first gate plug 261 located on each first gate structure 210, the first gate plug 261 is located between the adjacent first area A1 and the third area B; a second gate plug 262 located on each first gate structure 210, the second gate plug 262 is located between the adjacent second area A2 and the third area B; a sixth connection layer 271 connecting each first gate plug 261; and a seventh connection layer 272 connecting each second gate plug 262.

[0076] The semiconductor unit structure further includes: third plugs (not shown) respectively located on the first source regions; and fourth plugs (not shown) respectively located on the second source regions.

[0077] The semiconductor unit structure is an inverter unit structure. When the transistor type formed in the first area and the second area is a P-type, and the transistor type formed in the third area is an N-type, the third plug is electrically connected to the power line, and the fourth plug is electrically connected to the ground line. When the transistor type formed in the first area and the second area is an N-type, and the transistor type formed in the third area is a P-type, the third plug is electrically connected to the ground line, and the fourth plug is electrically connected to the power line.

[0078] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor unit structure, characterized in that: include: A substrate, the substrate comprising a first region and a third region located at both sides of the first region along a first direction, the first region comprising a first region and a second region arranged along the first direction, the transistor types formed in the first region and the second region are opposite to the transistor type formed in the third region; A first gate structure group is located on the substrate, the first gate structure group includes a first gate structure, and the first gate structure extends along a first direction to the first area, the second area, and a third area on both sides of the first area; A second gate structure is respectively located on the substrate on both sides of the first gate structure group; part of the second gate structure extends along the first direction to the adjacent first area and third area, part of the second gate structure extends along the first direction to the adjacent second area and third area, and the second gate structure on the first area and the second gate structure on the second area are disconnected; or the second gate structure extends along the first direction to the first area, the second area, and the third area on both sides of the first area; A first source region and a first drain region respectively located in the first region on both sides of the first gate structure, and respectively located in the second region on both sides of the first gate structure; a second source region and a second drain region respectively located in the third region on both sides of the first gate structure; The semiconductor unit structure is an inverter unit structure; The semiconductor unit structure further includes: a first plug located on the first drain region; a second plug located on the second drain region; a first connection structure connecting each first plug and each second plug; The first connection structure includes: a first connection layer located on the first area, the first connection layer connecting the top surfaces of the first plugs of each first area; a second connection layer located on the second area, the second connection layer connecting the top surfaces of the first plugs of each second area; a third connection layer located on the third area on one side of the first area in the first direction, the third connection layer connecting the top surfaces of the second plugs on one side of the first area in the first direction; a fourth connection layer located on the third area on the other side of the first area in the first direction, the fourth connection layer connecting the top surfaces of the second plugs on the other side of the first area in the first direction; and a fifth connection layer connecting the first connection layer, the second connection layer, the third connection layer and the fourth connection layer.

2. The semiconductor unit structure according to claim 1, characterized in that: The first region and the second region are used to form a PMOS transistor, and the third region is used to form an NMOS transistor.

3. The semiconductor unit structure according to claim 1, characterized in that: The first region and the second region are used to form an NMOS transistor, and the third region is used to form a PMOS transistor.

4. The semiconductor unit structure according to claim 1, characterized in that: The number of the first gate structure is one.

5. The semiconductor unit structure according to claim 1, characterized in that: There are multiple first gate structures.

6. The semiconductor unit structure according to claim 1, characterized in that: Also includes: The first gate plug located on each first gate structure is located between the adjacent first region and third region; the second gate plug located on each first gate structure is located between the adjacent second region and third region.

7. The semiconductor unit structure according to claim 6, characterized in that: The semiconductor unit structure is an inverter unit structure; the semiconductor unit structure further comprises: a sixth connection layer connecting the first gate plugs; and a seventh connection layer connecting the second gate plugs.

8. The semiconductor unit structure according to claim 1, characterized in that: Also includes: third plugs respectively located on the first source regions; Fourth plugs are respectively located on the second source regions.

9. The semiconductor unit structure according to claim 8, characterized in that: The semiconductor unit structure is an inverter unit structure; when the transistor type formed by the first area and the second area is P-type and the transistor type formed by the third area is N-type, the third plug is electrically connected to the power line and the fourth plug is electrically connected to the ground line; when the transistor type formed by the first area and the second area is N-type and the transistor type formed by the third area is P-type, the third plug is electrically connected to the ground line and the fourth plug is electrically connected to the power line.

10. A method for forming a semiconductor unit structure according to any one of claims 1 to 9, characterized in that: include: Providing a substrate, the substrate comprising a first region and a third region located on both sides of the first region along a first direction, the first region comprising a first region and a second region arranged along the first direction, and the transistor types formed in the first region and the second region are opposite to the transistor type formed in the third region; Forming a first gate structure group on the substrate, the first gate structure group including a first gate structure, the first gate structure extending along a first direction to the first region, the second region, and a third region on both sides of the first region; Second gate structures are formed on the substrates on both sides of the first gate structure group; part of the second gate structure extends along the first direction to the adjacent first area and third area, part of the second gate structure extends along the first direction to the adjacent second area and third area, and the second gate structure on the first area and the second gate structure on the second area are disconnected; or the second gate structure extends along the first direction to the first area, the second area, and the third area on both sides of the first area; Forming a first source region and a first drain region in the first region on both sides of the first gate structure and in the second region on both sides of the first gate structure respectively; forming a second source region and a second drain region in the third region on both sides of the first gate structure respectively; The semiconductor unit structure is an inverter unit structure; The method for forming a semiconductor unit structure further includes: forming a first plug on the first drain region; forming a second plug on the second drain region; forming a first connection structure connecting each first plug and each second plug; The method for forming a first connection structure includes: forming a first connection layer on a first region, the first connection layer connecting the top surfaces of the first plugs of each first region; forming a second connection layer on a second region, the second connection layer connecting the top surfaces of the first plugs of each second region; forming a third connection layer on a third region on one side of a first direction of the first region, the third connection layer connecting the top surfaces of the second plugs on one side of the first direction of the first region; forming a fourth connection layer on the third region on the other side of the first direction of the first region, the fourth connection layer connecting the top surfaces of the second plugs on the other side of the first direction of the first region; forming a fifth connection layer, the fifth connection layer connecting the first connection layer, the second connection layer, the third connection layer and the fourth connection layer.

11. The method for forming a semiconductor unit structure according to claim 10, characterized in that: The semiconductor unit structure is an inverter unit structure; the method for forming the semiconductor unit structure also includes: forming a first gate plug and a second gate plug on each first gate structure, the first gate plug is located between the adjacent first region and the third region, and the second gate plug is located between the adjacent second region and the third region; forming a sixth connection layer connecting each first gate plug; forming a seventh connection layer connecting each second gate plug.

12. The method for forming a semiconductor unit structure according to claim 10, wherein: Also includes: forming third plugs on the first source regions respectively; forming fourth plugs on the second source regions respectively; The semiconductor unit structure is an inverter unit structure; when the transistor type formed by the first area and the second area is P-type and the transistor type formed by the third area is N-type, the third plug is electrically connected to the power line and the fourth plug is electrically connected to the ground line; when the transistor type formed by the first area and the second area is N-type and the transistor type formed by the third area is P-type, the third plug is electrically connected to the ground line and the fourth plug is electrically connected to the power line.

Images