Dual width fin field effect transistor

Abstract

Embodiments of the present disclosure relate to dual-width fin field effect transistors. A dual-width SOI FinFET is disclosed in which different portions of a strained fin have different widths. A method of fabricating such a dual-width FinFET includes laterally recessing a strained fin in source and drain regions using a wet chemical etching process, thereby preserving high strain in the fin while simultaneously trimming the width of the fin in the source and drain regions to less than 5 nm. The resulting FinFET features a wider portion of the fin in a channel region under the gate and a narrower portion of the fin in the source and drain regions. The narrower fin has the advantage that it can be more easily doped during epitaxial growth of raised source and drain regions.

Description

[0001] This application is a divisional application of the invention patent application filed on September 24, 2015, with application number 201510621400.9 and invention title "Dual-width Fin Field-Effect Transistor". Technical Field

[0002] This disclosure generally relates to advanced transistor structures for use in integrated circuits. Background Technology

[0003] Advanced integrated circuits are typically characterized by strained-channel devices, silicon-on-insulator (SiI) substrates, FinFET (Fin Field-Effect Transistor) structures, or combinations thereof, in order to continue shrinking transistor gate lengths to below 20 nm. This technology allows for shrinking transistor channel lengths while minimizing undesirable consequences such as current leakage and other short-channel effects.

[0004] FinFET is an electronic switching device characterized by a conductive channel in the form of a semiconductor fin extending outward from the surface of a substrate. In this device, a gate that controls the current in the fin surrounds three sides of the fin, thus affecting the current flow from three surfaces rather than one. The advanced control achieved through FinFET design results in faster switching performance in the "on" state and less current leakage in the "off" state compared to what is possible in conventional planar devices.

[0005] Incorporating strain into the channel of a semiconductor device stretches the crystal lattice, thereby increasing the charge carrier mobility in the channel and making the device a more responsive switch. Introducing compressive strain into a PFET transistor tends to increase hole mobility in the channel, resulting in a faster switching response to changes in the voltage applied to the transistor gate. Similarly, introducing tensile strain into an NFET transistor tends to increase electron mobility in the channel, also leading to a faster switching response.

[0006] There are many methods to introduce strain into the channel region of a FinFET. Techniques for introducing strain typically involve incorporating an epitaxial layer of one or more materials having a crystal lattice size or geometry slightly different from that of the silicon substrate into the device. This epitaxial layer can be made, for example, of doped silicon or silicon-germanium (SiGe). This epitaxial layer can be incorporated into the source and drain regions, or into the transistor gate used to regulate current flow in the channel, or into the channel itself as a fin. Alternatively, strain can be induced in the fins from below the device by utilizing various types of silicon-on-insulator (SOI) substrates. SOI substrates are characterized by a buried insulator, typically a buried oxide layer (BOX) beneath the active region. SOI FinFET devices have been disclosed in patent applications assigned to this assignee, such as U.S. Patent Application No. 14 / 231,466 entitled “SOI FinFET Transistor with Strained Channel,” U.S. Patent Application No. 14 / 588,116 entitled “Silicon Germanium-on-insulator FinFET,” and U.S. Patent Application No. 14 / 588,221 entitled “Defect-Free Strain-Relaxed Buffer Layer,” all of which are incorporated herein by reference in their entirety. Summary of the Invention

[0007] Disclosed is a strained channel and a raised source and drain region, along with a method for fabricating a dual-width SOI FinFET. In fabricating strained FinFET devices, particularly those with short channels less than approximately 20 nm in length, a challenge arises in forming very narrow semiconductor fins to intentionally reduce strain in the fin material. This allows the fins to undergo a subtractive process, such as reactive ion etching (RIE), to remove material through a combination of mechanical and chemical mechanisms, where the mechanical aspect transfers destructive kinetic energy to the crystal lattice of the fin. The inventors have observed that this process tends to relax the strain in the crystal lattice, while wet etching, being a purely chemical process, more gently alters the lattice, thus offering the possibility of maintaining strain. However, wet etching is limited by its isotropic nature, lacking directional control.

[0008] A fabrication method is disclosed in which a wet chemical etching process is used to laterally recess strain fins in the source and drain regions, thereby maintaining high strain in the fins while trimming the fin width in the source and drain regions to less than 5 nm. The resulting FinFET is characterized by wider fins below the gate and narrower fins in the source and drain regions. The advantage of the narrower fins is that they can be more easily doped during epitaxial growth of the raised source and drain regions. Attached Figure Description

[0009] In the accompanying drawings, the same reference numerals identify similar elements or actions. The dimensions and relative positions of the elements in the accompanying drawings are not necessarily depicted to scale.

[0010] Figure 1 To illustrate the manufacturing process according to one embodiment described herein, such as... Figures 2A-6D The flowchart shows the steps in the dual-width FinFET method described in [the document].

[0011] Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A In order to utilize Figure 1 The top-plan view of a double-width FinFET during the fabrication process of the method shown, in successive steps, with sidewall spacers omitted for clarity.

[0012] Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B In order to utilize Figure 1 The cross-sectional view of the method shown during fabrication in successive steps along a cut line passing through the source / drain region of a double-width FinFET.

[0013] Figure 3C , Figure 4C , Figure 5C , Figure 6C In order to utilize Figure 1 The method shown is a cross-sectional view of the cut line along the fins of the double-width FinFET and across the gate during the fabrication process in successive steps.

[0014] Figure 3D , Figure 4D , Figure 5D , Figure 6D In order to utilize Figure 1 The cross-sectional view of the method shown is taken during the fabrication process in successive steps along the cut line passing through the gate of the double-width FinFET and across the fin. Detailed Implementation

[0015] In the following description, specific details are set forth in order to provide a full understanding of the various aspects of the disclosed subject matter. However, the disclosed subject matter may be practiced without these specific details. In some instances, known structures and methods of semiconductor processing that include embodiments of the subject matter disclosed herein are not described in detail in order to avoid obscuring other aspects of this disclosure.

[0016] Unless the context otherwise requires, throughout the specification and the appended claims, the term “comprising” and its variations such as “including” and “having” shall be interpreted in an open-ended, inclusive sense, meaning “including but not limited to”.

[0017] Throughout the specification, references to "an embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in association with an embodiment is included in at least one embodiment. Thus, the phrases "in one embodiment" or "in an embodiment" appearing in various places throughout the specification do not necessarily all refer to the same aspect. Furthermore, specific features, structures, or characteristics may be combined in any suitable manner in one or more aspects of this disclosure.

[0018] Throughout the specification, it is stated that an integrated circuit generally means to include integrated circuit components built on a semiconductor substrate, whether or not said components are coupled together into a circuit or can be interconnected. Throughout the specification, the term "layer" is used in its broadest sense, thus including films, capping layers or the like, and a layer may include multiple sublayers.

[0019] Throughout this specification, conventional thin film deposition techniques for depositing silicon nitride, silicon dioxide, metals, or similar materials include, for example, chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), metal-organic chemical vapor deposition (MOCVD), plasma-enhanced chemical vapor deposition (PECVD), plasma vapor deposition (PVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), electroplating, electroless plating, and similar processes. Specific embodiments are described herein with reference to examples of such processes. However, this disclosure and references to specific deposition techniques should not be limited to these descriptions. For example, in some settings, a description referring to CVD may be performed alternatively using PVD, or a description specifying electroplating may be performed alternatively using electroless plating. Furthermore, conventional techniques for thin film formation may include in-situ film growth. For example, in some embodiments, controlled growth of oxides to a desired thickness can be achieved by exposing the silicon surface to oxygen or to a humid environment in a heated chamber.

[0020] Throughout the specification, conventional photolithography techniques are mentioned. In the semiconductor manufacturing industry, it is known for patterning various thin films, including spin-exposure-development sequence typically following an etching process. Alternatively or additionally, photoresist can be used to pattern hard masks (e.g., silicon nitride hard masks), which in turn can be used to pattern underlying films.

[0021] Throughout this specification, conventional etching techniques known in the semiconductor manufacturing field for selectively removing polysilicon, silicon nitride, silicon dioxide, metals, photoresist, polyimide, or similar materials include, for example, wet chemical etching, reactive ion (plasma) etching (RIE), washing, wet cleaning, pre-cleaning, spray cleaning, chemical mechanical planarization (CMP), and similar processes. Specific embodiments are described herein with reference to examples of such processes. However, this disclosure and references to specific deposition techniques should not be limited to those described. In some instances, two such techniques may be used interchangeably. For example, stripping photoresist may include immersing the sample in a wet chemical bath or alternatively spraying wet chemicals directly onto the sample.

[0022] Specific embodiments are described herein with reference to manufactured dual-width FinFETs; however, this disclosure and the references to specific materials, dimensions, details, and the order of processing steps are exemplary and should not be limited to those shown.

[0023] Returning to the attached diagram, Figure 1 The steps in a method for fabricating a double-width FinFET for high-performance integrated circuits according to one embodiment are illustrated. The steps in method 100 for constructing a double-width FinFET on silicon-on-insulator (SOI) are further described by… Figures 2A-6D The following descriptions and explanations are provided below. In each of the figures, A is a top plan view of the device at the current step during manufacturing, showing the cut lines for the other views. B is a cross-sectional view along the cut line through the gate; C is a cross-sectional view along the cut line across the gate aligned with the fins; and D is a cross-sectional view along the cut line across the fins in the source / drain regions.

[0024] In 102, according to one embodiment, strained fins 122 are formed on an SOI wafer, the strained fins 122 having a substantially uniform fin width 126. The SOI wafer includes a silicon substrate, a buried oxide (BOX) layer 118, and a top silicon layer 120 having a thickness in the range of about 35 nm to 50 nm. Note that for simplicity, the silicon substrate is omitted from the figure. Alternatively, a strained SOI (sSOI) wafer can be used, which is provided with strain already imparted to the top silicon layer 120. SOI wafers and sSOI wafers are standard starting materials commonly used in the semiconductor industry. Alternatively, a bulk silicon wafer can be used as the starting material, wherein both the BOX layer 118 and the strained top silicon layer 120 can be formed as an initial step in the current manufacturing process. If strained silicon-germanium (SiGe) fins are desired, for example for PFET devices, germanium atoms can be incorporated into the top silicon layer 120 using methods known in the art to form a tensile-strained SiGe film. A strain relaxation buffer (SRB) layer, as known in the art, may optionally be included in the substrate to stabilize the top silicon layer 120 with a high germanium concentration. Alternatively, carbon atoms may be incorporated into the top silicon layer 120 to create strained silicon carbide (SiC) fins.

[0025] The top silicon layer 120 can be patterned to form a structure using conventional far-ultraviolet (EUV) direct lithography for wider fins or, for example, self-aligned sidewall image transfer (SIT) for narrower fins. Figure 2A , Figure 2B The fin 122 is shown in the diagram. In the embodiment described herein, the fin width 126 is narrow, ideally in the range of approximately 6nm-12nm, which can be achieved using the SiN Interchange Injection (SIT) technique. The SIT technique is known in the art and therefore will not be explained in detail here. The SIT process enables the use of SiN sidewall spacers as a hard mask to define a very high aspect ratio fin 122. According to the SIT technique, a mandrel or temporary structure is first formed on top of the top silicon layer 120. A silicon nitride film is then conformally deposited over the mandrel and planarized to form sidewall spacers on the sides of the mandrel. The mandrel is then removed, leaving a pair of narrow sidewall spacers as a hard mask to define the fin 122. Once the hard mask is patterned, the fin 122 is etched into the top silicon layer 120 down to BOX 118. The fin 122 thus formed will serve as the channel region for a FinFET.

[0026] After forming fin 122, a thick gate oxide 124 is grown from the silicon surface, such as... Figure 2B As shown. Next, the fin 122 is patterned so that the gate oxide 124 is removed from the portions of the fin that will be located in the source and drain regions of the FinFET while being held in the gate region.

[0027] At 104, a gate structure 128 is formed that surrounds the three sides of each fin 122, as shown. Figures 3A-3D As shown, the gate structure 128 thus depicts three parts for each fin 122. The first central part below the gate structure is the channel region of the FinFET. The second part extends from the gate structure 128 into the source region of the FinFET. The third part of the fin extends from the gate structure 128 into the drain region of the FinFET.

[0028] The processing steps for forming this gate structure are known in the art and therefore do not need to be described in detail here. In one embodiment, the gate structure 128 includes a polysilicon gate 130, a silicon nitride (SiN) capping layer 132, and sidewall spacers 134 made of SiN or a low-k material such as silicon boron carbonitride (SiBCN). Note that the gate structure does not appear in Figure 3B In the middle, because the cleaving line intersects with the fin outside the gate region.

[0029] At 106, a silicon dioxide (SiO2) film 140 is directionally deposited on top of the fin 122 and on top of the SiN capping layer 132, as shown. Figures 4A-4D As shown. Directional deposition can be performed using, for example, a gas cluster ion beam (GCIB) process. The GCIB process is known in the art and has been described in U.S. Patent Publication No. 2014 / 0239401 for angular implantation. Directional deposition processes employing GCIB can be obtained, for example, as a proprietary process provided with a thin film deposition apparatus supplied by Applied Materials. The directional deposition process preferentially deposits an oxide film 140 on the horizontal surface, with minimal deposition on the sidewalls of the fin 122 or the sidewall spacers 134. In one embodiment, the oxide film 140 has a thickness in the range of about 10 nm to 15 nm. After the directional deposition step, a brief hydrofluoric acid (HF) immersion can be performed to contact the sidewalls without removing a significant portion of the oxide film 140 from the horizontal surface.

[0030] At 108, fin 122 is trimmed to reduce the fin width 126 of the second and third portions of the fin outside the gate region to a narrower fin width 142, as shown. Figures 5A-5D As shown in the diagram. Simultaneously, the fin retains its initial fin width 126 in the channel region below the gate structure 128, thereby creating a dual-width fin. The first fin width 124 and the second fin width 126 are... Figure 5AAs indicated in the text. In one embodiment, the narrower fin width 142 is approximately 4 nm, while the original fin width 126 is targeted to be approximately 8 nm. The fin width can be trimmed by laterally disrupting the silicon or SiGe fin using, for example, an SCI wet etching process while the oxide film 140 protects the top of the fin 122, as shown. Figure 5B As shown. The etchant will also trim the ends of the fins 122 furthest from the gate structure 128, resulting in a slight reduction in the overall length of the fins. However, beneath the gate structure 128, the fins 122 are protected by oxide 124, as well as a polysilicon gate 130 and a SiN capping layer 132, which contact the sidewalls and top of the fins, as shown. Figure 5D As shown. The oxide film 140 on top of the capping layer, as... Figure 5C As shown, it is not actually needed, but it is also harmless.

[0031] One advantage of having a narrower fin width 142 in the source and drain regions is that the narrower fins can be more easily doped. For example, when dopant is introduced into the thinner portion of the fin, the dopant is more uniformly distributed, which contributes to a sharper source and drain junction. Disadvantageously, etching the fin 122 tends to relax the strain. However, with the double-width fin 122, the channel region of the fin, i.e., the region below the gate structure 128, remains unetched, so the strain in the channel region is not compromised. Therefore, the charge carrier mobility in the channel region remains enhanced, preserving the performance advantages of strained channel devices.

[0032] At 110, the oxide film 140 is removed using a conventional pre-cleaning process, such as a brief hydrofluoric acid (HF) immersion. The top portion of the box can be removed during the pre-cleaning step; however, the box will be largely unaffected due to its significantly thicker thickness than the oxide film 140. After the oxide film 140 is removed, elevated source and drain (RSD) regions 144 are epitaxially grown from the side and top surfaces of the fin 122, as... Figures 6A-6D As shown, a charge storage reservoir with an elongated diamond-shaped profile is formed. The RSD region 144 can be in-situ doped during the epitaxial process, where arsenic (As) or phosphorus (P) is used for NFET devices, or boron (B) for PFET devices. Exposure of the fin 122 to dopant species also introduces dopant into the fin, which is distributed across the narrow fin width 142 rather than uniformly. During FinFET operation, the RSD region 144 provides charge carriers to support current flow within the channel portion of the fin 122. The RSD region 144 grows only outside the gate structure 128 exposed by the fin 122. Therefore, the RSD region 144 is not shown in the diagram. Figure 6D In the cross-sectional view.

[0033] At 112, the polysilicon gate 130 can be removed and replaced with a metal gate using a substitution metal gate (RMG) process known in the art. In the RMG process, the polysilicon gate 130 is exposed to an etchant that selectively consumes polysilicon for SiN, thereby leaving the sidewall spacers substantially undamaged. The sidewall spacer structure is then filled with metal. The metal gate may comprise multiple layers of work function metals such as, for example, titanium nitride (TiN) or titanium carbide (TiC), and the gate electrode is typically made of tungsten (W).

[0034] Finally, contacts are fabricated for the completed double-width FinFET device using, for example, a conventional damascus process that includes depositing an interlayer dielectric (ILD), etching contact holes in the ILD, and filling the contact holes with metal.

[0035] It should be understood that while specific embodiments of this disclosure have been described herein for illustrative purposes, various modifications may be made without departing from the spirit and scope of this disclosure. Accordingly, this disclosure is not limited except by the appended claims.

[0036] Given the detailed description above, these and other changes may be made to the embodiments. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but rather as encompassing all possible embodiments as the entire scope of the equivalents covered by the claims. Accordingly, the claims are not limited by this disclosure.

[0037] The various embodiments described above can be combined to provide further embodiments. All U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications mentioned in this specification and / or listed in the application data sheets are incorporated herein by reference in their entirety. Modifications to aspects of the embodiments may be made if necessary to incorporate concepts from various patents, applications and publications to provide further embodiments.

Claims

1. A method for fabricating a fin field effect transistor, comprising: forming a strained silicon fin on a substrate, the strained silicon fin having a first fin width; forming a first oxide layer on the strained silicon fin; forming a gate structure on the strained silicon fin and the first oxide layer, the gate structure covering a first portion of the strained silicon fin and leaving a second portion of the strained silicon fin exposed; forming a second oxide layer on a first side of the second portion of the strained silicon fin, the second oxide layer leaving a second side and a third side of the second portion of the strained silicon fin exposed; thinning the second portion of the strained silicon fin to a second fin width while the second oxide layer is on the first side of the second portion of the strained silicon fin; removing the second oxide layer; and forming a source region and a drain region on the second portion of the strained silicon fin after the second oxide layer is removed, the source region and the drain region wrapping around the first side, the second side, and the third side of the strained silicon fin.

2. The method of claim 1, wherein the first fin width is at least 20% greater than the second fin width.

3. The method of claim 1, wherein the source region and the drain region have a diamond shape profile. forming a gate on the oxide layer, a spacer on the strained silicon fin, and a cap layer on the gate.

4. The method of claim 1, wherein forming the gate structure comprises: forming a gate that wraps around three sides of the fin.

5. The method of claim 1, wherein forming the gate structure comprises:

6. The method of claim 1, wherein the source region and the drain region are raised source and drain regions.

7. The method of claim 1, wherein the first portion of the strained silicon fin is a channel region.

8. A fin field effect transistor, comprising: a raised source region; a raised drain region; a fin extending from the raised source region to the raised drain region, the fin having a non-uniform fin width that varies along a length of the fin, a channel region of the fin being twice as thick as portions of the fin outside of the channel region; and a gate wrapping around three sides of the channel region of the fin, the gate configured to control a current flow within the channel region between the raised source region and the raised drain region, wherein the raised source region and the raised drain region have a diamond shape profile.

9. The fin field effect transistor of claim 8, wherein the channel region of the fin is a strained channel region.

10. The fin field effect transistor of claim 8, wherein portions of the fin outside of the channel region exhibit a substantially uniform dopant distribution.

11. An electronic device, comprising: a silicon substrate; a buried oxide layer in the silicon substrate; a strained silicon fin on top of the buried oxide layer, the strained silicon fin including a wide portion having a first fin width and a narrow portion having a second fin width; ​ a gate structure adjacent to the strained silicon fin, the gate structure including a metal gate electrode and a gate oxide adjacent to the gate electrode; and raised source and drain regions adjacent to the strained silicon fin, the wide portion corresponding to a channel region, the narrow portion corresponding to the raised source and drain regions, wherein the raised source and drain regions have a diamond shape profile.

12. The electronic device of claim 11, wherein the silicon substrate is a strained silicon-on-insulator substrate.

13. The electronic device of claim 11, wherein the wide portion and the narrow portion have substantially the same degree of strain.

14. The electronic device of claim 11, wherein the wide portion is at least 20% wider than the narrow portion.

15. A fin field effect transistor, comprising: a raised source region; a raised drain region; a fin extending from the raised source region to the raised drain region, the fin having a non-uniform fin width that varies along a length of the fin, a channel region of the fin being thicker than portions of the fin outside the channel region, the portions of the fin outside the channel region of the fin having a substantially uniform dopant profile; and a gate wrapped around three sides of the channel region of the fin, the gate configured to control current flow within the channel region between the raised source region and the raised drain region, wherein the raised source and drain regions have a diamond shape profile.

16. The fin field effect transistor of claim 15, wherein the channel region of the fin is twice as thick as the portions of the fin outside the channel region.

17. A method for manufacturing a fin field effect transistor, comprising: forming a strained fin on a substrate, the strained fin having a first width; forming a gate structure on the strained fin, the gate structure on a first portion of the strained fin and leaving a second portion of the strained fin exposed; forming an oxide layer on a first side of the second portion of the strained fin, the oxide layer leaving a second side and a third side of the second portion of the strained fin exposed; thinning the second portion of the strained fin to a second width while the oxide layer is on the first side of the second portion of the strained fin; removing the oxide layer; and forming a source region or a drain region on the second portion of the strained fin after the oxide layer is removed.

18. The method of claim 17, wherein the source region or the drain region wraps around the first side, the second side, and the third side of the strained fin.

19. The method of claim 17, wherein the first width is at least 20% greater than the second width.

20. The method of claim 17, wherein the source region or the drain region has a diamond shape profile.

21. The method of claim 17, wherein forming the gate structure comprises: forming a gate on the oxide layer, forming a spacer on the strained fin, and forming a cap layer on the gate.

22. The method of claim 17, wherein forming the gate structure comprises: forming a gate, the gate wrapping around three sides of the fin.

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