A circuit for improving the latch-up resistance of ESD devices

Abstract

The application provides a circuit for improving the anti-latch-up effect of an ESD device, comprising an ESD device, a suppression resistor arranged between the emitter and the base of the ESD device, a first parasitic triode, a second parasitic triode, a third parasitic triode and an external power supply; the bases of the first and second parasitic triodes are connected with the collector of the ESD device, the emitters of the first and second parasitic triodes are connected with the base of the ESD device, and the collectors of the first and second parasitic triodes are connected with the external power supply respectively; the base of the third parasitic triode is connected with the base of the ESD device and the emitter of the first parasitic triode respectively, the emitter of the third parasitic triode is connected with the emitter of the ESD device, and the collector of the third parasitic triode is connected with the collector of the ESD device, the base of the first parasitic triode and the base of the second parasitic triode respectively. The application can improve the anti-latch-up effect of the ESD device.

Description

Technical Field

[0001] The present invention belongs to the field of electronic technology, and in particular relates to a circuit for improving the anti-latch effect capability of an ESD device. Background Art

[0002] Latch-up occurs when the parasitic NPN and PNP circuits form a PNPN structure, creating a positive feedback loop with a loop gain greater than 1. Once the circuit enters latch-up, it cannot automatically exit. The feedback loop persists and amplifies, ultimately damaging the chip. Common latch-up testing methods include voltage and current testing to simulate the chip's ability to resist interference when subjected to voltage or current transients.

[0003] in Figure 1 This is a cross-sectional view of a PNP transistor, with BE shorted and serving as an external I / O port; collector C is grounded. HN denotes high-voltage N-well, NW denotes N-well, and PW denotes P-well. N+ and P+ denote heavily N-type and heavily P-type doping, respectively. PNP ESD devices, similar to GGNMOS, exhibit snapback, providing excellent protection for internal circuits.

[0004] but Figure 1 The following problems may occur during latch-up testing: When performing I / O negative current testing, such as Figure 2 As shown in the figure, a parasitic NPN is formed: QN1 / QN2. The base of the ESD device serves as the emitter of the parasitic QN1 / QN2, Psub serves as the base, and the collector is provided by the external power supply VDD. Figure 2 In the figure, esd_mn5_io_3t represents the ESD device for the external power supply VDD. RSUB and RNWELL represent the substrate resistance and N-well resistance, respectively. After the NPN circuit is formed, a PNP structure is also formed (the emitter of the PNP is supplied by the P+ terminal of another module, such as a power PMOS), resulting in a PNPN structure. If QN1 / QN2 are not optimized, a latch-up structure with a loop gain greater than 1 can easily form, generating high currents and potentially damaging the chip. This shows that existing ESD device circuits have low latch-up resistance. Summary of the Invention

[0005] An embodiment of the present invention provides a circuit for improving the anti-latch effect capability of an ESD device, aiming to solve the problem of low anti-latch effect capability of the ESD device circuit in the prior art.

[0006] An embodiment of the present invention provides an energy storage converter with an automatic protection function, comprising:

[0007] An ESD device; a suppression resistor disposed between an emitter and a base of the ESD device; a first parasitic transistor; a second parasitic transistor; a third parasitic transistor and an external power supply;

[0008] The bases of the first parasitic transistor and the second parasitic transistor are respectively connected to the collector of the ESD device, the emitters of the first parasitic transistor and the second parasitic transistor are respectively connected to the base of the ESD device, and the collectors of the first parasitic transistor and the second parasitic transistor are respectively connected to an external power supply;

[0009] The base of the third parasitic transistor is respectively connected to the base of the ESD device and the emitter of the first parasitic transistor, the emitter of the third parasitic transistor is connected to the emitter of the ESD device, and the collector of the third parasitic transistor is respectively connected to the collector of the ESD device, the base of the first parasitic transistor and the base of the second parasitic transistor.

[0010] Furthermore, it further includes a first resistor and a second resistor;

[0011] One end of the first resistor is connected to the collector of the ESD device, and the other end of the first resistor is connected to the collector of the third parasitic transistor, the base of the first parasitic transistor, and the base of the second parasitic transistor respectively;

[0012] One end of the second resistor is connected to the collector of the ESD device, and the other end of the second resistor is respectively connected to the collector of the third parasitic transistor, the base of the first parasitic transistor, the base of the second parasitic transistor and the other end of the first resistor.

[0013] Furthermore, a fourth parasitic transistor is included;

[0014] The base of the fourth parasitic transistor is respectively connected to the collector of the first parasitic transistor, the collector of the second parasitic transistor and the base of the ESD device in the external power supply, the emitter of the fourth parasitic transistor is connected to the emitter of the ESD device in the external power supply, and the collector of the fourth parasitic transistor is respectively connected to the collector of the ESD device in the external power supply, the base of the first parasitic transistor and the base of the second parasitic transistor.

[0015] Furthermore, the ESD device is a PNP transistor.

[0016] Furthermore, the first parasitic transistor and the second parasitic transistor are both NPN transistors.

[0017] Furthermore, the third parasitic transistor and the fourth parasitic transistor are both PNP transistors.

[0018] Furthermore, the ESD device in the external power supply is an NPN transistor.

[0019] Furthermore, the ESD device in the external power supply is a power PMOS.

[0020] Furthermore, the power supply voltage provided by the power PMOS is 24V.

[0021] The present invention achieves the beneficial effects of suppressing the parasitic first and second parasitic transistors by adding a suppression resistor between the emitter and base of the ESD device, while simultaneously reducing the loop gain of the PNPN structure, thereby lowering the risk of latch-up in the ESD device. Furthermore, the addition of the suppression resistor does not affect the ESD resistance of the ESD device itself. Therefore, the circuit for improving the latch-up resistance of an ESD device proposed in the present invention can improve the latch-up resistance of the ESD device, suppressing the parasitic first and second parasitic transistors without affecting the ESD resistance of the ESD device itself. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is a cross-sectional view of an ESD device with a triode PNP structure provided by the prior art;

[0023] Figure 2 yes Figure 1 Diagram of the parasitic device structure formed during the latch-up effect test;

[0024] Figure 3 1 is a schematic structural diagram of a circuit for improving the latch-up resistance of an ESD device provided by an embodiment of the present invention;

[0025] Figure 4 1 is a schematic structural diagram of another circuit for improving the anti-latch effect capability of an ESD device provided by an embodiment of the present invention;

[0026] Figure 5 yes Figure 4 Equivalent circuit diagram. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0028] The present invention suppresses the parasitic first and second parasitic transistors by adding a suppression resistor between the emitter and base of an ESD device, while simultaneously reducing the loop gain of the PNPN structure, thereby lowering the risk of latch-up in the ESD device. Furthermore, the addition of the suppression resistor does not affect the ESD resistance of the ESD device itself. Therefore, the circuit for improving the latch-up resistance of an ESD device proposed in the present invention can improve the latch-up resistance of the ESD device, suppressing the parasitic first and second parasitic transistors without affecting the ESD resistance of the ESD device itself.

[0029] Example 1

[0030] like Figure 3 As shown, Figure 3 The present invention provides a schematic structural diagram of a circuit for improving the latch-up resistance of an ESD device.

[0031] The circuit 1 for improving the anti-latch effect capability of an ESD device comprises an ESD device 2; a suppression resistor R arranged between the emitter and the base of the ESD device 2; ESD ; a first parasitic transistor QN1; a second parasitic transistor QN2; a third parasitic transistor QP1 and an external power supply 3.

[0032] The bases of the first parasitic transistor QN1 and the second parasitic transistor QN2 are respectively connected to the collector of the ESD device 2, the emitters of the first parasitic transistor QN1 and the second parasitic transistor QN2 are respectively connected to the base of the ESD device 2, and the collectors of the first parasitic transistor QN1 and the second parasitic transistor QN2 are respectively connected to the external power supply 3.

[0033] The base of the third parasitic transistor QP1 is respectively connected to the base of the ESD device 2 and the emitter of the first parasitic transistor QN1, the emitter of the third parasitic transistor QP1 is connected to the emitter of the ESD device 2, and the collector of the third parasitic transistor QP1 is respectively connected to the collector of the ESD device 2, the base of the first parasitic transistor QN1 and the base of the second parasitic transistor QN2.

[0034] The ESD (Electro-Static discharge) device may be a diode, a transistor, a MOS, etc. In the embodiment of the present invention, the ESD device 2 is mainly described by taking a PNP transistor as an example.

[0035] Latch-up effect Latch-up effect is a serious problem in CMOS integrated circuits. This problem can cause confusion in chip functions or the circuit to stop working or even burn out.

[0036] Suppression resistor R ESD It is used to limit the current of the emitter of the first parasitic transistor QN1 and the second parasitic transistor QN2, thereby reducing the current of the first parasitic transistor QN1 and the second parasitic transistor QN2. ESD It can also be replaced by other suppression devices with the same function. In the embodiment of the present invention, the suppression resistor R ESD Take this as an example to illustrate.

[0037] The first parasitic transistor QN1 and the second parasitic transistor QN2 are both NPN transistors. The first parasitic transistor QN1 and the second parasitic transistor QN2 are parasitic transistors formed when the ESD device 2 is subjected to a negative charge test.

[0038] The third parasitic transistor QP1 is a PNP transistor.

[0039] External power supply 3 may be a power supply that provides a power supply voltage to ESD device 2. External power supply 3 also includes an ESD device within external power supply 3. The ESD device within external power supply 3 may be an NPN transistor. A parasitic transistor is formed between the ESD device within external power supply 3 and ESD device 2 within the present circuit. Figure 3 esd_mn5_io_3t in FIG is the ESD device of VDD of external power supply 3.

[0040] In an embodiment of the present invention, the circuit for improving the latch-up resistance of the ESD device 2 further includes a substrate resistor RSUB and an N-well resistor RNWELL.

[0041] Specifically, when a negative current test is performed on the I / O port, an NPN transistor (first parasitic transistor QN1 / second parasitic transistor QN2) will be formed, where the base of the ESD device 2 serves as the emitter of the first parasitic transistor QN1 / second parasitic transistor QN2, Psub of the ESD device 2 serves as the base, and the collector of the first parasitic transistor QN1 / second parasitic transistor QN2 is provided by VDD of the external power supply 3.

[0042] After the NPN transistors (first parasitic transistor QN1 / second parasitic transistor QN2) are formed, a PNP transistor (third parasitic transistor QP1) is also formed. The emitter of the PNP transistor is provided by the P+ of another module, such as a power PMOS, thus forming a PNPN structure.

[0043] When the first parasitic transistor QN1 / the second parasitic transistor QN2 is turned on, the suppression resistor R is set between the emitter and the base of the ESD device 2. ESD , the first parasitic transistor QN1 / the second parasitic transistor QN2 can be suppressed, and the emitter of the first parasitic transistor QN1 / the second parasitic transistor QN2 is current limited, thereby reducing the current of the first parasitic transistor QN1 / the second parasitic transistor QN2.

[0044] Suppression resistor R ESD The value is generally tens of ohms, so that during the latch-up negative current test (such as ±200mA), even if the first parasitic transistor QN1 / the second parasitic transistor QN2 is turned on, no large current will be generated.

[0045] At the same time, adding a resistor to the emitter of the NPN (first parasitic transistor QN1 / second parasitic transistor QN2) can make the loop gain of the PNPN structure less than 1. In this way, the PNPN structure will not form a locked latch-up, and even if it enters latch-up, it will automatically exit.

[0046] When the BE junction of the first parasitic transistor QN1 / the second parasitic transistor QN2 is turned on, the parasitic third parasitic transistor QP1 is also turned on. Since the third parasitic transistor QP1 is in the amplification region, it has a current amplification function and can increase the discharge capacity of negative current. At the same time, due to the added suppression resistor R ESD It is small and does not affect the ESD capability of the device itself.

[0047] In one embodiment of the present invention, the circuit for improving the latch-up resistance capability of the ESD device 2 further includes a first resistor and a second resistor.

[0048] One end of the first resistor is connected to the collector of the ESD device 2 , and the other end of the first resistor is connected to the collector of the third parasitic transistor QP1 , the base of the first parasitic transistor QN1 , and the base of the second parasitic transistor QN2 .

[0049] One end of the second resistor is connected to the collector of the ESD device 2 , and the other end of the second resistor is respectively connected to the collector of the third parasitic transistor QP1 , the base of the first parasitic transistor QN1 , the base of the second parasitic transistor QN2 , and the other end of the first resistor.

[0050] In the embodiment of the present invention, a suppression resistor R is added between the emitter and the base of the ESD device 2. ESDThe method is used to suppress the parasitic first parasitic transistor QN1 / the second parasitic transistor QN2, and at the same time reduce the loop gain of the PNPN structure, thereby reducing the risk of latch-up of the ESD device 2, and adding the suppression resistor R ESD The ESD capability of the ESD device 2 itself will not be affected. Therefore, the circuit for improving the latch-up resistance of the ESD device 2 proposed in the present invention can improve the latch-up resistance of the ESD device 2, while suppressing the parasitic first parasitic transistor QN1 / second parasitic transistor QN2, without affecting the ESD capability of the ESD device 2 itself.

[0051] Example 2

[0052] like Figure 4 As shown, the circuit for improving the latch-up resistance of the ESD device 2 further includes a fourth parasitic transistor QP2;

[0053] The base of the fourth parasitic transistor QP2 is respectively connected to the collector of the first parasitic transistor QN1, the collector of the second parasitic transistor QN2 and the base of the ESD device in the external power supply 3, the emitter of the fourth parasitic transistor QP2 is connected to the emitter of the ESD device in the external power supply 3, and the collector of the fourth parasitic transistor QP2 is respectively connected to the collector of the ESD device in the external power supply 3, the base of the first parasitic transistor QN1 and the base of the second parasitic transistor QN2.

[0054] The fourth parasitic transistor QP2 is a PNP transistor. The ESD device in the external power supply 3 is a power PMOS. When the ESD device in the external power supply 3 is a power PMOS, the power voltage provided by the power PMOS can be 24 V. PK is P_sinker.

[0055] Specifically, Figure 4 The equivalent circuit corresponding to the circuit for improving the latch-up resistance of the ESD device 2 provided in Figure 5 The equivalent circuit includes the power input terminal VIN (24V), the third resistor R1, the fourth resistor R2, the first parasitic transistor QN1, the second parasitic transistor QN2, the fourth parasitic transistor QP2, the suppression resistor R ESD , ground terminal GND, and I / O port.

[0056] in, Figure 5 The suppression resistor R ESD Can be used with Figure 3 The suppression resistor R ESD The same, that is, the corresponding suppression resistor R ESD

[0057] More specifically, one end of the third resistor R1 is connected to the power input terminal VIN, and the other end of the third resistor R1 is respectively connected to the collector of the first parasitic transistor QN1, the collector of the second parasitic transistor QN2, and the base of the fourth parasitic transistor QP2.

[0058] The emitter of the fourth parasitic transistor QP2 is connected to the power input terminal VIN, and the collector of the fourth parasitic transistor QP2 is connected to one end of the fourth resistor R2, the base of the first parasitic transistor QN1, and the base of the second parasitic transistor QN2. The other end of the fourth resistor R2 is connected to the ground terminal GND.

[0059] Suppression resistor R ESD One end of the resistor R is connected to the emitter of the first parasitic transistor QN1 and the emitter of the second parasitic transistor QN2. ESD The other end is connected to the I / O port.

[0060] Depend on Figure 5 It can be seen that when the latch-up negative current test is performed at the I / O, the first parasitic transistor QN1 / the second parasitic transistor QN2 and the fourth parasitic transistor QP2 form a positive feedback loop. If the suppression resistor R is not added ESD , the gain of the positive feedback loop is greater than 1, resulting in latch-up effect. Adding a suppression resistor R ESD This can suppress the parasitic first and second parasitic transistors QN1 and QN2, reducing the positive feedback loop gain. When the first and second parasitic transistors QN1 and QN2 conduct, the parasitic fourth transistor QP2 also conducts. This fourth transistor QP2 is in the amplification region, increasing its ability to discharge negative current. This reduces the likelihood of a latch-up effect and improves the reliability of the protection circuit.

[0061] In the embodiment of the present invention, a suppression resistor R is set at the emitter of the first parasitic transistor QN1 / the second parasitic transistor QN2. ESD The method is used to suppress the parasitic first parasitic transistor QN1 / the second parasitic transistor QN2, and at the same time reduce the loop gain of the PNPN structure, thereby reducing the risk of latch-up of the ESD device 2, and adding the suppression resistor R ESD The ESD capability of the ESD device 2 itself will not be affected. Therefore, the circuit for improving the latch-up resistance of the ESD device 2 proposed in the present invention can improve the latch-up resistance of the ESD device 2, while suppressing the parasitic first parasitic transistor QN1 / second parasitic transistor QN2, without affecting the ESD capability of the ESD device 2 itself.

[0062] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A circuit for improving the latch-up resistance of an ESD device, characterized in that: include: ESD devices; A suppression resistor is provided between the emitter and base of the ESD device; The first parasitic transistor; The second parasitic transistor; a third parasitic transistor and an external power supply; The bases of the first parasitic transistor and the second parasitic transistor are respectively connected to the collector of the ESD device, the emitters of the first parasitic transistor and the second parasitic transistor are respectively connected to the base of the ESD device, and the collectors of the first parasitic transistor and the second parasitic transistor are respectively connected to an external power supply; The base of the third parasitic transistor is respectively connected to the base of the ESD device and the emitter of the first parasitic transistor, the emitter of the third parasitic transistor is connected to the emitter of the ESD device, and the collector of the third parasitic transistor is respectively connected to the collector of the ESD device, the base of the first parasitic transistor and the base of the second parasitic transistor.

2. The circuit for improving the latch-up resistance of an ESD device as claimed in claim 1, wherein: Also includes a first resistor and a second resistor; One end of the first resistor is connected to the collector of the ESD device, and the other end of the first resistor is connected to the collector of the third parasitic transistor, the base of the first parasitic transistor, and the base of the second parasitic transistor respectively; One end of the second resistor is connected to the collector of the ESD device, and the other end of the second resistor is respectively connected to the collector of the third parasitic transistor, the base of the first parasitic transistor, the base of the second parasitic transistor and the other end of the first resistor.

3. The circuit for improving the latch-up resistance of an ESD device as claimed in claim 1, wherein: Also included is a fourth parasitic transistor; The base of the fourth parasitic transistor is respectively connected to the collector of the first parasitic transistor, the collector of the second parasitic transistor and the base of the ESD device in the external power supply, the emitter of the fourth parasitic transistor is connected to the emitter of the ESD device in the external power supply, and the collector of the fourth parasitic transistor is respectively connected to the collector of the ESD device in the external power supply, the base of the first parasitic transistor and the base of the second parasitic transistor.

4. The circuit for improving the latch-up resistance of an ESD device according to any one of claims 1 to 3, wherein: The ESD device is a PNP transistor.

5. The circuit for improving the latch-up resistance of an ESD device according to any one of claims 1 to 3, wherein: The first parasitic transistor and the second parasitic transistor are both NPN transistors.

6. The circuit for improving the latch-up resistance of an ESD device according to claim 3, wherein: The third parasitic transistor and the fourth parasitic transistor are both PNP transistors.

7. The circuit for improving the latch-up resistance of an ESD device according to any one of claims 1 to 2, wherein: The ESD device in the external power supply is an NPN transistor.

8. The circuit for improving the latch-up resistance of an ESD device according to claim 3, wherein: The ESD device in the external power supply is a power PMOS.

9. The circuit for improving the latch-up resistance of an ESD device according to claim 8, wherein: The power supply voltage provided by the power PMOS is 24V.

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