Graphical mask layer and method for forming the same, memory and method for forming the same

Abstract

A graphical mask layer and a method for forming the same, a memory device and a method for forming the same. The method for forming the graphical mask layer includes: forming a mask material layer; patterning the mask material layer to form a sub-mask layer having a plurality of sub-mask patterns distributed in an array; removing the sub-mask patterns located within the edge region of the sub-mask layer; and forming sidewalls on the sidewall surfaces of the remaining sub-mask patterns to form the graphical mask layer. The above method reduces the difficulty of forming the graphical mask layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a patterned mask layer and a method for forming the same, and a memory and a method for forming the same. Background Art

[0002] A memory includes a plurality of memory cells arranged in an array, and each memory cell is formed on an active area (AA). During the formation of a memory in the prior art, it is usually necessary to etch a substrate to form an array of active areas.

[0003] As the storage capacity and density of the memory increase, the line width of the active area gradually decreases. When forming a plurality of mask patterns arranged in an array on the surface of the substrate as a mask for the active area, some mask patterns located in the edge area of the array may be incomplete, and the active area formed by etching the substrate using such a mask is likely to collapse. To avoid the above problems, it is usually necessary to remove the incomplete mask patterns in the edge area after forming the mask patterns. Please refer to Figure 1 , a partial schematic diagram of the mask pattern of the active area. When removing the mask pattern 101 at the edge, the edge area and the middle area are separated by a curve 102. Since the spacing between adjacent mask patterns 101 is small, the arc curvature α of the curve 102 is small. Since in the lithography process, smaller-sized patterns are prone to generate a large optical proximity effect (OPE), during the process of manufacturing a photomask, it is necessary to perform optical proximity correction (OPC) on the lithography pattern. And the small curvature of the curve 102 increases the difficulty of OPC correction. Once the photomask pattern correction is insufficient, it is easy to cause the originally complete active area 101 to be etched. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a patterned mask layer and a method for forming the same, a memory and a method for forming the same, so as to reduce the formation difficulty of the patterned mask layer and the memory.

[0005] To solve the above problems, the present invention provides a method for forming a patterned mask layer, including: forming a mask material layer; patterning the mask material layer to form a sub-mask layer having a plurality of sub-mask patterns distributed in an array; removing the sub-mask patterns located in the edge area of the sub-mask layer; and forming sidewalls on the sidewall surfaces of the remaining sub-mask patterns to form the patterned mask layer.

[0006] Optionally, the sub-mask patterns are arranged in parallel.

[0007] Optionally, the contour of the edge area includes at least a part of a curve.

[0008] Optionally, an edge etching mask is used to define the edge region of the sub-mask layer; the edge etching mask includes a reserved region and an etching region surrounding the reserved region, the etching region corresponding to the edge region of the sub-mask layer, and the boundary line between the etching region and the reserved region includes at least a part of a curve.

[0009] Optionally, after removing the sub-mask patterns within the edge region, the remaining sub-mask patterns have the same shape and size.

[0010] Optionally, the method for forming the sub-mask layer includes: etching the mask material layer to form a plurality of long strip-shaped patterns arranged in parallel along a first direction; etching the long strip-shaped patterns to divide the long strip-shaped patterns into a plurality of sub-mask patterns.

[0011] Optionally, the edge region of the sub-mask layer includes at least a plurality of defective sub-mask patterns.

[0012] To solve the above problems, the technical solution of the present invention further provides a patterned mask layer, including: a plurality of sub-mask patterns distributed in an array; sidewalls located on the sidewall surfaces of the sub-mask patterns.

[0013] Optionally, the sub-mask patterns are arranged in parallel.

[0014] Optionally, the shapes and sizes of the respective sub-mask patterns are the same.

[0015] To solve the above problems, the technical solution of the present invention further provides a method for forming a memory, including: adopting the method for forming the above-mentioned patterned mask layer to form a patterned mask layer on the surface of a substrate, the patterned mask layer including a plurality of sub-mask patterns arranged in an array, and sidewalls being present on the sidewall surfaces of the sub-mask patterns; using the patterned mask layer as a mask to etch the substrate to form a plurality of active regions arranged in an array within the substrate.

[0016] Optionally, the active regions are arranged in parallel.

[0017] Optionally, the shapes and sizes of the respective active regions are the same.

[0018] To solve the above problems, the technical solution of the present invention further includes a memory, including: a substrate, with a plurality of active regions arranged in an array formed within the substrate; the active regions being formed by etching the substrate using the patterned mask layer described in any one of the above.

[0019] The method for forming the patterned mask layer of the present invention first patterns the mask material layer to form sub-mask patterns, and the size of the sub-mask patterns is smaller than the size of the active region to be formed, thereby increasing the spacing between the sub-mask patterns and reducing the difficulty of removing the defective sub-mask patterns in the edge region, so that the patterned mask layer is more easily formed. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic diagram of the division between the edge region and the middle region when removing the mask pattern at the edge;

[0021] Figures 2 to 7 It is a schematic structural diagram of the formation process of the patterned mask layer in a specific embodiment of the present invention;

[0022] Figure 8 It is a schematic structural diagram of a memory in a specific embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0023] The following will describe in detail the specific embodiments of the patterned mask layer provided by the present invention, its formation method, the memory and its formation method with reference to the accompanying drawings.

[0024] Please refer to Figures 2 to 7 , which is a schematic structural diagram of the formation process of the patterned mask layer in a specific embodiment of the present invention.

[0025] Please refer to Figure 2 , and form a mask material layer 201.

[0026] In this specific embodiment, the mask material layer 201 is formed on the surface of the substrate 200. The mask material layer 201 includes a single-layer or multi-layer mask material layer such as silicon oxide, silicon nitride, silicon oxynitride, amorphous carbon, photoresist, etc.

[0027] The substrate 200 may be a semiconductor substrate, including a single-crystal silicon substrate, a single-crystal germanium substrate, a germanium-silicon substrate, or a silicon-on-insulator substrate, etc. Figure 2 In, only a partial region of the substrate 200 and the mask material layer 201 is shown.

[0028] Please refer to Figure 3 , and pattern the mask material layer 201 to form a plurality of strip-shaped patterns 301 arranged parallel to the first direction.

[0029] The width of the strip-shaped pattern 301 is smaller than the width of the active region to be formed.

[0030] The double patterning (SADP, self-aligned double patterning) process can be adopted to pattern the grinding material layer 201 to form the strip-shaped pattern 301. In other specific embodiments, a single patterning process can also be adopted to form the strip-shaped pattern 301.

[0031] The strip-shaped patterns 301 are all arranged in parallel in the same direction, and the spacing between adjacent strip-shaped patterns 301 is the same.

[0032] Please refer to Figure 4 , etch the strip-shaped pattern 301 (please refer to Figure 3 ), and divide the strip-shaped pattern 301 into several sub-mask patterns 401, and the several sub-mask patterns 401 form a sub-mask layer.

[0033] By further etching the strip-shaped pattern 301, each strip-shaped pattern 301 is divided into sub-mask patterns 401, and the sub-mask patterns 401 are distributed in an array. The length and width of the sub-mask pattern 401 are both smaller than the length and width of the active region to be formed.

[0034] Some sub-mask patterns 401 located on the surface of the array edge may have defects. For example, for the sub-mask pattern 401a, there may be problems such as a shorter length or an uneven edge, which cannot be used to form a complete active region and is prone to collapse in subsequent processes.

[0035] Please refer to Figure 5 , form a patterned photoresist layer 500, and the patterned photoresist layer 500 exposes the edge region 501 and some sub-mask patterns 401 located on the edge region 501.

[0036] In this specific embodiment, the sub-mask patterns on the edge region exposed by the patterned photoresist layer 300 are all incomplete patterns. Through the etching process, the incomplete sub-mask patterns in the edge region 501 are removed to retain the complete sub-mask pattern 401 on the surface of the substrate 200.

[0037] In order to improve the utilization rate of the substrate 200, in this specific embodiment, only the incomplete sub-mask patterns are removed. The contour of the edge region 501 at least includes part of a curve, and the radian of the curve is positively correlated with the spacing between adjacent sub-mask patterns 401. The smaller the spacing between adjacent sub-mask patterns 401, the smaller the radian of the curve.

[0038] The method for forming the patterned photoresist layer 500 includes: forming a photoresist layer on the surface of the substrate 200, then using an edge etching mask to define the positions of the sub-mask patterns to be removed, and removing the photoresist layer located on the edge region 501 to form the patterned photoresist layer 500. The pattern of the edge etching mask needs to be OPC corrected to accurately expose the edge region 501. The edge etching mask includes a reserved region and an etching region surrounding the reserved region, and the boundary line between the etching region and the reserved region includes at least part of a curve. The etching region is used to expose the edge region 501.

[0039] In this specific embodiment, since the width and length of the formed sub-mask pattern 401 are both smaller than the width of the active region to be formed, at the same storage density, the spacing between adjacent sub-mask patterns 401 is increased, so that the arcs of the curve are increased, reducing the optical proximity effect when using the edge etching mask to expose and develop the photoresist layer, and thus reducing the difficulty of OPC correction for the pattern of the edge etching mask.

[0040] Please refer to Figure 6 , using the patterned photoresist layer 500 (please refer to Figure 5 ) as a mask, removing the sub-mask pattern 401 within the edge region 501, and then removing the patterned photoresist layer 500.

[0041] The remaining sub-mask patterns 401 on the substrate 200 are all complete patterns, and the complete sub-mask patterns 401 are arranged in parallel, with the same shape and size, and are distributed in an array.

[0042] Please refer to Figure 7 , forming sidewalls 701 on the sidewall surfaces of each of the remaining sub-mask patterns 401 to form a patterned mask layer.

[0043] The thickness of the sidewall 701 is adjusted according to the size of the active region to be formed.

[0044] The method for forming the sidewall 701 includes: forming a sidewall material layer covering the surface of the substrate 200 and the sub-mask pattern 401; etching the sidewall material layer in a direction perpendicular to the surface of the substrate 200 to remove the sidewall material located on the surface of the substrate 200 and on the top surface of the sub-mask pattern 401, and forming the sidewall 701 on the sidewall surface of the sub-mask pattern 401.

[0045] The sub-mask pattern 401 and the sidewall 701 on its sidewall surface together serve as a mask pattern to define the pattern of the active region to be formed.

[0046] In the method for forming the above-mentioned graphical mask layer, first, the mask material layer is patterned to form sub-mask patterns, and the size of the sub-mask patterns is smaller than the size of the active regions to be formed, thereby increasing the spacing between the sub-mask patterns and reducing the difficulty of removing defective sub-mask patterns in the edge regions.

[0047] The specific embodiments of the present invention further provide a graphical mask layer.

[0048] Please refer to Figure 7 , the graphical mask layer includes: a plurality of sub-mask patterns 401 distributed in an array; sidewalls 701 located on the sidewall surfaces of the sub-mask patterns 401.

[0049] The sub-mask patterns 401 are arranged in parallel, and the shapes and sizes of the sub-mask patterns 401 are the same.

[0050] The contour of the edge region outside the region where the sub-mask patterns 401 are located includes at least part of a curve. The radian of the curve is greater than a preset value, thereby reducing the difficulty of forming the sub-mask patterns 401.

[0051] The specific embodiments of the present invention further provide a memory and a method for forming the same.

[0052] Please refer to Figure 8 , using the graphical mask layer formed by the above specific embodiments as a mask, etching the substrate 200 to form a plurality of active regions 801 arranged in an array in the substrate 200. The active regions 801 are arranged in parallel, and the shapes and sizes of the active regions 801 are the same. After forming the active regions 801, an insulating dielectric material is filled between the active regions 801 to isolate the active regions 801.

[0053] The method for forming the memory further includes forming memory cells on each of the active regions 801.

[0054] The specific embodiments of the present invention further provide a memory, please refer to Figure 8 , the memory includes a substrate 200, and a plurality of active regions 801 arranged in an array are formed in the substrate 200; an insulating dielectric material is filled between the active regions 801, and memory cells are further formed on each of the active regions 801.

[0055] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can still be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. A method for forming a patterned mask layer, characterized in that, comprising: forming a mask material layer; patterning the mask material layer to form a sub-mask layer having a plurality of sub-mask patterns distributed in an array; wherein, the size of the sub-mask pattern is smaller than the size of the active region to be formed; forming a patterned photoresist layer, the patterned photoresist layer exposing the edge region of the sub-mask layer and a part of the sub-mask patterns located within the edge region; using the patterned photoresist layer as a mask to remove the sub-mask patterns located within the edge region of the sub-mask layer; forming sidewalls on the sidewall surfaces of the remaining respective sub-mask patterns to form the patterned mask layer.

2. The method for forming a patterned mask layer according to claim 1, characterized in that, the sub-mask patterns are arranged in parallel.

3. The method for forming a patterned mask layer according to claim 1, characterized in that, the contour of the edge region at least includes a part of a curve.

4. The method for forming a patterned mask layer according to claim 1, characterized in that, defining the edge region of the sub-mask layer by using an edge etching mask; the edge etching mask includes a reserved region and an etching region surrounding the reserved region, the etching region corresponding to the edge region of the sub-mask layer, and the boundary line between the etching region and the reserved region at least includes a part of a curve.

5. The method for forming a patterned mask layer according to claim 1, characterized in that, after removing the sub-mask patterns within the edge region, the remaining sub-mask patterns have the same shape and size.

6. The method for forming a patterned mask layer according to claim 1, characterized in that, the method for forming the sub-mask layer includes: etching the mask material layer to form a plurality of elongated patterns arranged in parallel along a first direction; etching the elongated patterns to divide the elongated patterns into a plurality of sub-mask patterns.

7. The method for forming a patterned mask layer according to claim 1, characterized in that, the edge region of the sub-mask layer at least includes a plurality of defective sub-mask patterns.

8. A patterned mask layer formed by using the method for forming a patterned mask layer according to any one of claims 1 to 7, characterized in that, comprising: a plurality of sub-mask patterns distributed in an array; wherein, the size of the sub-mask pattern is smaller than the size of the active region to be formed; sidewalls located on the sidewall surfaces of the sub-mask patterns.

9. The patterned mask layer according to claim 8, characterized in that, the sub-mask patterns are arranged in parallel.

10. The patterned mask layer according to claim 8, characterized in that, the shapes and sizes of the respective sub-mask patterns are the same.

11. A method for forming a memory, characterized in that, comprising: using the method for forming a patterned mask layer according to any one of claims 1 to 7 to form a patterned mask layer on a substrate surface, the patterned mask layer including a plurality of sub-mask patterns arranged in an array, and sidewalls being provided on the sidewall surfaces of the sub-mask patterns; using the patterned mask layer as a mask to etch the substrate to form a plurality of active regions arranged in an array within the substrate.

12. The method for forming a memory according to claim 11, wherein, the active regions are arranged in parallel.

13. The method for forming a memory according to claim 11, wherein, the shapes and sizes of the active regions are the same.

14. A memory, wherein, comprising: a substrate, in which a plurality of active regions arranged in an array are formed; the active regions are formed by etching the substrate using the patterned mask layer according to any one of claims 8 to 10 as a mask.

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