A thyristor chip, a thyristor and a manufacturing method thereof

Abstract

The present invention discloses a thyristor chip and a manufacturing method, wherein the chip comprises an N-type base region and a P-type base region located on an anode P-type layer; a cathode N-type region located on the upper surface of the P-type base region; a cathode metal located on the cathode emitter N-type region; an amplifying gate metal and a center gate metal located on the surface of the P-type base region; a dielectric film layer of a specified thickness located between the gate cathode metal; and an anode metal under the anode P-type layer. The present invention does not require changes to the mature thyristor design and process, does not affect the various parameters of the thyristor, can improve the ability to withstand di / dt, is conducive to improving the performance of the thyristor, and prolongs the service life.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a thyristor chip, a thyristor and a manufacturing method thereof. Background Art

[0002] Thyristor chip is a three-terminal four-layer semiconductor device, such as Figure 1 As shown, the three ends of the conventional thyristor are respectively an anode metal 31, a cathode metal 32, and a gate metal 33 (including an amplifying gate metal 34), and the four layers are respectively: an anode P-type layer 35 of a deep diffusion layer, a low-resistance N-type base region 36, a P-type base region 37 of a deep diffusion layer, and a high-concentration cathode N-type region 38 diffused to form an ohmic contact metal electrode on the anode P-type layer 35 and the cathode N-type region 38 as the anode and cathode terminals respectively, and an ohmic contact metal electrode is led out from the P-type base region 37 as the gate.

[0003] The rate of rise of the on-state current of the thyristor, di / dt, refers to the maximum rate of rise of the on-state current that the thyristor can withstand and will not cause damage to the thyristor when the thyristor changes from blocking to conducting. That is, at the moment when the thyristor is triggered to conduct, if the rate of increase of the anode current (di / dt) is too large, even if the current value does not exceed the rated value of the component, the internal current of the thyristor will not have time to expand to the PN junction surface and burn out due to excessive current density. Therefore, when using thyristors, the current rise rate of the circuit cannot be greater than the rate of rise of the on-state current of the thyristor, di / dt, otherwise the thyristor will be damaged.

[0004] The turn-on process of thyristors includes three stages: delay, rise, and expansion. In the delay stage, the voltage on the device is high, but the current is small, so the instantaneous power is small; in the rise stage, the voltage across the device drops rapidly, the current rises sharply, and the instantaneous power is maximum; in the expansion stage, the voltage drops slowly, and the current is basically maintained at a stable current value, and its instantaneous power is much smaller than that in the rise stage. Because the conduction current in the rise stage is concentrated in the initial conduction area, the higher the di / dt, the earlier the peak of the instantaneous power is, and the more concentrated it is on the smaller initial conduction area.

[0005] The di / dt that a thyristor can withstand is related not only to the size and expansion speed of the initial conduction area, but also to the heat capacity of the conduction area. Since silicon has a small specific heat, a small heat capacity, and a low thermal conductivity (148W / mk), at the extreme of the rise, most of the heat generated by the current is concentrated in the conduction area, and only a small amount of heat can be transferred out, causing the temperature of the conduction area to rise rapidly. When the temperature reaches a certain critical value, the hot carriers have exceeded the injected carriers, which leads to thermal feedback. The larger the current, the higher the temperature, and the lower the body resistance of the conduction area. At this time, a larger current will flow through the area, so that the temperature will rise further. In this cycle, the current will be concentrated at a certain point with the highest temperature in a short time, forming a hot spot, which will make the device unable to work normally or even burn out. According to relevant literature, the damage temperature caused by the di / dt failure of the opening is in the range of 1100℃ to 1300℃. This temperature is only slightly lower than the melting point of silicon (1415°C), or the temperature caused by the fault far exceeds the melting point of the metal-semiconductor contact, causing the device to burn out in a very short time. The usual phenomenon of di / dt damage is a small but obvious hole burned near the gate.

[0006] The existing methods of improving the di / dt of thyristors include: strong triggering to increase the expansion speed; measures to improve the design of photolithography patterns to increase the length of the initial conduction line; measures to improve the crystal orientation, cross-sectional resistivity uniformity, and residual minority carrier lifetime of single crystal materials; design issues to coordinate di / dt and dv / dt, etc. There are also methods that use thermal conductive paste to cover the silicon between the gate cathode electrodes and other measures to effectively improve the di / dt capability of thyristors. .

[0007] Improving the ability of thyristors to withstand di / dt without changing the mature thyristor design and process and without affecting the various performance parameters of the thyristors has always been a technical problem that technical personnel in the field want to solve. Therefore, a new structure and manufacturing method that can improve the thyristor's ability to withstand di / dt without greatly increasing the cost is needed. Summary of the invention

[0008] The present invention solves the technical problem of the di / dt tolerance of the thyristor without affecting various performance parameters of the thyristor, improves the di / dt tolerance of the thyristor, enhances the electrical performance of the thyristor, and prolongs the service life.

[0009] The present invention provides a thyristor chip, characterized by comprising:

[0010] An N-type base region located above the anode P-type layer, and a P-type base region located above the N-type base region;

[0011] a cathode N-type region located in a partial area of ​​the P-type base region and having an upper surface flush with the upper surface of the P-type base region, wherein the cathode N-type region includes a cathode emitter N-type region and a gate N-type region closer to the center of the chip in a direction parallel to the surface of the P-type base region;

[0012] A cathode metal located above the cathode emission N-type region and exposing a portion of the upper surface of the cathode emission N-type region;

[0013] an amplified gate metal located on the surface of the P-type base region and in contact with both the P-type base region and the gate N-type region, and a central gate metal located on the upper surface of the P-type base region and not in contact with the gate N-type region;

[0014] A dielectric film layer of a specified thickness located on the P-type base region not covered by the cathode metal, the amplification gate metal and the center gate metal;

[0015] In an embodiment of the present invention,

[0016] The amplifying gate metal and the cathode metal have the same thickness, and the dielectric film layer has a thickness much smaller than that of the amplifying gate metal and the cathode metal.

[0017] In an embodiment of the present invention,

[0018] The specified thickness of the dielectric thin film layer is set to 20-500 nm.

[0019] The total thickness of the chip is set to 1.2 mm;

[0020] The thickness of the amplifying gate metal and the cathode metal is set to 30 μm;

[0021] The carrier concentration of the N-type base region is set to 10 13 cm -3 ;

[0022] The anode P-type layer and the P-type base region are doped with aluminum, and the carrier concentration is set to 10 14 cm -3 ~ 10 16 cm -3 ;

[0023] The cathode N-type region is doped with phosphorus, and the carrier concentration is set to 10 19 cm -3 ;

[0024] The dielectric film layer includes a DLC film and an aluminum nitride film;

[0025] The anode metal, cathode metal and gate metal are made of aluminum.

[0026] The present invention provides a thyristor, characterized in that:

[0027] A thyristor chip comprising any of the above.

[0028] The present invention provides a method for manufacturing a thyristor chip, which is characterized by comprising the following steps:

[0029] Simultaneously forming an anode P-type layer and a P-type base region on the lower surface and upper surface of the N-type substrate respectively;

[0030] Forming a cathode N-type region in a partial region of the P-type base region, the upper surface of which is flush with the upper surface of the P-type base region, wherein the cathode N-type region includes a cathode emitter N-type region and a gate N-type region;

[0031] Synchronously forming ohmic contact electrode metals on the cathode emitter N-type region, the P-type base region, the gate N-type region and under the anode P-type layer, wherein a cathode metal exposing a portion of the upper surface of the cathode emitter N-type region is formed on the cathode emitter N-type region, an amplified gate metal contacting both the P-type base region and the gate N-type region is formed on the surface of the P-type base region, a central gate metal not contacting the gate N-type region is formed on the upper surface of the P-type base region, and an anode metal is formed under the anode P-type layer;

[0032] A first dielectric film layer of a specified thickness is formed on the amplification gate metal by a deposition process.

[0033] In an embodiment of the present invention,

[0034] The deposition process includes chemical vapor deposition process, physical vapor deposition process, ion beam deposition process, filtered vacuum cathode arc process, pulsed laser deposition process, magnetron sputtering process, wherein the chemical vapor deposition process includes PECVD process;

[0035] The amplifying gate metal and the cathode metal have the same thickness, the dielectric film layer has a thickness much smaller than that of the amplifying gate metal and the cathode metal, and the dielectric film layer includes a DLC film and an aluminum nitride film.

[0036] In an embodiment of the present invention,

[0037] The specified thickness of the dielectric thin film layer is set to 20 to 500 nm;

[0038] The PECVD process parameters for depositing the DLC film include the following settings:

[0039] The vacuum pressure of the deposition chamber was set to 10 -6 Pa;

[0040] The alkane gas flow rate range is set to 0-500 sccm;

[0041] The pressure range in the deposition chamber is set to 0-66.5 Pa;

[0042] The RF source was set to 13.56 MHz;

[0043] The deposition process time range is set to 3 to 10 minutes;

[0044] The chip temperature is kept constant during the deposition process, and the chip temperature is ≤300° C. during the deposition process.

[0045] The present invention provides a method for manufacturing a thyristor, including the method for manufacturing a thyristor chip according to any one of the above.

[0046] Compared with the prior art, one or more embodiments of the present invention may have the following advantages:

[0047] The present invention applies DLC (diamond-like carbon) thin film material to the structure of the thyristor chip. Since DLC is a very good heat dissipation material, the heat dissipation capacity near the gate is improved. There is no need to change the mature thyristor design and process, and the parameters of the thyristor are not affected. The ability of thyristors of various types, sizes and structures to withstand di / dt can be improved, which is beneficial to improving the performance of the thyristor and extending the service life.

[0048] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0050] Figure 1 This is a schematic diagram of the structure of a traditional thyristor chip;

[0051] Figure 2 This is a schematic diagram of the gate and cathode structure in a traditional thyristor chip;

[0052] Figure 3 is a schematic diagram of the structure of a thyristor chip according to an embodiment of the present invention;

[0053] Figure 4 is a schematic flow chart of a method for manufacturing a thyristor chip according to an embodiment of the present invention;

[0054] Figure 5-Figure 6 is a schematic diagram of the structure of a thyristor chip for performing step 3 according to an embodiment of the present invention;

[0055] Figure 7 is a schematic diagram of the structure of a thyristor chip for performing step 4 according to an embodiment of the present invention;

[0056] Figure 8 Schematic diagram of a PEVCD process according to an embodiment of the present invention. DETAILED DESCRIPTION

[0057] In order to make the purpose, technical solution and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings, so that the implementation process of how the present invention applies technical means to solve technical problems and achieve technical effects can be fully understood and implemented accordingly. It should be noted that as long as there is no conflict, the various embodiments of the present invention and the various features in the embodiments can be combined with each other, and the technical solutions formed are all within the protection scope of the present invention.

[0058] First embodiment

[0059] Figure 2 This is a schematic diagram of the gate and cathode structure in a traditional thyristor chip;

[0060] Figure 3 It is a schematic diagram of the structure of a thyristor chip according to an embodiment of the present invention.

[0061] like Figure 3 As shown, this embodiment provides a thyristor chip, including: an anode metal 31 (not shown), a cathode metal 32, a center gate metal 33, an amplifying gate metal 34, an anode P-type layer 35, an N-type base region 36, a P-type base region 37, a cathode N-type region 38 (including a cathode emitter N-type region 381 and a gate N-type region 382), and a DLC film layer 391.

[0062] Diamond like carbon (DLC) film is a metastable type of amorphous carbon film containing a certain amount of diamond bonds (sp3). The main component of the film is carbon, in which the carbon atoms are bonded by covalent bonds. It has excellent properties such as high infrared transmittance, high hardness, low friction coefficient, high corrosion resistance, high resistivity, high thermal conductivity, and high chemical stability. It has many applications in the field of power semiconductor chip manufacturing.

[0063] This embodiment provides a thyristor chip, including:

[0064] An N-type base region 36 located on the anode P-type layer 35, and a P-type base region 37 located on the N-type base region 36;

[0065] A cathode N-type region 38 located in a partial region of the P-type base region 37 and having an upper surface flush with the upper surface of the P-type base region 37 , wherein the cathode N-type region 38 includes a cathode emitter N-type region 381 and a gate N-type region 382 ;

[0066] A cathode metal 32 located on the cathode emission N-type region 381 and partially exposing the upper surface of the cathode emission N-type region 381;

[0067] an enlarged gate metal 34 located on the upper surface of the P-type base region 37 and in contact with both the P-type base region 37 and the gate N-type region 382 , and a central gate metal 33 located on the surface of the P-type base region 37 and not in contact with the gate N-type region 382 ;

[0068] A DLC film layer 391 with a specified thickness located on the P-type base region 37 not covered by the cathode metal 32, the amplified gate metal 34 and the central gate metal 33;

[0069] and the anode metal 31 below the anode P-type layer 35 .

[0070] Specifically, the four layers of the thyristor chip of this embodiment are all made of semiconductor material silicon, and the total thickness of the thyristor chip is set to 1.2 mm. An N-type base region 36 is set on the anode P-type layer 35, and a P-type base region 37 is set on the N-type base region 36; a cathode N-type region 38 that does not completely cover the P-type base region 37 is set on the upper surface of the P-type base region 37, wherein the cathode N-type region 38 includes a cathode emitter N-type region 381 and a gate N-type region 382 that is closer to the center of the chip in a direction parallel to the surface of the P-type base region 37;

[0071] The anode P-type layer 35 and the P-type base region 37 are doped with aluminum, and the carrier concentration is set to 10 14 cm -3 ~ 10 16 cm -3 ; The carrier concentration of the N-type base region 36 is set to 10 13 cm -3 ; The cathode N-type region 38 is doped with phosphorus, and the carrier concentration is set to 10 19 cm -3 ;

[0072] A cathode metal 32 which does not completely cover the cathode emitter N-type region 381 is arranged on the cathode emitter N-type region 381, an amplified gate metal 34 which is in contact with both the P-type base region 37 and the gate N-type region 382 is arranged on the upper surface of the P-type base region 37, and a central gate metal 33 which is not in contact with the gate N-type region 382 is arranged on the surface of the P-type base region 37, the amplified gate metal 34 and the cathode metal 32 have the same thickness, and the thickness of the amplified gate metal and the cathode metal is set to 30μm, and an anode metal 31 is arranged under the anode P-type layer 35, and the anode metal, cathode metal and gate metal are all made of aluminum.

[0073] A dielectric film layer 391 of a specified thickness is also provided on the upper surface of the P-type base region 37 not covered by the cathode metal 32, the amplification gate metal 34 and the center gate metal 33. The specified thickness of the dielectric film layer 391 is set to 20 to 500 nm, and the dielectric film layer includes a DLC film and an aluminum nitride film.

[0074] In this embodiment, a layer of DLC (diamond-like carbon) film is deposited on the amplifying gate metal 34. The DLC film is a very good thermal conductive material with an ultra-high thermal conductivity (>900W / m·k), and the thickness is set to be nanometers. It can conduct away the heat near the gate when the thyristor is turned on, reduce the temperature of the initial conduction area, and improve the ability of the thyristor to withstand high di / dt. At the same time, the DLC film is also a very good insulating dielectric material with a very high resistivity (>10 7 Ω﹒ ㎝), with a thickness of 20 to 500nm, and will not affect other parameter characteristics and packaging structure of the thyristor. The present invention can improve the heat dissipation capacity near the gate mentioned in the background technology, conduct the heat in the chip to the outside of the chip as soon as possible through heat conduction, and improve the ability of the thyristor to withstand di / dt, without changing the mature thyristor design and process, and without affecting the various parameters of the thyristor, which is conducive to improving the performance of the thyristor and extending the service life.

[0075] In summary, one or more embodiments of the present invention have the following advantages:

[0076] The present invention applies DLC (diamond-like carbon) thin film material to the structure of the thyristor chip. Since DLC is a very good heat dissipation material, the heat dissipation capacity near the gate is greatly improved without changing the mature thyristor design and process and without affecting the various parameters of the thyristor. The ability of thyristors of various types, sizes and structures to withstand di / dt can be improved, which is beneficial to improving the performance of the thyristor and extending the service life.

[0077] Second embodiment

[0078] This embodiment provides a thyristor, including a thyristor chip with any structure in the above first embodiment, and has the advantages of the first embodiment.

[0079] Third embodiment

[0080] Figure 2 is a schematic diagram of the structure of a thyristor chip according to an embodiment of the present invention;

[0081] Figure 4 is a schematic flow chart of a method for manufacturing a thyristor chip according to an embodiment of the present invention;

[0082] Figure 5 is a schematic diagram of the structure of a thyristor chip for performing step 3 according to an embodiment of the present invention;

[0083] Figure 6 , Figure 7 is a schematic diagram of the structure of a thyristor chip for performing step 4 according to an embodiment of the present invention;

[0084] Figure 8 Schematic diagram of a PEVCD process according to an embodiment of the present invention.

[0085] like Figure 2 As shown, a thyristor chip is manufactured by a thyristor chip manufacturing method provided by this embodiment, including: an anode metal 31, a cathode metal 32, a center gate metal 33, an amplifying gate metal 34, an anode P-type layer 35, an N-type base region 36, a P-type base region 37, a cathode N-type region 38 (including a cathode emitter N-type region 381 and a gate N-type region 382), and a DLC film layer 391.

[0086] This embodiment provides a method for manufacturing a thyristor chip, comprising the following steps:

[0087] Step 1: synchronously forming an anode P-type layer 35 and a P-type base region 37 on the lower surface and upper surface of an N-type substrate respectively.

[0088] Step 2, forming a cathode N-type region 38 whose upper surface is flush with the upper surface of the P-type base region 37 in a partial area of ​​the P-type base region 37, wherein the cathode N-type region 38 includes a cathode emitter N-type region 381 and a gate N-type region 382 that is closer to the center of the chip in a direction parallel to the surface of the P-type base region 37.

[0089] Specifically, after the upper surface of the P-type base region 37 is photolithographically processed, ions are injected at the corresponding position to form a cathode N-type region 38 that does not completely cover the P-type base region 37, wherein the cathode N-type region 38 includes a cathode emitter N-type region 381 and a gate N-type region 382 that is closer to the center of the chip in a direction parallel to the surface of the P-type base region 37.

[0090] Step 3, simultaneously forming ohmic contact electrode metals on the cathode emitter N-type region 381, the P-type base region 37, the gate N-type region 382 and under the anode P-type layer 35, wherein a cathode metal 32 is formed on the cathode emitter N-type region 381 to expose a portion of the upper surface of the cathode emitter N-type region 381, and an amplified gate metal 34 is formed on the upper surface of the P-type base region 37 to contact both the P-type base region 37 and the gate N-type region 382, ​​and a central gate metal 33 is formed on the upper surface of the P-type base region 37 that is not in contact with the gate N-type region 382, ​​and an anode metal is formed under the anode P-type layer.

[0091] Specifically, a metal layer is deposited on the upper surface of the P-type base region 37 of the thyristor silicon-based chip by an evaporation / sputtering process; a photoresist layer consistent with the target pattern is obtained on the metal layer by a photolithography process; the metal layer at a non-target position is removed by an etching method to obtain a metal layer of the target pattern, and the photoresist is removed, thereby obtaining a cathode metal 32 on the cathode emission N-type region 381 that does not completely cover the cathode emission N-type region 381, an amplifying gate metal 34 on the upper surface of the P-type base region 37 that contacts the P-type base region 37 and the gate N-type region 382, ​​and a central gate metal 33 on the upper surface of the P-type base region 37 that does not contact the gate N-type region 382, ​​as shown in FIG. Figure 5 As shown, the gate metal 34 and the cathode metal 32 have the same thickness. While the metal layer is formed on the upper surface of the P-type base region 37, the anode metal 31 is also deposited under the anode P-type layer 35.

[0092] Step 4: a dielectric film layer 391 of a specified thickness is further disposed on the upper surface of the P-type base region 37 not covered by the cathode metal 32 , the amplifying gate metal 34 and the central gate metal 33 .

[0093] Specifically, firstly, photoresist is coated on the surface of the amplified gate metal 34, the central gate metal 33, the cathode metal 32 and the P-type base region 37 not covered by the metal. Figure 6 As shown, a dielectric film 39 of a specified thickness is deposited on the photoresist and on the upper surface of the P-type base region 37 not covered by the cathode metal 32, the amplifying gate metal 34 and the center gate metal 33 by a PECVD process, as shown in FIG. Figure 7 As shown, the photoresist is removed to form Figure 2 The thyristor chip structure shown in the figure. The thickness of the dielectric film layer is much smaller than the thickness of the amplifying gate metal and the cathode metal, and the dielectric film layer includes a DLC film and an aluminum nitride film.

[0094] like Figure 8 As shown in the figure, the PECVD process places the thyristor chip on which the DLC film is to be deposited on a heating plate and evacuates the vacuum pressure in the deposition chamber to 10 -6Pa; the alkane gas flow rate is set to 0-500sccm and sprayed into the cavity; the pressure in the cavity is automatically adjusted to 0-500mTorr, i.e., 0-66.5Pa, by the vacuum regulating valve; the alkane gas sprayed into the cavity is decomposed into C n H m+ ; The RF power supply is applied to both ends of the parallel plate capacitor, the heating plate is used as the cathode and grounded, the deposition chamber wall is used as the anode, and the areas of the positive and negative plates are different; the movement speeds of ions and electrons in the plasma are different under the excitation of the RF source, and the different areas of the plates cause a negative bias voltage of 200 to 1000 V between the plates, C n H m+ Under the action of negative bias, the substrate material is bombarded at high speed, and a DLC film with a thickness of about 20 to 500 nm is obtained in a deposition process time of 3 to 10 minutes. The temperature of the heating plate is set to remain constant during the deposition process, and the chip temperature is set to no more than 300°C during the deposition process. If the temperature is too high, the deposited diamond structure (sp 3 ) to graphite structure (sp 2 )change.

[0095] The deposition process also includes a chemical vapor deposition process, a physical vapor deposition process, an ion beam deposition process, a filtered vacuum cathode arc process, a pulsed laser deposition process, and a magnetron sputtering process, wherein the chemical vapor deposition process includes a PECVD process.

[0096] In summary, this embodiment has the following advantages:

[0097] Through the manufacturing method of this embodiment, DLC (diamond-like carbon) thin film material is applied to the structure of the thyristor chip. Since DLC is a very good heat dissipation material, the heat dissipation capacity near the gate is greatly improved without changing the mature thyristor design and process, and without affecting the various parameters of the thyristor. The ability of thyristors of various types, sizes, and structures to withstand di / dt can be improved, which is beneficial to improving the performance of the thyristor and extending the service life.

[0098] Fourth embodiment

[0099] This embodiment provides a method for manufacturing a thyristor, including the method for manufacturing a thyristor chip in the third embodiment, and the advantages are as described in the third embodiment.

[0100] Although the embodiments disclosed in the present invention are as above, the contents described are only embodiments adopted for facilitating the understanding of the present invention, and are not intended to limit the present invention. Any technician in the technical field of the present invention can make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in the present invention. The protection scope of the present invention is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A thyristor chip, characterized in that: include: An N-type base region located above the anode P-type layer, and a P-type base region located above the N-type base region; a cathode N-type region located in a partial area of ​​the P-type base region and having an upper surface flush with the upper surface of the P-type base region, wherein the cathode N-type region includes a cathode emitter N-type region and a gate N-type region closer to the center of the chip in a direction parallel to the surface of the P-type base region; A cathode metal located above the cathode emission N-type region and exposing a portion of the upper surface of the cathode emission N-type region; an amplified gate metal located on the surface of the P-type base region and in contact with both the P-type base region and the gate N-type region, and a central gate metal located on the upper surface of the P-type base region and not in contact with the gate N-type region; A dielectric film layer of a specified thickness located on the P-type base region not covered by the cathode metal, the amplifying gate metal and the center gate metal; the thickness of the dielectric film layer is much smaller than the thickness of the amplifying gate metal and the cathode metal; the specified thickness of the dielectric film layer is set to 20 to 500 nm; the dielectric film layer includes a DLC film; and the anode metal under the anode P-type layer; the anode P-type layer, the N-type base region, the P-type base region and the cathode N-type region are all made of semiconductor material silicon.

2. The thyristor chip according to claim 1, characterized in that: The amplifying gate metal and the cathode metal have the same thickness.

3. The thyristor chip according to claim 2, characterized in that: The total thickness of the chip is set to 1.2 mm; The thickness of the amplifying gate metal and the cathode metal is set to 30 μm.

4. The thyristor chip according to claim 3, characterized in that: The carrier concentration of the N-type base region is set to 10 13 cm -3 ; The anode P-type layer and the P-type base region are doped with aluminum, and the carrier concentration is set to 10 14 cm -3 ~10 16 cm -3 ; The cathode N-type region is doped with phosphorus, and the carrier concentration is set to 10 19 cm -3 .

5. The thyristor chip according to claim 2, characterized in that: The anode metal, cathode metal and gate metal are made of aluminum.

6. A thyristor, characterized in that: A thyristor chip comprising any one of claims 1 to 5.

7. A method for manufacturing a thyristor chip, characterized in that: The following steps are involved: Simultaneously forming an anode P-type layer and a P-type base region on the lower surface and upper surface of the N-type substrate respectively; Forming a cathode N-type region in a partial region of the P-type base region, the upper surface of which is flush with the upper surface of the P-type base region, wherein the cathode N-type region includes a cathode emitter N-type region and a gate N-type region; Synchronously forming ohmic contact electrode metals on the cathode emitter N-type region, the P-type base region, the gate N-type region and under the anode P-type layer, wherein a cathode metal exposing a portion of the upper surface of the cathode emitter N-type region is formed on the cathode emitter N-type region, an amplified gate metal contacting both the P-type base region and the gate N-type region is formed on the surface of the P-type base region, a central gate metal not contacting the gate N-type region is formed on the upper surface of the P-type base region, and an anode metal is formed under the anode P-type layer; Forming a dielectric film layer of a specified thickness on the upper surface of the P-type base region not covered by the cathode metal, the amplifying gate metal and the center gate metal, wherein the thickness of the dielectric film layer is much smaller than the thickness of the amplifying gate metal and the cathode metal; The specified thickness of the dielectric film layer is set to 20-500 nm; the dielectric film layer includes a DLC film; the anode P-type layer, the N-type substrate, the P-type base region and the cathode N-type region are all made of semiconductor material silicon.

8. The method according to claim 7, characterized in that The deposition process includes chemical vapor deposition process, physical vapor deposition process, ion beam deposition process, filtered vacuum cathode arc process, pulsed laser deposition process, and magnetron sputtering process, wherein the chemical vapor deposition process includes PECVD process; The amplifying gate metal and the cathode metal have the same thickness.

9. The method according to claim 8, It is characterized in that in, The PECVD process parameters for depositing the DLC film include the following settings: The vacuum pressure of the deposition chamber was set to 10 -6 Pa; The alkane gas flow rate range is set to 0-500 sccm; The pressure range in the deposition chamber is set to 0-66.5 Pa; The RF source was set to 13.56 MHz; The deposition process time range is set to 3 to 10 minutes; The chip temperature is kept constant during the deposition process, and the chip temperature is ≤300° C. during the deposition process.

10. A method for manufacturing a thyristor, characterized in that: A method for manufacturing a thyristor chip comprising the steps of any one of claims 7 to 9.

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