LED chip system-level packaging structure and packaging method

Abstract

The present invention provides a system-level packaging structure and method for an LED chip, wherein the packaging structure comprises: a heat sink structure, a first chip, a first packaging layer, a second packaging layer, a rewiring layer, an LED chip, a PCB board, and a third packaging layer. The present invention adopts a fan-out system-level packaging to integrate chips with multiple functions, including a first chip (such as an ASIC chip), an LED chip, etc., into a packaging structure, which can realize a variety of different system function requirements and improve the performance of the packaging system. The electrical connection between the first chip, the LED chip, and the PCB board is realized through the rewiring layer, the metal connecting column, and the metal lead, etc., and a three-dimensional vertical stacking packaging is realized, which effectively reduces the area of ​​the packaging system and improves the integration of the packaging system. The packaging and protection between the chips are realized through the first packaging layer, the second packaging layer, and the third packaging layer, and a packaging structure with good performance and stability is obtained.

Description

Technical Field

[0001] The invention belongs to the field of chip packaging, and in particular relates to a LED chip system-level packaging structure and a packaging method. Background Art

[0002] With the advent of the 5G communication and artificial intelligence (AI) era, the amount of data that chips used in such related fields need to transmit and process at high speed is very huge. Such chips usually have a huge number of pad pins (hundreds or even thousands), ultra-fine pin size and spacing (a few microns or even smaller). On the other hand, the demand for mobile Internet and the Internet of Things is becoming stronger and stronger, and the miniaturization and multi-functionality of electronic terminal products have become a major trend in industrial development. How to integrate and package multiple high-density chips of different types together to form a powerful system or subsystem with relatively small volume and power consumption has become a major challenge in the field of advanced packaging of semiconductor chips.

[0003] At present, for multi-chip integrated packaging of such high-density chips, the industry usually adopts methods such as through silicon vias (TSV) and silicon interposers to lead out and effectively interconnect the ultra-fine pins of the chip to form a functional module or system, but the cost of this technology is relatively high, which greatly limits its scope of application. Fan-out packaging technology uses the method of reconstructing wafers and rewiring RDL to provide a good platform for realizing multi-chip integrated packaging. However, due to the limited wiring accuracy in the existing fan-out packaging technology, the area and thickness of the package body are large, and there are many problems such as numerous processes and low reliability. In addition, the existing LED chip packaging structure is generally COB packaging, which mostly adopts chip-level packaging structure. This packaging method has the advantages of low cost and simple structure, but its connection method is easy to break. As the chip size decreases, it is difficult to effectively integrate with other integrated circuit chips. With the increasing demand for packaging components and functions, the existing system-level packaging will occupy an increasingly large area and thickness, which is not conducive to the improvement of integration.

[0004] Therefore, it is necessary to propose a new system-level LED chip packaging structure and a preparation method thereof to solve the above problems. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a LED chip system-level packaging structure and packaging method to solve the problems of the prior art that the system-level packaging volume is difficult to reduce and the LED chip is effectively packaged.

[0006] To achieve the above-mentioned object and other related objects, the present invention provides a system-level packaging method for LED chips, the packaging method comprising the following steps:

[0007] Providing a chip wafer having a first surface and a second surface opposite to each other, wherein the chip wafer includes a plurality of first chips;

[0008] forming a plurality of connection pillar structures on the first surface of the chip wafer to electrically lead out the first chip;

[0009] forming a first packaging layer on the first surface of the chip wafer, wherein the first packaging layer covers the connecting pillar structure;

[0010] Cutting the chip wafer to form a plurality of first chip initial packaging structures, including the first chip, a connecting column structure located on the first chip, and the first packaging layer covering the connecting column structure;

[0011] Providing a supporting substrate, forming a separation layer on the supporting substrate, and forming the second surface of the first chip initial packaging structure on the separation layer;

[0012] forming a second packaging layer on the separation layer, wherein the second packaging layer covers the initial packaging structure of the first chip, and thinning the second packaging layer until the connecting column structure is exposed;

[0013] Preparing a rewiring layer on the second packaging layer, wherein the rewiring layer is electrically connected to the connecting pillar structure;

[0014] Based on the separation layer, the support substrate is peeled off to expose the second surface of the first chip initial packaging structure, and the first chip intermediate packaging structure is obtained by cutting.

[0015] Providing an LED chip, and forming the LED chip on a side of the rewiring layer away from the initial packaging structure of the first chip, to obtain a chip combination packaging structure;

[0016] Forming the chip combination packaging structure on a heat sink structure, and electrically connecting the rewiring layer formed on one side of the LED chip to a PCB board through metal wires; and

[0017] A third packaging layer is formed at least around the LED chip to obtain a LED chip system-level packaging structure.

[0018] Optionally, the packaging method further includes a step of forming a protective layer on the separation layer, wherein the first chip initial packaging structure is formed on the surface of the protective layer, and after peeling off the supporting substrate, the method further includes a step of removing the protective layer.

[0019] Optionally, an upper surface of the first encapsulation layer is higher than an upper surface of the connecting pillar structure; and an upper surface of the second encapsulation layer is higher than an upper surface of the first encapsulation layer.

[0020] Optionally, the LED chip is electrically connected via a plurality of metal bumps formed on the rewiring layer, and the third encapsulation layer is also formed between the metal bumps at the bottom of the LED chip.

[0021] Optionally, the PCB board is formed on the heat sink structure and is located at a side of the chip combination packaging structure, and the third packaging layer is also formed above the PCB board and the rewiring layer and covers the metal leads.

[0022] Optionally, a thermal adhesive layer is formed between the chip combination packaging structure and the heat sink structure.

[0023] Optionally, the first chip includes an ASIC chip.

[0024] The present invention further provides a system-level packaging structure for an LED chip, wherein the LED chip system-level packaging structure preferably adopts the packaging method of the present invention, and of course, other packaging methods may also be adopted. The packaging structure comprises:

[0025] Heat sink structure;

[0026] A first chip formed on the heat sink structure;

[0027] A connecting column structure is formed on the first chip to electrically lead out the first chip;

[0028] A first packaging layer is formed on the first chip, the first packaging layer covers the connecting column structure, and the first chip, the connecting column structure and the first packaging layer constitute an initial packaging structure of the first chip;

[0029] A second packaging layer is formed on the heat sink structure and covers the first chip initial packaging structure;

[0030] a rewiring layer, formed on the second packaging layer and the first chip initial packaging structure, the rewiring layer being electrically connected to the connection column structure;

[0031] An LED chip is formed on a side of the rewiring layer away from the initial packaging structure of the first chip;

[0032] A PCB board, the PCB board being electrically connected to the rewiring layer formed on one side of the LED chip through metal leads; and

[0033] The third packaging layer is formed at least around the LED chip.

[0034] Optionally, the upper surface of the first packaging layer is flush with the upper surface of the second packaging layer and the connecting column structure is exposed; a plurality of metal bumps are formed between the LED chip and the rewiring layer to achieve electrical connection between the LED chip and the rewiring layer, and the third packaging layer is also formed between the metal bumps at the bottom of the LED chip.

[0035] Optionally, the PCB board is formed on the heat sink structure and is located at a side of the chip combination packaging structure, and the third packaging layer is also formed above the PCB board and the rewiring layer and covers the metal leads.

[0036] Optionally, a thermal adhesive layer is formed between the chip combination packaging structure and the heat sink structure.

[0037] Optionally, the first chip includes an ASIC chip.

[0038] As described above, the LED chip system-level packaging structure and packaging method of the present invention use fan-out system-level packaging to integrate chips with multiple functions, such as LED chips, ASIC chips, etc., into one packaging structure, which can meet a variety of different system function requirements and improve the performance of the packaging system. Through the rewiring layer and the metal connecting column, a three-dimensional vertical stacking package is realized, which effectively reduces the area of ​​the packaging system and improves the integration of the packaging system. Through the rewiring layer, the metal connecting column and the metal lead, etc., the electrical connection between the first chip (such as the ASIC chip), the LED chip and the PCB board is achieved, and the close connection between the rewiring layers is achieved, which can effectively shorten the conduction path between the chips and reduce the power consumption of the packaging system. The first packaging layer, the second packaging layer and the third packaging layer are used to achieve packaging and protection between the chips, and a packaging structure with beneficial performance and stability is obtained. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 Shown is a process flow chart of the preparation of the LED chip system-level packaging of the present invention.

[0040] Figure 2-18 It shows a schematic diagram of the structure presented in each step of the LED chip system-level packaging manufacturing method of the present invention.

[0041] Component number description

[0042] 100 Chip Wafer

[0043] 100a First Chip

[0044] 101 Connecting column structure

[0045] 102 First packaging layer

[0046] 103 First Chip Initial Packaging Structure

[0047] 104 First packaging layer on first chip

[0048] 105 Support substrate

[0049] 106 Separation Layer

[0050] 107 protective layer

[0051] 108 Die Attach Film

[0052] 109 Second packaging layer

[0053] 110 Rewiring Layer

[0054] 111 LED Chip

[0055] 112 metal bumps

[0056] 113 Heat sink structure

[0057] 114 Thermal adhesive layer

[0058] 115 PCB board

[0059] 116 Metal lead

[0060] 117 Third packaging layer

[0061] Steps S1 to S11 DETAILED DESCRIPTION

[0062] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0063] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0064] For ease of description, spatial relational terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship between an element or feature shown in the drawings and other elements or features. It will be understood that these spatial relational terms are intended to include other directions of the device in use or operation in addition to the directions depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can be one or more intervening layers. In addition, "between..." used in the present invention includes two endpoint values.

[0065] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0066] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0067] like Figure 1 As shown, the present invention provides a system-level packaging method for LED chips, the packaging method comprising the steps of:

[0068] First, if Figure 1 S1 and Figure 2 As shown, step S1 is performed to provide a chip wafer 100 having a first side and a second side relative to each other, wherein the chip wafer 100 includes a plurality of first chips 100a. As an example, the chip wafer 100 is an ASIC wafer, and the first chip 100a may be an ASIC chip, Application Specific Integrated Circuit. Among them, the first side of the chip wafer 100 is the first side of the first chip 100a, and the second side of the chip wafer 100 is the second side of the first chip 100a. Those skilled in the art can understand that the subsequent description can be based on this for corresponding description. In one example, the front side of the first chip is the first side, and the back side of the first chip is the second side.

[0069] Then, if Figure 1 S2 and Figure 3As shown, step S2 is performed to form a plurality of connecting pillar structures 101 on the first surface of the chip wafer 100 to electrically lead out the first chip 100a. The connecting pillar structure 101 can be a copper pillar. In one example, the step of forming a seed layer is also included before forming the connecting pillar structure 101. In one example, the connecting pillar structure 101 is electrically connected to the pad of the first chip 100a to electrically lead out the first chip. In one example, a process for forming the copper pillar is provided: an insulating layer is formed on a chip wafer, a through hole is formed in the insulating layer to expose the first chip pad, and then the connecting pillar structure 101 is made on the pad or seed layer by electroplating. During the electroplating process, the insulating layer can be used as a barrier layer, and the connecting pillar structure only grows at the through hole. In addition, the connecting pillar structure 101 is made by electroplating to obtain a connecting pillar structure with a larger width, for example, a width of 50 μm to 100 μm, such as 80 μm, or more than 100 μm, such as 120 μm, 150 μm, which can greatly improve its conduction capacity. The connecting pillar structure 101 can be arranged vertically to shorten the conduction path. The connecting pillar structure 101 is one of Au, Ag, Cu, and Al. In this embodiment, the connecting pillar structure 101 can be copper to improve its stability and reduce impedance.

[0070] Then, if Figure 1 S3 and Figure 4 As shown, step S3 is performed to form a first packaging layer 102 on the first surface of the chip wafer 100, and the first packaging layer 102 covers the connecting column structure 101. The method for forming the first packaging layer 102 includes one of compression molding, transfer molding, liquid sealing molding, vacuum lamination and spin coating. The material of the packaging layer 102 includes one of polyimide (PI), silica gel and epoxy resin. In a preferred example, a PI material layer is selected, that is, PI coating (PI Coating) is performed to form the first packaging layer 102. In one example, in this step, the upper surface of the first packaging layer 102 is higher than the upper surface of the connecting column structure 101, so as to protect the chip.

[0071] Then, if Figure 1 S4 and Figure 5-6As shown, step S4 is performed to cut the chip wafer 100 to form a plurality of first chip initial packaging structures 103, including the first chip 100a, the connecting column structure 101 located on the first chip, and the first packaging layer covering the connecting column structure, that is, the first chip packaging layer 104. Through this step, the first chip initial packaging structure 103 is formed for subsequent chip bonding (die bonder). Among them, laser cutting can be used for cutting to obtain an independent packaging structure, which is beneficial to the protection of the chip and the packaging layer and meets the cutting requirements.

[0072] Then, if Figure 1 S5 and Figure 7-9 As shown, step S5 is performed to provide a support substrate 105 , form a separation layer 106 on the support substrate, and form the second surface of the first chip initial packaging structure 103 on the separation layer 106 .

[0073] As an example, the support substrate 105 includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate and a ceramic substrate. In this embodiment, the support substrate 105 is selected as a glass substrate, which has a low cost, is easy to form a separation layer 106 on its surface, and can reduce the difficulty of the subsequent stripping process.

[0074] As an example, the separation layer 106 includes a light-to-heat conversion layer (LTHC), which is formed on the support substrate 105 by a spin coating process and then solidified by a curing process. The light-to-heat conversion layer (LTHC) has stable performance and a smooth surface, which is conducive to the subsequent preparation of the rewiring layer, and in the subsequent stripping process, the stripping difficulty is relatively low.

[0075] In addition, the first chip initial packaging structure 103 prepared by the aforementioned steps is combined and formed on the separation layer 106, and the number and arrangement of the first chip initial packaging structure 103 can be set according to actual needs. In one example, the packaging method also includes the step of forming a protective layer 107 on the separation layer 106, wherein the first chip initial packaging structure 103 is formed on the surface of the protective layer 107, and after peeling off the supporting substrate, it also includes the step of removing the protective layer 107. The material of the protective layer 107 can be PI (polyimide) or epoxy (epoxy resin) material, which can be formed by spin coating. The protective layer 107 can protect the first chip to prevent damage to the system-level chip and the power management chip by corrosive gases, water vapor, etc.

[0076] In one example, the first chip initial packaging structure 103 can be directly bonded to the separation layer or protective layer using an insulating adhesive, such as directly bonding the first chip to the second surface, which is simple in process and can effectively reduce costs. Of course, other commonly used die attach films (DAF, die attach film) in the art can also be used to achieve the first chip bonding.

[0077] Then, if Figure 1 S6 and Figure 10-11 As shown, step S6 is performed to form a second packaging layer 109 (molding) on ​​the separation layer 106 , wherein the second packaging layer 109 covers the first chip initial packaging structure 103 , and the second packaging layer 109 is thinned to expose the connecting column structure 101 .

[0078] The second encapsulation layer 109 is formed by a method including compression molding, transfer molding, liquid sealing molding, vacuum lamination and spin coating, and the material of the second encapsulation layer 109 includes one of polyimide, silicone and epoxy resin. In one example, the upper surface of the second encapsulation layer 109 is higher than the height of the first encapsulation layer 102 in the structure encapsulated therein. Further, optionally, during the thinning process, the second encapsulation layer 109 and the first encapsulation layer 102 are thinned until the connecting column structure 101 is exposed. At this time, the upper surfaces of the second encapsulation layer 109 and the first encapsulation layer 102 are flush, and the first chip 100a is simultaneously covered by the second encapsulation layer 109 and the first encapsulation layer 102. It should be noted that the encapsulation layers before and after thinning are represented by the same name in this article, which can be understood by technicians in this field.

[0079] Then, if Figure 1 S7 and Fig.12 As shown, step S7 is performed to prepare a rewiring layer 110 on the second packaging layer 109, and the rewiring layer 110 is electrically connected to the connecting pillar structure 101, so as to realize the electrical lead-out of the first chip 100a. The rewiring layer 110 has a metal wiring layer, and the metal wiring layer is electrically connected to the connecting pillar structure 101, and the connecting pillar structure 101 is electrically connected to the first chip 100a.

[0080] As an example, making the rewiring layer 110 includes the steps of:

[0081] First, a first dielectric layer is formed on the surface of the second packaging layer and the first chip initial packaging structure by a chemical vapor deposition process or a physical vapor deposition process, and the material of the first dielectric layer includes one or a combination of two or more of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphorus silicon glass, and fluorine-containing glass. Preferably, the material of the first dielectric layer 201 is PI (polyimide) to further reduce the process difficulty and process cost.

[0082] Next, a first metal layer is formed on the surface of the first dielectric layer by sputtering, and the metal layer is etched to form a patterned first metal wiring layer. The material of the first metal wiring layer includes one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium.

[0083] Next, a second dielectric layer is formed on the surface of the patterned first metal wiring layer by a chemical vapor deposition process or a physical vapor deposition process, and the second dielectric layer is etched to form a second dielectric layer with patterned through holes. The material of the second dielectric layer includes one or a combination of two or more of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphorus silicon glass, and fluorine-containing glass. Preferably, the material of the second dielectric layer is PI (polyimide) to further reduce the process difficulty and process cost.

[0084] Next, a conductive plug is filled in the patterned through hole, and then a second metal layer is formed on the surface of the second dielectric layer by a sputtering process, and the metal layer is etched to form a patterned second metal wiring layer. The material of the second metal wiring layer includes one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium.

[0085] Finally, the above steps can be repeated to form a rewiring layer with a multi-layer stacked structure to achieve different wiring functions. For example, in this embodiment, the rewiring layer 110 also includes a patterned third dielectric layer, a patterned third metal wiring layer, a patterned fourth dielectric layer and a patterned fourth metal wiring layer.

[0086] Then, if Figure 1 S8 and Figure 13-15 As shown, step S8 is performed to peel off the support substrate 105 based on the separation layer 106, revealing the second surface of the first chip initial packaging structure 103, and cutting is performed to obtain a first chip intermediate packaging structure. In this embodiment, the light-to-heat conversion layer is irradiated with a laser to separate the light-to-heat conversion layer from the second packaging layer and the first chip initial packaging structure from the support substrate 105, thereby peeling off the support substrate.

[0087] In one example, when the protective layer 107 is formed, in this step, the protective layer 107 and the supporting substrate 105 are separated based on the separation layer 106. Further, after peeling off the supporting substrate 105, the protective layer 107 is removed. Further, when other material layers are formed on the second side (the back side in this embodiment) of the first chip 100a, the back side is thinned to remove the above-mentioned material layers to expose the back side of the first chip. In one example, the lower surface of the first chip is flush with the lower surface of the second packaging layer, where the upper and lower may refer to the upper and lower illustrated in the package. Of course, even if there are no other material layers on the back side of the chip, a thinning process may be performed in this step to provide a flat surface.

[0088] In addition, after thinning, the step of cutting the formed intermediate packaging structure of the first chip is also included to obtain the structure of the first chip required for subsequent packaging with the LED chip. During the cutting process, the packaging structure can be attached to the blue film and continued to be cut. In one example, the blue film can be removed after the cutting is completed. As an example, before the cutting, the step of placing the above-mentioned structure on the cutting blue film and fixing the cutting blue film on a fixing ring is also included, such as Fig.15 shown.

[0089] As an example, the material of the fixing ring includes one of glass, metal, semiconductor, polymer and ceramic. In the present embodiment, the material of the fixing ring is glass. When glass is used as the fixing ring, it is easier to tear off when it is subsequently separated from the cutting blue film, thereby improving the efficiency and stability of separation. The shape of the fixing ring can be circular, rectangular, or other desired shapes. The cutting blue film has a sticky side that is bonded and fixed to the fixing ring to fix the cutting blue film, prevent the occurrence of warping and the like, and improve stability.

[0090] Then, if Figure 1 S9 and Fig.16 As shown, step S9 is performed to provide an LED chip 111, and the LED chip 111 is formed on a side of the rewiring layer 110 away from the first chip initial packaging structure 103, and the LED chip 111 is electrically connected to the rewiring layer 110 to obtain a chip combination packaging structure. The electrical connection between the LED chip 111 and the first chip 100a (such as an ASIC chip) is achieved through the rewiring layer 110.

[0091] In one example, the LED chip 111 is electrically connected to the rewiring layer 110 through a plurality of metal bumps 112. In one example, the step of forming the metal bumps 112 on the surface of the rewiring layer 110 may be: first, a window is formed in the dielectric layer on the upper surface of the rewiring layer by laser, or a dielectric layer is re-formed on the surface of the rewiring layer, and then a window is formed in the dielectric layer, wherein the window reveals the metal layer in the rewiring layer, and then the metal bump is made in the window. For example, the metal bump 112 may be one of tin solder, silver solder and gold-tin alloy solder. In another example, the connecting solder ball (the metal bump) may be made by ball implantation and reflow process, and the material of the connecting solder ball may be tin or a tin-containing alloy, such as pure tin, tin-gold alloy, tin-lead alloy, etc. The arrangement and selection of the LED chip may be based on actual settings.

[0092] Then, if Figure 1 S10 and Fig.17 As shown, step S10 is performed to form the chip combination package structure on the heat sink structure 113, and the rewiring layer 110 formed with the side of the LED chip 111 is electrically connected to the PCB board 115 through the metal lead 116. In this step, the electrical connection between the LED chip 111, the first chip 100a and the PCB board 115 is realized through the metal lead 116, and the electrical lead-out method can be realized based on the rewiring layer. In addition, the connection between the metal lead 116 and the rewiring layer 110 and the PCB board can adopt the existing process.

[0093] As an example, the material of the heat sink structure 113 may be copper, or other commonly used heat sinks.

[0094] As an example, a thermal adhesive layer 114 is formed between the chip combination packaging structure and the heat sink structure 113, for example, it can be a reactive hot melt adhesive "Hi-PURSHOT", commonly known as PUR, or other hot melt adhesive commonly used in the art.

[0095] Finally, if Figure 1 S11 and Fig.18As shown, step S11 is performed to form a third packaging layer 117 at least around the LED chip 111 to obtain a LED chip system-level packaging structure. In this step, the upper packaging of the chip combination packaging structure is realized. The forming method of the third packaging layer 117 includes one of compression molding, transfer molding, liquid sealing molding, vacuum lamination and spin coating, and the material of the third packaging layer 117 includes one of polyimide, silica gel and epoxy resin. In addition, when the metal bumps 112 are formed, the third packaging layer 117 also fills the gaps between the metal bumps 112 at the bottom of the LED chip 111 to improve stability.

[0096] As an example, the PCB board 115 is formed on the heat sink structure 113 and is located on the side of the chip combination packaging structure. The third packaging layer 117 is also formed on the PCB board 115 and the rewiring layer 110 and covers the metal lead 116. In this example, the PCB board 115 is formed on the side of the chip combination packaging structure, which is equivalent to the chip combination packaging structure being recessed in the groove formed by the PCB board 115. In one example, the PCB board is flush with the upper surface of the rewiring layer. The third packaging layer 117 is simultaneously formed on the PCB board, the rewiring layer and around the LED chip, and covers the metal lead 116 to achieve upper packaging.

[0097] In a specific implementation process, the overall size (length × width) of the fan-out system-level packaging structure can be 13mm × 16mm, and the total height is less than or equal to 1mm, which can be 0.5mm or 0.8mm. The present invention uses a fan-out system-level packaging to integrate chips with multiple functions, including a first chip (such as an ASIC chip), an LED chip, etc., into a packaging structure, which can realize a variety of different system function requirements and improve the performance of the packaging system, that is, it constitutes a systematic integration, which can integrate chips with different functions together. The present invention realizes the electrical connection of the first chip (such as an ASIC chip), the LED chip and the PCB board through a rewiring layer, a metal connecting column and a metal lead, realizes a three-dimensional vertical stacking package, effectively reduces the area of ​​the packaging system, and improves the integration of the packaging system. The present invention realizes a close connection between the rewiring layers through the above structure, which can effectively shorten the conduction path between the chips and reduce the power consumption of the packaging system. The fan-out system-level packaging structure of the present invention can achieve a packaging thickness of less than 1 mm, which greatly reduces the overall thickness of the packaging system compared to the traditional SiP packaging structure. The present invention realizes encapsulation and protection between chips through the first encapsulation layer, the second encapsulation layer and the third encapsulation layer, thereby obtaining a packaging structure with beneficial performance and stability.

[0098] like Fig.18 As shown, and refer to Figure 1-17 The present invention also provides a system-level packaging structure for an LED chip, and the LED chip system-level packaging structure preferably adopts the packaging method of the present invention. Of course, other packaging methods may also be used. The description of the components and related features in the packaging structure can refer to the corresponding description in the packaging method, and will not be repeated here. The LED chip system-level packaging structure:

[0099] Heat sink structure 113;

[0100] A first chip 100a, formed on the heat sink structure 113;

[0101] A connecting pillar structure 101 is formed on the first chip 100a to electrically lead out the first chip 100a;

[0102] A first packaging layer 104 is formed on the first chip 100a, the first packaging layer 104 covers the connecting column structure 101, and the first chip, the connecting column structure and the first packaging layer constitute an initial packaging structure of the first chip;

[0103] A second packaging layer 109 is formed on the heat sink structure 103 and covers the first chip initial packaging structure 103;

[0104] A rewiring layer 110 is formed on the second packaging layer 109 and the first chip initial packaging structure 103, and the rewiring layer 110 is electrically connected to the connection pillar structure 101;

[0105] The LED chip 111 is formed on a side of the rewiring layer 110 away from the initial packaging structure of the first chip;

[0106] A PCB board 115, wherein the PCB board 115 is electrically connected to the rewiring layer 110 formed on one side of the LED chip 111 through a metal lead 116; and

[0107] The third packaging layer 117 is formed at least around the LED chip 111 .

[0108] As an example, the upper surface of the first encapsulation layer 102 is flush with the upper surface of the second encapsulation layer 109 and the connecting pillar structure 101 is exposed; the structure here is thinned, which can be known by those skilled in the art based on the packaging method.

[0109] As an example, a plurality of metal bumps 112 are formed between the LED chip 111 and the rewiring layer 110 to achieve electrical connection between the LED chip and the rewiring layer, and the third encapsulation layer 117 is also formed between the metal bumps 112 at the bottom of the LED chip 111 .

[0110] As an example, the PCB board 115 is formed on the heat sink structure 113 and is located at the side of the chip combination packaging structure, and the third packaging layer 117 is also formed above the PCB board 115 and the rewiring layer 110 and covers the metal lead 116 .

[0111] As an example, a thermal adhesive layer 114 is further formed between the chip combination packaging structure and the heat sink structure 113 .

[0112] As an example, the first chip 100a includes an ASIC chip.

[0113] In summary, the present invention uses a fan-out system-level package to integrate chips with multiple functions, including a first chip (such as an ASIC chip), an LED chip, etc., into a packaging structure, which can achieve a variety of different system function requirements and improve the performance of the packaging system. The present invention realizes the electrical connection of the first chip (such as an ASIC chip), the LED chip and the PCB board through a rewiring layer, a metal connecting column and a metal lead, realizes a three-dimensional vertical stacking package, effectively reduces the area of ​​the packaging system, and improves the integration of the packaging system. The present invention realizes a close connection between the rewiring layers through the above structure, which can effectively shorten the conduction path between the chips and reduce the power consumption of the packaging system. The fan-out system-level packaging structure of the present invention can achieve a packaging thickness of less than 1 mm, which greatly reduces the overall thickness of the packaging system compared to the traditional SiP packaging structure. The present invention realizes the packaging and protection between chips through the first packaging layer, the second packaging layer and the third packaging layer, and obtains a packaging structure with beneficial performance and stability. Therefore, the present invention effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0114] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A system-level packaging method for LED chips, characterized in that: The packaging method comprises the following steps: Providing a chip wafer having a first surface and a second surface opposite to each other, wherein the chip wafer includes a plurality of first chips; forming a plurality of connection pillar structures on the first surface of the chip wafer to electrically lead out the first chip; forming a first packaging layer on the first surface of the chip wafer, wherein the first packaging layer covers the connecting pillar structure; Cutting the chip wafer to form a plurality of first chip initial packaging structures, including the first chip, a connecting column structure located on the first chip, and the first packaging layer covering the connecting column structure; Providing a supporting substrate, forming a separation layer on the supporting substrate, and forming the second surface of the first chip initial packaging structure on the separation layer; forming a second packaging layer on the separation layer, wherein the second packaging layer covers the initial packaging structure of the first chip, and thinning the second packaging layer until the connecting column structure is exposed; Preparing a rewiring layer on the second packaging layer, wherein the rewiring layer is electrically connected to the connecting pillar structure; Based on the separation layer, the support substrate is peeled off to expose the second surface of the first chip initial packaging structure, and the first chip intermediate packaging structure is obtained by cutting. Providing an LED chip, and forming the LED chip on a side of the rewiring layer away from the initial packaging structure of the first chip, to obtain a chip combination packaging structure; Forming the chip combination packaging structure on a heat sink structure, and electrically connecting the rewiring layer formed on one side of the LED chip to a PCB board through metal wires; and A third packaging layer is formed at least around the LED chip to obtain a LED chip system-level packaging structure.

2. The system-level packaging method for LED chips according to claim 1, characterized in that: The packaging method further includes the step of forming a protective layer on the separation layer, wherein the first chip initial packaging structure is formed on the surface of the protective layer, and after peeling off the supporting substrate, the method further includes the step of removing the protective layer.

3. The system-level packaging method for LED chips according to claim 1, characterized in that: The upper surface of the first packaging layer is higher than the upper surface of the connecting pillar structure; the upper surface of the second packaging layer is higher than the upper surface of the first packaging layer.

4. The system-level packaging method for LED chips according to claim 1, characterized in that: The LED chip is electrically connected via a plurality of metal bumps formed on the rewiring layer, and the third encapsulation layer is also formed between the metal bumps at the bottom of the LED chip.

5. The system-level packaging method for LED chips according to any one of claims 1 to 4, characterized in that: The PCB board is formed on the heat sink structure and is located at a side of the chip combination packaging structure. The third packaging layer is also formed above the PCB board and the rewiring layer and covers the metal leads.

6. The system-level packaging method for LED chips according to claim 5, characterized in that: A thermal adhesive layer is also formed between the chip combination packaging structure and the heat sink structure.

7. The system-level packaging method for LED chips according to claim 5, characterized in that: The first chip includes an ASIC chip.

8. A system-level packaging structure of an LED chip, characterized in that: The packaging structure comprises: Heat sink structure; A first chip formed on the heat sink structure; A connecting column structure is formed on the first chip to electrically lead out the first chip; A first packaging layer is formed on the first chip, the first packaging layer covers the connecting column structure, and the first chip, the connecting column structure and the first packaging layer constitute an initial packaging structure of the first chip; A second packaging layer is formed on the heat sink structure and covers the first chip initial packaging structure; a rewiring layer formed on the second packaging layer and the first chip initial packaging structure, the rewiring layer being electrically connected to the connecting column structure, the second packaging layer, the first chip initial packaging structure and the rewiring layer forming a first chip intermediate packaging structure; An LED chip is formed on a side of the rewiring layer away from the first chip initial packaging structure, and the LED chip and the first chip intermediate packaging structure constitute a chip combined packaging structure; A PCB board, the PCB board being electrically connected to the rewiring layer formed on one side of the LED chip through metal leads; and A third encapsulation layer is formed at least around the LED chip; The upper surface of the first encapsulation layer is flush with the upper surface of the second encapsulation layer and the connecting pillar structure is exposed; A plurality of metal bumps are formed between the LED chip and the rewiring layer to achieve electrical connection between the LED chip and the rewiring layer, and the third packaging layer is also formed between the metal bumps at the bottom of the LED chip.

9. The system-in-package structure of the LED chip according to claim 8, characterized in that: The PCB board is formed on the heat sink structure and is located at a side of the chip combination packaging structure. The third packaging layer is also formed above the PCB board and the rewiring layer and covers the metal leads.

10. The system-in-package structure of LED chip according to claim 9, characterized in that: A thermal adhesive layer is also formed between the chip combination packaging structure and the heat sink structure.

11. The system-in-package structure of LED chip according to claim 9, characterized in that: The first chip includes an ASIC chip.

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