Resistor circuit and artificial intelligence chip

Abstract

The present invention discloses a resistor circuit and an artificial intelligence chip. The resistor circuit includes a stacked structure. The stacked structure includes multiple resistor material layers and multiple insulating layers stacked in an interlaced manner. The resistor circuit includes at least two unit resistors electrically connected in series or in parallel. The at least two unit resistors are respectively defined in different layers of resistor material layers.

Description

Technical Field

[0001] The present invention relates to a resistor circuit, and in particular to a resistor circuit used in an artificial intelligence chip. Background Art

[0002] Recently, a neural computing device implemented by a memory array has been proposed. Compared with using a processor to perform neural computing, this type of neural computing device has the advantage of low power consumption and can be applied to artificial intelligence chips.

[0003] A neuron-like computing device generally includes a plurality of synapses. Each synapse corresponds to a weight value. When an input vector is applied to the neuron-like computing device, the input vector is multiplied by a weight vector consisting of weight values ​​corresponding to one or more associated synapses to obtain a sum of products. The sum of products operation is widely used in neuron-like devices. Summary of the invention

[0004] The present invention relates to a resistance circuit and an artificial intelligence chip. The electrically connected unit resistors of the resistance circuit are respectively defined in different layers of resistance material layers in a stacked structure.

[0005] According to one aspect of the present invention, a resistor circuit is provided, which includes a stacked structure. The stacked structure includes a plurality of resistor material layers and a plurality of insulating layers stacked in an interlaced manner. The resistor circuit includes at least two unit resistors electrically connected in series or in parallel. The at least two unit resistors are respectively defined in different layers of resistor material layers.

[0006] According to another aspect of the present invention, an artificial intelligence chip is provided, which includes a neural computing device. The neural computing device includes a stacked structure. The stacked structure includes multiple resistor material layers and multiple insulating layers stacked in an interlaced manner. The neural computing device includes a resistor circuit. The resistor circuit includes at least two unit resistors electrically connected in series or in parallel. The at least two unit resistors are respectively defined in different layers of resistor material layers. The neural computing device includes multiple synaptic units. Each synaptic unit includes a resistor circuit.

[0007] In order to better understand the above and other aspects of the present invention, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A cross-sectional view of a resistor circuit according to an embodiment is shown.

[0009] Figure 2 Draw Figure 1 Equivalent circuit diagram of the resistor circuit.

[0010] Figure 3 A cross-sectional view of a resistor circuit according to an embodiment is shown.

[0011] Figure 4 A cross-sectional view of a resistor circuit according to an embodiment is shown.

[0012] Figure 5 A cross-sectional view of a resistor circuit according to an embodiment is shown.

[0013] Figure 6 to Figure 7 The steps of a method for manufacturing a resistor circuit according to an embodiment are shown.

[0014] [Description of Reference Numerals]

[0015] 102, 602: stacked structure

[0016] 102S, 104S: upper surface

[0017] 104: Substrate

[0018] 106: Insulation layer

[0019] 108: Insulation film

[0020] 320: Contact window

[0021] 622: Photoresist

[0022] D1: First direction

[0023] D2: Second direction

[0024] D3: Third direction

[0025] E: Conductor layer

[0026] Ein: Input conductor

[0027] Eout: output conductor

[0028] EC, EC1, EC2, EC3, EC4, EC5, EC6, EC7: Connecting conductor

[0029] h: thickness

[0030] K, KA1, KA2, KA3, KA4, KA5, KA6, KA7, KA8, KB1, KB2, KB3, KB4, KB5, KB6, KB7, KB8: conductor elements

[0031] KS: Bottom conductor

[0032] L: Length

[0033] R, R1, R2, R3, R4, R5, R6, R7, R8: unit resistance

[0034] RM, RM1, RM2, RM3, RM4, RM5, RM6, RM7, RM8: resistor material layer

[0035] w: width DETAILED DESCRIPTION

[0036] The following are some embodiments for illustration. It should be noted that the present invention does not show all possible embodiments, and other implementation forms not proposed in the present invention may also be applicable. Furthermore, the dimensional ratios in the drawings are not drawn in proportion to the actual product. Therefore, the description and the illustrated contents are only used to describe the embodiments, and do not limit the scope of protection of the present invention. In addition, the descriptions in the embodiments, such as detailed structures, process steps and material applications, etc., are only for illustration, and do not limit the scope of protection of the present invention. The steps and structural details of the embodiments can be changed and modified according to the needs of the actual application process without departing from the spirit and scope of the present invention. The following is an illustration of the same / similar elements represented by the same / similar symbols.

[0037] Figure 1 A cross-sectional view of a resistor circuit of a semiconductor circuit is shown.

[0038] Please refer to Figure 1 , the stacked structure 102 may be disposed on the substrate 104. The stacked structure 102 may include insulating layers 106 and at least two resistive material layers RM that are alternately stacked in a first direction D1 (e.g., Z direction) that is substantially perpendicular to the upper surface 104S of the substrate 104. For example, the resistive material layer RM includes a first layer of resistive material layer RM1, a second layer of resistive material layer RM2, ... to an eighth layer of resistive material layer RM8 that are sequentially stacked from the substrate 104. However, the present invention is not limited thereto, and the stacked structure 102 may include other numbers of resistive material layers RM and insulating layers 106, such as four layers of resistive material layers RM.

[0039] Insulating films 108 of different heights may be formed in the stacked structure 102. The conductor elements KA1-KA8 and the conductor elements KB1-KB8 extend from the upper surface 102S of the stacked structure 102 in the first direction D1 (Z direction, or depth direction, or height direction, or thickness direction) through the stacked structure 102 and are electrically connected to the resistive material layer RM. In the present invention, the conductor elements KA1-KA8 and the conductor elements KB1-KB8 may also be represented as a whole by the symbol K for illustration. The conductor element K may be formed on the side surface of the insulating film 108 and may include a bottom conductor portion KS contacting one of the resistive material layers RM1-RM8. In this embodiment, the bottom conductor portion KS contacting the resistive material layer RM is the bottom surface of the conductor element K. The other upper conductor portions of the conductor element K may be separated from other higher-level resistive material layers RM by the insulating film 108. For example, the bottom conductor portion KS of the conductor element KA1 and the conductor element KB1 is in electrical contact with the first layer of the resistive material layer RM1, and the other portions of the conductor element KA1 and the conductor element KB1 are separated from the resistive material layers RM2 to RM8 by the insulating film 108. The bottom conductor portion KS of the conductor element KA2 and the conductor element KB2 is in electrical contact with the second layer of the resistive material layer RM2, and the other portions of the conductor element KA2 and the conductor element KB2 are separated from the resistive material layers RM3 to RM8 by the insulating film 108. Other element configurations can be deduced by analogy. In one embodiment, the insulating film 108 may have a ring shape and may surround the side surface of the conductor element K. In one embodiment, the conductor element K may have a columnar shape, such as a cylindrical shape, but is not limited thereto and may also have other suitable shapes.

[0040] In an embodiment, the resistance circuit includes at least two unit resistors R formed in different resistance material layers RM. Conductor elements K of different heights (or dimensions in the first direction D1) can contact different parts of the resistance material layers RM of different layers in pairs, respectively, to define a unit resistor R electrically connected between a pair of conductor elements K in the resistance material layer RM, one of the pair of conductor elements K serving as the input end of the unit resistor R, and the other serving as the output end of the unit resistor R. For example, conductor element KA1 and conductor element KB1 of the same first height contact different parts of the resistance material layer RM1 in pairs, to define a unit resistor R1 electrically connected between conductor element KA1 and conductor element KB1 in the resistance material layer RM1. Conductor element KA8 and conductor element KB8 of the same eighth height contact different parts of the resistance material layer RM8 in pairs, to define a unit resistor R8 electrically connected between conductor element KA8 and conductor element KB8 in the resistance material layer RM8. The unit resistors R2 to R7 defined by other pairs of conductor elements K in the resistance material layers RM2 to RM7 can be deduced in the same way.

[0041] In this embodiment, the conductor elements K are arranged along the second direction D2 (e.g., the X direction), wherein the conductor elements KA1 to KA8 are arranged in order from left to right in a step-like manner, and the conductor elements KB8 to KB1 are arranged in a step-like manner from left to right. Thus, a pair of conductor elements KA1 and KB1 at the first height have the largest distance (e.g., the distance in the second direction D2), and the conductor elements K with lower heights have a smaller distance (e.g., the distance in the second direction D2), for example, a pair of conductor elements KA8 and KB8 at the eighth height have the smallest distance. In one embodiment, the resistance values ​​of the unit resistors R of different layers are proportional to the distance between the conductor elements K. Therefore, the unit resistor R1 in the first layer of the resistance material layer RM1 has the largest resistance value, and so on, the unit resistor R in the upper layer has a smaller resistance value, that is, R1>R2>R3>R4>R5>R6>R7>R8. However, the present invention is not limited to this, and the resistance material layer RM and the conductor element K can also be appropriately adjusted according to actual needs, so as to form the desired unit resistor R in the resistance material layer RM. In other embodiments, for example, the resistance value of the unit resistor R may be determined according to the shape, relative distance, contact area, position and / or size, material, shape of the resistance material layer RM of the corresponding pair of conductor elements K, so that the resistance values ​​of the unit resistors R of different layers can be arbitrarily controlled to be the same or different. For example, the resistance material layer RM may have the same or different thicknesses. The resistance material layer RM may have the same or different material properties. The material of the resistance material layer RM may include a semiconductor material, such as a silicon material such as polysilicon, or a carbon-based material, or a metal nitride such as TiN, TaN, etc., or other suitable resistance materials. The material of the resistance material layer RM may include an N-type semiconductor material or a P-type semiconductor material. For example, the resistance material layer RM may have the same or different doping conditions, such as the same or different types of doping impurities, and / or the same or different doping concentrations. Doping impurities include but are not limited to elements such as P, B, In, C, and N.

[0042] For example, in one embodiment, R1:R2:R3:R4=1:1:1:1. In one embodiment, R1:R2:R3:R4=1:2:4:8. In one embodiment, R1:R2:R3:R4=1:2:4:12. In one embodiment, R1:R2:R3:R4=1:3:9:27. In one embodiment, R1=R2=R3. In one embodiment, R1<R2<R3. In one embodiment, R3=2R1=4R2. In one embodiment, R1=3R2=9R3. In one embodiment, R1=R2=R3<R4=R5=R6. In one embodiment, R1=R2=R3>R4=R5=R6. In one embodiment, R3=2R1=4R2. In one embodiment, R1=3R2=9R3.

[0043] In another embodiment, the conductor elements KA1 - KA8 and KB1 - KB8 may be arranged in a staggered manner or in other suitable manners.

[0044] The conductor layer E may be formed on the upper surface of the stacked structure 102, the conductor element K and the insulating film 108, and electrically connected to the conductor element K. The conductor element K may be electrically connected between the conductor layer E and the resistance material layer RM. In an embodiment, the electrical connection between the unit resistors R of different resistance material layers RM and / or the effective resistance of the resistance circuit may be determined by the pattern configuration of the conductor layer E. For example, in this embodiment, the conductor layer E includes an input conductor portion Ein, an output conductor portion Eout, and a connecting conductor portion EC that are separated from each other. The connecting conductor portion EC may include connecting conductor portions EC1 to EC7 that are separated from each other. The input conductor portion Ein, which serves as the input end of the resistance circuit, is electrically connected to at least one conductor element K, which is the conductor element KA1 in this embodiment. The output conductor portion Eout, which serves as the output end of the resistance circuit, is electrically connected to at least one conductor element K, which is the conductor element KA8 in this embodiment. The connecting conductor portion EC is electrically connected between the input conductor portion Ein and the output conductor portion Eout via the conductor element K and the resistance material layer RM.

[0045] The connecting conductor part EC electrically connects at least two conductor elements K of different heights, so that the unit resistors R of different layers are electrically connected to each other. For example, in this embodiment, the connecting conductor part EC1 is electrically connected to the conductor element KB1 and the conductor element KB2, so that the unit resistor R1 is electrically connected in series with the unit resistor R2. The connecting conductor part EC2 is electrically connected to the conductor element KA2 and the conductor element KA3, so that the unit resistor R2 is electrically connected in series with the unit resistor R3. This can be deduced in this way. Figure 1 The connection relationship between other connecting conductor parts EC3~EC7 and conductor elements KA4~KA7, KB3~KB8 is shown in FIG.

[0046] In an embodiment, the resistance value of the resistive material layer RM may be greater than the resistance values ​​of the conductor element K and the conductor layer E, so that the overall effective resistance of the resistance circuit may be substantially caused by the unit resistance R in the resistive material layer RM. For example, the conductor element K and the conductor layer E may be used as contacts with high conductive properties.

[0047] In one embodiment, Figure 1 The resistor circuit shown in the figure includes unit resistors R1 to R8 electrically connected in series between the input conductor Ein and the output conductor Eout. The corresponding circuit can be shown as follows: Figure 2 In this embodiment, the effective resistance Rio of the resistance circuit can be substantially the sum of the unit resistances R1 to R8 of each layer connected in series. That is, Rio = R1 + R2 + R3 + R4 + R5 + R6 + R7 + R8.

[0048] In another embodiment, the resistance circuit may include unit resistors R electrically connected in parallel through the pattern configuration of the conductive layer E. The unit resistors R in a portion of the resistance material layer RM may be floating.

[0049] For example, please refer to Figure 3 The resistor circuit with Figure 1 The differences in the resistance circuits shown are described as follows. The conductor layer E includes an input conductor portion Ein and an output conductor portion Eout. The input conductor portion Ein is electrically connected to a contact via 320 on the conductor elements KA1 to KA8. The output conductor portion Eout is electrically connected to a contact via 320 on the conductor elements KB1, KB6, and KB8. The conductor layer E is not electrically connected to the conductor elements KB2 to KB5 and KB7, so the conductor elements KB2 to KB5 and KB7 and the resistance material layers RM2 to RM5 and RM7 (or unit resistors R2 to R5 and R7) connected thereto are floating. In this embodiment, the relationship between the total resistance value Rio of the resistance circuit and the unit resistance R can be expressed as 1 / Rio=1 / R1+1 / R6+1 / R8.

[0050] In another embodiment, for example, Figure 3 The resistance circuit is changed into the output conductor part Eout being electrically connected to the conductor elements KB1~KB8 at the same time, or being electrically connected to the contact window 320 on the conductor elements KB1~KB8 (not shown), so that the resistance circuit can become an equivalent circuit caused by the unit resistances R1~R8 being connected in parallel, and the relationship between its total resistance value Rio and the unit resistances R1~R8 can be expressed as 1 / Rio=1 / R1+1 / R2+1 / R3+1 / R4+1 / R5+1 / R6+1 / R7+1 / R8.

[0051] Please refer to Figure 4 The resistor circuit with Figure 1The differences of the resistor circuit shown are explained as follows. The conductor layer E includes an input conductor portion Ein, an output conductor portion Eout, and a connecting conductor portion EC that are separated from each other. The input conductor portion Ein is electrically connected to the contact window 320 on the conductor element KA2. The output conductor portion Eout is electrically connected to the contact window 320 on the conductor element KA8. The connecting conductor portion EC is electrically connected to the contact windows 320 on the conductor elements KB2 and KB8. The conductor layer E is not electrically connected to the conductor elements KA1, KA3-KA7, KB1, and KB3-KB7, so the conductor elements KA1, KA3-KA7, KB1, and KB3-KB7 and the resistor material layers RMI, RM3-RM7 (or unit resistors R1 and R3-R7) connected thereto are floating. In this embodiment, the relationship between the total resistance value Rio of the resistor circuit and the unit resistance R can be expressed as Rio=R2+R8.

[0052] In yet another embodiment, the pattern of the conductive layer E may be configured so that a portion of the unit resistors R of the resistance circuit are electrically connected in parallel, and another portion are electrically connected in series.

[0053] Please refer to Figure 5 The resistor circuit with Figure 1 The differences in the resistance circuits shown are described as follows. The conductor layer E includes an input conductor portion Ein, an output conductor portion Eout, and a connecting conductor portion EC that are separated from each other. The connecting conductor portion EC may include connecting conductor portions EC1 to EC3 that are separated from each other. The input conductor portion Ein is electrically connected to the conductor element KA1. The output conductor portion Eout is electrically connected to the conductor elements KA4 to KA8. The connecting conductor portion EC1 is electrically connected to the conductor elements KB1 and KB2. The connecting conductor portion EC2 is electrically connected to the conductor elements KA2 and KA3. The connecting conductor portion EC3 is electrically connected to the conductor elements KB3 to KB8. In this embodiment, the resistance circuit includes a parallel resistor Rp that is essentially composed of unit resistors R4 to R8, and the parallel resistor Rp is electrically connected in series with other unit resistors R1 to R3. Therefore, the relationship between the total resistance value Rio of the resistance circuit and the unit resistances R1 to R8 can be expressed as Rio=R1+R2+R3+Rp, where 1 / Rp=1 / R4+1 / R5+1 / R6+1 / R7+1 / R8.

[0054] In an embodiment, the resistance circuit can be applied to any semiconductor circuit. In one embodiment, each of the multiple synapse units (synapse) of the neural computing device of the artificial intelligence chip may include a resistance circuit according to the concept of the embodiment of the present invention. In one embodiment, the resistance circuit can be configured in a semiconductor package structure, such as a multi-chip package, and the resistance circuit can be electrically connected to the chip using technologies such as wire bonding, micro-bumps, and Si-interposer. In one embodiment, the resistance circuit can be formed on a silicon interposer circuit board. However, the present invention is not limited to this, and the resistance circuit can also be applied to other semiconductor devices or electronic devices as needed.

[0055] Figure 6 to Figure 7 The steps of a method for manufacturing a resistor circuit according to an embodiment are shown.

[0056] Please refer to Figure 6 , the insulating layer 106 and the resistive material layer RM are alternately stacked on the substrate 104 to form a stacked structure 602. The substrate 104 may include, but is not limited to, a silicon substrate, or other suitable substrate materials. The insulating layer 106 may include, but is not limited to, for example, silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials formed by deposition. The material of the resistive material layer RM may include, but is not limited to, a semiconductor material, such as an N-type semiconductor material or a P-type semiconductor material, such as polysilicon doped with P, B, In, C, or N impurities, or a carbon-based material, or a metal nitride such as TiN, TaN, etc., or other suitable resistive materials.

[0057] Please refer to Figure 6 Then, the stacked structure 602 may be patterned using a yellow light photolithography process. For example, a patterned photoresist 622 may be formed to cover a portion of the upper surface 102S of the stacked structure 602, and then the pattern of the photoresist 622 may be transferred downward into the stacked structure 602. Specifically, the photoresist 622 (or hard mask) may be used as an etching mask, and an etching step may be performed to remove the portion of the stacked structure 602 not covered by the photoresist 622 (or hard mask), thereby forming a structure such as Figure 7The patterned stacked structure 102 is shown. In one embodiment, all the resistor material layers RM1 to RM8 of the stacked structure 102 of the resistor circuit are formed by patterning simultaneously using the same photoresist 622, so that the outer side walls of the resistor material layers RM1 to RM8 of different layers are aligned with each other, and the resistor material layers RM1 to RM8 may have the same pattern as the photoresist 622. In detail, the resistor material layers RM1 to RM8 may have a consistent outer side wall profile. In one embodiment, for example, in a top view, the upper surface of the photoresist 622 has a rectangular shape, and the resistor material layers RM1 to RM8 formed by patterning the photoresist 622 also have the same shape, so the outer side walls of the resistor material layers RM1 to RM8 have a consistent rectangular profile. However, the present invention is not limited to this, and the stacked structure 102 may be patterned into other suitable shapes, such as triangles, squares, L-shapes, other polygons, regular shapes, irregular shapes, rings, circles, etc. Then, the photoresist 622 may be removed or the upper surface 102S of the stack structure 102 may be further planarized by, for example, chemical mechanical polishing (CMP) or other suitable etching methods.

[0058] In one embodiment, the resistance material layers RM1-RM8 may each have a thickness h (a dimension in the first direction D1, or a height), a length L (a dimension in the second direction D2), and a width w (a dimension in the third direction D3, such as a dimension in the Y direction). For example, h<w. 10h<L. In one embodiment, the thickness h of the resistance material layers RM1-RM8 is the same. However, the present invention is not limited thereto, and the conditions of the resistance material layers RM may also be appropriately adjusted.

[0059] Then, for example, see Figure 1, openings of different depths can be formed in the stacked structure 102, which respectively expose different layers of the resistive material layers RM1-RM8. A patterned photoresist or hard mask (not shown) can be used as an etching mask to remove a portion of the stacked structure 102 to form an opening. An insulating film 108 can be formed on the side surface of the stacked structure 102 exposed by the opening. The insulating film 108 may include, but is not limited to, for example, silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials formed by deposition. Conductive elements KA1-KA8, KB1-KB8 can be formed on the sidewalls of the insulating film 108 in the opening and on the resistive material layers RM1-RM8 exposed by the opening. The upper surfaces of the stacked structure 102 and the conductor elements KA1-KA8, KB1-KB8 formed therein and the insulating film 108 can be planarized by, for example, chemical mechanical polishing (CMP) or other suitable etching methods. A conductive material film can be formed on the stacked structure 102, the conductor elements KA1-KA8, KB1-KB8 and the insulating film 108. The conductor material film may include, but is not limited to, tungsten, aluminum, copper, or other suitable metals or metal silicides with high conductivity formed by a deposition method. A patterned photoresist or hard mask (not shown) may be used as an etching mask to remove a portion of the conductor material film to form a patterned conductor layer E, which at least includes an input conductor portion Ein and an output conductor portion Eout separated from each other, and may further include at least one connecting conductor portion EC.

[0060] In another embodiment, for example, referring to Figure 3 , a contact window 320 may be formed on the conductor element K. The contact window 320 may be disposed in a dielectric layer (not shown) formed on the upper surface of the stacked structure 102, the conductor element K and the insulating film 108. The method for forming the contact window 320 may include forming a patterned photoresist or hard mask (not shown) as an etching mask on the dielectric layer, and transferring the pattern to the dielectric layer by an etching step to form an opening, and filling the opening with a conductive material. The conductive material used to form the contact window 320 may include tungsten, aluminum, copper, or other suitable metals or metal silicides with high conductive properties. A conductive layer E may be formed on the upper surface of the contact window 320 and the dielectric layer (not shown).

[0061] According to the above embodiments, the present invention provides a resistor circuit, which is composed of unit resistors respectively defined in different resistor material layers in a stacked structure.

[0062] In summary, although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. A person skilled in the art of the present invention may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the attached claims.

Claims

1. A resistance circuit, comprising: A stacked structure, comprising a plurality of resistor material layers and a plurality of insulating layers stacked alternately, wherein the resistor circuit comprises at least two unit resistors electrically connected in series or in parallel, and the at least two unit resistors are respectively defined in the resistor material layers at different layers; A plurality of conductor elements are arranged in the stack structure, and the at least two unit resistors are respectively defined between different pairs of the conductor elements; as well as an insulating film surrounding a side wall surface of a conductor element, wherein the conductor element has a columnar shape; The uppermost layer of the stacked structure is a top insulating layer, and the top surface of the top insulating layer is flush with the top surface of the insulating film.

2. The resistor circuit as claimed in claim 1, wherein at least one of the resistor material layers is floating.

3. The resistor circuit as claimed in claim 1, wherein the at least two unit resistors have the same or different resistance values. 4 . The resistor circuit as claimed in claim 1 , wherein an effective resistance of the resistor circuit is caused by the at least two unit resistors. The resistor circuit as claimed in claim 1 , wherein outer sidewalls of the resistor material layers are aligned with each other.

6. The resistance circuit as described in claim 1 further includes a conductor layer, which is arranged on the stacked structure and electrically connects these conductor elements, wherein the conductor layer includes an input conductor part and an output conductor part, and the resistance circuit is defined between the input conductor part and the output conductor part, wherein the input conductor part is used as an input end of the resistance circuit, and the output conductor part is used as an output end of the resistance circuit.

7. The resistance circuit as described in claim 6, wherein the conductor layer further includes a connecting conductor portion, electrically connecting at least two of these conductor elements and electrically connecting between the input conductor portion and the output conductor portion, wherein the connecting conductor portion is electrically connected to these conductor elements at different heights.

8. The resistor circuit as claimed in claim 1, wherein the at least two unit resistors include: a unit resistor defined in one of the resistive material layers; and Another unit resistor is defined in another resistor material layer of the resistor material layers, wherein the one resistor material layer and the other resistor material layer include silicon material. 9 . The resistor circuit as claimed in claim 8 , wherein the one unit resistor and the other unit resistor have different resistance values, and the one resistor material layer and the other resistor material layer have different doping impurities and / or doping concentrations.

10. An artificial intelligence chip, comprising a type of neural computing device, the type of neural computing device comprising: A stacked structure, comprising a plurality of resistor material layers and a plurality of insulating layers stacked in an alternating manner, wherein the neural computing device comprises a resistor circuit, the resistor circuit comprises at least two unit resistors electrically connected in series or in parallel, the at least two unit resistors are respectively defined in the resistor material layers at different layers, and the neural computing device comprises a plurality of synaptic units, each of which comprises the resistor circuit; A plurality of conductor elements are arranged in the stack structure, and the at least two unit resistors are respectively defined between different pairs of the conductor elements; as well as an insulating film surrounding a side wall surface of a conductor element, wherein the conductor element has a columnar shape; The uppermost layer of the stacked structure is a top insulating layer, and the top surface of the top insulating layer is flush with the top surface of the insulating film.

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