Display panel

Abstract

A display panel is provided. The display panel includes a base substrate, a pixel including a thin film transistor and a display element, a first signal line connected with the pixel, and a second signal line arranged on a different layer from the first signal line. At least one of the first signal line and the second signal line includes a lower layer and an upper layer, wherein the lower layer includes a conductive material, and the upper layer is arranged on the lower layer and includes a conductive material. The upper layer has an etching selectivity greater than or equal to about 0.5 and less than or equal to about 3 with respect to the lower layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from and all benefits derived from Korean Patent Application No. 10-2019-0070878, filed on June 14, 2019, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a display panel, and more particularly, to a display panel having low external light reflectivity. Background Art

[0004] The display device includes signal lines and electronic components connected to the signal lines to display images. The signal lines and the electronic components include a plurality of conductive layers. Summary of the Invention

[0005] The present disclosure provides a display panel having relatively low external light reflectivity and improved process reliability.

[0006] Embodiments of the present invention provide a display panel including a base substrate, pixels, and signal lines, wherein the pixels are located on the base substrate and include thin film transistors and display elements connected to the thin film transistors, and the signal lines are connected to the pixels. The signal lines include a lower layer including a conductive material and an upper layer including a conductive material. The upper layer has an etch selectivity within a range of greater than or equal to approximately 0.5 and less than or equal to approximately 3 relative to the lower layer.

[0007] The upper layer may be in direct contact with the lower layer.

[0008] The upper layer may include an opaque material and have a thickness of about 100 angstroms or less.

[0009] The lower layer may include a first layer, a second layer having a lower resistivity than the first layer, and a third layer having a lower light reflectivity than the second layer. The upper layer may be in contact with the third layer.

[0010] The upper layer may comprise the same material as the second layer.

[0011] The upper layer may have a thickness smaller than that of each of the first layer, the second layer, and the third layer.

[0012] The upper layer and the second layer may include copper.

[0013] The first, second, and third layers may comprise a different material than the upper layer.

[0014] The upper layer may include a transparent conductive oxide material, a metal material, or a metal oxide material.

[0015] The etch selectivity may be an etch selectivity relative to a non-aqueous etchant.

[0016] In a cross-sectional view, a side surface of the upper layer and a side surface of the lower layer may be aligned with each other along a predetermined imaginary line.

[0017] The imaginary line may be inclined with respect to the upper surface of the base substrate.

[0018] The display panel may further include an insulating layer. A plurality of signal lines may be provided, the plurality of signal lines including a first signal line and a second signal line each connected to a pixel. The first signal line and the second signal line may be located in different layers with the insulating layer interposed therebetween.

[0019] The thin film transistor includes a control electrode, an input electrode, and an output electrode spaced apart from each other, and the output electrode is connected to the display element.

[0020] The signal line may include at least one of a control electrode, an input electrode, and an output electrode.

[0021] The display element may include a pixel electrode, a common electrode, and an optical control layer located between the pixel electrode and the common electrode. In a plan view, an upper layer and a lower layer of the signal line may overlap with the pixel electrode.

[0022] Embodiments of the present invention provide a display panel including a base substrate, pixels, and signal lines, wherein the pixels are located on the base substrate and include thin film transistors and display elements connected to the thin film transistors, and the signal lines are connected to the pixels. The signal lines include an upper layer having a thickness of approximately 100 angstroms or less and a lower layer located between the base substrate and the upper layer.

[0023] The lower layer may include a first layer, a second layer, and a third layer, wherein the first layer includes a first metal (e.g., a metallic material), the second layer contacts the first layer and includes a second metal (e.g., a metallic material) different from the first metal, and the third layer contacts the second layer and the upper layer and includes a third metal (e.g., a metallic material) the same as the first metal.

[0024] The upper layer may include the same metal material as the second layer, and the second layer may be thicker than the upper layer.

[0025] The third layer may have a lower reflectivity than the second layer and a higher resistivity than the second layer.

[0026] According to one or more exemplary embodiments, when a signal line having low light reflectivity is provided or formed, the side surfaces of the signal line can be arranged along a single plane in a cross-sectional view. Consequently, damage or breakage of the insulating layer covering the signal line due to the inconsistent side surfaces of the signal line can be reduced or effectively prevented. Furthermore, even when the signal line is arranged to overlap with an area emitting light or displaying an image, the visibility of the signal line caused by reflection of external light can be reduced. Consequently, the reflectivity of external light of a display panel including such a signal line can be reduced, and the process reliability of the display panel including such a signal line can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other advantages of the present disclosure will become readily apparent by referring to the following detailed description when considered in conjunction with the accompanying drawings, in which:

[0028] Figure 1 is a block diagram illustrating an exemplary embodiment of a display device;

[0029] Figure 2 It shows Figure 1 A perspective view of an exemplary embodiment of a display device shown in FIG;

[0030] Figure 3A is a top plan view illustrating an exemplary embodiment of a display panel;

[0031] Figure 3B It is along Figure 3A An enlarged cross-sectional view taken along line II' shown in FIG.

[0032] Figure 4A is an enlarged cross-sectional view of an exemplary embodiment showing a portion of a display panel;

[0033] Figure 4B is an enlarged cross-sectional view showing a portion of a comparative embodiment of a display panel;

[0034] Figure 4C is an enlarged cross-sectional view of an exemplary embodiment showing a portion of a display panel;

[0035] Figure 5 is a graph showing light reflectance of an exemplary embodiment of a display panel;

[0036] Figure 6 is a top plan view illustrating an exemplary embodiment of a display panel; and

[0037] 7A to 7C is an enlarged cross-sectional view illustrating an exemplary embodiment of a method of manufacturing a display panel. DETAILED DESCRIPTION

[0038] The present invention will now be described more fully hereinafter with reference to the accompanying drawings showing various embodiments. However, the present invention may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those skilled in the art.

[0039] In the present disclosure, it should be understood that when an element or layer is referred to as being associated with another element, such as being "on," "connected to," or "coupled to" another element or layer, the element or layer can be directly on the other element or layer, or can be connected to or coupled to the other element, or intervening elements or layers may be present. In contrast, when an element or layer is referred to as being associated with another element, such as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers.

[0040] Throughout the specification, like reference numerals refer to like elements. In the drawings, the thickness, proportion, and size of components are exaggerated for effective description of technical contents.

[0041] Unless the context clearly indicates otherwise, as used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well. For example, unless the context clearly indicates otherwise, "element" has the same meaning as "at least one element." "At least one" should not be interpreted as limiting "a" or "an." "Or" means "and / or." As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0042] It should be understood that although the terms first, second, etc. can be used to describe various elements, components, areas, layers and / or parts in this article, these elements, components, areas, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer or part from another element, component, area, layer or part. Therefore, the first element, component, area, layer or part discussed below can be referred to as the second element, component, area, layer or part without departing from the teachings of the present disclosure.

[0043] Spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper,” etc. may be used herein for convenience of description to describe the relationship of one element or feature to another element or feature as shown in the figures.

[0044] As used herein, "about" or "approximately" includes stated values ​​and means that are within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the errors associated with the measurements and the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, 20%, 10%, or 5% of the stated value.

[0045] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will also be understood that, unless expressly defined as such herein, terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense.

[0046] It will also be understood that when the terms “comprise” and / or “comprising”, “include” and / or “including” are used in this specification, they specify the presence of stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or clusters thereof.

[0047] In a display device, a signal line and / or a conductive layer of an electronic component connected to the signal line may include an optically opaque material. The conductive layer may be visible from outside the display device due to external light reflected by the conductive layer. When the signal line or electronic component is visible from outside the display device due to reflection of external light, the reflected external light affects the visibility of an image displayed by the display device.

[0048] Hereinafter, the present invention will be explained in detail with reference to the accompanying drawings.

[0049] Figure 1 is a block diagram illustrating an exemplary embodiment of the display device DS. Figure 2 It shows Figure 1 , which is a perspective view of an exemplary embodiment of a portion of a display device DS shown in FIG. Figure 1 and Figure 2 The present disclosure is described.

[0050] Reference Figure 1 , the display device DS includes a signal controller TC, a gate driver GD, a data driver DD and a display panel DP.

[0051] The display panel DP is electrically connected to the gate driver GD and the data driver DD, and is operated by electrical signals supplied from the gate driver GD and the data driver DD. The display panel DP is not particularly limited, and for example, the display panel DP may be an organic light-emitting display panel, a liquid crystal display panel, a plasma display panel, an electrophoretic display panel, or an electrowetting display panel. In this exemplary embodiment, a liquid crystal display device including a liquid crystal display panel will be described as a representative example.

[0052] The display device DS may further include a backlight unit (not shown) that provides light to the display panel DP, and optical components including a polarizing plate. The display panel DP controls the amount of light transmitted therethrough from the light generated and provided by the backlight unit to display an image. However, this is merely exemplary, and when an organic light-emitting display panel is used as the display panel DP, the backlight unit may be omitted. Here, the organic light-emitting display panel may generate and control light to produce an image.

[0053] The display panel DP includes a plurality of signal lines G1 to Gm and D1 to Dn and a plurality of pixels PX (e.g., a plurality of pixels PX) connected to the plurality of signal lines G1 to Gm and D1 to Dn. The plurality of signal lines G1 to Gm and D1 to Dn include a plurality of gate lines G1 to Gm and a plurality of data lines D1 to Dn.

[0054] A plurality of gate lines G1 to Gm extend longitudinally along a first direction DR1 and are arranged along a second direction DR2 intersecting the first direction DR1. The plurality of gate lines G1 to Gm connect a gate driver GD to pixels PX. The plurality of gate lines G1 to Gm respectively apply gate signals, which are electrical signals, provided from the gate driver GD to the pixels PX. The thickness of the display device DS and its components is defined along directions intersecting each of the first direction DR1 and the second direction DR2.

[0055] A plurality of data lines D1 to Dn extend longitudinally along a second direction DR2 and are arranged along a first direction DR1. The plurality of data lines D1 to Dn connect a data driver DD to pixels PX. The data lines D1 to Dn respectively apply data signals, which are electrical signals, provided by the data driver DD to the pixels PX. The plurality of data lines D1 to Dn intersect the plurality of gate lines G1 to Gm while being insulated from the plurality of gate lines G1 to Gm.

[0056] Each of the plurality of pixels PX is connected to a corresponding gate line among a plurality of gate lines G1 to Gm and a corresponding data line among a plurality of data lines D1 to Dn. Each of the plurality of pixels PX includes a switching element (such as a thin film transistor) and a capacitor (such as a liquid crystal capacitor) connected to the thin film transistor. The pixel PX displays an image by controlling the amount of charge in the liquid crystal capacitor. This will be described in detail later.

[0057] The signal controller TC applies electrical signals to the gate driver GD and the data driver DD to control the operation of the gate driver GD and the data driver DD. The signal controller TC receives input image signals RGB, converts the input image signals RGB into image data R'G'B' suitable for the operation of the display panel DP, and outputs the image data R'G'B'. In addition, the signal controller TC receives various control signals CS (e.g., a vertical synchronization signal, a horizontal synchronization signal, a main clock signal, and a data enable signal) as electrical signals, and generates and outputs a first control signal CONT1 and a second control signal CONT2 as additional electrical signals.

[0058] The data driver DD receives a first control signal CONT1 and image data R'G'B'. The data driver DD converts the image data R'G'B' into data voltages and applies the data voltages, which are electrical signals, to the data lines D1 to Dn. The first control signal CONT1 includes a horizontal start signal that starts the operation of the data driver DD, an inversion signal that inverts the polarity of the data voltage, and an output instruction signal that determines the output timing of the data voltage from the data driver DD.

[0059] The gate driver GD outputs a gate signal as an electrical signal to the gate lines G1 to Gm in response to the second control signal CONT2. The second control signal CONT2 includes a vertical start signal that starts the operation of the gate driver GD, a gate clock signal that determines the output timing of the gate voltage, and an output enable signal that determines the on-pulse width of the gate voltage.

[0060] Reference Figure 2 , the display panel DP may include a first substrate 100, a second substrate 200, and an optical control (or optical transmission) layer such as a liquid crystal layer 300. The first substrate 100 may include a plurality of pixel areas PA (e.g., a plurality of pixel areas PA). A plurality of pixels PX may be arranged in the plurality of pixel areas PA, respectively. In the exemplary embodiment of the present disclosure, the plurality of pixel areas PA may be planar areas that display light transmitted or generated by the plurality of pixels PX, respectively. Although not shown in the figure, the first substrate 100 may include some components of the pixel PX (e.g., a conductive layer, an insulating layer, a light-blocking layer, etc.).

[0061] The second substrate 200 is disposed on the first substrate 100. The second substrate 200 faces the first substrate 100 with the optical control layer interposed therebetween. Although not shown in the figure, the second substrate 200 may include some components of the pixel PX (eg, a conductive layer, an insulating layer, a light blocking layer, etc.).

[0062] The liquid crystal layer 300 is disposed between the first substrate 100 and the second substrate 200. The liquid crystal layer 300 may include an optical control medium, such as liquid crystal molecules LC (refer to Figure 3B The liquid crystal molecules LC may include a material whose alignment is controlled by an electric field provided or formed in the pixel area PA. The liquid crystal layer 300 may be a component of the pixel PX.

[0063] Figure 3A is a top plan view illustrating an exemplary embodiment of the display panel DP. Figure 3B It is along Figure 3A An enlarged cross-sectional view taken along line II' shown in FIG. Figure 3A 1 is a top plan view showing the first substrate 100. For convenience of explanation, Figure 3A The first substrate 100 is shown Figure 2 A portion corresponds to four pixel areas PA1 , PA2 , PA3 , and PA4 adjacent to each other among the plurality of pixel areas PA shown in FIG. Figure 3B FIG. 1 shows an enlarged cross-sectional view of the display panel DP. Figure 3A and Figure 3B The present disclosure is described.

[0064] Four pixels PX1, PX2, PX3, and PX4 may be arranged in four pixel areas PA1, PA2, PA3, and PA4, respectively. Each of the four pixels PX1, PX2, PX3, and PX4 may be connected to a corresponding gate line and a corresponding data line. Specifically, among the four pixels PX1, PX2, PX3, and PX4, the first pixel PX1 is connected to the first gate line G1 and the first data line D1, and the second pixel PX2 is connected to the first gate line G1 and the second data line D2. The third pixel PX3 is connected to the second gate line G2 and the first data line D1, and the fourth pixel PX4 is connected to the second gate line G2 and the second data line D2. In this exemplary embodiment, for convenience of explanation, one pixel area PA1 (hereinafter referred to as "first pixel area PA1") among the four pixel areas PA1, PA2, PA3, and PA4 will be described as a representative example.

[0065] The first pixel area PA1 may be a planar area where the first pixel PX1 generates and / or transmits light to display an image. A plurality of pixels PX, each having a structure corresponding to that of the first pixel PX1, may be arranged in other pixel areas PA. However, this is merely exemplary, and the pixels PX arranged in other pixel areas PA may have a different structure from that of the first pixel PX1, and should not be limited to a particular embodiment.

[0066] The first pixel PX1 may include a first thin film transistor TR1, a display element connected to the first thin film transistor TR1, and a first capacitor (e.g., a first liquid crystal capacitor). The first liquid crystal capacitor may include a collective structure of a first pixel electrode PE1, a common electrode CE, and a liquid crystal layer 300. The display element may include the first pixel electrode PE1, the common electrode CE, and the liquid crystal layer 300 disposed between the first pixel electrode PE1 and the common electrode CE, but is not limited thereto.

[0067] The first substrate 100 may include a first base substrate BS1 (hereinafter also referred to as a base substrate BS), a first gate line G1, a second gate line G2, a first data line D1, a second data line D2, a first thin-film transistor TR1, a second thin-film transistor TR2, a third thin-film transistor TR3, a fourth thin-film transistor TR4, a plurality of pixel electrodes, and a plurality of insulating layers. The insulating layers include a first insulating layer 10 and a second insulating layer 20. The first base substrate BS1 may include an insulating material. The first base substrate BS1 may be optically transparent. Accordingly, light generated and provided by a backlight unit (not shown) disposed below the first base substrate BS1 may reach the liquid crystal layer 300 after passing through the first base substrate BS1. In exemplary embodiments, the first base substrate BS1 may include, for example, a glass substrate or a plastic substrate.

[0068] The first gate line G1 and the second gate line G2 are arranged between the first base substrate BS1 and the first insulating layer 10. In a top plan view, the first gate line G1 includes or defines a portion thereof that protrudes in a direction substantially parallel to the second direction DR2 and may function as a first control electrode CE1 of the first thin film transistor TR1 and a second control electrode CE2 of the second thin film transistor TR2. The first thin film transistor TR1 is connected to the first gate line G1 at the first control electrode CE1 to receive a gate signal provided from the first gate line G1.

[0069] The first gate line G1 and the first control electrode CE1 are covered by the first insulating layer 10. The first insulating layer 10 may include an organic material (eg, an organic layer) and / or an inorganic material (eg, an inorganic layer).

[0070] The first semiconductor pattern SP1 of the first thin film transistor TR1 may be disposed on the first insulating layer 10. When viewed in a cross-sectional view, the first semiconductor pattern SP1 may be disposed to be spaced apart from the first control electrode CE1 with the first insulating layer 10 interposed therebetween.

[0071] The first semiconductor pattern SP1 may include a semiconductor material. In example embodiments, for example, the semiconductor material may include at least one of amorphous silicon, polysilicon, crystalline silicon, an oxide semiconductor, and a compound semiconductor.

[0072] The second insulating layer 20 covers the first input electrode IE1 and the first output electrode OE1 of the first thin-film transistor TR1. The second insulating layer 20 also covers the second input electrode IE2 and the second output electrode OE2 of the second thin-film transistor TR2. The second insulating layer 20 may include an organic material and / or an inorganic material. The first input electrode IE1, the first output electrode OE1, the second input electrode IE2, and the second output electrode OE2 may be arranged between the first insulating layer 10 and the second insulating layer 20.

[0073] The first input electrode IE1 may be defined by a portion of the first data line D1 that protrudes in a direction substantially parallel to the first direction DR1. The first input electrode IE1 and the first output electrode OE1 may be arranged in the same layer as the first data line D1 among the material layers arranged on the first base substrate BS1. The second input electrode IE2 may be defined by a portion of the second data line D2 that protrudes in a direction substantially parallel to the first direction DR1. The second input electrode IE2 and the second output electrode OE2 may be arranged in the same layer as the second data line D2 among the material layers arranged on the first base substrate BS1.

[0074] When viewed in a top plan view, the first input electrode IE1 may have a shape that surrounds a first end (e.g., a distal end) of the first output electrode OE1. A second end of the first output electrode OE1, opposite to the first end, corresponds to or overlaps with a contact hole, and the second end contacts the first pixel electrode PE1 through the contact hole. That is, the first thin film transistor TR1 is connected to the first pixel electrode PE1 at this contact hole. Each of the first input electrode IE1 and the first output electrode OE1 may be arranged on the same first semiconductor pattern SP1 and may be in direct contact with the first semiconductor pattern SP1.

[0075] However, this is merely exemplary, and the first input electrode IE1 and the first output electrode OE1 may be arranged to be spaced apart from the first semiconductor pattern SP1 by the intermediate layer in the thickness direction, and may contact the first semiconductor pattern SP1 at or through a separate contact hole defined in the intermediate layer. The first thin film transistor TR1 according to the exemplary embodiment of the present disclosure may have various planar shapes and / or cross-sectional shapes and may not be limited to a specific embodiment.

[0076] The third thin film transistor TR3 and the fourth thin film transistor TR4 may have substantially the same structure, configuration, etc. as the first thin film transistor TR1 and the second thin film transistor TR2 described above, but are not limited thereto.

[0077] Reference Figure 3B , for example, at least one of the plurality of gate lines G1 and G2 and the plurality of data lines D1 and D2 may include a plurality of gate lines G1 and G2 along a thickness direction (eg, Figure 3BIn the present exemplary embodiment, the plurality of gate lines G1 and G2 have a structure of four layers stacked one on top of the other. When viewed in a cross-sectional view, each of the plurality of gate lines G1 and G2 may include a side surface inclined relative to the first base substrate BS1.

[0078] Refer again Figure 3B The plurality of data lines D1 and D2 have a structure of four layers stacked one on top of the other. When viewed in cross-section, each of the plurality of data lines D1 and D2 may include a side surface that is inclined relative to the first base substrate BS1. The plurality of data lines D1 and D2 have a structure corresponding to the plurality of gate lines G1 and G2. That is, the plurality of data lines D1 and D2 and the plurality of gate lines G1 and G2 have the same structure of four layers stacked one on top of the other.

[0079] In the present exemplary embodiment, the first control electrode CE1 may branch from the first gate line G1 and may have substantially the same cross-sectional layer structure as the first gate line G1. The first input electrode IE1 may branch from the first data line D1 and may have substantially the same cross-sectional layer structure as the first data line D1.

[0080] The plurality of data lines D1 and D2 may have a cross-sectional layer structure that is different from the cross-sectional layer structure of the plurality of gate lines G1 and G2. In an exemplary embodiment, for example, one group among the plurality of gate lines G1 and G2 as a first group and the plurality of data lines D1 and D2 as a second group may have a multi-layer structure, and the other group among the plurality of gate lines G1 and G2 as a first group and the plurality of data lines D1 and D2 as a second group may have a single-layer structure. As another example, one of the plurality of gate lines G1 and G2 and the plurality of data lines D1 and D2 may have an n-layer structure (n is a natural number), and the other of the plurality of gate lines G1 and G2 and the plurality of data lines D1 and D2 may have an m-layer structure (m is a natural number different from n). According to the present disclosure, the external light reflectivity of the display panel DP can be easily reduced by controlling at least one layer structure of the plurality of signal lines among the plurality of gate lines G1 and G2 as a group and the plurality of data lines D1 and D2 as another group. This will be described in detail later.

[0081] The first pixel electrode PE1 is arranged on the second insulating layer 20. The first pixel electrode PE1 and the second pixel electrode PE2 may be arranged to be spaced apart from each other along the first direction DR1 with the second data line D2 interposed therebetween. The third pixel electrode PE3 and the fourth pixel electrode PE4 may be arranged to be spaced apart from the first pixel electrode PE1 and the second pixel electrode PE2, respectively, along the second direction DR2 with the first gate line G1 interposed therebetween.

[0082] The first pixel electrode PE1 is connected to the first thin film transistor TR1 at a contact hole defined in the second insulating layer 20. Figure 3B For example, at a contact hole in the second insulating layer 20, a portion of the first pixel electrode PE1 extends into and through the second insulating layer 20 to be connected to the first output electrode OE1 at the contact hole. The first pixel electrode PE1 can receive the voltage output from the first thin film transistor TR1 as an electrical signal.

[0083] Reference Figure 3A The first pixel electrode PE1 may include a first vertical portion VP1, a first horizontal portion HP1 intersecting the first vertical portion VP1, and a plurality of branches B1 to B4. The first vertical portion VP1, the first horizontal portion HP1, and the plurality of branches B1 to B4 are connected to each other to form the first pixel electrode PE1 in a single integral form.

[0084] The first vertical portion VP1 extends longitudinally in the second direction DR2. The first vertical portion VP1 may extend longitudinally in a direction substantially parallel to the first and second data lines D1 and D2.

[0085] The first horizontal portion HP1 is connected to the first vertical portion VP1. The first horizontal portion HP1 extends longitudinally in a first direction DR1. The first horizontal portion HP1 may be connected to the first vertical portion VP1 while intersecting the first vertical portion VP1. In the present exemplary embodiment, the first vertical portion VP1 and the first horizontal portion HP1 are shown as intersecting at each other's center. However, this is merely exemplary, and the first horizontal portion HP1 may be arranged closer to one end of the first vertical portion VP1 relative to the center of the length of the first vertical portion VP1, or closer to one end of the first horizontal portion HP1 relative to the center of the length of the first horizontal portion HP1.

[0086] The plurality of branches B1 to B4 are connected to the first horizontal portion HP1 and / or the first vertical portion VP1 . Each of the plurality of branches B1 to B4 may longitudinally extend in a direction inclined with respect to the first direction DR1 and / or the second direction DR2 .

[0087] Each of the plurality of branches B1 to B4 may extend longitudinally from the first horizontal portion HP1 and / or the first vertical portion VP1 in a radial manner. The plurality of branches B1 to B4 may be divided into a plurality of groups of branches according to the direction in which their lengths extend from the first horizontal portion HP1 and / or the first vertical portion VP1.

[0088] In an exemplary embodiment, for example, the plurality of branches B1 to B4 may be divided into a plurality of first branches B1 (e.g., a plurality of first branches B1), a plurality of second branches B2 (e.g., a plurality of second branches B2), a plurality of third branches B3 (e.g., a plurality of third branches B3), and a plurality of fourth branches B4 (e.g., a plurality of fourth branches B4). Slits SC may be provided or formed between adjacent branches within each group of the plurality of first branches B1 to B4. A plurality of slits SC may be provided (e.g., a plurality of slits SC), each corresponding to the distance between adjacent branches within each group of the plurality of first branches B1 to B4.

[0089] The plurality of first branches B1 longitudinally extend from the first horizontal portion HP1 and / or the first vertical portion VP1 along the third direction DR3 and may be arranged in a pattern substantially parallel to the fourth direction DR4 so as to be spaced apart from each other along the fourth direction DR4.

[0090] The second branches B2 extend longitudinally from the first horizontal portion HP1 and / or the first vertical portion VP1 in the fourth direction DR4 and may be arranged in a pattern substantially parallel to the third direction DR3 so as to be spaced apart from each other in the third direction DR3.

[0091] The third branches B3 extend from the first horizontal portion HP1 and / or the first vertical portion VP1 in the fifth direction DR5 and may be arranged in a pattern substantially parallel to the third direction DR3 so as to be spaced apart from each other in the third direction DR3.

[0092] The fifth direction DR5 may be a direction opposite to the fourth direction DR4. Accordingly, the third branch portion B3 may longitudinally extend in a direction substantially parallel to the length of the second branch portion B2.

[0093] The fourth branches B4 extend longitudinally from the first horizontal portion HP1 and / or the first vertical portion VP1 in the sixth direction DR6. The fourth branches B4 may be arranged in a pattern substantially parallel to the fourth direction DR4 so as to be spaced apart from each other in the fourth direction DR4.

[0094] The sixth direction DR6 may be a direction opposite to the third direction DR3 . Accordingly, the fourth branch portion B4 may longitudinally extend in a direction substantially parallel to the length of the first branch portion B1 .

[0095] Since the first pixel electrode PE1 includes the plurality of branch portions B1 to B4, the first pixel electrode PE1 can display a plurality of grayscales in a single pixel area PA. Specifically, a planar area in which the plurality of first branch portions B1 are arranged, a planar area in which the plurality of second branch portions B2 are arranged, a planar area in which the plurality of third branch portions B3 are arranged, and a planar area in which the plurality of fourth branch portions B4 are arranged can be defined as a plurality of domains that are distinguished from each other.

[0096] Depending on the extension direction (e.g., length) of the plurality of branch portions B1 to B4, the orientation of the liquid crystal molecules LC in the liquid crystal layer 300 can be changed. Therefore, the display panel DP can display various grayscales by domain in a single pixel area PA. As a result, the display panel DP can display an image with improved color reproducibility. Furthermore, a display device DS with high resolution can be realized.

[0097] Refer again Figure 3B The second substrate 200 includes a second base substrate BS2 and a common electrode CE. The second base substrate BS2 may be an optically transparent insulating substrate.

[0098] The common electrode CE forms an electric field with the first pixel electrode PE1. The common electrode CE overlaps with each of the plurality of pixel electrodes PE1, PE2, PE3, and PE4. That is, a single common electrode CE may correspond to each of the plurality of pixel electrodes PE1, PE2, PE3, and PE4 so as to be disposed in common therewith. Each of the plurality of pixel electrodes PE1, PE2, PE3, and PE4, the common electrode CE, and the liquid crystal layer 300 form a liquid crystal capacitor.

[0099] Although not shown in the figure, the display panel DP may further include a plurality of alignment layers. The alignment layers may be disposed between the liquid crystal layer 300 and the second insulating layer 20 and between the liquid crystal layer 300 and the common electrode CE, respectively. Each of the alignment layers may control the initial alignment of the liquid crystal molecules LC.

[0100] Figure 4A is an enlarged cross-sectional view illustrating an exemplary embodiment of a signal line of the display panel DP. Figure 4B is an enlarged cross-sectional view showing a signal line of a comparative display panel. Figure 4A Shown Figure 3B , and Figure 4B An enlarged cross-section of a comparative first gate line G1 -C is shown. Figure 4C A modified exemplary embodiment of the signal lines of the display panel DP is shown.

[0101] In the following, reference will be made to Figure 4A and Figure 4C The present disclosure is described. Figures 4A to 4CIn the Figures 1 to 3B , and therefore detailed description of the same elements will be omitted.

[0102] Reference Figure 4A The first gate line G1 may include a first layer L1, a second layer L2, a third layer L3, and a fourth layer L4 (e.g., first, second, third, and fourth layers L1, L2, L3, and L4). The first layer L1, the second layer L2, the third layer L3, and the fourth layer L4 may be formed along a base substrate BS (refer to Figure 3A The fourth layer L4 may define an upper layer, while the first layer L1, the second layer L2, and the third layer L3 may define a lower layer. In an exemplary embodiment, the upper layer is in direct contact with the lower layer. Layers in direct contact may form an interface therebetween.

[0103] The first layer L1 may include a metal. In an exemplary embodiment, for example, the first layer L1 may include titanium, molybdenum, tungsten, or a combination thereof. The first layer L1 may have an adhesive strength with respect to the second layer L2 that is higher than an adhesive strength with respect to the base substrate BS. The first layer L1 has a first thickness T1. In this exemplary embodiment, when the first layer L1 includes titanium (Ti), the first thickness T1 may be designed to have a range of approximately 50 angstroms or more and approximately 500 angstroms or less.

[0104] The second layer L2 may include a metal. The second layer L2 may have a resistivity lower than that of the first layer L1. As the resistivity of the second layer L2 decreases, the resistivity of the first gate line G1 may decrease. The second layer L2 has a second thickness T2. The second thickness T2 of the second layer L2 may be greater than the first thickness T1 of the first layer L1. As the second thickness T2 increases, the resistivity of the first gate line G1 may decrease. In this exemplary embodiment, when the second layer L2 includes copper (Cu), the second thickness T2 may be designed to have a range of greater than or equal to approximately 1,000 angstroms and less than or equal to approximately 20,000 angstroms.

[0105] The third layer L3 may include metal. The third layer L3 may cover the upper surface of the second layer L2. The third layer L3 may have a reflectivity lower than that of the second layer L2. The amount of light reflected from the upper surface of the second layer L2 may be greater than the amount of light reflected by the stacked structure of the lower layer including the second layer L2 and the third layer L3.

[0106] The third layer L3 may have a higher resistivity than the second layer L2. The third layer L3 may have a third thickness T3. In the present exemplary embodiment, when the third layer L3 includes titanium (Ti), the third thickness T3 may be designed to have a range of approximately 100 angstroms or more and approximately 500 angstroms or less.

[0107] The fourth layer L4 may cover the third layer L3. The fourth layer L4 may define the upper surface of the first gate line G1. The fourth layer L4 may include a metal or a metal oxide. In an exemplary embodiment, for example, the fourth layer L4 may include molybdenum oxide (MoOx), copper oxide (CuO), niobium oxide (NbOx), tantalum oxide (TaOx), molybdenum (Mo), tantalum (Ta), niobium (Nb), nickel (Ni), zinc (Zn), copper (Cu), or a combination thereof.

[0108] The fourth layer L4 may have a reflectivity lower than that of the second layer L2. The fourth layer L4 may have a fourth thickness T4. The reflectivity of the fourth layer L4 may be controlled or limited by the material of the fourth layer L4 and the fourth thickness T4 of the fourth layer L4. In an exemplary embodiment, for example, the fourth layer L4 may include an opaque conductive material. In this exemplary embodiment, when the fourth layer L4 includes copper (Cu), the fourth thickness T4 may be designed to have a value of less than or equal to approximately 100 angstroms.

[0109] As another example, the fourth layer L4 may include a transparent conductive material. In an exemplary embodiment, for example, the fourth layer L4 may include a transparent conductive oxide ("TCO"). Even if the fourth thickness T4 is designed to have a value greater than or equal to about 100 angstroms, the fourth layer L4 may have a relatively low reflectivity.

[0110] In an exemplary embodiment, the first layer L1 , the second layer L2 , and the third layer L3 as the lower layer may each include a different material from an upper layer (eg, the fourth layer L4 ), but is not limited thereto.

[0111] The etching rate of the predetermined etchant with respect to the fourth layer L4 may be within a range of approximately 0.5 times or more and approximately 3 times or less of the etching rate of the predetermined etchant with respect to the first layer L1, the second layer L2, and the third layer L3. That is, the fourth layer L4 may include a material having an etching selectivity within a range of approximately 0.5 or more and approximately 3 or less compared to the first layer L1, the second layer L2, and the third layer L3 with respect to the same etchant. In the present disclosure, the etching selectivity may be set to a value such as thickness per second or angstroms per second (angstroms / second or angstroms / second). )’s etching rate ratio.

[0112] The predetermined etchant may be provided in various forms. In the present exemplary embodiment, the etchant may include a non-aqueous-based solvent.

[0113] When viewed in a cross-sectional view, the first gate line G1 may include an inclined side surface. The side surface of the first gate line G1 may be defined by a set of a plurality of side surfaces S1, S2, S3, and S4 (hereinafter referred to as the first side surface S1, the second side surface S2, the third side surface S3, and the fourth side surface S4) of the first layer L1, the second layer L2, the third layer L3, and the fourth layer L4, respectively. The first side surface S1, the second side surface S2, the third side surface S3, and the fourth side surface S4 may be inclined at a predetermined angle θ relative to the upper surface of the base substrate BS. A The inclined imaginary lines VL are aligned. The first side surface S1 , the second side surface S2 , the third side surface S3 , and the fourth side surface S4 may be coplanar with each other to define inclined side surfaces of the first gate line G1 .

[0114] Reference Figure 4B , the comparative first gate line G1-C may include a comparative first layer L1C, a comparative second layer L2C, a comparative third layer L3C, and a comparative fourth layer L4C. The comparative first layer L1C, the comparative second layer L2C, the comparative third layer L3C, and the comparative fourth layer L4C are sequentially stacked along the thickness direction of the base substrate BS. Figure 4B , the comparative first layer L1C, the comparative second layer L2C, and the comparative third layer L3C may correspond to the first layer L1, the second layer L2, and the third layer L3 according to one or more exemplary embodiments of the present disclosure, and the comparative fourth layer L4C may be different from the fourth layer L4 according to one or more exemplary embodiments of the present disclosure. The side surface of the comparative first gate line G1-C may be defined by a plurality of comparative side surfaces S1C, S2C, S3C, and S4C (hereinafter referred to as comparative first side surface S1C, comparative second side surface S2C, comparative third side surface S3C, and comparative fourth side surface S4C) of the comparative first layer L1C, the comparative second layer L2C, the comparative third layer L3C, and the comparative fourth layer L4C.

[0115] Compared to the first gate line G1 according to one or more exemplary embodiments of the present disclosure, the comparative first gate line G1-C may further include a tip portion TP. The tip portion TP may be provided or formed as a protrusion of the comparative third layer L3C and the comparative fourth layer L4C, which define the comparative third side surface S3C and the comparative fourth side surface S4C relative to the comparative first side surface S1C and the comparative second side surface S2C. The comparative third layer L3C and the comparative fourth layer L4C may each extend further than the comparative first side surface S1C and the comparative second side surface S2C to define the tip portion TP.

[0116] In the comparative first gate line G1-C, the comparative fourth layer L4C may be an oxide of the comparative third layer L3C. For example, when the comparative third layer L3C includes titanium, the comparative fourth layer L4C may include titanium oxide TiOx. The comparative fourth layer L4C may be provided or formed when the material used to form the comparative third layer L3C is oxidized during the process of providing or forming the comparative first gate line G1-C. That is, in the comparative first gate line G1-C, the comparative first layer L1C, the comparative second layer L2C, and the comparative third layer L3C may correspond to a previously designed structure, and the comparative fourth layer L4C may be a byproduct generated during a process (e.g., a deposition process or an etching process).

[0117] With respect to the same etchant, the comparative fourth layer L4C may have a relatively lower etching rate than the comparative first layer L1C, the comparative second layer L2C, and the comparative third layer L3C. The comparative third layer L3C may be protected from the etchant by the comparative fourth layer L4C. Accordingly, during the etching process, due to the difference in etching rates between the comparative first layer L1C and the comparative second layer L2C and the comparative third layer L3C and the comparative fourth layer L4C, a tip portion TP may be formed in the comparative first gate line G1-C.

[0118] The tip portion TP may serve as a locally causing the first insulating layer 10 (refer to Figure 3B ) or the second insulating layer 20 (refer to Figure 3B ) is damaged. The first insulating layer 10 or the second insulating layer 20 may be disconnected or damaged by the tip portion TP. Accordingly, the display panel DP (refer to Figure 1 ) process reliability may be reduced.

[0119] According to the present disclosure, since the fourth layer L4 is intentionally and additionally provided or formed when forming the first gate line G1, the formation of an oxide layer such as the comparative fourth layer L4C formed on the comparative third layer L3C can be reduced or effectively prevented compared to the comparative fourth layer L4C generated as a by-product during the manufacturing process of the comparative first gate line G1-C. Therefore, in the etching process of the first gate line G1, the plurality of side surfaces S1, S2, S3, and S4 can be formed at a predetermined angle θ. A The tip portion TP is provided or formed, and thus, the formation of the tip portion TP can be suppressed. As a result, the process reliability of the display panel DP can be improved.

[0120] like Figure 4C As shown in FIG, an exemplary embodiment of the first gate line G1-1 may include two layers L11 and L21, which are less than the four layers included in the first gate line G1. The first layer L11 may include a conductive material. The first layer L11 has a first thickness T11 and a first side surface S11.

[0121] The second layer L21 is directly disposed on the first layer L11. The second layer L21 includes a conductive material and has a second thickness T21 and a second side surface S21.

[0122] The first and second side surfaces S11 and S21 may be arranged along a predetermined angle θ with respect to the upper surface of the base substrate BS. A The inclined imaginary lines VL are continuously connected to each other.The first side surface S11 and the second side surface S21 may be coplanar with each other.

[0123] In this exemplary embodiment, the second layer L21 can be designed to have an etching rate within a range of approximately 0.5 times or greater and approximately 3 times or less of the etching rate of the first layer L11 with respect to the same etchant. Specifically, the etching selectivity of the material of the second layer L21 with respect to the specific etchant can be within a range of approximately 0.5 to approximately 3 times that of the material of the first layer L11. As the difference in etching rate between the first layer L11 and the second layer L21 decreases, the formation of the tip portion TP can be easily suppressed.

[0124] According to the present disclosure, when the first gate line G1 has a structure in which multiple layers are sequentially stacked, the uppermost layer is formed of a material having an etching rate within a range of approximately 0.5 times or more and approximately 3 times or less of the etching rate of the lower layer below the uppermost layer relative to the etching rate of a predetermined etchant. Therefore, the difference in etching rate between the uppermost layer and the lower layer can be reduced. Therefore, the occurrence of process defects such as the tip portion TP can be reduced or effectively prevented, and the process reliability of the display panel DP can be improved.

[0125] Figure 5 Graph showing light reflectance in a plurality of embodiments. Figure 5 The average external light reflectance percentage (%) of a plurality of comparative embodiments C1, C2 and C3 and a plurality of exemplary embodiments E1, E2, E3, E4, E5 and E6 of the present invention is shown. Figure 5 The present disclosure is described.

[0126] The plurality of comparative embodiments C1, C2, and C3 may include a first comparative embodiment C1, a second comparative embodiment C2, and a third comparative embodiment C3. The first comparative embodiment C1 relates to a comparative embodiment having a stacked structure including a single lower layer including copper and having a thickness of approximately 6000 angstroms and an uppermost layer including titanium and having a thickness of approximately 200 angstroms. The second comparative embodiment C2 relates to a comparative embodiment having a structure including a single layer including titanium and having a thickness of approximately 1000 angstroms. The third comparative embodiment C3 relates to a comparative embodiment having a stacked structure including a double lower layer including a layer including titanium and having a thickness of approximately 250 angstroms and a layer including copper and having a thickness of approximately 6000 angstroms, the uppermost layer including titanium and having a thickness of approximately 200 angstroms.

[0127] In several comparative embodiments C1, C2, and C3, a single lower layer comprising only copper has an etching rate of approximately 150 Å / s, and a single layer comprising only titanium has an etching rate of approximately 3.3 Å / s. However, in the third comparative embodiment C3 having a titanium / copper / titanium structure, the etching rate of the uppermost titanium layer may be approximately 3.3 Å / s, and the etching rate of the lower titanium layer may be approximately 25 Å / s. Because the oxide layer is formed on titanium, which is highly reactive with oxygen, the uppermost titanium layer has a relatively low etching rate compared to the lower titanium layer without the oxide layer. In the third comparative embodiment C3, the lower layer of the copper / titanium stacked structure, excluding the uppermost titanium layer, has an etching rate of approximately 130 Å / s. Accordingly, the etching rate of the uppermost layer comprising titanium is approximately 0.022 times the etching rate of the lower layer in the first comparative embodiment C1 and approximately 0.025 times in the third comparative embodiment C3, and does not meet the range of greater than or equal to about 0.5 and less than or equal to about 3.

[0128] The various exemplary embodiments E1, E2, E3, E4, E5, and E6 of the present disclosure may include a first exemplary embodiment E1, a second exemplary embodiment E2, a third exemplary embodiment E3, a fourth exemplary embodiment E4, a fifth exemplary embodiment E5, and a sixth exemplary embodiment E6. Each of the first exemplary embodiment E1, the second exemplary embodiment E2, the third exemplary embodiment E3, the fourth exemplary embodiment E4, the fifth exemplary embodiment E5, and the sixth exemplary embodiment E6 has the same Figure 4A The first gate line G1 shown in FIG. Figure 4A ) and only the fourth layer L4 (refer to Figure 4A) have different thicknesses from each other. In each of the first exemplary embodiment E1, the second exemplary embodiment E2, the third exemplary embodiment E3, the fourth exemplary embodiment E4, the fifth exemplary embodiment E5, and the sixth exemplary embodiment E6, the first layer L1, the second layer L2, and the third layer L3 (refer to Figure 4A ) may correspond to the third comparative embodiment C3. That is, the first exemplary embodiment E1, the second exemplary embodiment E2, the third exemplary embodiment E3, the fourth exemplary embodiment E4, the fifth exemplary embodiment E5, and the sixth exemplary embodiment E6 may be provided with the fourth layer L4 added thereto.

[0129] Specifically, the first exemplary embodiment E1 may include a lower layer and an uppermost layer, wherein the lower layer sequentially comprises a layer comprising titanium and having a thickness of approximately 250 angstroms, a layer comprising copper and having a thickness of approximately 6000 angstroms, and a layer comprising titanium and having a thickness of approximately 200 angstroms, and the uppermost layer, disposed directly on the lower layer, comprises copper and has a thickness of 20 angstroms. A second exemplary embodiment E2 may be an embodiment in which the uppermost layer of the first exemplary embodiment E1 is replaced by a copper layer having a thickness of approximately 30 angstroms. A third exemplary embodiment E3 may be an embodiment in which the uppermost layer of the first exemplary embodiment E1 is replaced by a copper layer having a thickness of approximately 40 angstroms. Copper has an etching rate of approximately 150 angstroms / second, and the lower layer having a stacked structure of titanium / copper / titanium has an etching rate of approximately 115 angstroms / second. Accordingly, the etching selectivity of the uppermost layer comprising copper relative to the lower layer is approximately 1.30, satisfying a range of approximately 0.5 or greater and approximately 3 or less.

[0130] A fourth exemplary embodiment E4 may be an embodiment in which the uppermost layer of the first exemplary embodiment E1 is replaced by a copper layer having a thickness of approximately 50 angstroms. A fifth exemplary embodiment E5 may be an embodiment in which the uppermost layer of the first exemplary embodiment E1 is replaced by a copper layer having a thickness of approximately 60 angstroms. A sixth exemplary embodiment E6 may be an embodiment in which the uppermost layer of the first exemplary embodiment E1 is replaced by a copper layer having a thickness of approximately 70 angstroms.

[0131] Figure 5 The graph shown in shows relative external light reflectance of each of the plurality of embodiments C1, C2, C3, E1, E2, E3, E4, E5, and E6, when it is assumed that the external light reflectance of a single layer including aluminum is about 100%, and shows an average value. Figure 5 The present disclosure is described.

[0132] like Figure 5As shown in , the first exemplary embodiment E1, the second exemplary embodiment E2, the third exemplary embodiment E3, the fourth exemplary embodiment E4, the fifth exemplary embodiment E5, and the sixth exemplary embodiment E6 may have relatively low reflectivity compared to the first comparative embodiment C1 among the plurality of comparative embodiments C1, C2, and C3, and may have an external light reflectivity close to that of aluminum ( Figure 5 Compared to the second comparative embodiment C2 and the third comparative embodiment C3 among the plurality of comparative embodiments C1, C2, and C3, the first exemplary embodiment E1, the second exemplary embodiment E2, the third exemplary embodiment E3, the fourth exemplary embodiment E4, the fifth exemplary embodiment E5, and the sixth exemplary embodiment E6 may have relatively high reflectivity.

[0133] Since the second comparative embodiment C2 has the lowest reflectivity but has a single layer including titanium, the second comparative embodiment C2 may have a relatively high resistivity compared to other embodiments including copper. Therefore, the electrical characteristics of the display panel DP including the structure of the second comparative embodiment C2 may be degraded due to the relatively high resistivity compared to the first, second, third, fourth, fifth, and sixth exemplary embodiments E1, E2, E3, E4, E5, and E6.

[0134] The third comparative embodiment C3 may have a relatively low reflectivity compared to the first exemplary embodiment E1, the second exemplary embodiment E2, the third exemplary embodiment E3, the fourth exemplary embodiment E4, the fifth exemplary embodiment E5, and the sixth exemplary embodiment E6. The third comparative embodiment C3 may substantially correspond to Figure 4B That is, the third comparative embodiment C3 may have a relatively low reflectivity. However, during the process of forming the third comparative embodiment C3, it is likely to generate a tip portion TP (refer to FIG. Figure 4B ), and the process reliability of the display panel DP including the structure of the third comparative embodiment C3 is deteriorated.

[0135] As described above, in the first, second, third, fourth, fifth, and sixth exemplary embodiments E1, E2, E3, E4, E5, and E6, the likelihood of an oxide layer forming during the process is relatively low. Furthermore, the ratio of the etching rate of the uppermost layer to the lower layer can be maintained within a predetermined range. Therefore, defects such as the formation of a tip portion TP caused by the difference in etching rate between the uppermost and lower layers can be reduced or effectively prevented.

[0136] In addition, the external light reflectivity of the first example embodiment E1, the second example embodiment E2, the third example embodiment E3, the fourth example embodiment E4, the fifth example embodiment E5 and the sixth example embodiment E6 is relatively greater than the external light reflectivity of the third comparative embodiment C3, but the difference in external light reflectivity between the first example embodiment E1 to the sixth example embodiment E6 and the third comparative embodiment C3 is not large, and the external light reflectivity of the first example embodiment E1 to the sixth example embodiment E6 is greatly reduced compared with the embodiment including only aluminum or the first comparative embodiment C1.

[0137] According to one or more exemplary embodiments of the present disclosure, a display panel DP including a conductive structure (e.g., signal lines, electrodes, electronic components) can be provided. The conductive structure has a resistivity similar to that of the first comparative embodiment C1 or the third comparative embodiment C3, has a lower light reflectivity than the first comparative embodiment C1, and has improved process reliability compared to the third comparative embodiment C3. Therefore, the external light reflectivity of the display panel DP can be reduced, and the visibility of the display panel DP can be improved. In addition, the process yield when setting the display panel DP can be improved, and the manufacturing cost of the display panel DP can be reduced.

[0138] Figure 6 is a top plan view illustrating a portion of a display panel according to an exemplary embodiment of the present disclosure. Figure 6 It is shown that on the first substrate 100 (refer to Figure 3B ) is a plan view of an area in which the first pixel area PA11 and the second pixel area PA21 are arranged. Figure 6 The present disclosure is described. Figure 6 In the Figures 1 to 5 , and therefore detailed description of the same elements will be omitted.

[0139] Reference Figure 6 The first pixel area PA11 may be disposed between two data lines D11 and D12, and one gate line G11 may intersect the first pixel area PA11. Two pixel electrodes PE11 and PE12 and two thin film transistors may be arranged in the first pixel area PA11.

[0140] The first semiconductor pattern SP11 is arranged in the first pixel area PA11 and overlaps the first gate line G11. A portion of the first gate line G11 overlapping the first semiconductor pattern SP11 may correspond to the first control electrode CE1 of the thin film transistor (refer to FIG. Figure 3A ).

[0141] The input electrode IE11 branched from the first data line D11 extends to overlap the first semiconductor pattern SP11. The input electrode IE11 may include a first input electrode IE11a surrounding a portion of the first output electrode OE11 and a second input electrode IE11b surrounding a portion of the second output electrode OE12.

[0142] A portion of the first gate line G11, a portion of the first semiconductor pattern SP11, the first input electrode IE11a, and the first output electrode OE11 may form a thin film transistor to control the first sub-pixel electrode PE11. A portion of the first gate line G11, a portion of the first semiconductor pattern SP11, the second input electrode IE11b, and the second output electrode OE12 may form a thin film transistor to control the second sub-pixel electrode PE12.

[0143] According to the present disclosure, two thin film transistors arranged in the first pixel area PA11 can be connected to one gate line G11 and one data line D11, and can control the voltages of the first sub-pixel electrode PE11 and the second sub-pixel electrode PE12, which are distinguished from each other. Similarly, the third sub-pixel electrode PE21 and the fourth sub-pixel electrode PE22 arranged in the second pixel area PA21 can be controlled by thin film transistors connected to one gate line G11 and one data line D21, respectively.

[0144] However, this is merely exemplary, and the first pixel area PA11 and the second pixel area PA21 according to the exemplary embodiment of the present disclosure may have various pixel structures and should not be particularly limited.

[0145] In this exemplary embodiment, the plurality of signal lines D11, D12, D21, D22, SL1, and SL2 may overlap at least a portion of the plurality of subpixel electrodes PE11, PE12, PE21, and PE22. For example, the first data line D11, the second data line D12, and the first conductive line SL1 may be arranged to overlap the first subpixel electrode PE11 and the second subpixel electrode PE12. As another example, the third data line D21, the fourth data line D22, and the second conductive line SL2 may be arranged to overlap the third subpixel electrode PE21 and the fourth subpixel electrode PE22.

[0146] According to the present disclosure, at least one of the plurality of signal lines D11, D12, D21, D22, SL1, and SL2 may have a Figure 4A and Figure 4CThe first gate line G1 and the first gate line G1-1 shown in FIG may have substantially the same structure. That is, at least one of the plurality of signal lines D11, D12, D21, D22, SL1, and SL2 may have a structure including a lower layer and an uppermost layer with an etching selectivity within a range of greater than or equal to about 0.5 and less than or equal to about 3 relative to a predetermined etchant compared to a lower layer.

[0147] Therefore, even if the plurality of signal lines D11, D12, D21, D22, SL1, and SL2 are arranged at positions where they overlap with the plurality of sub-pixel electrodes PE11, PE12, PE21, and PE22 and are visible to the user, the visibility of the plurality of signal lines D11, D12, D21, D22, SL1, and SL2 can be reduced because the plurality of signal lines D11, D12, D21, D22, SL1, and SL2 have low reflectivity with respect to external light. In addition, since the plurality of signal lines D11, D12, D21, D22, SL1, and SL2 include an uppermost layer having an etching selectivity not greater than that of a lower layer, improved process reliability can be ensured.

[0148] 7A to 7C is a cross-sectional view illustrating a method of manufacturing a display panel according to an exemplary embodiment of the present disclosure. 7A to 7C The present disclosure is described. 7A to 7C In the Figures 1 to 6 , and thus detailed description of the same elements will be omitted.

[0149] Reference Figure 7A , a first conductive layer CL1, a second conductive layer CL2, a third conductive layer CL3, and a fourth conductive layer CL4 are sequentially stacked on a base substrate BS. The first conductive layer CL1, the second conductive layer CL2, the third conductive layer CL3, and the fourth conductive layer CL4 can be formed by a deposition or coating process. The first conductive layer CL1, the second conductive layer CL2, the third conductive layer CL3, and the fourth conductive layer CL4 can be formed by a continuous process.

[0150] Then, refer to Figure 7B and Figure 7C The first conductive layer CL1, the second conductive layer CL2, the third conductive layer CL3 and the fourth conductive layer CL4 may be patterned to form a predetermined pattern PT. The pattern PT may be Figure 4A The first gate line G1 shown in FIG.

[0151] The first conductive layer CL1, the second conductive layer CL2, the third conductive layer CL3, and the fourth conductive layer CL4 may be patterned through an etching process. A predetermined mask MSK is disposed on the first conductive layer CL1, the second conductive layer CL2, the third conductive layer CL3, and the fourth conductive layer CL4, and an etchant ET is provided. Exposed portions of the first conductive layer CL1, the second conductive layer CL2, the third conductive layer CL3, and the fourth conductive layer CL4 not covered by the mask MSK may be etched and removed using the etchant ET.

[0152] The etchant ET may be a non-aqueous solvent. Accordingly, the first conductive layer CL1, the second conductive layer CL2, the third conductive layer CL3, and the fourth conductive layer CL4 may be formed of a material that is reactive with the etchant ET. However, this is merely exemplary, and as long as the first conductive layer CL1, the second conductive layer CL2, the third conductive layer CL3, and the fourth conductive layer CL4 are etched, the etchant ET may be selected from a water-based solvent depending on the materials of the first conductive layer CL1, the second conductive layer CL2, the third conductive layer CL3, and the fourth conductive layer CL4. The etchant ET is not particularly limited.

[0153] The first conductive layer CL1, the second conductive layer CL2, the third conductive layer CL3, and the fourth conductive layer CL4 may be etched in the order in which they are exposed to the etchant ET. Therefore, the first conductive layer CL1, the second conductive layer CL2, the third conductive layer CL3, and the fourth conductive layer CL4 may be etched in the order of the fourth conductive layer CL4, the third conductive layer CL3, the second conductive layer CL2, and the first conductive layer CL1. The fourth conductive layer CL4 may define an upper layer, while one or more of the first conductive layer CL1, the second conductive layer CL2, and the third conductive layer CL3 define a lower layer. The upper layer may be in direct contact with the lower layer.

[0154] According to the present exemplary embodiment, the fourth conductive layer CL4 among the first conductive layer CL1, the second conductive layer CL2, the third conductive layer CL3, and the fourth conductive layer CL4 may be formed of a material having an etching rate similar to that of the first conductive layer CL1, the second conductive layer CL2, and the third conductive layer CL3 with respect to the etchant ET. Specifically, the fourth conductive layer CL4 may be formed of a material having an etching selectivity in a range of approximately 0.5 or more and approximately 3 or less compared to the first conductive layer CL1, the second conductive layer CL2, and the third conductive layer CL3.

[0155] Accordingly, the first conductive layer CL1, the second conductive layer CL2, the third conductive layer CL3, and the fourth conductive layer CL4 may be etched at similar etching rates during the etching process. The first layer L1, the second layer L2, the third layer L3, and the fourth layer L4 may include a substrate BS having a predetermined angle θ with respect to the upper surface thereof. AA plurality of side surfaces S1 , S2 , S3 , and S4 are aligned on an inclined imaginary line VL.

[0156] According to the present disclosure, since the uppermost layer corresponding to the fourth layer L4 is formed of a material having an etching selectivity in a range of approximately 0.5 or more and approximately 3 or less compared to the first layer L1, the second layer L2, and the third layer L3 corresponding to the lower layers, the difference in etching rate between the uppermost layer and the lower layers can be reduced. Therefore, a pattern PT having low reflectivity and improved process reliability can be easily formed.

[0157] Although exemplary embodiments of the present invention have been described, it should be understood that the present invention should not be limited to these exemplary embodiments, but various changes and modifications may be made by one skilled in the art within the spirit and scope of the invention as defined in the appended claims.

[0158] Therefore, the disclosed subject matter should not be limited to any single embodiment described herein, and the scope of the present invention should be determined based on the following claims.

Claims

1. A display panel, comprising: base substrate; a pixel located on the base substrate and comprising a thin film transistor and a display element connected to the thin film transistor; as well as a signal line connected to the pixel, wherein the signal line comprises: a lower layer comprising a conductive material; and an upper layer, the upper layer comprising a conductive material, Wherein, the lower layer includes: a first layer, the first layer being located on the base substrate; a second layer located on the first layer; and a third layer, the third layer being located between the second layer and the upper layer, The upper layer has an etching selectivity in a range of greater than or equal to 0.5 and less than or equal to 3 relative to the lower layer, and The upper layer has a lower light reflectivity than the second layer.

2. The display panel according to claim 1, wherein: In the signal line, the upper layer is in direct contact with the lower layer.

3. The display panel according to claim 1, wherein: In the signal line, the upper layer includes an opaque material and has a thickness of less than or equal to 100 angstroms.

4. The display panel according to claim 3, wherein: The second layer has a lower resistivity than the first layer; and The third layer has lower light reflectivity than the second layer and is in contact with the upper layer.

5. The display panel according to claim 4, wherein: In the signal line, the upper layer includes the same material as the second layer of the lower layer.

6. The display panel according to claim 5, wherein: In the signal line, the upper layer has a thickness smaller than a thickness of each of the first layer, the second layer, and the third layer of the lower layer.

7. The display panel according to claim 5, wherein: In the signal line, the second layer of the upper layer and the lower layer each includes copper.

8. The display panel according to claim 4, wherein: In the signal line, the first layer, the second layer, and the third layer of the lower layer each include a material different from that of the upper layer.

9. The display panel according to claim 8, wherein: In the signal line, the upper layer includes a transparent conductive oxide material, a metal material, or a metal oxide material.

10. The display panel according to claim 1, wherein: The etching selectivity is the etching selectivity relative to a non-aqueous etchant.

11. The display panel according to claim 1, wherein: In the signal line, the upper layer includes a side surface, the lower layer includes a side surface, and the side surface of the upper layer and the side surface of the lower layer are aligned with each other along an imaginary line in a cross section of the base substrate.

12. The display panel according to claim 11, wherein: The imaginary line is inclined with respect to the upper surface of the base substrate.

13. The display panel according to claim 1, further comprising: an insulating layer, the insulating layer comprising an inorganic layer, The signal lines are provided in plurality, and the plurality of signal lines include a first signal line and a second signal line respectively connected to the pixel, and The first signal line and the second signal line are located in different layers from each other, and the insulating layer is interposed between the first signal line and the second signal line.

14. The display panel according to claim 1, wherein: The thin film transistor includes: control electrodes; and input electrodes and output electrodes spaced apart from each other, Wherein, the output electrode is connected to the display element.

15. The display panel according to claim 14, wherein: At least one of the control electrode, the input electrode, and the output electrode of the thin film transistor includes a lower layer and an upper layer.

16. The display panel according to claim 1, wherein: The display element includes a pixel electrode, a common electrode, and an optical control layer located between the pixel electrode and the common electrode, and In a plan view, the upper layer and the lower layer in the signal line each overlap with the pixel electrode.

17. A display panel comprising: base substrate; a pixel located on the base substrate and comprising a thin film transistor and a display element connected to the thin film transistor; as well as a signal line connected to the pixel, Wherein, the signal line includes: an upper layer having a thickness of 100 angstroms or less; and a lower layer, the lower layer being located between the base substrate and the upper layer, Wherein, the lower layer includes: a first layer, the first layer being located on the base substrate; a second layer located on the first layer; and a third layer located between the second layer and the upper layer, and The upper layer has a lower light reflectivity than the second layer.

18. The display panel according to claim 17, wherein: The first layer includes a first metal; the second layer includes a second metal different from the first metal, the second layer being in contact with the first layer; and The third layer includes a third metal that is the same as the first metal, and the third layer is in contact with the second layer and the upper layer.

19. The display panel according to claim 18, wherein: In the signal line, the upper layer includes the same metal as the second metal of the second layer of the lower layer, and The second layer of the lower layer is thicker than the upper layer.

20. The display panel according to claim 18, wherein In the signal line, the third layer has a lower reflectivity than the second layer and a higher resistivity than the second layer.

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